ALC885M-GR [REALTEK]
7.12 CHANNEL HIGH-PERFORMANCE HDA CODEC WITH CONTENT PROTECTION;
| 型号： | ALC885M-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.12 CHANNEL HIGH-PERFORMANCE HDA CODEC WITH CONTENT PROTECTION |
| 文件： | 总98页 (文件大小：1531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC885-GR
ALC885M-GR
7.1+2 CHANNEL HIGH-PERFORMANCE HDA
CODEC WITH CONTENT PROTECTION
DATASHEET
Rev. 1.1
18 October 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC885 Series
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC885 Audio Codec ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2006/06/06
2006/10/18
Summary
First release.
1.1
MIDI function is not supported as pins 47 and 48 are assigned as S/PDIF IO
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Datasheet
Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................ 2
2.1. HARDWARE FEATURES.....................................................................................................................2
2.2. SOFTWARE FEATURES ......................................................................................................................3
3. System Applications .................................................................................................... 3
4. Block Diagram............................................................................................................. 4
4.1. ANALOG INPUT/OUTPUT UNIT .........................................................................................................5
5. Pin Assignments........................................................................................................... 6
5.1. GREEN PACKAGE AND VERSION IDENTIFICATION ............................................................................6
6. Pin Descriptions........................................................................................................... 7
6.1. DIGITAL I/O PINS .............................................................................................................................7
6.2. ANALOG I/O PINS.............................................................................................................................7
6.3. FILTER/REFERENCE/NC ...................................................................................................................8
6.4. POWER/GROUND ..............................................................................................................................8
7. High Definition Audio Link Protocol ........................................................................ 9
7.1. LINK SIGNALS ..................................................................................................................................9
7.1.1.
7.1.2.
Signal Definitions.................................................................................................................................................10
Signaling Topology...............................................................................................................................................11
7.2. FRAME COMPOSITION.....................................................................................................................12
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.2.5.
Outbound Frame – Single SDO............................................................................................................................12
Outbound Frame – Multiple SDOs.......................................................................................................................13
Inbound Frame – Single SDI................................................................................................................................14
Inbound Frame – Multiple SDIs...........................................................................................................................15
Variable Sample Rates..........................................................................................................................................15
7.3. RESET AND INITIALIZATION............................................................................................................18
7.3.1.
7.3.2.
7.3.3.
Link Reset .............................................................................................................................................................18
Codec Reset..........................................................................................................................................................19
Codec Initialization Sequence ..............................................................................................................................20
7.4. VERB AND RESPONSE FORMAT.......................................................................................................21
7.4.1.
7.4.2.
Command Verb Format ........................................................................................................................................21
Response Format..................................................................................................................................................24
7.5. POWER MANAGEMENT ...................................................................................................................24
8. Supported Verbs and Parameters............................................................................ 26
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .................................................................................26
8.1.1.
8.1.2.
8.1.3.
8.1.4.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................26
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................26
Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................27
Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................27
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8.1.5.
8.1.6.
8.1.7.
8.1.8.
8.1.9.
Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................28
Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................28
Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................31
Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................34
Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................35
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................37
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................39
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................40
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................42
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................43
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................43
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................44
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................44
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .....................................................................45
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................45
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)........................................................................49
8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ........................................................................50
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................50
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H)............................................................................50
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................51
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..................................................................51
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................52
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).................................................................................54
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)........................................................................55
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H) .........................................................................57
8.15. VERB – GET POWER STATE (VERB ID=F05H)................................................................................58
8.16. VERB – SET POWER STATE (VERB ID=705H).................................................................................59
8.17. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................60
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................60
8.19. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................61
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................62
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................63
8.22. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................64
8.23. VERB – GET PIN SENSE (VERB ID=F09H)......................................................................................64
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H)..............................................................................65
8.25. VERB – GET VOLUME KNOB WIDGET (VERB ID=F0FH)................................................................65
8.26. VERB – SET VOLUME KNOB WIDGET (VERB ID=70FH).................................................................66
8.27. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................66
8.28. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
BYTES 0, 1, 2, 3).............................................................................................................................67
8.29. VERB – GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................67
8.30. VERB – SET BEEP GENERATOR (VERB ID=70AH) ........................................................................68
8.31. VERB – GET GPIO DATA (VERB ID=F15H)...................................................................................68
8.32. VERB – SET GPIO DATA (VERB ID=715H)....................................................................................69
8.33. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................69
8.34. VERB – SET GPIO ENABLE MASK (VERB ID=716H)......................................................................70
8.35. VERB – GET GPIO DIRECTION (VERB ID=F17H)...........................................................................70
8.36. VERB – SET GPIO DIRECTION (VERB ID=717H)............................................................................71
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8.37. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ...........................71
8.38. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ............................72
8.39. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................72
8.40. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............73
8.41. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................74
8.42. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H).......................................76
8.43. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR
[15:8], 720H FOR [7:0]) ..................................................................................................................76
9. Electrical Characteristics ......................................................................................... 77
9.1. DC CHARACTERISTICS ...................................................................................................................77
9.1.1.
9.1.2.
9.1.3.
9.1.4.
Absolute Maximum Ratings..................................................................................................................................77
Threshold Voltage.................................................................................................................................................77
Digital Filter Characteristics...............................................................................................................................78
S/PDIF Input/Output Characteristics...................................................................................................................78
9.2. AC CHARACTERISTIC.....................................................................................................................79
9.2.1.
9.2.2.
9.2.3.
9.2.4.
Link Reset and Initialization Timing.....................................................................................................................79
Link Timing Parameters at the Codec ..................................................................................................................80
S/PDIF Output and Input Timing .........................................................................................................................81
Test Mode..............................................................................................................................................................81
9.3. ANALOG PERFORMANCE ................................................................................................................82
10. Application Circuits .................................................................................................. 83
11. Application Supplements.......................................................................................... 86
11.1. STANDBY MODE.............................................................................................................................86
11.2. VOLUME KNOB CONTROL ..............................................................................................................86
11.2.1. GPI Volume Control via GPIO0 (Up/Down), GPIO1 (Mute)...............................................................................86
11.2.2. Volume Control by External Variable Resistor .....................................................................................................87
11.3. DIGITAL MICROPHONE IMPLEMENTATION......................................................................................88
12. Mechanical Dimensions ............................................................................................ 89
13. Ordering Information............................................................................................... 90
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List of Tables
Table 1. Digital I/O Pins ...........................................................................................................................7
Table 2. Analog I/O Pins...........................................................................................................................7
Table 3. Filter/Reference...........................................................................................................................8
Table 4. Power/Ground.............................................................................................................................8
Table 5. Link Signal Definitions.............................................................................................................10
Table 6. HDA Signal Definitions............................................................................................................10
Table 7. Defined Sample Rate and Transmission Rate...........................................................................16
Table 8. 48kHz Variable Rate of Delivery Timing .................................................................................16
Table 9. 44.1kHz Variable Rate of Delivery Timing ..............................................................................17
Table 10. 40-Bit Commands in 4-Bit Verb Format...................................................................................21
Table 11. 40-Bit Commands in 12-Bit Verb Format.................................................................................21
Table 12. Verbs Supported by the ALC885 (Y=Supported).....................................................................22
Table 13. Parameters in the ALC885 (Y=Supported)...............................................................................23
Table 14. Solicited Response Format .......................................................................................................24
Table 15. Unsolicited Response Format ...................................................................................................24
Table 16. System Power State Definitions ...............................................................................................24
Table 17. Power Controls in NID 01h ......................................................................................................25
Table 18. Powered Down Conditions .......................................................................................................25
Table 19. Verb – Get Parameters (Verb ID=F00h) ...................................................................................26
Table 20. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)...................................................26
Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................26
Table 22. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................27
Table 23. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................27
Table 24. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................28
Table 25. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................28
Table 26. Widget Capability Support........................................................................................................29
Table 27. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................31
Table 28. Sample Rate and PCM Size Supported in Each Converter.......................................................33
Table 29. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................34
Table 30. Stream Format Supported in Each Converter ...........................................................................34
Table 31. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................35
Table 32. Pin Capabilities.........................................................................................................................36
Table 33. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....37
Table 34. Output Amplifier Capabilities...................................................................................................37
Table 35. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...39
Table 36. Input Amplifier Capabilities .....................................................................................................39
Table 37. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................40
Table 38. Connection List Length for Widget Input Source.....................................................................41
Table 39. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................42
Table 40. Power State Supported in Each Widget ....................................................................................42
Table 41. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................43
Table 42. Coefficient Registers Supported in Realtek Defined Widget ...................................................43
Table 43. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................43
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Table 44. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................44
Table 45. Verb – Get Connection Select Control (Verb ID=F01h)...........................................................44
Table 46. Verb – Set Connection Select (Verb ID=701h).........................................................................45
Table 47. Verb – Get Connection List Entry (Verb ID=F02h)..................................................................45
Table 48. Verb – Get Processing State (Verb ID=F03h)...........................................................................49
Table 49. Verb – Set Processing State (Verb ID=703h)............................................................................50
Table 50. Verb – Get Coefficient Index (Verb ID=Dh).............................................................................50
Table 51. Verb – Set Coefficient Index (Verb ID=5h) ..............................................................................50
Table 52. Verb – Get Processing Coefficient (Verb ID=Ch).....................................................................51
Table 53. Verb – Set Processing Coefficient (Verb ID=4h)......................................................................51
Table 54. Verb – Get Amplifier Gain (Verb ID=Bh) ................................................................................52
Table 55. Verb – Set Amplifier Gain (Verb ID=3h)..................................................................................54
Table 56. Verb – Get Converter Format (Verb ID=Ah)............................................................................55
Table 57. Verb – Set Converter Format (Verb ID=2h)..............................................................................57
Table 58. Verb – Get Power State (Verb ID=F05h) ..................................................................................58
Table 59. Verb – Set Power State (Verb ID=705h)...................................................................................59
Table 60. Verb – Set Converter Stream, Channel (Verb ID=706h)...........................................................60
Table 61. Verb – Get Pin Widget Control (Verb ID=F07h) ......................................................................61
Table 62. Verb – Set Pin Widget Control (Verb ID=707h).......................................................................62
Table 63. Verb – Get Unsolicited Response Control (Verb ID=F08h) .....................................................63
Table 64. Verb – Set Unsolicited Response Control (Verb ID=708h) ......................................................64
Table 65. Verb – Get Pin Sense (Verb ID=F09h)......................................................................................64
Table 66. Verb – Execute Pin Sense (Verb ID=709h)...............................................................................65
Table 67. Verb – Get Volume Knob (Verb ID=F0Fh)...............................................................................65
Table 68. Verb – Set Volume Knob (Verb ID=70Fh)................................................................................66
Table 69. Verb – Get Configuration Default (Verb ID=F1Ch) .................................................................66
Table 70. Verb – Set Configuration Default Bytes 0, 1, 2, 3 ....................................................................67
Table 71. Verb – Get BEEP Generator (Verb ID= F0Ah).........................................................................67
Table 72. Verb – Set BEEP Generator (Verb ID= 70Ah)..........................................................................68
Table 73. Verb – Get GPIO Data (Verb ID= F15h) ..................................................................................68
Table 74. Verb – Set GPIO Data (Verb ID= 715h) ...................................................................................69
Table 75. Verb – Get GPIO Enable Mask (Verb ID= F16h).....................................................................69
Table 76. Verb – Set GPIO Enable Mask (Verb ID=716h).......................................................................70
Table 77. Verb – Get GPIO Direction (Verb ID=F17h)............................................................................70
Table 78. Verb – Set GPIO Direction (Verb ID=717h).............................................................................71
Table 79. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................71
Table 80. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)...................................72
Table 81. Verb – Function Reset (Verb ID=7FFh)....................................................................................72
Table 82. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)........................73
Table 83. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................74
Table 84. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)........................................76
Table 85. Verb – Set Subsystem ID [31:0] (Verb ID=723h, 722h, 721h, 720h).......................................76
Table 86. Absolute Maximum Ratings .....................................................................................................77
Table 87. Threshold Voltage .....................................................................................................................77
Table 88. Digital Filter Characteristics.....................................................................................................78
Table 89. S/PDIF Input/Output Characteristics........................................................................................78
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Table 90. Link Reset and Initialization Timing ........................................................................................79
Table 91. Link Timing Parameters at the Codec.......................................................................................80
Table 92. S/PDIF Output and Input Timing..............................................................................................81
Table 93. Analog Performance .................................................................................................................82
Table 94. Standby Mode ...........................................................................................................................86
Table 95. Volume Code Corresponding to DC Level at Pin 33................................................................87
Table 96. Ordering Information................................................................................................................90
List of Figures
Figure 1. Block Diagram ..........................................................................................................................4
Figure 2. Analog Input/Output Unit .........................................................................................................5
Figure 3. Pin Assignments........................................................................................................................6
Figure 4. HDA Link Protocol ...................................................................................................................9
Figure 5. Bit Timing ...............................................................................................................................10
Figure 6. Signaling Topology .................................................................................................................11
Figure 7. SDO Outbound Frame.............................................................................................................12
Figure 8. SDO Stream Tag is Indicated in SYNC ..................................................................................12
Figure 9. Striped Stream on Multiple SDOs...........................................................................................13
Figure 10. SDI Inbound Stream................................................................................................................14
Figure 11. SDI Stream Tag and Data ........................................................................................................14
Figure 12. Codec Transmits Data Over Multiple SDIs.............................................................................15
Figure 13. Link Reset Timing...................................................................................................................19
Figure 14. Codec Initialization Sequence.................................................................................................20
Figure 15. Link Reset and Initialization Timing.......................................................................................79
Figure 16. Link Signals Timing................................................................................................................80
Figure 17. Output and Input Timing.........................................................................................................81
Figure 18. Filter Connection.....................................................................................................................83
Figure 19. Front Panel Header Connection ..............................................................................................84
Figure 20. Jack Connection on Rear Panel...............................................................................................85
Figure 21. S/PDIF Input/Output Connection............................................................................................85
Figure 22. GPI Volume Control Implementation......................................................................................86
Figure 23. Volume Control by External Variable Resistor .......................................................................87
Figure 24. Digital Microphone Implementation-1....................................................................................88
Figure 25. Digital Microphone Implementation-2....................................................................................88
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1. General Description
The ALC885 is a high-performance 7.1+2 Channel High Definition Audio Codec with advanced lossless
content protection technology that protects pre-recorded content while still allowing full-rate audio
enjoyment from DVD audio, Blu-ray DVD, or HD DVD discs.
The ALC885 provides ten DAC channels that simultaneously support 7.1 sound playback, plus 2
channels of independent stereo sound output (multiple streaming) through the front panel stereo outputs.
Three stereo ADCs are integrated and can support a microphone array with Acoustic Echo Cancellation
(AEC), Beam Forming (BF), and Noise Suppression (NS) technologies simultaneously.
All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched
depending on the connected device type.
Support for 16/20/24-bit S/PDIF input and output offers easy connection of PCs to high-quality consumer
electronic products such as digital decoders and speakers. The series incorporates Realtek proprietary
converter technology to achieve 106dB Signal-to-Noise ratio (SNR) playback quality and 101dB SNR
recording quality, and is designed for Windows Vista premium desktop and laptop systems.
The ALC885 supports host/soft audio from the Intel ICH series chipset, and also from any other HDA
compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional
audio, and optional Dolby® Master Studio™, the ALC885 provides an excellent home entertainment
package and game experience for PC users.
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2. Features
2.1. Hardware Features
High-performance DACs with 106dB dynamic range (A-Weight), ADCs with 101dB dynamic range
(A-Weight)
Meets performance requirements for Microsoft WLP 3.0 Premium desktop and mobile PCs
Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of
concurrent independent stereo sound output (multiple streaming) through the front panel output
There stereo ADCs support 16/20/24-bit PCM format, one for stereo microphone, one for legacy
mixer recording
All DACs and ADCs supports 44.1k/48k/96k/192kHz sample rate
16/20/24-bit S/PDIF-OUT supports 44.1k/48k/96k/192kHz sample rate
16/20/24-bit S/PDIF-IN supports 44.1k/48k/96k/192kHz sample rate
Supports 444.1k/48k/96k/192kHz ADAT® digital output
Up to four channels of microphone array input are supported for AEC/BF application
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.75V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
Supports legacy analog mixer architecture
Software selectable boost gain (+10/+20/+30dB) for analog microphone input
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for each re-tasking jack
Two GPIOs (General Purpose Input and Output) for customized applications, and digital GPI
Volume Control
Supports anti-pop mode when analog power AVDD is on and digital power is off.
Supports stereo digital microphone interface for improved voice quality
Content Protection for Full Rate lossless Audio content playback (with selected versions of
WinDVD/PowerDVD)
48-pin LQFP ‘Green’ package
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2.2. Software Features
Compatible with Windows Vista Premium (complies with Microsoft WLP 3.0 specifications)
WaveRT-based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio
7.1+2 channel multi-streaming enables concurrent gaming/VoIP
Friendly user interface for 2-foot or 10-foot remote control applications
Emulation of 26 sound environments to enhance gaming experience
10-Band Software Equalizer
Voice Cancellation and Key Shifting in Karaoke mode
Realtek Media Player
Enhanced Configuration Panel to improve user experience
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
ALC885M-GRfeatures Dolby® Master Studio™ (optional software feature)
3. System Applications
Desktop multimedia PCs
Laptop PCs
Information appliances (IA) e.g., set-top box
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4. Block Diagram
Figure 1. Block Diagram
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Datasheet
4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IOs.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
EN_OBUF
EN_IBUF
Figure 2. Analog Input/Output Unit
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5. Pin Assignments
36 35 34 33 32 31 30 29 28 27 26 25
36 35 34 33 32 31 30 29 28 27 26 25
PORT-C-R
24
23
22
21
20
19
18
17
16
15
14
13
24
23
22
21
20
19
18
17
16
15
14
13
LINE1-R
LINE1-L
MIC1-R
MIC1-L
CD-R
CD-GND
CD-L
MIC2-R
MIC2-L
LINE2-R
LINE2-L
Sense A
37
38
39
40
41
42
43
44
45
46
47
48
NC
AVDD2
PORT-A-L
JDREF
PORT-A-L
AVSS2
37
38
39
40
41
42
43
44
45
46
47
48
NC
AVDD2
SURR-L
JDREF
SURR-R
AVSS2
PORT-C-L
PORT-B-R
PORT-B-L
CD-R
CD-GND
CD-L
ALC885
ALC885
PORT-G-L
PORT-G-R
PORT-H-L
PORT-H-R
SPDIFI/EAPD
SPDIFO
CENTER
LFE
SIDESURR-L
SIDESURR-R
SPDIFI/EAPD
SPDIFO
PORT-F-R
PORT-F-L
PORT-E-R
PORT-E-L
Sense A
LLLLLLL
TXXXV
LLLLLLL
TXXXV
1
2
3
4
5
6
7
8
9
10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘V’.
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6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Type Pin Description Characteristic Definition
Name
RESET#
I
I
11 H/W reset
Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDDIO
SYNC
10 Sample Sync (48kHz)
BITCLK
I
6
5
8
24MHz Bit clock input
Serial TDM data input
Serial TDM data output
SDATA-OUT
SDATA-IN
SPDIF-IN/
EAPD*1
I
O
Vt=0.5*DVDDIO, VOH=DVDDIO, VOL=DVSS
VIL=1.45V, VIH=1.85V /
I/O 47 Digital S/PDIF Input /
Signal to power down ext. amp /
48 Digital S/PDIF output and ADAT
V
OH=DVDD, VOL=DVSS
SPDIF-OUT*2
O
Output has 12mA@75Ω driving capability
VOH=DVDD, VOL=DVSS
Output
GPIO0 /
DMIC-CLK
GPIO1 /
I/O
I/O
2
3
General Purpose Input/Output 0 Input: Vt=(2/3)*DVDD
Clock output to digital MIC
Output: VOH=DVDD, VOL=DVSS
General Purpose Input/Output 1 Input: Vt=(2/3)*DVDD
Serial data in from digital MIC Output: VOH=DVDD, VOL=DVSS
Total: 9 Pins
DMIC-DATA
*1: Pin 47 can be configured to support secondary digital mic input (DMIC-R). It is supported via a customized
Realtek driver
*2: Pin 48 can output ADAT digital audio output. The function is enabled via a customized Realtek driver.
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Name
Type Pin Description
Characteristic Definition
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14 2nd line input left channel
15 2nd line input right channel
Analog input/output, default is input (JACK-E)
Analog input/output, default is input (JACK -E)
16
2
nd stereo microphone input Analog input/output, default is input (JACK -F)
left channel
nd stereo microphone input Analog input/output, default is input (JACK -F)
right channel
MIC2-R
IO
17
2
CD-L
I
I
18 CD input left channel
19 CD input reference ground
20 CD input right channel
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input/output, default is input (JACK -B)
CD-G
CD-R
MIC1-L
I
IO
21 1st stereo microphone input
left channel
MIC1-R
IO
22 1st stereo microphone input
right channel
23 1st line input left channel
24 1st line input right channel
Analog input/output, default is input (JACK -B)
LINE1-L
LINE1-R
IO
IO
Analog input/output, default is input (JACK -C)
Analog input/output, default is input (JACK -C)
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Name
Type Pin Description
Characteristic Definition
PCBEEP
FRONT-L
FRONT-R
SURR -L
SURR -R
CENTER
LFE
I
IO
IO
IO
IO
O
O
O
O
I
12 External PCBEEP input
Analog input, 1.6Vrms of full scale input
Analog output (JACK -D)
Analog output (JACK -D)
Analog output (JACK -A)
Analog output (JACK -A)
Analog output (JACK -G)
Analog output (JACK -G)
Analog output (JACK -H)
Analog output (JACK -H)
Jack resistor network input 1
Jack resistor network input 2
Total: 22 Pins
35 Front output left channel
36 Front output right channel
39 Surround out left channel
41 Surround out right channel
43 Center output
44 Low Frequency output
45 Side output left channel
46 Side output right channel
13 Jack Detect pin l
SIDESURR -L
SIDESURR -R
Sense A
Sense B
I
34 Jack Detect pin 2
6.3. Filter/Reference/NC
Table 3. Filter/Reference
Name
Type Pin Description
Characteristic Definition
VREF
-
27 2.5V Reference voltage
28 Bias voltage for MIC1 jack
10uf capacitor to analog ground
2.5V/3.75V reference voltage
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
NC
O
O
O
O
O
-
29 Bias voltage for LINE1 jack 2.5V/3.75V reference voltage
30 Bias voltage for MIC2 jack 2.5V/3.75V reference voltage
31 Bias voltage for LINE2 jack 2.5V/3.75V reference voltage
32 Bias voltage for MIC1 jack
37 Not Connected
2.5V/3.75V reference voltage
JDREF
-
40 Reference resistor for Jack
detection
20K, 1% external resistor to analog ground
Total: 8 Pins
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin Description
Characteristic Definition
AVDD1
AVSS1
AVDD2
AVSS2
DVDD
DVSS
I
I
I
I
I
I
I
I
25 Analog VDD
26 Analog GND
38 Analog VDD
42 Analog GND
Analog power for mixer and amplifier
Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital power for core
1
4
9
7
Digital VDD
Digital GND
Digital VDD
Digital GND
Digital ground for core
DVDD-IO
DVSS
Digital IO power for HDA bus (1.5V~3.3V)
Digital ground for HDA bus
Total: 8 Pins
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Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
T
=20.833 usec (48kHz)
frame_sync
Previous Frame
BCLK
Next Frame
Frame SYNC= 8 BCLK
Stream 'A' Tag
(Here 'A' = 5)
Stream 'B' Tag
(Here 'B' = 6)
SYNC
SDO
SDI
Command Stream
(40-bit data)
Stream 'B' Data
Stream 'A' Data
Stream
'C' Tag
Stream 'C' Data
Response Stream
(36-bit data)
(n bytes + 10-bit data)
RST#
Figure 4. HDA Link Protocol
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Datasheet
7.1.1. Signal Definitions
Table 5. Link Signal Definitions
Item
Description
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs
BCLK
SYNC
48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported
SDI
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs
Table 6. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Type for Controller Description
Output
Output
Global 24.0MHz bit clock
Controller
Global 48kHz Frame Sync and outbound tag signal
Serial data output from the controller
Controller
Output
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller
RST#
Controller
Output
Global active low reset signal
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
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7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0, and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 12 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC885 is
designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 6. Signaling Topology
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7.2. Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 7. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 8. SDO Stream Tag is Indicated in SYNC
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7.2.2. Outbound Frame – Multiple SDOs
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
the data stream is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 9. Striped Stream on Multiple SDOs
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7.2.3. Inbound Frame – Single SDI
An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at
each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 10. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 11. SDI Stream Tag and Data
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7.2.4. Inbound Frame – Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Response Stream Tag B
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 16, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 16, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
“12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)”
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
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Datasheet
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 9, page 17).
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
11.025kHz (1 sample block every 4 frames)
22.05kHz (1 sample block every 2 frames)
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 8. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame
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Table 9. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
88.2kHz
174.4kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
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Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1. Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 13, page 19, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
the end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
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Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Driven Low
Driven Low
Pulled Low
2
8
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 13. Link Reset Timing
7.3.2. Codec Reset
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
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7.3.3. Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Controller
Codec Drives SDIx
Turnaround
(477 BCLK
Max.)
Turnaround
(477 BCLK
Max.)
Figure 14. Codec Initialization Sequence
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7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs; one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 10. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 11. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
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Table 12. Verbs Supported by the ALC885 (Y=Supported)
Supported Verb
Get parameter
F00
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Connection Select
F01 701
Get Connection List
Entry
F02
Y
Y
Y
Processing State
Coefficient Index
Processing Coefficient
Amplifier Gain/Mute
Stream Format
F03 703
D-
C-
B-
A-
5-
4-
3-
2-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Digital Converter 1
Digital Converter 2
Power State
F0D 70D
F0D 70E
F05 705
F06 706
F04 704
F07 707
F08 708
F09 709
F0C 70C
F10 710
Y
Channel / Stream ID
SDI Select
Y
Y
Pin Widget Control
Unsolicited Enable
Pin Sense
Y
Y
Y
Y
Y
EAPD / BTL Enable
-
-
All GPIO Control
F1A 71A
Beep Generator Control F0A 70A
Y
Y
Volume Knob Control
Subsystem ID, Byte 0
Subsystem ID, Byte 1
Subsystem ID, Byte 2
Subsystem ID, Byte 3
F0F 70F
F20 720
F20 721
F20 722
F20 723
Y
Y
Y
Y
Config Default, Byte 0 F1C 71C
Config Default, Byte 1 F1C 71D
Config Default, Byte 2 F1C 71E
Config Default, Byte 3 F1C 71F
Y
Y
Y
Y
RESET
7FF
Y
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Table 13. Parameters in the ALC885 (Y=Supported)
Supported Parameter
Vendor ID
Revision ID
00
02
04
05
08
Y
Y
Y
Subordinate Node Count
Function Group Type
Y
Y
Y
Audio Function Group
Capabilities
Audio Widget Capabilities
Sample Size, Rate
09
0A
0B
0C
0D
12
0E
0F
10
11
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Stream Formats
Pin Capabilities
Input Amp Capabilities
Output Amp Capabilities
Connection List Length
Supported Power States
Processing Capabilities
GPI/O Count
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Volume Knob Capabilities
13
Y
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7.4.2. Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 14. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 15. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Response
Reserved
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower
32-bit field. Bit-35 is a ‘Valid’bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that
an unsolicited response was sent.
7.5. Power Management
The ALC885 does not support Wake-Up events when in low power mode. All power management state
changes in widgets are driven by software. Table 16 shows the System Power State Definitions.
In the ALC885, all the widgets, including output/input converters, support power control. Software may
have various power states depending on system configuration.
Table 17 indicates those nodes that support power management. To simplify power control, software can
configure whole codec power states through the audio function (NID=01h). Output converters (DACs)
and input converters (ADCs) have no individual power control to supply fine-grained power control.
Table 16. System Power State Definitions
Power States Definitions
D0
D1
All power on. Individual DACs and ADCs can be powered up or down as required
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off)
D3 (Hot)
Power still supplied. The codec stops the internal clock. State is maintained
All power removed. State lost
D3 (Cold)
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Table 17. Power Controls in NID 01h
Item
Audio Function
(NID=01h)
Description
D0
D1
Normal
PD
D2
Normal
PD
D3
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Link Reset
PD
LINK Response
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
FRONT DAC (NID 02h)
SURR DAC (NID 03h)
CEN/LFE DAC (NID 04h)
SIDESURR DAC (NID 05h)
FOUT DAC (NID 25h)
MIC ADC (NID07h)
LINE ADC (NID08h)
MIX ADC (NID 09h)
All Headphone Drivers
All Mixers
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down
Table 18. Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with
pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of
‘Link Reset Entry’ and ‘Link Reset Exit’ sequences are supported. All
states are maintained if DVDD is supplied
FRONT DAC powered down
SURR DAC powered down
CEN/LFE DAC powered down
SIDESURR DAC powered down
FOUT DAC powered down
LINE ADC powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
MIX ADC powered down
MIC ADC powered down
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
Analog block and digital filter are powered down. Data on SDATA-IN is
quiet
Headphone Driver powered down
Mixers powered down
All headphone drivers are powered down
All internal mixer widgets are powered down. The DC reference and
VREFOUTx at individual pin complexes are still alive
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
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8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC885. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget.
Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 21, for detailed information about supported parameters.
Table 19. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 20. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
31:16
15:0
Description
Vendor ID=10ECh (Realtek’s PCI vendor ID)
Device ID=0885h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC885 is fully
compliant. Response=0x1
19:16
15:8
7:0
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC885 is fully
compliant. Response=0x0
Revision ID. The vendor’s revision number
00h is for the first silicon version (A version), 01h is for the second version (B version), etc.
Stepping ID. The vendor’s stepping number within the given Revision ID
Note: The Root Node (NID=00h in the ALC885) supports this parameter.
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8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h,
Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 22. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
23:16
Reserved. Read as 0’s
Starting Node Number
The starting node number in the sequential widgets
Reserved. Read as 0’s
15:8
7:0
Total Number of Nodes
For a root node, the total number of function groups in the root node
For a function group, the total number of widget nodes in the function group
Description
Bits Æ
Reserved
Starting Node
Bit [23:16]
01h
Reserved
Total Fun/Widgets
Bit [31:24]
Bit [15:8]
Bit [7:0]
01h
Root Node
NID=00h
NID=01h
-
-
-
-
Audio Function
Others
02h
25h
Not supported (returns 00000000h)
8.1.4. Parameter – Function Group Type (Verb ID=F00h,
Parameter ID=05h)
Table 23. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
31:9
8
Description
Reserved. Read as 0’s
UnSol Capable. Read as 1.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
Function Group Type. Read as 01h.
00h: Reserved
7:0
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
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8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h,
Parameter ID=08h)
Table 24. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
31:17
16
Description
Reserved. Read as 0’s
Beep Generator, read as 1.
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group
15:12
11:8
7:4
Reserved. Read as 0’s
Input Delay. Read as 0xF.
Reserved. Read as 0’s
3:0
Output Delay. Read as 0xF.
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h,
Parameter ID=09h)
Table 25. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
Widget Type
0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex
5h: Power Widget 6h: Volume Knob Widget
7h~Eh: Reserved
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets
Reserved. Read as 0’s
Power Control
0: Power state control is not supported on this widget
1: Power state is supported on this widget
Digital
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
ConnList. Connection List
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget
9
8
7
6
0: No processing control
1: Processing control is supported
5
4
Reserved. Read as 0
Format Override
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Codec Response Format
Bit Description
3
2
1
0
AmpParOvr, AMP Param Override
OutAmpPre. Out AMP Present
InAmpPre. In AMP Present
Stereo
0: Mono Widget
1: Stereo Widget
Table 26. Widget Capability Support
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Bits Æ
Root
Node
NID=00h
Not supported (returns 00000000h)
Not supported (returns 00000000h)
Audio
Funct- NID=01h
ion
NID=02h
NID=03h
-
-
-
-
-
0h
0
0
0
0
0
-
-
-
-
-
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
-
-
-
-
-
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
0h
0h
0h
0h
NID=04h
Output
NID=05h
Conv-
NID=25h
erters
NID=06h
-
0h
0
-
0 0 1 0 0 0
-
1 0 0 0 1
(S/PDIF-
OUT)
NID=07h
-
-
-
1h
1h
1h
0
0
0
-
-
-
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
-
-
-
1 1 0 1 1
1 1 0 1 1
1 1 0 1 1
NID=08h
Input
NID=09h
Conv-
NID=0Ah
erters
-
1h
0
-
0 0 1 1 1 0
-
1 0 0 0 1
(S/PDIF-I
N)
NID=0Bh
NID=0Ch
NID=0Dh
-
-
-
-
-
-
-
-
-
2h
2h
2h
2h
2h
2h
2h
2h
2h
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
0 0 0 1 0 0
-
-
-
-
-
-
-
-
-
0 1 0 1 1
0 1 1 1 1
0 1 1 1 1
0 1 1 1 1
0 1 1 1 1
0 1 1 1 1
0 1 0 1 1
0 1 0 1 1
0 1 0 1 1
NID=0Eh
Mixer
NID=26h
(Sum)
NID=0Fh
NID=22h
NID=23h
NID=24h
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3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
Bits Æ
NID=14h
(FRONT)
NID=15h
(SURR)
-
-
4h
0
0
-
-
0 0 0 1 1 0
0 0 0 1 1 0
-
0 1 1 1 1
0 1 1 1 1
4h
4h
-
-
NID=16h
(CEN/LF
E)
-
-
0
0
-
-
0 0 0 1 1 0
0 1 1 1 1
NID=17h
(SIDESU
RR)
4h
0 0 0 1 1 0
-
0 1 1 1 1
NID=18h
(MIC1)
-
-
-
-
-
-
4h
4h
4h
4h
4h
4h
0
0
0
0
0
0
-
-
-
-
-
-
0 0 0 1 1 0
0 0 0 1 1 0
0 0 0 1 1 0
0 0 0 1 1 0
0 0 0 0 0 0
0 0 0 0 0 0
-
-
-
-
-
-
0 1 1 1 1
0 1 1 1 1
0 1 1 1 1
0 1 1 1 1
0 0 0 0 1
0 0 0 0 0
NID=19h
(MIC2)
Pin
Comp-
lex
NID=1Ah
(LINE1)
NID=1Bh
(LINE2)
NID=1Ch
(CD-IN)
NID=1Dh
(BEEP)
NID=1Eh
-
-
-
4h
4h
6h
0
0
-
-
-
-
0 0 1 1 0 0
0 0 1 0 0 0
0 0 0 0 1 0
-
-
-
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
(S/PDIF-
OUT)
NID=1Fh
(S/PDIF-
IN)
Vol-
ume
NID=21h
Knob
NID=20h
-
-
Fh
Fh
-
-
-
-
0 0 0 0 0 1
0 0 0 0 0 0
-
-
0 0 0 0 0
0 0 0 0 0
Vendor
Define
NID=10h
~13h
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8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h,
Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own
parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 27. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s
B32. 32-bit audio format support
0: Not supported
1: Supported
19
18
17
16
B24. 24-bit audio format support
0: Not supported
1: Supported
B20. 20-bit audio format support
0: Not supported
1: Supported
B16. 16-bit audio format support
0: Not supported
1: Supported
B8. 24-bit audio format support
0: Not supported
1: Supported
15:12
11
Reserved. Read as 0’s
R12. 384kHz (=8*48kHz) rate support
0: Not supported
1: Supported
10
9
R11. 192kHz (=4*48kHz) rate support
0: Not supported
1: Supported
R10. 176.4kHz (=4*44.1kHz) rate support
0: Not supported
1: Supported
8
R9. 96kHz (=2*48kHz) rate support
0: Not supported
1: Supported
7
R8. 88.2kHz (=2*44.1kHz) rate support
0: Not supported
1: Supported
6
R7. 48kHz rate support
0: Not supported
1: Supported
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Codec Response Format
Bit
Description
5
R6. 44.1kHz rate support
0: Not supported
1: Supported
4
3
2
1
0
R5. 32kHz (=2/3*48kHz) rate support
0: Not supported
1: Supported
R4. 22.05kHz (=1/2*44.1kHz) rate support
0: Not supported
1: Supported
R3. 16kHz (=1/3*48kHz) rate support
0: Not supported
1: Supported
R2. 11.025kHz (=1/4*44.1kHz) rate support
0: Not supported
1: Supported
R1. 8kHz (=1/6*48kHz) rate support
0: Not supported
1: Supported
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Table 28. Sample Rate and PCM Size Supported in Each Converter
B B B B
3 2 2 1
2 4 0 6
R R R
Reserved 1 1 1
2 1 0
B
8
R R R R R R R R R
9 8 7 6 5 4 3 2 1
Description
Reserved
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8 7 6 5 4 3 2 1 0
Bits Æ
Audio
Funct- NID=01h
ion
-
0 1 1 1 0
-
0 1 0 1 0 1 1 0 0 0 0 0
NID=02h
-
-
-
0 1 1 1 0
0 1 1 1 0
0 1 1 1 0
-
-
-
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
(Front
DAC)
NID=03h
(Surr DAC)
NID=04h
(Cen/Lfe
Output
DAC)
Conv-
NID=05h
erters
(SideSurr
DAC)
-
-
-
-
-
0 1 1 1 0
0 1 1 1 0
1 1 1 1 0
0 1 1 1 0
0 1 1 1 0
-
-
-
-
-
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 1 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
NID=25h
(Fout DAC)
NID=06h
(S/PDIF-
OUT)
NID=07h
(MIC ADC)
NID=08h
Input
Conv-
erters
(LINE
ADC)
NID=09h
(MIX ADC)
NID=0Ah
-
-
0 1 1 1 0
1 1 1 1 0
-
-
0 1 0 1 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 0 0 0 0 0
(S/PDIF-IN)
Others
Not supported (returns 00000000h)
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ALC885 Series
Datasheet
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h,
Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 29. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s
AC3
0: Not supported
1: Supported
Float32
0: Not supported
1: Supported
PCM
1
0
0: Not supported
1: Supported
Note: Input converters and output converters support this parameter.
Table 30. Stream Format Supported in Each Converter
Input converters and output converters support this parameter.
Description
Reserved
AC3 Float32 PCM
Bit [2] Bit [1] Bit [0]
Bits Æ
Bit [31:3]
Audio Function
Output Converters
Input Converters
Others
NID=01h
-
-
-
0
0
0
0
0
0
1
1
1
NID=02h~06h, 25h
NID=07h~0Ah
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
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ALC885 Series
Datasheet
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 31. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s
VREF Control Capability
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
L-R Swap. Indicates the capability of swapping the left and right
Balanced I/O Pin
‘1’ indicates this pin complex has balanced pins
Input Capable
‘1’ indicates this pin complex supports input
Output Capable
‘1’ indicates this pin complex supports output
Headphone Drive Capable
‘1’ indicates this pin complex has an amplifier to drive a headphone
Presence Detect Capable
‘1’ indicates this pin complex can detect whether there is anything plugged in
Trigger Required
‘1’ indicates whether a software trigger is required for an impedance measurement
Impedance Sense Capable
5
4
3
2
1
0
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.
7.1+2 Channel High-Performance HDA Codec
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ALC885 Series
Datasheet
Table 32. Pin Capabilities
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Bits Æ
31:17
0s
9 8
1 1
1 1
0 0
0 0
7
0
0
0
0
6
0
0
0
0
5
1
1
1
1
4
1
1
1
1
3
1
1
1
1
2
1
1
1
1
1
0
0
0
0
0
0
0
0
0
NID=14h (Front
Out)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
NID=15h (Surr
Out)
0s
NID=16h
(Cen/Lfe Out)
0s
NID=17h
(SideSurr Out)
0s
NID=18h (MIC1)
NID=19h (MIC2)
0s
0s
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1 1
1 1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
NID=1Ah
(LINE1)
Pin Complex
0s
0s
0s
0s
0s
0s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1 1
1 1
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NID=1Bh
(LINE2)
NID=1Ch
(CD-IN)
NID=1Dh
(BEEP-IN)
NID=1Eh (S/PDIF
Out)
NID=1Fh (S/PDIF
In)
Others
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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ALC885 Series
Datasheet
8.1.10. Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 33. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
15
Reserved. Read as 0
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7
Reserved. Read as 0
Offset
6:0
Indicates which step is 0dB
Table 34. Output Amplifier Capabilities
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6 5 4 3 2 1 0
Bits Æ
NID=
07h
(MIC
ADC)
0010000b
(=16 means
0dB)
0000011b
(=1.0dB per step)
0101110b
(-16.0~30dB in 47 step)
1
1
1
-
-
-
-
-
-
-
NID=
08h
(LINE
ADC)
Input
Conv-
erters
0010000b
(=16 means
0dB)
0000011b
(=1.0dB per step)
0101110b
(-16.0~30dB in 47 step)
-
-
NID=
09h
(MIX
ADC)
0010000b
(=16 means
0dB)
0000011b
(=1.0dB per step)
0101110b
(-16.0~30dB in 47 step)
0010111b
(=23d means
0dB)
Mixer
(Sum)
0000101b
(=1.5dB per step)
NID=
0Bh
0011111b
(-34.5~12dB in 32 step)
1
1
-
-
-
-
-
-
NID=
0Ch
0000000b
0000000b
0000000b
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ALC885 Series
Datasheet
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6 5 4 3 2 1 0
Bits Æ
NID=
0Dh
1
1
1
1
1
1
1
0
-
-
-
-
-
-
-
-
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0100111b
-
-
-
-
-
-
-
-
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0000011b
-
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
0000000b
NID=
0Eh
-
-
-
-
-
-
-
NID=
0Fh
NID=
26h
NID=
22h
NID=
23h
NID=
24h
Pin
Comp-
lex
NID=
14h
(=10dB per step)
(0~30dB in 4 step)
(=0d means
0dB)
NID=
15h
0
0
0
0
0
0
0
-
-
-
-
-
-
-
0100111b
(=10dB per step)
-
-
-
-
-
-
-
0000011b
(0~30dB in 4 step)
-
-
-
-
-
-
-
0000000b
(=0d means
0dB)
NID=
16h
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
NID=
17h
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
NID=
18h
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
NID=
19h
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
NID=
1Ah
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
NID=
1Bh
0100111b
(=10dB per step)
0000011b
(0~30dB in 4 step)
0000000b
(=0d means
0dB)
Others
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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ALC885 Series
Datasheet
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output
Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 35. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
Reserved. Read as 0
15
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
Reserved. Read as 0
7
6:0
Offset. Indicates which step is 0dB
Table 36. Input Amplifier Capabilities
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6 5 4 3 2 1 0
Bits Æ
Mixer NID=0Ch
(Sum)
0
-
0000011b
(=1.0dB per step)
-
1000000b
-
1000000b
(=64 means
0dB)
(-64~0dB in 65 step)
NID=0Dh
NID=0Eh
NID=0Fh
NID=26h
0
0
0
0
1
-
-
-
-
-
0000011b
0000011b
0000011b
0000011b
0000000b
-
-
-
-
-
1000000b
1000000b
1000000b
1000000b
0000000b
-
-
-
-
-
1000000b
1000000b
1000000b
1000000b
0000000b
NID=14h
(FRONT)
NID=15h
(SURR)
Pin
Com-
plex
1
1
1
1
-
-
-
-
0000000b
0000000b
0000000b
0000000b
-
-
-
-
0000000b
0000000b
0000000b
0000000b
-
-
-
-
0000000b
0000000b
0000000b
0000000b
NID=16h
(CEN/LFE)
NID=17h
(SIDESURR)
NID=18h
(MIC1)
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ALC885 Series
Datasheet
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6 5 4 3 2 1 0
Bits Æ
NID=19h
(MIC2)
1
1
1
-
-
-
0000000b
0000000b
0000000b
-
-
-
0000000b
0000000b
0000000b
-
0000000b
0000000b
0000000b
NID=1Ah
(LINE1)
NID=1Bh
(LINE2)
-
-
Others
Not supported (returns 00000000h)
8.1.12. Parameter – Connect List Length (Verb ID=F00h,
Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 37. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0
Short Form
0: Short Form
1: Long Form
6:0
Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (not a MUX widget)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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ALC885 Series
Datasheet
Table 38. Connection List Length for Widget Input Source
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2 1 0
Bits Æ
NID=07h
NID=08h
NID=09h
NID=0Ah
NID=0Bh
NID=0Ch
NID=0Dh
NID=0Eh
NID=0Fh
NID=26h
NID=22h
NID=23h
NID=24h
NID=14h
NID=15h
NID=16h
NID=17h
NID=18h
NID=19h
NID=1Ah
NID=1Bh
NID=1Ch
(CD-IN)
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
A
2
2
2
2
2
B
B
B
5
5
5
5
5
5
5
5
Input
Conv-
erters
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Mixer
(Sum)
Pin
Com-
plex
-
-
0
0
0
0
NID=1Dh
(BEEP-IN)
NID=1Eh
-
-
0
0
1
0
(S/PDIF-O
UT)
NID=1Fh
(S/PDIF-IN
)
Others
NID
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
41
Rev. 1.1
ALC885 Series
Datasheet
8.1.13. Parameter – Supported Power States (Verb ID=F00h,
Parameter ID=0Fh)
Table 39. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s
D3Sup
1: Power state D3 is supported
D2Sup
1: Power state D2 is supported
D1Sup
1: Power state D1 is supported
D0Sup
2
1
0
1: Power state D0 is supported
Table 40. Power State Supported in Each Widget
Description
Bits Æ
Reserved
Bit [31:3]
D3Sup D2Sup D1Sup D0Sup
Bit [3] Bit [2] Bit [1] Bit [0]
Rood Node
Audio Function
Output Converters
NID=00h
Not supported (returns 00000000h)
NID=01h
-
-
-
-
-
-
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
NID=02h~05h, 25h
NID=06h
Input Converters
NID=07h~09h
NID=0Ah
Mixer (Sum)
Pin Complex
NID=0Bh~0Fh,
22h~24h, 26h
NID=14h~1Fh
-
-
0
0
0
0
0
0
1
1
Vendor, Volume
Knob
NID=20h~21h,
10h~13h
7.1+2 Channel High-Performance HDA Codec
With Content Protection
42
Rev. 1.1
ALC885 Series
Datasheet
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h,
Parameter ID=10h)
Table 41. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s
NumCoeff. Number of Coefficient
Reserved. Read as 0’s
0
Benign
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
Table 42. Coefficient Registers Supported in Realtek Defined Widget
Description
Bits Æ
Reserved
Bit [31:3]
-
NumCoeff Reserved Benign
Bit [15:8]
Bit [7:1]
Bit [0]
Vendor Defined
Others
NID=20h
11h
-
0
Not supported (returns 00000000h)
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h,
Parameter ID=11h)
Table 43. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0
The ALC885 does not support GPIO wake up function
GPIUnsol=1
30
The ALC885 supports GPIO unsolicited response
Reserved. Read as 0’s
29:24
23:16
NumGPIs=00h
No GPI pin is supported
NumGPOs=00h
No GPO pin is supported
NumGPIOs=02h
15:8
7:0
Three GPIO pins are supported
7.1+2 Channel High-Performance HDA Codec
With Content Protection
43
Rev. 1.1
ALC885 Series
Datasheet
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h,
Parameter ID=13h)
Table 44. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
31:8
7
Description
Reserved. Read as 0s
Delta. Read as 0
0: Software will not modify the volume in Volume Control Knob
1: Software can write a base volume to the Volume Control Knob
NumSteps
6:0
The total number of steps in the range of the Volume Control Knob (NID=21h), response=0x20.
Note: The Volume Control knob (NID=21h) supports this parameter.
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 45. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H (NID=14h~1Bh)
Bit
31:8
7:0
Description
0’s
Connection Index current settings (Default value is 00h)
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Dh
02h: Sum Widget NID=0Eh
03h: Sum Widget NID=0Fh
04h: Sum Widget NID=26h
Other: Reserved
Codec Response for Digital Pin S/PDIF-OUT (NID=1Eh)
Bit
31:8
7:0
Description
0’s
Connection Index current settings (Default value is 00h)
00h: Digital Converter (S/PDIF-OUT) NID=06h
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
44
Rev. 1.1
ALC885 Series
Datasheet
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 46. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=701h
Select Index [7:0]
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 47. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=07h (MIC ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 24h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 23h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 22h (Sum Widget) for N=0~3
Returns 00h for N>3
7.1+2 Channel High-Performance HDA Codec
With Content Protection
45
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ALC885 Series
Datasheet
Codec Response for NID=0Ah (S/PDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16
15:8
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 00h for N>7
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 02h (Front DAC) for N=0~3
Returns 00h for N>3
7.1+2 Channel High-Performance HDA Codec
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ALC885 Series
Datasheet
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 03h (Surround DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Eh (Cen/LFE Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 04h (Cen/LFE DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Fh (Side-Surr Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 05h (Front DAC) for N=0~3
Returns 00h for N>3
7.1+2 Channel High-Performance HDA Codec
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ALC885 Series
Datasheet
Codec Response for NID=26h (Fout Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 25h (Fout1 DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=14h~1Bh (Port-A to port-H)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3
Returns 00h for n>3
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3
Returns 00h for N>3
Connection List Entry (N+1)
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3
Returns 26h (Sum Widget NID=26h) for N=4~7
Returns 00h for N>7
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2)
Returns 0000h
15:8
7:0
Connection List Entry (N+1)
Returns 00h
Connection List Entry (N)
Returns 06h (S/PDIF-OUT converter) for N=0~3
Returns 00h for N>3
7.1+2 Channel High-Performance HDA Codec
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Rev. 1.1
ALC885 Series
Datasheet
Codec Response for NID= 22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 0Bh (Sum Widget) for N=8~11
Returns 00h for N>11
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 48. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Response [31:0]
32-bit response
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F03h
0’s
Codec Response for All NID
Bit
Description
Not supported (returns 00000000h)
31:0
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.6. Verb – Set Processing State (Verb ID=703h)
Table 49. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 50. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
CAd=X
Node ID=20h
Verb ID=Dh
0’s
Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Coefficient Index
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 51. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
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Rev. 1.1
ALC885 Series
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 52. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Response [31:0]
Processing Coefficient [15:0]
Bit [31:28]
Bit [27:20]
Node ID=20h
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ch
0’s
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Processing Coefficient
Codec Response for Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 53. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
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Rev. 1.1
ALC885 Series
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 54. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
Reserved. Read as 0.
14
13
Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
Reserved. Read as 0’s
12:4
3:0
Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for 07h (MIC ADC), 08h (LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Gain [6:0]. 7-bit step value (0~46) specifying the
volume from –16dB~+30dB in 1.0dB steps
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0’s (No Output Amplifier Mute)
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the
volume from –34.5dB~+12dB in 1.5dB steps
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0’s (No Output Amplifier Mute)
7.1+2 Channel High-Performance HDA Codec
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Rev. 1.1
ALC885 Series
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, Cen/LFE, SIDESURR Sum)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain. Input Amplifier Mute, 0: Unmute, 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Mute)
Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0 (No Input Amplifier Gain)
6:0
Bit-15 is 1 in ‘Get Amplifier Gain. Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the
volume from –64dB~0dB in 1.0dB steps
Codec Response for NID=14h~1Bh (Pin Complex: Front/Surr/CenLFE/SIDESURR/MIC1/MIC2/LINE1/LINE2)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain. Output Amplifier Mute, 0:Unmute, 1:Mute
(NID=14h~1Bh,Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain. Read as 0’s
Bit-15 is 1 in ‘Get Amplifier Gain. Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 55. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp
‘1’ indicates output amplifier gain will be set
Set Input Amp
‘1’ indicates input amplifier gain will be set
Set Left Amp
14
13
‘1’ indicates left amplifier gain will be set
Set Right Amp
12
‘1’ indicates right amplifier gain will be set
Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is
not set
7
Mute
0: Unmute
1: Mute (-∞ gain)
6:0
Gain[6:0]
A 7-bit step value specifying the amplifier gain
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 56. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Codec Response Format
Response [31:0]
Bit[15:0] are converter format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
CAd=X
Verb ID=Ah
0’s
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT).
Codec Response for NID=07h~0Ah (Input Converters: MIC, LINE, MIX DAC, and S/PDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
The ALC885 does not support Divisor. Always read as 000b
Reserved. Read as 0.
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: reserved
3:0
Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels ….. 15: 16 channels
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
The output converter formats supported by the ALC885 are listed. It is software’s duty to set an applicable format.
BASE
MULT
DIV
BITS
Sample Rate
NID=02h (Front DAC)
NID=03h (Surr DAC)
NID=04h (Cen/Lfe DAC)
NID=05h (Side DAC)
NID=25h (Fout DAC)
NID=06h (S/PDIF-OUT)
0
000b, 001b, 011b
000b
001, 010b, 011b
48K, 96K,
192K
1
0
000b
000b
000b
001, 010b, 011b
001, 010b, 011b
44.1K
000b, 001b, 011b
48K, 96K,
192K
1
0
000b
000b
000b
001, 010b, 011b
001, 010b, 011b
44.1K
000b, 001b, 011b
48K, 96K,
192K
1
0
000b
000b
000b
001, 010b, 011b
001, 010b, 011b
44.1K
000b, 001b, 011b
48K, 96K,
192K
1
0
000b
000b
000b
001, 010b, 011b
001, 010b, 011b
44.1K
000b, 001b, 011b
48K, 96K,
192K
1
0
000b
000b
000b
001, 010b, 011b
44.1K
000b, 001b, 011b
001, 010b, 011b,
100b
48K, 96K,
192K
1
000b, 001b
000b
001, 010b, 011b,
100b
44.1K, 88.2K
The input converter formats supported by the ALC885 are listed. It is software’s duty to set an applicable format.
BASE
MULT
000b, 001b, 011b
000b
DIV
000b
000b
000b
000b
000b
000b
000b
BITS
Sample Rate
48K, 96K, 192K
44.1K
NID=07h (MIC ADC)
NID=08h (LINE ADC)
NID=09h (MIX ADC)
NID=0Ah (S/PDIF-IN)
0
1
0
1
0
1
0
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
000b, 001b, 011b
000b
48K, 96K, 192K
44.1K
000b, 001b, 011b
000b
48K, 96K, 192K
44.1K
000b, 001b, 011b
001b, 010b, 011b,
100b
48K, 96K,192K
1
000b
000b
001b, 010b, 011b,
100b
44.1K
Codec Response for other NID
Bit
Description
Not supported (returns 00000000h)
31:0
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 57. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=2h
Set format [15:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
1: 44.1kHz
13:11
10:8
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved
Sample Base Rate Divisor (DIV)
000b: /1 001b: /2 010b: /3 011b: /4 100b: /5
Reserved. Read as 0
101b: /6 110b: /7 111b: /8
7
6:4
Bits per Sample (BITS)
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels
0: 1 channel 1: 2 channels 2: 3 channels …..… 15: 16 channels
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.15. Verb – Get Power State (Verb ID=F05h)
Table 58. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set
3:2
1:0
Reserved. Read as 0’s
PS-Set, Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.16. Verb – Set Power State (Verb ID=705h)
Table 59. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
Reserved. Read as 0’s
3:2
1:0
PS-Set. Set Power State [1:0]
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
7.1+2 Channel High-Performance HDA Codec
With Content Protection
59
Rev. 1.1
ALC885 Series
Datasheet
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~06h, 25h (Output Converters: Front, Surr, Cen/LFE, Side-Surr, Fout DAC, S/PDIF-OUT)
Codec Response for NID=07h~0Ah (Input Converters: LINE ADC, MIX DAC, and S/PDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0]
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 60. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=706h
Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Set Channel[3:0]
1:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel
Note: This verb assigns stream and channel for output converters (NID=02h~06h, 25h) and input converters
(NID=07h~0Ah). Other widgets will ignore this verb.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 61. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Response [31:0]
Pin Control [7:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=F07h
0’s
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh
(Pin Complex: FRONT, SURR, CENLFE, SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT
and S/PDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled
1: Enabled
6
5
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled
1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:3
2:0
Reserved
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
61
Rev. 1.1
ALC885 Series
Datasheet
8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 62. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=707h
Pin Control [7:0]
‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 1Fh: (Pin Complex: FRONT, SURR, CENLFE,
SIDESURR, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT and S/PDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled
1: Enabled
6
5
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled
1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:3
2:0
Reserved
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD)
101b: 100% of AVDD
110b~111b: Reserved
7.1+2 Channel High-Performance HDA Codec
With Content Protection
62
Rev. 1.1
ALC885 Series
Datasheet
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 63. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO in Audio Function Group), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s
Unsolicited Response is Enabled
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s
Assigned Tag for Unsolicited Response
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
63
Rev. 1.1
ALC885 Series
Datasheet
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 64. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0] for NID=01h (GPIO in Audio Function Group), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s
Enable Unsolicited Response
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s
Tag for Unsolicited Response
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 65. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
32-bit Response
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance
30:0
The ALC885 does not support hardware impedance detection. This field is read as 0s.
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h)
7.1+2 Channel High-Performance HDA Codec
With Content Protection
64
Rev. 1.1
ALC885 Series
Datasheet
8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 66. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s
Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC885 does not support hardware impedance sensing and will ignore this control.
8.25. Verb – Get Volume Knob Widget (Verb ID=F0Fh)
Table 67. Verb – Get Volume Knob (Verb ID=F0Fh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=21h Verb ID= F0Fh
0’s
Bit[31:8]=0s, Bit[7:0] is volume
Codec Response for NID = 21h (Volume Knob Widget)
Bit
31:8
7
Description
Reserved
Direct
0: The volume generated by external HW volume control will be sent by unsolicited response. Software
is responsible for programming the amplifier appropriately.
1: The volume generated by external HW volume control will directly affect the volume of the amplifier.
The ALC885 does not support ‘Direct’ mode and will respond with 0s for this bit.
Volume in steps
6:0
7.1+2 Channel High-Performance HDA Codec
With Content Protection
65
Rev. 1.1
ALC885 Series
Datasheet
8.26. Verb – Set Volume Knob Widget (Verb ID=70Fh)
Table 68. Verb – Set Volume Knob (Verb ID=70Fh)
Set Command Format
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=21h Verb ID= 70Fh Bit[7] is ‘Direct’ control
‘Payload’ in Command Bit[7:0]
Bit
31:8
7
Description
Reserved
Direct
0: The volume generated by external HW volume control will be sent by unsolicited response. Software
is responsible for programming the amplifier appropriately.
1: The volume generated by external HW volume control will directly affect the volume of the amplifier.
The ALC885 does not support ‘Direct’ mode and will respond with 0s for this bit.
Reserved
6:0
8.27. Verb – Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 69. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, and 1Fh
Bit
Description
31:0
32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
7.1+2 Channel High-Performance HDA Codec
With Content Protection
66
Rev. 1.1
ALC885 Series
Datasheet
8.28. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh, e.g., placement and expected default device.
Table 70. Verb – Set Configuration Default Bytes 0, 1, 2, 3
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh,1Ch, 1Dh, 1Eh and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.29. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 71. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Bh
0’s
Divider [7:0]
‘Response’ for NID=01h (Audio Function Group)
Bit
Description
31:8
7:0
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
With Content Protection
67
Rev. 1.1
ALC885 Series
Datasheet
8.30. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 72. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=71Bh
Divider [7:0]
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.31. Verb – Get GPIO Data (Verb ID=F15h)
Table 73. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Data. Not supported in the ALC885
GPIO[1:0] Data
1:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
With Content Protection
68
Rev. 1.1
ALC885 Series
Datasheet
8.32. Verb – Set GPIO Data (Verb ID=715h)
Table 74. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] output Data. Not supported in the ALC885
GPIO[1:0] Output Data
1:0
The value written determines the value driven on a pin that is configured as an output pin
Codec Response for All NID
Bit
Description
31:0
0’s
8.33. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 75. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=F16h
0’s
EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
Reserved
1:0
GPIO[1:0] Enable mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.34. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 76. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=716h
Enable Mask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Enable Mask. Not supported in the ALC885
GPIO[1:0] Enable Mask
1:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.35. Verb – Get GPIO Direction (Verb ID=F17h)
Table 77. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC885
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
With Content Protection
70
Rev. 1.1
ALC885 Series
Datasheet
8.36. Verb – Set GPIO Direction (Verb ID=717h)
Table 78. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC885
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.37. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 79. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=F19h
0’s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC885
GPIO[1:0] Unsolicited Enable mask
0: Unsolicited response will not be sent on link
1:0
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.38. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 80. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format Codec Response Format
Response [31:0]
0’s for all nodes
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=719h
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC885
GPIO[1:0] Unsolicited Enable Mask
0: Unsolicited response will not be sent on link
1:0
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.39. Verb – Function Reset (Verb ID=7FFh)
Table 81. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01h)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s
Note: The Function Reset command causes all widgets in the ALC885 to return to their power on default state.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
8.40. Verb – Get Digital Converter Control 1 & Control 2 (Verb
ID= F0Dh, F0Eh)
Table 82. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/
F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h (S/PDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
7.1+2 Channel High-Performance HDA Codec
With Content Protection
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Rev. 1.1
ALC885 Series
Datasheet
NID=0Ah (S/PDIF-IN) Response to Get verb (F0Dh)
NID=0Ah (S/PDIF-IN) Response to Get verb (F0Eh)
Bit
31:16
15
Description (part of S/PDIF-IN Channel Status)
Reserved. Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
Reserved
2
1
In‘V’alid. V bit in sub-frame of S/PDIF-IN
0: Data X and Y are valid, or S/PDIF-IN is not locked
1: At least one of data X and Y is invalid
Digital Enable. DigEn
0
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s
8.41. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 83. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
SIC [15:8]
74
CAd=X
Node ID=Xh
Verb ID=70Eh
7.1+2 Channel High-Performance HDA Codec
With Content Protection
Rev. 1.1
ALC885 Series
Datasheet
‘Payload’ in Set Control 1 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
LEVEL (Generation Level)
PRO (Professional or Consumer format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h (S/PDIF-OUT)
Bit
7
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
6:0
CC[6:0] (Category Code)
‘Payload’ in Set Control 1 for NID=0Ah (S/PDIF-IN)
Bit
7:1
0
Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved
Digital Enable. DigEn
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (S/PDIF-IN)
Bit Description – SIC (S/PDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
7:0
Note: Other widgets will ignore this verb.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
75
Rev. 1.1
ALC885 Series
Datasheet
8.42. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/F22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 84. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h Verb ID=F20h
0s
32-bit Response
Codec Response for NID=01h
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8]. (Default=10ECh)
Subsystem ID[7:0]. (Default=08h).
Assembly ID[7:0]. (Default=85h).
8.43. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8],
720h for [7:0])
Table 85. Verb – Set Subsystem ID [31:0] (Verb ID=723h, 722h, 721h, 720h)
Set Command Format
Bit [31:28] Bit [27:20]
Codec Response Format
Response [31:0]
Bit [19:8]
Payload Bit [7:0]
CAd = X Node ID=01h Verb ID=723h,
Label [7:0]
0s for all nodes
722h, 721h,
720h
Codec Response for all NID
Bit
Description
0s
31:0
7.1+2 Channel High-Performance HDA Codec
With Content Protection
76
Rev. 1.1
ALC885 Series
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 86. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supply:
Digital power for core
Digital power for HDA link
Analog
DVDD
DVDD-IO*
AVDD**
Ta
3.0
1.5
3.3
0
3.3
3.3
5.0
-
3.6
3.6
5.25
+70
V
V
V
oC
Ambient Operating
Temperature
Storage Temperature
Ts
+125
oC
ESD (Electrostatic Discharge)
Susceptibility Voltage
3500V
All Pins
Note*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
Note** : The standard testing condition before shipping is AVDD = 5.0V unless specified. Customer designing with a
different AVDD should contact Realtek technical support representatives for special testing support.
9.1.2. Threshold Voltage
DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 87. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
DVDD +0.30
0.30*
DVDDIO
-
Units
Input Voltage Range
-0.30
-
-
-
V
Low Level Input Voltage
(HDA link)
VIL
V
High Level Input Voltage
(HDA link)
VIH
VIL
VIH
0.65*
DVDDIO
-
-
-
V
V
Low Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Input Voltage
(S/PDIF-IN/OUT, GPIOs)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
0.44*DVDD
(1.45)
-
0.56* DVDD
V
(1.85)
VOH
0.9*DVDD
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
-
µA
µA
mA
Ω
-
5
-
50k
-
7.1+2 Channel High-Performance HDA Codec
With Content Protection
77
Rev. 1.1
ALC885 Series
Datasheet
9.1.3. Digital Filter Characteristics
Table 88. Digital Filter Characteristics
Filter
Description
Minimum
0
Typical
Maximum
Units
kHz
kHz
dB
ADC Lowpass Filter Passband
Stopband
-
0.45*Fs
0.60*Fs
Stopband Rejection
-76.0
Passband
dB
±0.02
Frequency Response
DAC Lowpass Filter Passband
0
-
0.45*Fs
kHz
kHz
dB
Stopband
0.60*Fs
Stopband Rejection
Passband
-78.5
dB
±0.02
Frequency Response
Note: Fs=Sample rate
9.1.4. S/PDIF Input/Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 89. S/PDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
V
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output
S/PDIF-IN High Level Input
S/PDIF-IN Low Level Input
S/PDIF-IN Bias Level
3.0
3.3
-
0.3
-
-
0
V
1.85
-
-
V
VIL
-
-
1.45
-
V
Vt
1.65
V
7.1+2 Channel High-Performance HDA Codec
With Content Protection
78
Rev. 1.1
ALC885 Series
Datasheet
9.2. AC Characteristic
9.2.1. Link Reset and Initialization Timing
Table 90. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
Startup delay for PLL ready time
SDI Initialization Request
1.0
20
-
-
-
-
TPLL
µs
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
SDO
SDI
Normal Frame
SYNC
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 15. Link Reset and Initialization Timing
7.1+2 Channel High-Performance HDA Codec
With Content Protection
79
Rev. 1.1
ALC885 Series
Datasheet
9.2.2. Link Timing Parameters at the Codec
Table 91. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
24.0
-
Tcycle
Tjitter
Thigh
-
41.67
-
BCLK Jitter
-
-
-
2.0
ns
BCLK High Pulse Width
18.75
(45%)
18.75
(45%)
2.1
22.91
(55%)
22.91
(55%)
-
ns
(%)
ns
(%)
ns
BCLK Low Pulse Width
Tlow
-
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Tsetup
Thold
Ttco
-
SDO Hold Time at Both Rising and
Falling Edge of BCLK
2.1
-
-
8.0
-
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1: 50pF external load)
-
-
7.5
2.0
SDI Flight Time
Tflight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 16. Link Signals Timing
7.1+2 Channel High-Performance HDA Codec
With Content Protection
80
Rev. 1.1
ALC885 Series
Datasheet
9.2.3. S/PDIF Output and Input Timing
Table 92. S/PDIF Output and Input Timing
Parameter
Symbol
-
Minimum
Typical
3.072
Maximum
Units
MHz
ns
S/PDIF-OUT Frequency
S/PDIF-OUT Period *1
S/PDIF-OUT Jitter
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
325.6
-
-
-
4
ns
S/PDIF-OUT High Level Width
S/PDIF-OUT Low Level Width
S/PDIF-OUT Rising Time
S/PDIF-OUT Falling Time
S/PDIF-IN Period *2
156.2 (48%)
162.8 (50%)
162.8 (50%)
2.0
169.2 (52%)
ns (%)
ns (%)
ns
156.2 (48%)
169.2 (52%)
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
325.6
-
ns
S/PDIF-IN Jitter
-
-
10
ns
S/PDIF-IN High Level Width
S/PDIF-IN Low Level Width
146.4 (45%)
146.4 (45%)
162.8 (50%)
162.8 (50%)
179 (55%)
179 (55%)
ns (%)
ns (%)
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT
*2: Bit parameters for 48kHz sample rate of S/PDIF-IN
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 17. Output and Input Timing
9.2.4. Test Mode
The ALC885 does not support codec test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel High-Performance HDA Codec
With Content Protection
81
Rev. 1.1
ALC885 Series
Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 93. Analog Performance
Parameter
Min
Typical
Max
Units
Full Scale Input Voltage
All Inputs (gain=0dB)
ADC
-
-
1.4
1.4
-
-
Vrms
Vrms
Full Scale Output Voltage
DAC
-
-
1.4
1.0
-
-
Vrms
Vrms
Headphone Amplifier Output@32Ω Load
Dynamic Range with –60dB signal (A-Weight)
ADC
-
-
-
101
106
106
-
-
-
dB FSA
dB FSA
dB FSA
DAC
Headphone Amplifier Output@32Ω Load
THD+N with –3dB signal (No A-Weight)
ADC
-
-
-
-90
-95
-75
-
-
-
dB FS
dB FS
dB FS
DAC
Headphone Amplifier Output@32Ω Load
Magnitude Response (10KΩ load)
All DAC @Fs=48KHz (FR=±0.05dB)
All DAC @Fs=96KHz (FR=±0.05dB)
All DAC @Fs=192KHz (FR=±0.05dB)
All ADC @Fs=48KHz (FR=±0.05dB)
All ADC @Fs=96KHz (FR=±0.05dB)
All ADC @Fs=192KHz (FR=±0.05dB)
Power Supply Rejection
10
10
10
10
10
10
-
-
-
-
-
-
21,792
43,584
87,168
19,200
38,400
76,800
Hz
Hz
Hz
Hz
Hz
Hz
-
-
-
-
-60
1.0
-
-
dB
dB
Amplifier Gain Step
Channel Separation (Crosstalk)
Input Impedance (gain=0dB)
-100
47
dB
-
-
KΩ
Output Impedance
Amplified Output
Non-amplified Output
-
1
100
Ω
Ω
Digital Power Supply Current (normal/DVD-Audio)
DVDD=3.3V
-
-
-
40/70
70/46
-
1000
-
mA
µA
Digital Power Supply Current (power down mode)
DVDD=3.3V
Analog Power Supply Current (normal operation)
AVDD=5.0V/3.3V
mA
Analog Power Supply Current (power down mode)
AVDD=5.0V/3.3V
-
2.25
-
900/500
µA
V
VREFOUTx Output Voltage
2.50
5
3.75
-
VREFOUTx Output Current
mA
7.1+2 Channel High-Performance HDA Codec
With Content Protection
82
Rev. 1.1
ALC885 Series
Datasheet
10. Application Circuits
The ALC885 is in a 48-pin LQFP package and is pin-to-pin compatible with the ALC882, ALC883, and
ALC888. A board designed for those Codecs can use the ALC885 directly.
To get the best compatibility in hardware design and software driver, any modification should be
confirmed by Realtek. Realtek may update the latest application circuits onto our web site
(www.realtek.com.tw) without modifying this datasheet.
Figure 18. Filter Connection
7.1+2 Channel High-Performance HDA Codec
With Content Protection
83
Rev. 1.1
ALC885 Series
Datasheet
Option 1 in Figure 19 comes from by Intel’s front panel IO connectivity design guide. A drawback of this
option is that the ports connected to the front panel must use the same jack detection pin. According to the
HD Audio standard specification, ports A/B/C/D use ‘Sense A’ as the jack detect pin; ports E/F/G/H use
‘Sense B’ as the jack detect pin. This is not a good option when the system integrators want to use port-A
(pin 39/41) and port-F (pin 16/17) to be the front panel ports, as ‘Sense A’ and ‘Sense B’ cannot be tied
together.
Option 2 in Figure 19 shows an alternative front panel header design that is also compatible with standard
front panel I/O cable. The option 2 header design lets the two ports use an individual sense pin, and is
compatible with current HD Audio front panel cable.
Option 1: Follow Intel's HD Audio front panle header design
(Two ports must be in the same jack detect group)
MIC2-VREFO
D3
D4
HD Audio Front Panel I/O Cable
1N4148
1N4148
+3.3VD
J2
FIO-PORT1-L
1
3
5
7
9
2
4
6
8
10
R11
R12
FIO-PORT1-R
FIO-PORT2-R
FIO-SENSE
FIO-PRESENCE#
PORT1-SENSE-RETURN
KEY
PORT2-SENSE-RETURN
4.7K
4.7K
R14
FIO-PORT2-L
MIC2-L
MIC2-R
C35
C37
1u
1u
10K
CON10A
J3
1
3
5
7
9
2
4
6
8
10
PRESENCE#
System GPI
LINE2-R
LINE2-L
C38
C39
100u
100u
MIC2-JD
Key
FRONT-IO-JD
FIO-SENSE
LINE2-JD
R19
39.2K,1%
R18
JACK 7
CON10A
Onboard front
panel header
4
3
5
PORT2-SENSE-RETURN
20K,1%
FIO-PORT2-R
FIO-PORT2-L
L14
L15
FERB
FERB
2
1
C41
C42
FIO-PORT2 (Jack-E)
Option 2: A more flexible front panel header
100P
100P
(Each port can be in different jack detect group)
MIC2-VREFO
D5
D6
1N4148
1N4148
FIO-SENSE
+3.3VD
R20
R21
JACK 8
4
3
5
4.7K
4.7K
R23
PORT1-SENSE-RETURN
FIO-PORT1-R
FIO-PORT1-L
L16
L17
FERB
FERB
MIC2-L
MIC2-R
C44
C46
1u
1u
10K
2
1
PRESENCE#
J5
System GPI
1
3
5
7
9
2
4
6
8
10
R25
R26
C49
C50
20K,1%
LINE2-R
LINE2-L
C48
C51
100u
100u
MIC2-JD
LINE2-JD
FIO-PORT1 (Jack-F)
Sense B
Sense B
Key
100P
100P
CON10A
Onboard front
panel header
39.2K,1%
Figure 19. Front Panel Header Connection
7.1+2 Channel High-Performance HDA Codec
With Content Protection
84
Rev. 1.1
ALC885 Series
Datasheet
MIC1-VREFO-L
MIC1-VREFO-R
R234
4.7K
JACK 30
R235
4.7K
L70
JACK 31
SURR-JD
FERB
FERB
4
3
5
MIC1-JD
4
3
5
SURR-R
SURR-L
C218 1u
C220 1u
L69
L72
MIC1-R
MIC1-L
C219 1u
C221 1u
FERB
FERB
2
1
L73
2
1
C222
C223
C224
100P
C225
100P
MIC-IN (Port-B)
SURROUND (Port-A)
2.2~4.7uF for DA (LF)
frequence response
100P
100P
JACK 32
JACK 33
CEN-JD
4
3
5
FRONT-JD
4
3
5
LFE
C228 1u
C232 1u
L74
L76
FERB
FERB
FRONT-R
FRONT-L
C231
C233
100u
100u
L75
L77
FERB
FERB
CEN
2
1
2
1
C234
C235
100P
C236
100P
C237
100P
CENTER/LFE (Port-G)
2.2~4.7uF for DA (LF)
frequence response
FRONT-OUT (Port-D)
100P
JACK 35
JACK 34
LINE1-JD
SIDESURR-JD
FERB
4
3
5
4
3
5
LINE1-R
LINE1-L
C239 1u
C241 1u
L78
L80
FERB
FERB
SIDE-R
SIDE-L
C240 1u
C242 1u
L79
L81
FERB
2
1
2
1
C245
100P
C246
100P
LINE-IN (Port-C)
C247
100P
C248
100P
SIDESURR (Port-H)
2.2~4.7uF for DA (LF)
frequence response
Figure 20. Jack Connection on Rear Panel
Figure 21. S/PDIF Input/Output Connection
7.1+2 Channel High-Performance HDA Codec
With Content Protection
85
Rev. 1.1
ALC885 Series
Datasheet
11. Application Supplements
11.1. Standby Mode
In standby mode the ALC885 turns on all DC bias on all input and output ports (NID=14h~1Bh). This is
a special application to avoid ‘PoP’ noise while in power on and power off periods.
Table 94 shows the DC bias state when Standby mode is enabled.
Table 94. Standby Mode
+3.3V on DVDD (Pin-1)
No (<2.0V)
+5VA on AVDD
Operation Mode
Shut Down
Standby Mode
Normal
No
Yes
No
No (<2.0V)
Yes (>2.0V)
Yes (>2.0V)
Yes
Normal
11.2. Volume Knob Control
11.2.1. GPI Volume Control via GPIO0 (Up/Down), GPIO1 (Mute)
Low pulses, generated at GPIO0 and GPIO1, are used to calculate the Up and Down count into 7 bits of
volume step. ‘Mute’ is also sampled by 512*SYNC to toggle the mute status. Hardware will not adjust
volume; the count value will be reported by unsolicited response to software.
Figure 22. GPI Volume Control Implementation
7.1+2 Channel High-Performance HDA Codec
With Content Protection
86
Rev. 1.1
ALC885 Series
Datasheet
11.2.2. Volume Control by External Variable Resistor
A 5-bit resolution ADC operating at 64*SYNC clock rate is used to converts the DC level on VAR into 32
steps for the Volume knob. Hardware will not directly change the volume, the DC level change will be
reflected to software by unsolicited response in every 64 SYNC(=64*20.84usec)
Figure 23. Volume Control by External Variable Resistor
Table 95. Volume Code Corresponding to DC Level at Pin 33
Input DC
Voltage
Volume
Code
Input DC
Voltage
Volume
Code
Input DC
Voltage
Volume
Code
Input DC
Voltage
Volume
Code
95.0%=< DC
1F
1E
1D
1C
1B
1A
19
71.0%< DC <= 74.0%
68.0%< DC <= 71.0%
65.0%< DC <= 68.0%
62.0%< DC <= 65.0%
59.0%< DC <= 62.0%
56.0%< DC <= 59.0%
53.0%< DC <= 56.0%
50.0%< DC <= 53.0%
17
16
15
14
13
12
11
10
47.0%< DC <= 50.0%
44.0%< DC <= 47.0%
41.0%< DC <= 44.0%
38.0%< DC <= 41.0%
35.0%< DC <= 38.0%
32.0%< DC <= 35.0%
29.0%< DC <= 32.0%
26.0%< DC <= 29.0%
0F
0E
0D
0C
0B
0A
09
23.0%< DC <= 26.0%
20.0%< DC <= 23.0%
17.0%< DC <= 20.0%
14.0%< DC <= 17.0%
11.0%< DC <= 14.0%
8.0%< DC <= 11.0%
5.0%< DC <= 8.0%
DC <= 5.0%
07
06
05
04
03
02
01
00
92.0%< DC <= 95.0%
89.0%< DC <= 92.0%
86.0%< DC <= 89.0%
83.0%< DC <= 86.0%
80.0%< DC <= 83.0%
77.0%< DC <= 80.0%
74.0%< DC <= 77.0%
18
08
7.1+2 Channel High-Performance HDA Codec
With Content Protection
87
Rev. 1.1
ALC885 Series
Datasheet
11.3. Digital Microphone Implementation
This section describes the ALC885 digital microphone implementation. There is one Clock output pin
and 1 Data input pin in the ALC885. The ALC885 provides the clock signal to the digital microphone.
When the digital microphone receives the external sound input, it converts the analog signals to digital in
a 1-bit format. The 1-bit data is delivered to the codec though the data input pin. The Digital Filter in the
audio codec converts the 1-bit data stream into Pulse Code Modulation (PCM) data. The PCM data is sent
to the HDA controller through the HDA link.
Figure 24. Digital Microphone Implementation-1
The ALC885 supports a two-wire interface for the digital microphone and operates in single channel
(mono type) or stereo channels (stereo mode) of digital microphones. One pin is clock output to the
digital microphone, and the other is a serial pin. The default clock output is 2.048MHz.
In Type 1 (Figure 25), the ALC885 uses one data pin to support mono input from digital microphones
with LMV1024 (L), SPD0205ND (L), or AKU2000 (L).
In Type 2 (Figure 25), the ALC885 uses one data pin to support stereo inputs from digital microphones
with LMV1024/1026 (L/R), SPD0205ND (L & R), or AKU2000 (L & R).
Figure 25. Digital Microphone Implementation-2
7.1+2 Channel High-Performance HDA Codec
With Content Protection
88
Rev. 1.1
ALC885 Series
Datasheet
12. Mechanical Dimensions
L
L1
MILLIMETER
INCH
SYMBOL
MIN TYP MAX MIN TYP MAX
A
A1
A2
c
1.60
0.15 0.002
0.063
0.006
0.05
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
1.35 1.40 1.45 0.053 0.055 0.057
0.09 0.20 0.004 0.008
0.354 BSC
D
9.00 BSC
7.00 BSC
5.50
LEADFRAME MATERIAL
D1
D2
E
E1
E2
b
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
APPROVE
CHECK
DOC. NO.
VERSION 02
DWG NO. PKGC-065
DATE
9.00 BSC
7.00BSC
5.50
REALTEK SEMICONDUCTOR CORP.
0.17 0.20 0.27 0.007 0.008 0.011
e
TH
L
0.50 BSC
0.0196 BSC
0o
3.5o
7o
0o
3.5o 7o
0.45 0.60 0.75 0.018 0.0236 0.030
1.00 0.0393
L1
7.1+2 Channel High-Performance HDA Codec
With Content Protection
89
Rev. 1.1
ALC885 Series
Datasheet
13. Ordering Information
Table 96. Ordering Information
Part Number
ALC885-GR
Description
Status
MP
LQFP-48 with ‘Green’ package
ALC885-GR + Dolby® Master Studio™ (software feature)
ALC885M-GR
MP
Note 1: See page 6 for ‘Green’package and version identification.
Note 2: Above parts are tested under AVDD =5.0V. Customers requesting lower AVDD support should contact Realtek
sales representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
7.1+2 Channel High-Performance HDA Codec
With Content Protection
90
Rev. 1.1
相关型号：
SI9130DB
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