ALC888S-VC2-GR [REALTEK]
7.12 CHANNEL HIGH DEFINITION AUDIO CODEC;
| 型号： | ALC888S-VC2-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 7.12 CHANNEL HIGH DEFINITION AUDIO CODEC |
| 文件： | 总83页 (文件大小：1188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC888S-VC
(PN: ALC888S-VC2-GR, ALC888SDD-VC2-GR)
7.1+2 CHANNEL HIGH DEFINITION AUDIO
CODEC WITH TWO INDEPENDENT SPDIF-OUT
DATASHEET
Rev. 1.1
21 May 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC888S-VC (ALC888S Version C) High Definition Audio Codec ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date Summary
1.0
2008/04/07
2008/05/21
First release
1.1
Update part number and production status in section 12 Ordering Information, page 75.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
ii
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Table of Contents
1.
2.
GENERAL DESCRIPTION ..............................................................................................................................................1
FEATURES .........................................................................................................................................................................2
2.1.
2.2.
2.3.
HARDWARE FEATURES .................................................................................................................................................2
SOFTWARE FEATURES ..................................................................................................................................................3
ENHANCED FEATURES..................................................................................................................................................4
3.
4.
SYSTEM APPLICATIONS ...............................................................................................................................................4
BLOCK DIAGRAM...........................................................................................................................................................5
4.1.
ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................6
5.
6.
PIN ASSIGNMENTS..........................................................................................................................................................7
5.1.
5.2.
5.3.
ALC888S-VC2............................................................................................................................................................7
GREEN PACKAGE AND VERSION IDENTIFICATION.........................................................................................................7
ALC888S (VERSION B) ...............................................................................................................................................8
PIN DESCRIPTIONS.........................................................................................................................................................9
6.1.
DIGITAL I/O PINS .........................................................................................................................................................9
ANALOG I/O PINS ........................................................................................................................................................9
FILTER/REFERENCE....................................................................................................................................................10
POWER/GROUND........................................................................................................................................................11
PIN DIFFERENCES: ALC888S-VC VS. ALC888S (VERSION B) ..................................................................................11
6.2.
6.3.
6.4.
6.5.
7.
HIGH DEFINITION AUDIO LINK PROTOCOL........................................................................................................12
7.1.
LINK SIGNALS............................................................................................................................................................12
7.1.1. Signal Definitions.................................................................................................................................................13
7.1.2. Signaling Topology...............................................................................................................................................14
7.2.
FRAME COMPOSITION ................................................................................................................................................15
7.2.1. Outbound Frame – Single SDO............................................................................................................................15
7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................16
7.2.3. Inbound Frame – Single SDI................................................................................................................................17
7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................18
7.2.5. Variable Sample Rates..........................................................................................................................................18
7.3.
RESET AND INITIALIZATION........................................................................................................................................21
7.3.1. Link Reset .............................................................................................................................................................21
7.3.2. Codec Reset..........................................................................................................................................................22
7.3.3. Double Function Reset .........................................................................................................................................22
7.3.4. Codec Initialization Sequence ..............................................................................................................................23
7.4.
VERB AND RESPONSE FORMAT...................................................................................................................................23
7.4.1. Command Verb Format ........................................................................................................................................23
7.4.2. Response Format..................................................................................................................................................26
7.5.
POWER MANAGEMENT...............................................................................................................................................27
7.5.1. ALC888S-VC Additional Power Features ............................................................................................................28
8.
SUPPORTED VERBS AND PARAMETERS ................................................................................................................29
8.1.
VERB – GET PARAMETERS (VERB ID=F00H) .............................................................................................................29
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................29
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................29
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................30
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
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Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)...........................................................30
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................30
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................31
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................32
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................33
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................33
8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)...........................34
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h).........................34
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)........................................................35
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)..................................................35
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..................................................35
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...........................................................36
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)...............................................36
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................37
VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................37
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..........................................................................................38
VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................41
VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................42
VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................42
VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................42
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................43
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................43
VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................44
VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................45
VERB – GET CONVERTER FORMAT (VERB ID=AH) ....................................................................................................46
VERB – SET CONVERTER FORMAT (VERB ID=2H)......................................................................................................47
VERB – GET POWER STATE (VERB ID=F05H) ............................................................................................................47
VERB – SET POWER STATE (VERB ID=705H) .............................................................................................................48
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................48
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................49
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...............................................................................................49
VERB – SET PIN WIDGET CONTROL (VERB ID=707H)................................................................................................50
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................50
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................51
VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................51
VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................52
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ........................................................................................52
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) .53
VERB – GET BEEP GENERATOR (VERB ID=F0AH)....................................................................................................53
VERB – SET BEEP GENERATOR (VERB ID=70AH).....................................................................................................54
VERB – GET GPIO DATA (VERB ID=F15H)................................................................................................................54
VERB – SET GPIO DATA (VERB ID=715H).................................................................................................................55
VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................55
VERB – SET GPIO ENABLE MASK (VERB ID=716H)..................................................................................................56
VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................56
VERB – SET GPIO DIRECTION (VERB ID=717H)........................................................................................................57
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................57
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)........................................................58
VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................58
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)...........................................59
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................61
VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ..................................................................62
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0])
62
8.42.
GET/SET EAPD ENABLE (VID=70CH/F0CH)............................................................................................................63
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
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Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.
ELECTRICAL CHARACTERISTICS...........................................................................................................................64
9.1.
DC CHARACTERISTICS...............................................................................................................................................64
9.1.1. Absolute Maximum Ratings..................................................................................................................................64
9.1.2. Threshold Voltage.................................................................................................................................................64
9.1.3. Digital Filter Characteristics...............................................................................................................................65
9.1.4. SPDIF Input/Output Characteristics....................................................................................................................65
9.2.
AC CHARACTERISTIC.................................................................................................................................................66
9.2.1. Link Reset and Initialization Timing.....................................................................................................................66
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................67
9.2.3. SPDIF Output and Input Timing...........................................................................................................................68
9.2.4. Test Mode..............................................................................................................................................................68
9.3.
ANALOG PERFORMANCE............................................................................................................................................69
10.
APPLICATION CIRCUITS .......................................................................................................................................70
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
FILTER CONNECTION..................................................................................................................................................70
ONBOARD FRONT PANEL HEADER CONNECTION........................................................................................................71
JACK CONNECTION ON REAR PANEL ..........................................................................................................................72
SPDIF INPUT/OUTPUT CONNECTION .........................................................................................................................72
SECONDARY SPDIF-OUT CONNECTED TO HDMI TX CONNECTOR ...........................................................................73
DIFFERENTIAL ANALOG CD USED AS LINE LEVEL INPUT ..........................................................................................73
11. MECHANICAL DIMENSIONS......................................................................................................................................74
12. ORDERING INFORMATION ...................................................................................................................................75
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
v
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS .........................................................................................................................................................9
TABLE 2. ANALOG I/O PINS.........................................................................................................................................................9
TABLE 3. FILTER/REFERENCE ....................................................................................................................................................10
TABLE 4. POWER/GROUND........................................................................................................................................................11
TABLE 5. PIN DIFFERENCE: ALC888S-VC VS. ALC888S (VERSION B) ....................................................................................11
TABLE 6. LINK SIGNAL DEFINITIONS.........................................................................................................................................13
TABLE 7. HDASIGNAL DEFINITIONS ........................................................................................................................................13
TABLE 8. DEFINED SAMPLE RATE AND TRANSMISSION RATE ....................................................................................................19
TABLE 9. 48KHZ VARIABLE RATE OF DELIVERY TIMING ...........................................................................................................19
TABLE 10. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING........................................................................................................20
TABLE 11. 40-BIT COMMANDS IN 4-BIT VERB FORMAT..............................................................................................................23
TABLE 12. 40-BIT COMMANDS IN 12-BIT VERB FORMAT............................................................................................................23
TABLE 13. SUPPORTED COMMANDS............................................................................................................................................24
TABLE 14. SUPPORTED PARAMETERS ..........................................................................................................................................25
TABLE 15. SOLICITED RESPONSE FORMAT ..................................................................................................................................26
TABLE 16. UNSOLICITED RESPONSE FORMAT .............................................................................................................................26
TABLE 17. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................27
TABLE 18. POWER CONTROLS IN NID 01H..................................................................................................................................27
TABLE 19. POWERED DOWN CONDITIONS...................................................................................................................................28
TABLE 20. VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................29
TABLE 21. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................29
TABLE 22. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) ........................................................................29
TABLE 23. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H)................................................30
TABLE 24. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H).......................................................30
TABLE 25. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H) ..........................................30
TABLE 26. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H)..............................................31
TABLE 27. PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ............................................32
TABLE 28. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)............................................33
TABLE 29. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ................................................................33
TABLE 30. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH)........................34
TABLE 31. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) .....................34
TABLE 32. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH).......................................................35
TABLE 33. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) .................................................35
TABLE 34. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)...................................................35
TABLE 35. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) .............................................................36
TABLE 36. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H)..............................................36
TABLE 37. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................37
TABLE 38. VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................37
TABLE 39. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................38
TABLE 40. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................41
TABLE 41. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................42
TABLE 42. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................42
TABLE 43. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................42
TABLE 44. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................43
TABLE 45. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................43
TABLE 46. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................44
TABLE 47. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................45
TABLE 48. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................46
TABLE 49. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................47
TABLE 50. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................47
TABLE 51. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................48
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
vi
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
TABLE 52. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H)................................................................................49
TABLE 53. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................49
TABLE 54. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................50
TABLE 55. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)...........................................................................50
TABLE 56. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................51
TABLE 57. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................51
TABLE 58. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................52
TABLE 59. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH)........................................................................................52
TABLE 60. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)53
TABLE 61. VERB – GET BEEP GENERATOR (VERB ID= F0AH)...................................................................................................53
TABLE 62. VERB – SET BEEP GENERATOR (VERB ID= 70AH)....................................................................................................54
TABLE 63. VERB – GET GPIO DATA (VERB ID= F15H)...............................................................................................................54
TABLE 64. VERB – SET GPIO DATA (VERB ID= 715H)................................................................................................................55
TABLE 65. VERB – GET GPIO ENABLE MASK (VERB ID= F16H)................................................................................................55
TABLE 66. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................56
TABLE 67. VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................56
TABLE 68. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................57
TABLE 69. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................57
TABLE 70. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................58
TABLE 71. VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................58
TABLE 72. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)...........................................59
TABLE 73. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................61
TABLE 74. VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H)...................................................................62
TABLE 75. VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0]).........................................................................................................................................................................62
TABLE 76. VERB – GET/SET EAPD [31:0] ..................................................................................................................................63
TABLE 77. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................64
TABLE 78. THRESHOLD VOLTAGE ...............................................................................................................................................64
TABLE 79. DIGITAL FILTER CHARACTERISTICS ...........................................................................................................................65
TABLE 80. SPDIF INPUT/OUTPUT CHARACTERISTICS.................................................................................................................65
TABLE 81. LINK RESET AND INITIALIZATION TIMING..................................................................................................................66
TABLE 82. LINK TIMING PARAMETERS AT THE CODEC ................................................................................................................67
TABLE 83. SPDIF OUTPUT AND INPUT TIMING ...........................................................................................................................68
TABLE 84. ANALOG PERFORMANCE............................................................................................................................................69
TABLE 85. ORDERING INFORMATION ..........................................................................................................................................75
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
vii
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT....................................................................................................................................6
FIGURE 3. ALC888S-VC (VERSION C) PIN ASSIGNMENTS .........................................................................................................7
FIGURE 4. ALC888S (VERSION B) PIN ASSIGNMENT..................................................................................................................8
FIGURE 5. HDALINK PROTOCOL ..............................................................................................................................................12
FIGURE 6. BIT TIMING...............................................................................................................................................................13
FIGURE 7. SIGNALING TOPOLOGY .............................................................................................................................................14
FIGURE 8. SDO OUTBOUND FRAME..........................................................................................................................................15
FIGURE 9. SDO STREAM TAG IS INDICATED IN SYNC...............................................................................................................15
FIGURE 10. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................16
FIGURE 11. SDI INBOUND STREAM.............................................................................................................................................17
FIGURE 12. SDI STREAM TAG AND DATA....................................................................................................................................17
FIGURE 13. CODEC TRANSMITS DATA OVER MULTIPLE SDIS .....................................................................................................18
FIGURE 14. LINK RESET TIMING .................................................................................................................................................22
FIGURE 15. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................23
FIGURE 16. LINK RESET AND INITIALIZATION TIMING ................................................................................................................66
FIGURE 17. LINK SIGNALS TIMING .............................................................................................................................................67
FIGURE 18. OUTPUT AND INPUT TIMING .....................................................................................................................................68
FIGURE 19. FILTER CONNECTION................................................................................................................................................70
FIGURE 20. FRONT PANEL HEADER CONNECTION.......................................................................................................................71
FIGURE 21. JACK CONNECTION ON REAR PANEL ........................................................................................................................72
FIGURE 22. SPDIF INPUT/OUTPUT CONNECTION .......................................................................................................................72
FIGURE 23. SECONDARY SPDIF-OUT CONNECTED TO HDMI TX CONNECTOR .........................................................................73
FIGURE 24. DIFFERENTIAL ANALOG CD USED AS LINE LEVEL INPUT.........................................................................................73
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
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Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
1. General Description
The ALC888S-VC2 and ALC888SDD-VC2 are high-performance 7.1+2 Channel High Definition Audio
Codecs with two independent SPDIF outputs. They feature ten DAC channels that simultaneously support
7.1 sound playback, plus independent stereo sound output (multiple streaming) through the front panel
stereo outputs, and integrate two stereo ADCs that can support a stereo microphone, and feature Acoustic
Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) for voice applications.
The ALC888S-VC supports 16/20/24-bit SPDIF input and output functions with sampling rate of up to
192kHz, offering easy connection of PCs to high quality consumer electronic products such as digital
decoders and Minidisk devices. In addition to the standard (primary) SPDIF output function, the
ALC888S-VC features another independent (secondary) SPDIF-OUT output and converters that transport
digital audio output to a High Definition Media Interface (HDMI) transmitter (becoming more common
in high-end PCs).
All analog IO are input and output capable, and headphone amplifiers are also integrated at each analog
output. All analog IOs can be re-tasked according to user’s definitions, or automatically switched.
The ALC888S-VC series support host audio controller from the Intel ICH series chipset, and also from
any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and
excellent software utilities like environment sound emulation, multiple-band software equalizer and
dynamic range control, optional Dolby® Digital Live, DTS® CONNECT™, and Dolby® Home Theater
programs, the ALC888S provides an excellent home entertainment package and game experience for PC
users.
The ALC888S-VC is an upgraded version of the ALC888S version B that meets the current WLP3.10
(Windows Logo Program) and future WLP requirements that become effective from 01 June 2008 (See
section 2.3 Enhanced Features, page 4). The ALC888S-VC also conforms to Intel’s Audio Codec low
power state white paper and is ECR compliant.
Note: ALC888S-VC version differences are listed in section 12 Ordering Information, page 75.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
1
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
2. Features
2.1. Hardware Features
Meets premium audio requirements for Microsoft WLP 3.10
Meets stricter performance requirements for future WLP effective from 01 June 2008
High-performance DACs with 97dB SNR (A-Weighting), ADCs with 90dB SNR (A-Weighting)
Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels of
independent stereo sound output (multiple streaming) through the front panel output
Two stereo ADCs support 16/20/24-bit PCM format recording simultaneously
All DACs supports 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate
All ADCs supports 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate
Two independent SPDIF-OUT converters support 16/20/24-bit, 44.1k/48k/88.2k/96k/192kHz sample
rate. One converter for normal SPDIF output, the other outputs an independent digital stream to the
HDMI transmitter
One SPDIF-IN converter supports 44.1k/48k/96k/192k Hz sample rate
High-quality analog differential CD input
Supports external PCBEEP input, built-in digital BEEP generator, and pass-through function in D3
mode
Software selectable 2.5V/3.75V/4.7V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
Extra jack detection pin for CD input when it is used as an optional line level input, SPDIF input and
output
Supports legacy analog mixer architecture
Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog mixer gain
Software selectable boost gain (+10/+20/+30dB) for analog microphone input
All analog jacks are stereo input and output re-tasking for analog plug & play
Built-in headphone amplifiers for each re-tasking jack
Two GPIOs for customized applications
Supports Anti-pop mode when analog power AVDD is on and digital power is off
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
2
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Supports stereo digital microphone interface to improve voice quality
Integrates high-pass filter to cancel DC offset generated from digital microphone
48-pin LQFP ‘Green’ package
Supports low voltage IO for HDA Link (1.5V~3.3V)
Intel low power ECR compliant, supports power status control for each analog converter and pin
widgets, supports jack detection and wake up event in D3 mode
2.2. Software Features
Meets Microsoft WLP 3.10 and future WLP audio requirements
WaveRT based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
Emulation of 26 sound environments to enhance gaming experience
Multi bands of software equalizer and tool are provided
Voice Cancellation and Key Shifting effect
Dynamic range control (expander, compressor and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Provides 10-foot GUI for Windows Media Center
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
DTS® CONNECT™ (optional software feature)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
3
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
SRS® TrueSurround HD (optional software feature)
Fortemedia® SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)
Creative® Host Audio program (optional software feature)
Voice recognition and Realtek proprietary API (SkyTel) is supported (optional software feature)
2.3. Enhanced Features
Meets performance requirements in future WLP version (Effective from 01 June 2008)
ADC supports 24-bit PCM format and 192kHz sample rate recording
Supports secondary SPDIF-OUT converter to output digital audio to external HDMI transmitter
PCBEEP pass-through function is supported when Codec is in D3 power down mode
3rd jack detection pin for CD input, SPDIF output, and SPDIF input connector
Integrated high-pass filter to cancel DC offset generated from a digital microphone
Intel low power ECR compliant, supports power status control for each analog converter and pin
widget, supports jack detection and wake-up event in D3 mode
3. System Applications
Desktop multimedia PCs
Notebook PCs
Information appliances (IA) e.g., set-top box
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
4
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
4. Block Diagram
Figure 1. Block Diagram
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
5
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
4.1. Analog Input/Output Unit
Pin Complex widgets NID=14h~1Bh are re-tasking IO.
Left
A
R
EN_OBUF
EN_AMP
Right
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
EN_OBUF
EN_IBUF
Figure 2. Analog Input/Output Unit
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
6
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
5. Pin Assignments
5.1. ALC888S-VC2
36 35 34 33 32 31 30 29 28 27 26 25
PIN37-VREFO
AVDD2
SURR- L ( Port- A-L)
LINE1- R( Port-C-R)
LINE1- L ( Port-C-L)
MIC1- R( Port-B-R)
MIC1- L ( Port-B-L)
CD-R
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
JDREF
SURR- R( Port- A-R)
AVSS2
ALC888S
CD-GND
CENTER (Port-G-L)
LFE ( Port-G-R)
CD-L
MIC2- R ( Port-F-R)
MIC2- L ( Port-F-L)
SIDE-
(Port-H-L)
L
LLLLLLL GXXXCV
SIDE-R (Port-H-R)
SPDIFI/EAPD
SPDIFO
LINE2- R( Port-E-
LINE2- L ( Port-E-
R)
L)
Sense
A
1
2
3
5 7 8 9 10 11 12
6
4
Figure 3. ALC888S-VC (Version C) Pin Assignments
*Pin differences between the ALC888S-VC version and version B are listed in section 6.5, page 11.
5.2. Green Package and Version Identification
Green package is indicated by a ‘G’ as shown in Figure 3. The version number is shown in the location
marked ‘CV’. For example, ‘CV=C0’ indicates silicon version ‘C’ and stepping version ‘0’, which is the
first stepping of the ALC888S-VC.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
7
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
5.3. ALC888S (Version B)
36 35 34 33 32 31 30 29 28 27 26 25
PIN37-VREFO
AVDD2
SURR- L ( Port- A-L)
LINE1- R( Port-C-R)
LINE1- L ( Port-C-L)
MIC1- R( Port-B-R)
MIC1- L ( Port-B-L)
CD-R
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
JDREF
SURR- R( Port-A-R)
AVSS2
ALC888S
CD-GND
CENTER (Port-G-L)
LFE ( Port-G-R)
CD-L
MIC2- R ( Port-F-R)
MIC2- L ( Port-F-L)
SIDE-
(Port-H-L)
L
LLLLLLL GXXXBV
SIDE-R (Port-H-R)
SPDIFI/EAPD
SPDIFO
LINE2- R( Port-E-
R)
L)
LINE2- L ( Port-E-
Sense
A
1
3
6
10
7 8 9 11 12
2
5
4
Figure 4. ALC888S (Version B) Pin Assignment
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
8
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name
Type Pin Description
Characteristic Definition
Vt=0.5*DVDD
RESET#
SYNC
I
I
11 H/W Reset
10 Sample Sync (48kHz)
Vt=0.5*DVDD
BITCLK
SDATA-OUT
SDATA-IN
I
6
5
8
24MHz Bit Clock Input
Serial TDM Data Input
Serial TDM Data Output
Vt=0.5*DVDD
I
Vt=0.5*DVDDIO
O
Vt=0.5*DVDDIO, VOH=DVDDIO,
VOL=DVSS
SPDIFI /
EAPD
I/O
O
47 SPDIF Input /
Signal to Power Down External Amplifier
48 First SPDIF Output
VIL=1.45V, VIH=1.85V /
V
OH=DVDD, VOL=DVSS
Output has 12mA@75Ω driving capability
OH=DVDD, VOL=DVSS
SPDIFO
V
SPDIFO2
O
2
3
4
Secondary SPDIF Output for Digital
Audio Output to HDMI
Output has 12mA@75Ω driving capability
VOH=DVDD, VOL=DVSS
Input: Vt=(2/3)*DVDD
Output: VOH=DVDD, VOL=DVSS
Input: Vt=(2/3)*DVDD
GPIO0 /
DMIC-CLK
GPIO1 /
IO
IO
General Purpose Input/Output 0
Clock Output to Digital MIC
General Purpose Input/Output 1
Serial Data from Digital MIC
DMIC-DATA
Output: VOH=DVDD, VOL=DVSS
Total: 10 Pins
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Type Pin Description Characteristic Definition
Name
LINE2-L
LINE2-R
MIC2-L
IO
IO
IO
14 2nd Line Input Left Channel
15 2nd Line Input Right Channel
Analog input/output, default is input (JACK-E)
Analog input/output, default is input (JACK –E)
Analog input/output, default is input (JACK –F)
16
2
nd Stereo Microphone Input Left
Channel
nd Stereo Microphone Input Right Analog input/output, default is input (JACK –F)
Channel
MIC2-R
IO
17
2
CD-L
I
I
18 CD Input Left Channel
19 CD Input Reference Ground
20 CD Input Right Channel
Analog input, 1.6Vrms of full-scale input
Analog input, 1.6Vrms of full-scale input
Analog input, 1.6Vrms of full-scale input
Analog input/output, default is input (JACK –B)
CD-GND
CD-R
I
MIC1-L
IO
21 1st Stereo Microphone Input Left
Channel
MIC1-R
IO
22 1st Stereo Microphone Input Right
Channel
Analog input/output, default is input (JACK –B)
LINE1-L
LINE1-R
PCBEEP
IO
IO
I
23 1st Line Input Left Channel
24 1st Line Input Right Channel
12 External PCBEEP Input
Analog input/output, default is input (JACK –C)
Analog input/output, default is input (JACK –C)
Analog input, 1.6Vrms of full-scale input
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
9
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Name
Type Pin Description
Characteristic Definition
FRONT-L
FRONT-R
SURR–L
SURR–R
CENTER
LFE
IO
IO
IO
IO
O
35 Front Output Left Channel
Analog output (JACK –D)
36 Front Output Right Channel
39 Surround Out Left Channel
41 Surround Out Right Channel
43 Center Output
Analog output (JACK –D)
Analog output (JACK –A)
Analog output (JACK –A)
Analog output (JACK –G)
O
44 Low Frequency Output
45 Side Output Left Channel
46 Side Output Right Channel
13 Jack Detect Pin l
Analog output (JACK –G)
SIDE–L
SIDE–R
Sense A
O
Analog output (JACK –H)
O
Analog output (JACK –H)
I
Jack resistor network input 1 for port A/B/C/D
{39.2k, 20k, 10k, 5.1k} with 1% accuracy
Jack resistor network input 2 for port E/F/G/H
{39.2k, 20k, 10k, 5.1k} with 1% accuracy
Sense B
Sense C
I
I
34 Jack Detect Pin 2
33 Jack Detect Pin 3
Jack resistor network input 3 for CD, 1st SPDIF
Out, 2nd SPDIF Out, SPDIF-IN
{39.2k, 20k, 10k, 5.1k} with 1% accuracy
Total: 23 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
Type Pin Description
Name
Characteristic Definition
VREF
-
27 2.5V Reference Voltage
10µf capacitor to analog ground
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
2.5V/3.75V reference voltage
MIC1-VREFO-L
LINE1-VREFO
MIC2-VREFO
LINE2-VREFO
MIC1-VREFO-R
PIN37-VREFO
JDREF
O
O
O
O
O
O
-
28 Bias Voltage for MIC1 Jack
29 Bias Voltage for LINE1 Jack
30 Bias Voltage for MIC2 Jack
31 Bias Voltage for LINE2 Jack
32 Bias Voltage for MIC1 Jack
37 Bias Voltage for Software Select Jack 2.5V/3.75V reference voltage
40 Reference Resistor for Jack Detection 20K, 1% external resistor to analog ground
Total: 8 Pins
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
10
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
6.4. Power/Ground
Table 4. Power/Ground
Name
Type Pin Description
Characteristic Definition
AVDD1
AVSS1
AVDD2
AVSS2
DVDD
DVDD-IO
DVSS
I
I
I
I
I
I
I
25 Analog VDD
26 Analog GND
38 Analog VDD
42 Analog GND
Analog power for mixer and amplifier
Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital power for core
1
9
7
Digital VDD
Digital VDD
Digital GND
Digital IO power for HDA bus
Digital ground for HDA bus
Total: 7 Pins
6.5. Pin Differences: ALC888S-VC vs. ALC888S (Version B)
Table 5. Pin Difference: ALC888S-VC vs. ALC888S (Version B)
Pin Number
ALC888S-VC
ALC888S (Version B) Description for ALC888S-VC
Pin 2
SPDIFO2
GPIO0/DMIC-CLK/
SPDIFO2
Pin 2 is assigned as secondary SPDIF-OUT, not
shared with GPIO and digital microphone interface*1
GPIO0/DMIC-CLK is shifted to pin 3*2
Pin 3
Pin 4
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA
Sense C
GPIO1/DMIC-DATA
DVSS
GPIO1/DMIC-DATA is shifted to pin 4*3
Pin 33 is designed to support 3rd jack detect
Pin 33
AGPIO
*1: The secondary SPDIF output is default disabled and floated.
*2: Pin 3 is default configured as a GPI input. The clock output of the digital microphone is functional when the BIOS
program digital MIC port is enabled.
*3: Pin 4 is default defined as a GPI input. Data input to the digital microphone is functional when the BIOS program
digital MIC port is enabled. If the digital MIC function is not used, the ALC888S-VC is pin compatible with the ALC888S
B version, and can be mounted directly on a B version PCB layout.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
11
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7. High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 5 shows the basic concept of the HDA link protocol.
T
= 20.833 盜 (48KHz)
frame_sync
Previous Frame
BCLK
Next Frame
Frame SYNC= 8 BCLK
Stream 'A' Tag
(Here 'A' = 5)
Stream 'B' Tag
(Here 'B' = 6)
SYNC
SDO
SDI
Command Stream
(40-bit data)
Stream 'B' Data
Stream 'A' Data
Stream
'C' Tag
Stream 'C' Data
Response Stream
(36-bit data)
(n bytes + 10-bit data)
RST#
Figure 5. HDA Link Protocol
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
12
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.1.1.
Signal Definitions
Table 6. Link Signal Definitions
Item
Description
BCLK
SYNC
24.0MHz bit clock sourced from the HDA controller and connecting to all codecs.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 7. HDA Signal Definitions
Signal Name
BCLK
SYNC
SDO
Source
Controller
Type for Controller Description
Output
Output
Global 24.0MHz bit clock
Controller
Global 48kHz Frame Sync and outbound tag signal
Serial data output from controller
Controller
Output
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller
RST#
Controller
Output
Global active low reset signal
BCLK
8-Bit Frame SYNC
SYNC
Start of Frame
7
6
5
4
3
2
1
0
999 998 997 996995 994 993 992 991 990
SDO
SDI
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK
Controller samples SDI at rising edge of BCLK
Figure 6. Bit Timing
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
13
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 7 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 15 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 7 can be implemented concurrently in an HDA system. The
ALC888S-VC is designed to receive a single SDO stream.
SDI14
.
.
.
.
.
.
SDI13
SDI2
HDA
Controller
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
. . .
Codec 0
Codec 1
Codec 2
Codec N
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
Two SDOs
Multiple SDIs
Figure 7. Signaling Topology
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
14
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.2. Frame Composition
7.2.1.
Outbound Frame – Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be two blocks in the same stream to carry
96kHz samples (Figure 8).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 9).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams
Previous Frame
Next Frame
Frame SYNC
Stream 'A' Tag
(Here 'A' = 5)
Stream 'X' Tag
(Here 'X' = 6)
SYNC
SDO
Command Stream
0s
Stream 'A' Data
Stream 'X' Data
Padded at the
end of Frame
Null Field
One or multiple blocks in a stream
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples
..
.
Block 1
Block 2
Block Y
..
.
Sample 1 Sample 2
Sample Z
Z channels of PCM Sample
...
msb first in a sample
msb
lsb
Figure 8. SDO Outbound Frame
BCLK
SYNC
Stream Tag
msb lsb
1 0 1 0
Stream=10
(4-Bit)
Preamble
(4-Bit)
Data of Stream 10
7 6 5 4 3 2 1 0
Previous Stream
SDO
Figure 9. SDO Stream Tag is Indicated in SYNC
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
15
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.2.2.
Outbound Frame – Multiple SDOs
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines that the target codec supports multiple SDO
capability, it enables the ‘Stripe Control’ bit in the controller’s Output Stream Control Register to initiate
a specific stream (Stream ‘A’ in Figure 10) to be transmitted on multiple SDOs. In this case, the MSB of
the stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To ensure that all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 10. Striped Stream on Multiple SDOs
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
16
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.2.3.
Inbound Frame – Single SDI
An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), the SDI is driven by the codec at
each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 11).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 12).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Previous Frame
Frame SYNC
Next Frame
SYNC
SDI
0s
Stream 'X'
Response Stream
Stream 'A'
Null Field
Padded at the end of Frame
Stream Tag
Sample Block(s)
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
...
Block Y Null Pad
Block 1
Block 2
Sample 1 Sample 2
msb ...
...
Sample Z Z channels of PCM Sample
lsb msb first in a sample
Figure 11. SDI Inbound Stream
BCLK
SDI
n-Bit Sample Block
Null Pad
Next Stream
Stream Tag
Data Length in Bytes
B5 B4 B3 B2 B1
B8
Dn-1 Dn-2
0
0
B9
B7 B6
B0
D0
0
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 12. SDI Stream Tag and Data
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
17
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.2.4.
Inbound Frame – Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data into separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
Stream 'A'
SDI
Tag A
Data A
Response Stream
Stream 'X'
0s
Stream 'Y'
0s
0
Stream 'B'
Data B
SDI
Tag B
Response Stream
1
Stream A, B, X, and Y are independent and have separate IDs
Codec drives SDI0 and SDI1
Figure 13. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 8, page 19, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 9, page 19, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no
sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery
rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
18
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame
AND interleave an empty frame between non-empty frames (Table 10, page 20).
Table 8. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base
44.1kHz Base
1/6
1/4
1/3
1/2
2/3
1
8kHz (1 sample block every 6 frames)
-
12kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
-
11.025kHz (1 sample block every 4 frames)
-
22.05kHz (1 sample block every 2 frames)
-
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
44.1kHz (1 sample block per frame)
88.2kHz (2 sample blocks per frame)
176.4kHz (4 sample blocks per frame)
2
4
Table 9. 48kHz Variable Rate of Delivery Timing
Rate
8kHz
Delivery Cadence
YNNNNN (repeat)
YNNN (repeat)
YNN (repeat)
Y2NN (repeat)
Y (repeat)
Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame
12kHz
16kHz
32kHz
48kHz
96kHz
192kHz
Y2 (repeat)
Y4 (repeat)
N: No sample block in a frame.
Y: One sample block in a frame.
Yx: X sample blocks in a frame
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
19
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Table 10. 44.1kHz Variable Rate of Delivery Timing
Delivery Cadence
Rate
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz
88.2kHz
174.4kHz
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz
12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no
sample block.
88.2kHz
122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no
sample block.
174.4kHz 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no
sample block.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
20
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.3. Reset and Initialization
There are two types of reset within an HDA link:
• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state
• Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state
An initialization sequence is requested after any of the following three events:
1. Link Reset
2. Codec Reset
3. Codec changes its power state (for example, hot docking a codec to an HDA system)
7.3.1.
Link Reset
A link reset may be caused by 3 events:
1. The HDA controller asserts RST# for any reason (power up, or PCI reset)
2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA
controller
3. Software initiates power management sequences. Figure 14, page 22, shows the ‘Link Reset’ timing
including the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)
Enter ‘Link Reset’:
n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a
link reset
o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at
the end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
21
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Exit from ‘Link Reset’:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
100µsec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
last bit of frame SYNC, it means the codec requests an initialization sequence)
>=100 usec >= 4 BCLK
Initialization Sequence
Previous Frame
4 BCLK
4 BCLK
Link in Reset
BCLK
SYNC
SDOs
SDIs
Normal Frame
SYNC
Normal Frame
SYNC is absent
Driven Low
Pulled Low
2
8
Driven Low
Driven Low
Pulled Low
Pulled Low
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 14. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence will not
be requested. In the extended power state, a function reset cannot initialize the register setting in power
state D3. The Host SW needs to send a ‘double function reset’ to reset all settings.
7.3.3.
Double Function Reset
Double Function Reset is executed by sending two Function Group resets back to back. This Function
Group ‘Double’ reset shall do a full initialization and reset all settings to their power on defaults. This
Double Reset is defined as two Function Group Reset verbs received without any other intervening valid
verbs. The reset verbs are not required to be received in sequential frames, but there must not be any other
verbs received in frames between the consecutive Function Group Reset verbs. It is allowed that there are
several null commands received in frames between Function Group Reset verbs.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
22
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.3.4.
Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec will stop driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operation state
Turnaround Frame
(Non-48kHz Frame)
Address Frame
(Non-48kHz Frame)
Exit from Reset Connection Frame
Normal Operation
BCLK
Frame SYNC
SYNC
Frame SYNC
Frame SYNC
5
4
6
Response
SDIx
SD14
SD0 SD1
3
1
2
7
8
RST#
Codec
Drives SDIx
Codec
Controller Drives SDIx
Codec Drives SDIx
Controller
Turnaround
(477 BCLK
Max.)
Turnaround
( 477 BCLK
Max.)
Figure 15. Codec Initialization Sequence
7.4. Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 11 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 12 is the 12-bit verb structure that gets and
controls parameters in the codec.
Table 11. 40-Bit Commands in 4-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Bit [15:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
Table 12. 40-Bit Commands in 12-Bit Verb Format
Bit [39:32]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Bit [7:0]
Reserved
Codec Address
Node ID
Verb ID
Payload
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
23
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Table 13. Supported Commands
Supported Verb
Get parameter
F00
F01 701
F02
-
Y
-
Y
-
-
-
-
-
-
-
-
-
-
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
-
Y
-
Y
-
Connection Select
Get Connection List
Entry
-
-
-
-
Y
-
-
-
-
Processing State
Coefficient Index
Processing Coefficient
Amplifier Gain/Mute
Stream Format
F03 703
D-- 5--
C-- 4--
B-- 3--
A-- 2--
F0D 70D
F0D 70E
F05 705
F06 706
F04 704
F07 707
F08 708
F09 709
F0C 70C
F10- 710-
F1A 71A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
-
Y
-
Y
-
-
-
Y
Y
Y
-
-
-
Digital Converter 1
Digital Converter 2
Power State
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
Channel / Stream ID
SDI Select
Y
-
Y
-
-
-
-
-
-
-
-
-
-
Pin Widget Control
Unsolicited Enable
Pin Sense
-
-
-
Y
Y
Y
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
EAPD / BTL Enable
All GPIO Control
-
-
-
-
-
-
-
-
-
-
-
-
-
Beep Generator Control F0A 70A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
Volume Knob Control
Subsystem ID, Byte 0
Subsystem ID, Byte 1
Subsystem ID, Byte 2
Subsystem ID, Byte 3
Config Default, Byte 0
Config Default, Byte 1
Config Default, Byte 2
Config Default, Byte 3
RESET
F0F 70F
F20 720
F20 721
F20 722
F20 723
F1C 71C
F1C 71D
F1C 71E
F1C 71F
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
7FF
Y
-
*1: The ALC888S does not support Modem/HDMI/Vendor groups and Power State widgets.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
24
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Table 14. Supported Parameters
Supported Parameter
Vendor ID
00
02
04
05
08
09
0A
0B
0C
0D
12
0E
0F
10
11
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Revision ID
Subordinate Node Count
Function Group Type
Audio Function Group Capabilities
Audio Widget Capabilities
Sample Size, Rate
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
-
Y
Y
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
-
Y
Y
-
Stream Formats
-
-
-
-
-
-
-
-
Pin Capabilities
-
Y
-
-
-
-
-
-
-
Input Amp Capabilities
Output Amp Capabilities
Connection List Length
Supported Power States
Processing Capabilities
GPI/O Count
-
-
-
Y
-
Y
Y
Y
Y
-
Y
-
-
-
-
-
-
-
-
Y
Y
Y
-
-
-
-
-
-
-
-
Y
Y
-
Y
Y
-
-
-
-
-
-
Y
-
Y
-
-
-
-
Y
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Volume Knob Capabilities
13
-
-
-
-
-
-
-
-
-
-
-
*1: The ALC888S does not support Modem/HDMI/Vendor groups and Power State widgets.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
25
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Table 15. Solicited Response Format
Bit [35]
Bit [34]
Bit [33:32]
Bit [31:0]
Valid
Unsol=0
Reserved
Response
Table 16. Unsolicited Response Format
Bit [35]
Valid
Bit [34]
Unsol=1
Bit [33:32]
Bit [31:28]
Tag
Bit [27:0]
Reserved
Response
Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit
field. Bit-35 is a ‘Valid’bit to indicate the response is ‘Ready’. Bit-34 is set to indicate that an unsolicited
response was sent.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
26
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
7.5. Power Management
The ALC888S-VC does not support Wake-Up events when in low power mode. All power management
state changes in widgets are driven by software. Table 17 shows the System Power State Definitions.
In the ALC888S-VC, all the widgets, including output/input converters, support power control. Software
may have various power states depending on system configuration.
Table 18 indicates those nodes that support power management. To simplify power control, software can
configure whole codec power states through the audio function (NID=01h). Output converters (DACs)
and input converters (ADCs) have no individual power control to supply fine-grained power control.
Table 17. System Power State Definitions
Power States Definitions
D0
D1
All power on. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up.
D2
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference is off (D1 + analog reference off).
D3 (Hot)
Power still supplied. The codec stops the internal clock. State is maintained.
All Power removed. State lost.
D3 (Cold)
Table 18. Power Controls in NID 01h
Item
Description
D0
D1
Normal
PD
D2
Normal
PD
D3
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Link Reset
PD
Audio Function LINK Response
(NID=01h)
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Front DAC
PD
Surr DAC)
PD
PD
PD
Cen/Lfe DAC
Side DAC
PD
PD
PD
PD
PD
PD
Fout DAC
PD
PD
PD
LINE ADC
PD
PD
PD
MIX ADC
PD
PD
PD
All Headphone Drivers
All Mixers
Normal
Normal
Normal
PD
Normal
Normal
Normal
PD
All Reference
PD
Note: PD=Powered Down
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
27
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Table 19. Powered Down Conditions
Condition
Description
LINK Response powered down
Internal clock is stopped. SDATA-IN and SPDIF-OUT are floated with pulled low
47K resistors internally. SPDIF-IN is also floated. Detection of ‘Link Reset Entry’
and ‘Link Reset Exit’ sequences are supported. All states are maintained if DVDD
is supplied
Front DAC powered down
Surr DAC powered down
CEN/LFE DAC powered down
SIDESURR DAC powered down
Fout DAC powered down
LINE ADC powered down
MIX ADC powered down
Headphone Driver powered down
Mixers powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
All headphone drivers are powered down
All internal mixer widgets are powered down. The DC reference and VREFOUTx
at individual pin complexes are still alive
Reference power down
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
7.5.1.
ALC888S-VC Additional Power Features
The ALC888S-VC is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B
compliant. It meets the five attributes discussed in the white paper:
1. D3 state power < 30mW.
2. Exit latency (D3 to D0 transfer) < 10ms.
3. Audio pop/click suppression during D3 and D0 transition < -65dBV.
4. Supports Jack detection in D3 state.
5. D3 functions with or without the BITCLK
The ALC888S-VC minimizes D3 state idle mode power consumption and increases overall battery life in
mobile systems.
In D3 mode, only a power on reset or a ‘double function reset’ resets all ALC888S-VC settings, cutting
software configuration time spent entering/leaving D3 state, and reducing latency time for D3 to D0
transitions.
The ALC888S-VC supports Wake-Up events in D3 mode, including jack detection and GPIO status
changes. If the HDA-Link was alive (with BCLK), the ALC888S-VC Wake-Up response is as normal. If
no BITCLK is present, the ALC888S-VC drives the SDI high in order to wake up the system
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
28
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8. Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC888S-VC. If a
verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1. Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget.
Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
to get detailed information about supported parameters.
Table 20. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 21. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
Description
31:16
15:0
Vendor ID=10ECh (Realtek’s PCI vendor ID)
Device ID=0888h
Note: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 22. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC888S-VC is fully
compliant
19:16
15:8
7:0
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC888S-VC is fully
compliant
Revision ID. The vendor’s revision number.
00h is for ALC888, 01h is for ALC888S, 02h is for ALC888S-VC, etc.
Stepping ID. The vendor’s stepping number within the given Revision ID
Note: The Root Node (NID=00h in the ALC888S-VC) supports this parameter.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
29
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.3.
Parameter – Subordinate Node Count (Verb ID=F00h,
Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node. For function group nodes, it provides the total number of widgets
associated with this function node.
Table 23. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24 Reserved. Read as 0’s.
23:16 Starting Node Number.
The starting node number in the sequential widgets
15:8 Reserved. Read as 0’s.
7:0
Total Number of Nodes. For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group
8.1.4.
Parameter – Function Group Type (Verb ID=F00h,
Parameter ID=05h)
Table 24. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
Description
31:9 Reserved. Read as 0’s.
8
UnSol Capable.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
7:0
Function Group Type.
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
Note: The Audio Function Group (NID=01h) supports this parameter.
8.1.5.
Parameter – Audio Function Capabilities (Verb ID=F00h,
Parameter ID=08h)
Table 25. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
Description
31:17 Reserved. Read as 0’s.
16
Beep Generator. A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12 Reserved. Read as 0’s.
11:8 Input Delay.
7:4
3:0
Reserved. Read as 0’s.
Output Delay.
Note: The Audio Function Group (NID=01h) supports this parameter.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
30
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.6.
Parameter – Audio Widget Capabilities (Verb ID=F00h,
Parameter ID=09h)
Table 26. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
23:20
Reserved. Read as 0’s
Widget Type
0h: Audio Output
3h: Selector
6h: Volume Knob Widget
1h: Audio Input
4h: Pin Complex
7h~Eh: Reserved
2h: Mixer
5h: Power Widget
Fh: Vendor defined audio widget
19:16
15:11
10
Delay. Samples delayed between the HDA link and widgets
Reserved. Read as 0’s
Power Control
0: Power state control is not supported on this widget
1: Power state is supported on this widget
Digital
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (SPDIF, I2S, etc.)
ConnList. Connection List
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
UnsolCap. Unsolicited Capable
0: Unsolicited response is not supported
1: Unsolicited response is supported
ProcWidget. Processing Widget
0: No processing control
9
8
7
6
1: Processing control is supported
Reserved. Read as 0
5
4
3
2
1
0
Format Override
AmpParOvr, AMP Param Override
OutAmpPre. Out AMP Present
InAmpPre. In AMP Present
Stereo
0: Mono Widget
1: Stereo Widget
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
31
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.7.
Parameter – Supported PCM Size, Rates (Verb ID=F00h,
Parameter ID=0Ah)
Parameters here provide default information about formats. Individual converters have their own
parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 27. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
31:21
20
Description
Reserved. Read as 0’s
B32. 32-bit audio format support
0: Not supported
1: Supported
1: Supported
1: Supported
1: Supported
1: Supported
19
18
17
16
B24. 24-bit audio format support
0: Not supported
B20. 20-bit audio format support
0: Not supported
B16. 16-bit audio format support
0: Not supported
B8. 24-bit audio format support
0: Not supported
15:12
11
Reserved. Read as 0’s
R12. 384kHz (=8*48kHz) rate support
0: Not supported
1: Supported
10
9
8
7
6
5
4
3
2
1
0
R11. 192kHz (=4*48kHz) rate support
0: Not supported
1: Supported
R10. 176.4kHz (=4*44.1kHz) rate support
0: Not supported
1: Supported
R9. 96kHz (=2*48kHz) rate support
0: Not supported
1: Supported
R8. 88.2kHz (=2*44.1kHz) rate support
0: Not supported
1: Supported
R7. 48kHz rate support
0: Not supported
1: Supported
1: Supported
R6. 44.1kHz rate support
0: Not supported
R5. 32kHz (=2/3*48kHz) rate support
0: Not supported
1: Supported
R4. 22.05kHz (=1/2*44.1kHz) rate support
0: Not supported
1: Supported
R3. 16kHz (=1/3*48kHz) rate support
0: Not supported
1: Supported
R2. 11.025kHz (=1/4*44.1kHz) rate support
0: Not supported
1: Supported
R1. 8kHz (=1/6*48kHz) rate support
0: Not supported
1: Supported
32
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.8.
Parameter – Supported Stream Formats (Verb ID=F00h,
Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 28. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
31:3
2
Description
Reserved. Read as 0’s
AC3
0: Not supported
1: Supported
1: Supported
1: Supported
1
0
Float32
0: Not supported
PCM
0: Not supported
Note: Input converters and output converters support this parameter.
8.1.9.
Parameter – Pin Capabilities (Verb ID=F00h,
Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 29. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
31:16
15:8
Description
Reserved. Read as 0’s
VREF Control Capability. ‘1’ in corresponding bit field indicates signal levels of associated Vrefout are
specified as a percentage of AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
L-R Swap. Indicates the capability of swapping the left and rights
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is anything plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sense on the attached device to determine its type
Note: Only Pin Complex widgets support this parameter.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
33
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h,
Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 30. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
31
Description
(Input) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
15
Reserved. Read as 0
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
7
Reserved. Read as 0
Offset
6:0
Indicates which step is 0dB
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h,
Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 31. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
31
Description
(Output) Mute Capable
30:23
22:16
Reserved. Read as 0
Step Size
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
‘0’ indicates a step of 0.25dB. ‘127’ indicates a step of 32dB
Reserved. Read as 0
15
14:8
Number of Steps
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed
Reserved. Read as 0
7
6:0
Offset. Indicates which step is 0dB
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
34
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.12. Parameter – Connect List Length (Verb ID=F00h,
Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 32. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
31:8
7
Description
Reserved. Read as 0
Short Form
0: Short Form
1: Long Form
6:0
Connect List Length
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input,
and there is no Connection Select Control (Not a MUX widget)
8.1.13. Parameter – Supported Power States (Verb ID=F00h,
Parameter ID=0Fh)
Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
31:4
3
Description
Reserved. Read as 0’s
D3Sup
1: Power state D3 is supported
2
1
0
D2Sup
1: Power state D2 is supported
D1Sup
1: Power state D1 is supported
D0Sup
1: Power state D0 is supported
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h,
Parameter ID=10h)
Table 34. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
31:16
15:8
7:1
Description
Reserved. Read as 0’s
NumCoeff. Number of Coefficient
Reserved. Read as 0’s
0
Benign
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
35
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h,
Parameter ID=11h)
Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0
The ALC888S-VC does not support GPIO wake up function
GPIUnsol=1
30
The ALC888S-VC supports GPIO unsolicited response
Reserved. Read as 0’s
29:24
23:16
NumGPIs=00h
No GPI pin is supported
NumGPOs=00h
No GPO pin is supported
NumGPIOs=02h
15:8
7:0
Three GPIO pins are supported
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h,
Parameter ID=13h)
Table 36. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
31:8
7
Description
Reserved. Read as 0’s
Delta
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
NumSteps
6:0
The number of steps in the range of the Volume Control Knob
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
36
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.2. Verb – Get Connection Select Control (Verb ID=F01h)
Table 37. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for Analog Port-A/B/C/D/E/F/G/H
Bit
31:8
7:0
Description
0’s
Connection Index Currently Set (Default value is 00h)
00h: Sum Widget NID=0Ch
02h: Sum Widget NID=0Eh
04h: Sum Widget NID=26h
01h: Sum Widget NID=0Dh
03h: Sum Widget NID=0Fh
Other: Reserved
Codec Response for first Digital Pin SPDIF-OUT 1Eh
Bit
31:8
7:0
Description
0’s
Connection Index Currently Set (Default value is 00h)
00h: Digital Converter (SPDIF-OUT) NID=06h
Other: Reserved
Codec Response for second Digital Pin SPDIF-OUT 11h
Bit
31:8
7:0
Description
0’s
Connection Index Currently Set (Default value is 00h)
00h: Digital Converter (SPDIF-OUT) NID=10h
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
8.3. Verb – Set Connection Select (Verb ID=701h)
Table 38. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=701h
Select Index [7:0]
0’s for all nodes
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
37
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.4. Verb – Get Connection List Entry (Verb ID=F02h)
Table 39. Verb – Get Connection List Entry (Verb ID=F02h)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F02h
Offset Index - N[7:0]
32-bit Response
Codec Response for NID=08h (LINE ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 23h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=09h (MIX ADC)
Bit
Description
15:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 22h (Sum Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Ah (SPDIF-IN Converter)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1)
Returns 000000h
7:0
Connection List Entry (N)
Returns 1Fh (SPDIF-IN Pin Widget) for N=0~3
Returns 00h for N>3
Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
Returns 00h for N>7
23:16
15:8
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
7:0
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
38
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
Returns 00h for N>3
Connection List Entry (N)
Returns 02h (Front DAC) for N=0~3
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
Returns 00h for N>3.
Connection List Entry (N)
Returns 03h (Surround DAC) for N=0~3
Codec Response for NID=0Eh (Cen/Lfe Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
Returns 00h for N>3
Connection List Entry (N)
Returns 04h (Cen/Lfe DAC) for N=0~3
Codec Response for NID=0Fh (Side-Surr Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
Returns 00h for N>3
Connection List Entry (N)
Returns 05h (Front DAC) for N=0~3
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
39
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Codec Response for NID=26h (Fout Sum)
Bit
Description
31:24
Connection List Entry (N)
Returns 00h
23:16
15:8
Connection List Entry (N+2)
Returns 00h
Connection List Entry (N+1)
Returns 0Bh (Mixer) for N=0~3
Returns 00h for N>3
7:0
Connection List Entry (N)
Returns 25h (Fout1 DAC) for N=0~3
Returns 00h for N>3
Codec Response for NID=14h~1Bh (Port-A to port-H)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 0Fh (Sum Widget NID=0Fh) for N=0~3
Returns 00h for n>3
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3
Returns 00h for N>3
Connection List Entry (N+1)
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3
Returns 00h for N>3
Connection List Entry (N)
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3
Returns 26h (Sum Widget NID=26h) for N=4~7
Returns 00h for N>7
Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT)
Bit
Description
31:16
Connection List Entry (N+3) and (N+2)
Returns 0000h
15:8
7:0
Connection List Entry (N+1)
Returns 00h
Connection List Entry (N)
Returns 06h (SPDIF-OUT converter) for N=0~3
Returns 00h for N>3
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
40
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Codec Response for NID= 22h/23h/ (Sum Widget before MIX/LINE ADCs)
Bit
Description
31:24
Connection List Entry (N+3)
Returns 1Bh (Pin Complex – LINE2) for N=0~3
Returns 15h (Pin Complex-SURR) for N=4~7
Returns 00h for N>7
23:16
15:8
7:0
Connection List Entry (N+2)
Returns 1Ah (Pin Complex – LINE1) for N=0~3
Returns 14h (Pin Complex – FRONT) for N=4~7
Returns 0Bh (Sum Widget) for N=8~11
Returns 00h for N>11
Connection List Entry (N+1)
Returns 19h (Pin Complex – MIC2) for N=0~3
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7
Returns 17h (Pin Complex – SIDESURR) for N=8~11
Returns 00h for N>11
Connection List Entry (N)
Returns 18h (Pin Complex – MIC1) for N=0~3
Returns 1Ch (Pin Complex – CD) for N=4~7
Returns 16h (Pin Complex – CEN/LFE) for N=8~11
Returns 00h for N>11
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
8.5. Verb – Get Processing State (Verb ID=F03h)
Table 40. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F03h
0’s
32-bit response
Codec Response for All NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
41
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.6. Verb – Set Processing State (Verb ID=703h)
Table 41. Verb – Set Processing State (Verb ID=703h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=703h
Processing State [7:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
8.7. Verb – Get Coefficient Index (Verb ID=Dh)
Table 42. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=Dh
0’s
Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Coefficient Index
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
8.8. Verb – Set Coefficient Index (Verb ID=5h)
Table 43. Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
42
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.9. Verb – Get Processing Coefficient (Verb ID=Ch)
Table 44. Verb – Get Processing Coefficient (Verb ID=Ch)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=Ch
0’s
Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Registers)
Bit
31:16
15:0
Description
Reserved. Read as 0’s
Processing Coefficient
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 45. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
43
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 46. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
CAd=X
Node ID=Xh
Verb ID=Bh
‘Get’ payload [15:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14
13
Reserved. Read as 0.
Get Left/Right
0: Right amplifier gain is requested
1: Left amplifier gain is requested
12:4
3:0
Reserved. Read as 0’s
Index[3:0] for Input Source
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored
Codec Response for 08h (LINE ADC) and 09h (MIX ADC)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –16.5B~+30dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0. (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
44
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
Codec Response for NID=0Ch~0Fh (Sum Widget: Front, Surr, CenLfe, SideSurr)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute 1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0. (No Input Amplifier Gain)
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –46.5dB~0dB in 1.5dB steps.
Codec Response for NID=14h~1Bh (Pin Complex: Front, Surr, CenLfe, SideSurr, MIC1, MIC2, LINE1, LINE2)
Bit
31:8
7
Description
0’s
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0:Unmute
1:Mute (NID=14h~1Bh,Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0’s
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 47. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh
Verb ID=3h
‘Set’ payload [7:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
15
Description
Set Output Amp. ‘1’ indicates output amplifier gain will be set
Set Input Amp. ‘1’ indicates input amplifier gain will be set
Set Left Amp. ‘1’ indicates left amplifier gain will be set
Set Right Amp. ‘1’ indicates right amplifier gain will be set
Index Offset (for input amplifiers on Sum widgets and Selector Widgets)
14
13
12
11:8
5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not set
7
Mute
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0]. A 7-bit step value specifying the amplifier gain.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
45
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Table 48. Verb – Get Converter Format (Verb ID=Ah)
Codec Response Format
Get Command Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Verb ID=Ah
0’s
Bit[15:0] are converter format
Codec Response for NID=02h~06h, 10h, 25h (Output Converters: Front, Surr, Cen/Lfe, SideSurr, 1st SPDIF-OUT, 2nd
SPDIF-OUT, Fout DAC).
Codec Response for NID=08h~0Ah (Input Converters: LINE, MIX DAC, and SPDIF-IN)
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2
Sample Base Rate Divisor (DIV)
1: 44.1kHz
13:11
10:8
010b: *3
011b: *4
011b: /4
100b~111b: Reserved
100b: /5
000b: /1
101b: /6
001b: /2
110b: /7
010b: /3
111b: /8
The ALC888S-VC does not support Divisor. Always read as 000b
Reserved. Read as 0.
7
6:4
Bits per Sample (BITS)
000b: 8 bits
101b~111b: reserved
Number of Channels
001b: 16 bits
010b: 20 bits
2: 3 channels
011b: 24 bits
………
100b: 32 bits
3:0
0: 1 channel
1: 2 channels
15: 16 channels
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
46
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.14. Verb – Set Converter Format (Verb ID=2h)
Table 49. Verb – Set Converter Format (Verb ID=2h)
Codec Response Format
Set Command Format
Bit [31:28]
CAd=X
Bit [27:20]
Node ID=Xh
Bit [19:16]
Verb ID=2h
Payload Bit [15:0]
Set format [15:0]
Response [31:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
31:16
15
Description
Reserved. Read as 0
Stream Type (TYPE)
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE)
0: 48kHz
Sample Base Rate Multiple (MULT)
000b: *1 001b: *2 010b: *3
Sample Base Rate Divisor (DIV)
1: 44.1kHz
13:11
10:8
011b: *4
100b~111b: Reserved
000b: /1
100b: /5
001b: /2
101b: /6
010b: /3
110b: /7
011b: /4
111b: /8
7
Reserved. Read as 0
6:4
Bits per Sample (BITS)
000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits
Number of Channels
101b~111b: Reserved
3:0
0: 1 channel 1: 2 channels 2: 3 channels ………
15: 16 channels
8.15. Verb – Get Power State (Verb ID=F05h)
Table 50. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h
Verb ID=Ah
0’s
Power State [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set
Reserved. Read as 0’s
3:2
1:0
PS-Set, Set Power State [1:0]
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Set controls the current power setting of the referenced node
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
47
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.16. Verb – Set Power State (Verb ID=705h)
Table 51. Verb – Set Power State (Verb ID=705h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=705h
Power State [7:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
7:6
5:4
Description
Reserved. Read as 0’s
PS-Act. Actual Power State [1:0]
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
Reserved. Read as 0’s
3:2
1:0
PS-Set. Set Power State [1:0]
00: Power state is D0
10: Power state is D2
01: Power state is D1
11: Power state is D3
8.17. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 49. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~06h, 10h, 25h (Output Converters: Front, Surr, Cen/Lfe, SideSurr, 1st SPDIF-OUT, 2nd
SPDIF-OUT, Fout DAC)
Codec Response for NID=08h~0Ah (Input Converters: LINE ADC, MIX DAC, and SPDIF-IN)
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
Channel[3:0]
3:0
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
48
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.18. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 52. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=706h
Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
31:8
7:4
Description
Reserved. Read as 0’s
Set Stream[3:0]
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0
Set Channel[3:0]
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel
Note: This verb assigns stream and channel for output converters (NID=02h~06h 10h, 25h) and input converters
(NID=08h~0Ah). Other widgets will ignore this verb.
8.19. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 53. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F07h
0’s
Pin Control [7:0]
Codec Response for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh
(Pin Complex: Front, Surr, CenLfe, SideSurr, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, 1st SPDIF-OUT, 2nd
SPDIF-OUT and SPDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit)
0: Disabled
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit)
0: Disabled 1: Enabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
1: Enabled
6
5
0: Disabled
1: Enabled
4:
Reserved
2:0
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
010b: Ground 0V
001b: 50% of AVDD
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
Codec Response for other NID
Bit
Description
Not Supported (returns 00000000h)
31:0
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
49
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.20. Verb – Set Pin Widget Control (Verb ID=707h)
Table 54. Verb – Set Pin Widget Control (Verb ID=707h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=707h
Pin Control [7:0]
0’s for all nodes
‘Pin Control’ in command [7:0] for NID=14h~1Bh, 1Ch, 1Dh, 1Eh, 11h, 1Fh: (Pin Complex: Front, Surr, CenLfe,
SideSurr, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, 1st SPDIF-OUT, 2nd SPDIF-OUT and SPDIF-IN)
Bit
31:1
7
Description
Reserved. Read as 0’s
H-Phn Enable
0: Disabled
1: Enabled
1: Enabled
6
5
Out Enable
0: Disabled
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit)
0: Disabled
1: Enabled
4:
Reserved
2:0
VrefEn (Vrefout Enable Control)
000b: Hi-Z (Disabled)
011b: Reserved
001b: 50% of AVDD
100b: 80% of AVDD)
010b: Ground 0V
101b: 100% of AVDD
110b~111b: Reserved
8.21. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real-time event.
Table 55. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s
Unsolicited Response is Enabled
0: Disabled
1: Enabled
6:4
3:0
Reserved. Read as 0’s
Assigned Tag for Unsolicited Response
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
50
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.22. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 56. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit[7:0] for NID=01h (GPIO), 14h~1Bh (Port A to H)
Bit
31:8
7
Description
Reserved. Read as 0’s
Enable Unsolicited Response
0: Disable
1: Enable
6:4
3:0
Reserved. Read as 0’s
Tag for Unsolicited Response
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses
8.23. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 57. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F09h
0’s
32-bit Response
Codec Response for NID = 14h~1Bh, 1Eh, 1Fh
Bit
Description
31
Presence Detect Status
0: No device is attached to the pin
1: Device is attached to the pin
Measured Impedance
30:0
The ALC888S does not support hardware impedance detection. This field is read as 0’s.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h)
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
51
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.24. Verb – Execute Pin Sense (Verb ID=709h)
Table 58. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0]
Bit
7:1
0
Description
Reserved. Read as 0’s
Right (Ring) Channel Select
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC888S does not support hardware impedance sensing and will ignore this control.
8.25. Verb – Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 59. Verb – Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=14h, 15h, 16h, 17h, 18h, 19h, 1Ah, 1Bh, 1Eh, 11h and 1Fh
Bit
Description
31:0
32-bit configuration information for each pin widget
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
52
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.26. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 60. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=71Ch,
Label [7:0]
0’s for all nodes
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~1Bh, 1Eh, 11h, and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.27. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 61. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Node ID=Xh
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID= F1Bh
0’s
Divider [7:0]
‘Response’ for NID=01h (Audio Function Group)
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
53
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.28. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 62. Verb – Set BEEP Generator (Verb ID= 70Ah)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=71Bh
Divider [7:0]
0’s for all nodes
‘Divider’ in Set Command
Bit
31:8
7:0
Description
Reserved
Frequency Divider, F[7:0]
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0]
The lowest tone is 48kHz/(255*4)=47Hz
The highest tone is 48kHz/(1*4)=12kHz
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.29. Verb – Get GPIO Data (Verb ID=F15h)
Table 63. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=F15h
0’s
32-bit Response
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Data. Not supported in the ALC888S-VC
GPIO[1:0] Data
1:0
The value written (output) or sensed (input) on the corresponding pin if it is enabled
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
54
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.30. Verb – Set GPIO Data (Verb ID=715h)
Table 64. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=715h
Data [7:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Output Data. Not supported in the ALC888S-VC
GPIO[1:0] Output Data
1:0
The value written determines the value driven on a pin that is configured as an output pin
Codec Response for All NID
Bit
Description
31:0
0’s
8.31. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 65. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F16h
0’s
EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
Reserved
1:0
GPIO[1:0] Enable Mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
55
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.32. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 66. Verb – Set GPIO Enable Mask (Verb ID=716h)
Codec Response Format
Set Command Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=716h
Enable Mask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Enable Mask. Not supported in the ALC888S-VC
GPIO[1:0] Enable Mask
1:0
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s
8.33. Verb – Get GPIO Direction (Verb ID=F17h)
Table 67. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC888S-VC
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
56
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.34. Verb – Set GPIO Direction (Verb ID=717h)
Table 68. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Direction Control. Not supported in the ALC888S-VC
GPIO[1:0] Direction Control
1:0
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.35. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 69. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F19h
0’s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VC
GPIO[1:0] Unsolicited Enable Mask
1:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
57
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.36. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 70. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=719h
UnsolEnable [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
31:8
7:2
Description
Reserved
GPIO[7:2] Unsolicited Enable Mask. Not supported in the ALC888S-VC
GPIO[1:0] Unsolicited Enable Mask
1:0
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’and Verb-‘Unsolicited
Response’for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s
8.37. Verb – Function Reset (Verb ID=7FFh)
Table 71. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=01h Verb ID=7FFh
0’s
Codec Response
Bit
Description
Reserved. Read as 0’s
31:0
Note: The Function Reset command causes all widgets in the ALC888S-VC to return to their power on default state.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
58
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.38. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID= F0Dh, F0Eh)
Table 72. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh Verb ID=F0Dh/F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h and 10h (1st and 2nd SPDIF-OUT) Response to ‘Get verb’ – F0Dh (Control 1 for SIC bit[15:0])
NID=06h and 10h (1st and 2nd SPDIF-OUT) Response to ‘Get verb’ – F0Eh (Control 2 for SIC bit[15:0])
Bit
31:16
15
Description – SIC (SPDIF IEC Control) Bit[7:0]
Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
PRO (Professional or Consumer Format)
0: Consumer format
6
1: Professional format
5
4
3
/AUDIO (Non-Audio Data Type)
0: PCM data
1: AC3 or other digital non-audio data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-Emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
2
1
0
0: OFF
1: ON
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
59
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
NID=0Ah (SPDIF-IN) Response to ‘Get verb (F0Dh)
NID=0Ah (SPDIF-IN) Response to ‘Get verb (F0Eh)
Bit
31:16
15
Description (part of SPDIF-IN Channel Status)
Reserved. Read as 0’s
Reserved. Read as 0’s
14:8
7
CC[6:0] (Category Code)
LEVEL (Generation Level)
6
PRO (Professional or Consumer Format)
0: Consumer format
/AUDIO (Non-Audio Data Type)
0: PCM data
1: Professional format
1: AC3 or other digital non-audio data
5
4
3
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-Emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
Reserved
In‘V’alid. V Bit in Sub-Frame of SPDIF-IN
0: Data X and Y are valid, or SPDIF-IN is not locked
1: At least one of data X and Y is invalid
Digital Enable. DigEn
0
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
60
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.39. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 73. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Xh, Set Control 1)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
Set Command Format (Verb ID=70Yh, Set Control 2)
Codec Response Format
Response [31:0]
0’s
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=Xh Verb ID=70Eh
SIC [15:8]
‘Payload’ in Set Control 1 for NID=06h and 10h (1st and 2nd SPDIF-OUT)
Bit
7
Description – SIC (SPDIF IEC Control) Bit[7:0]
LEVEL (Generation Level)
6
PRO (Professional or Consumer Format)
0: Consumer format
1: Professional format
1: AC3 or other digital non-audio data
5
4
3
/AUDIO (Non-Audio Data Type)
0: PCM data
COPY (Copyright)
0: Asserted
1: Not asserted
PRE (Pre-Emphasis)
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
1
0
VCFG for Validity Control (control V bit and data in Sub-Frame)
V for Validity Control (control V bit and data in Sub-Frame)
Digital Enable. DigEn
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h and 10h (1st and 2nd SPDIF-OUT)
Bit
7
Description – SIC (SPDIF IEC Control) Bit[7:0]
Reserved. Read as 0’s
6:0
CC[6:0] (Category Code)
‘Payload’ in Set Control 1 for NID=0Ah (SPDIF-IN)
Bit
7:1
0
Description – SIC (SPDIF IEC Control) Bit[7:0]
Reserved
Digital Enable. DigEn
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=0Ah (SPDIF-IN)
Bit
Description – SIC (SPDIF IEC Control) Bit[7:0]
7:0
Reserved. Read as 0’s
Note: Other widgets will ignore this verb.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
61
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.40. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 74. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h Verb ID=F20h
0’s
32-bit Response
Codec Response for NID=01h
Bit
31:16
15:8
7:0
Description
Subsystem ID[23:8]. (Default=10ECh)
Subsystem ID[7:0]. (Default=08h).
Assembly ID[7:0]. (Default=88h).
8.41. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24],
722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 75. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X Node ID=01h
Verb ID=723h,
Label [7:0]
0’s for all nodes
722h, 721h, 720h
Codec Response for all NID
Bit
Description
31:0
0’s
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
62
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
8.42. Get/Set EAPD Enable (VID=70Ch/F0Ch)
Table 76. Verb – Get/Set EAPD [31:0]
Get Command Format
Codec Response Format
Response [31:0]
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd = X
Node ID=Xh Verb ID=F0Ch
0s
Bit[1] is EAPD Control
CODEC response in Get Command for NID=14h (LINE-OUT Pin Widget), 15h (HP-OUT Pin Widget)
Bit
31:3
2
Description
Reserved
L-R Swap
The ALC888S-VC does not support swapping left and right channel, it is read as 0.
EAPD Enable
0: EAPD pin state is not controlled by power state of corresponding pin widget.
1: EAPD pin state is controlled by power state of corresponding pin widget.
BTL Enable
1
0
The ALC888S-VC does not support BTL output, it is read as 0.
CODEC Response in Get Command for other NID
Bit
Description
31:0
0’s.
Set Command Format
Bit [27:20] Bit [19:8]
Node ID=Xh Verb ID=70Ch
Codec Response Format
Response [31:0]
0s
Bit [31:28]
Payload Bit [7:0]
CAd = X
Bit[1] is EAPD Control
CODEC Response in Set Command for all nodes
Bit
Description
31:0
0’s.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
63
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 77. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supply
Digital Power for Core
Digital Power for HDA Link
Analog
DVDD
DVDD-IO*
AVDD**
Ta
3.0
1.5
3.3
0
3.3
3.3
5.0
-
3.6
3.6
5.5
V
V
V
oC
oC
Ambient Operating Temperature
Storage Temperature
+70
+125
Ts
-
-
ESD (Electrostatic Discharge)
Susceptibility Voltage
Pass 3500V
All Pins
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customer designing with a different
AVDD should contact Realtek technical support representatives for special testing support.
9.1.2.
Threshold Voltage
DVDD= 3.3V±5%, Tambient=25°C, with 50pF external load.
Table 78. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
DVDD+0.30
0.30*DVDDIO
-
Units
V
Input Voltage Range
-0.30
-
-
-
-
Low Level Input Voltage (HDA link)
High Level Input Voltage (HDA link)
Low Level Input Voltage
(SPDIF-IN/OUT, GPIOs)
High Level Input Voltage
(SPDIF-IN/OUT, GPIOs)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VIL
-
V
VIH
0.65*DVDDIO
-
V
VIL
0.44*DVDD
(1.45)
V
VIH
0.56*DVDD
-
-
V
(1.85)
VOH
0.9*DVDD
-
-
V
V
VOL
-
-10
-10
-
-
-
0.1*DVDD
-
-
-
-
10
10
-
µA
µA
mA
Ω
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
-
5
-
50k
-
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
64
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.1.3.
Digital Filter Characteristics
Table 79. Digital Filter Characteristics
Filter
Description
Minimum
Typical
Maximum
Units
kHz
kHz
dB
ADC Lowpass Filter
Passband
0
-
-
0.45*Fs
Stopband
0.60*Fs
-
Stopband Rejection
Passband Frequency Response
Passband
-
-76.0
±0.02
-
-
-
-
dB
DAC Lowpass Filter
0
0.45*Fs
kHz
kHz
dB
Stopband
0.60*Fs
-
-
-
-
Stopband Rejection
Passband Frequency Response
-
-
-78.5
±0.020
dB
Note: Fs=Sample rate.
9.1.4.
SPDIF Input/Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Table 80. SPDIF Input/Output Characteristics
Parameter
Symbol
VOH
VOL
VIH
Minimum
Typical
Maximum
Units
V
SPDIF-OUT High Level Output
SPDIF-OUT Low Level Output
SPDIF-IN High Level Input
SPDIF-IN Low Level Input
SPDIF-IN Bias Level
3.0
3.3
-
0.3
-
-
0
V
1.85
-
-
V
VIL
-
-
1.45
-
V
Vt
1.65
V
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
65
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.2. AC Characteristic
9.2.1.
Link Reset and Initialization Timing
Table 81. Link Reset and Initialization Timing
Parameter
Symbol
TRST
Minimum
Typical
Maximum
Units
µs
RESET# Active Low Pulse Width
RESET# Inactive to BCLK
1.0
20
-
-
-
-
TPLL
µs
Startup Delay for PLL Ready Time
SDI Initialization Request
TFRAME
-
-
1
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
4 BCLK
BCLK
SYNC
Normal Frame
SYNC
SDO
SDI
Initialization
Request
RESET#
TRST
TPLL
TFRAME
Figure 16. Link Reset and Initialization Timing
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
66
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.2.2.
Link Timing Parameters at the Codec
Table 82. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
Units
MHz
ns
BCLK Frequency
BCLK Period
-
24.0
-
-
Tcycle
-
41.67
-
BCLK Jitter
Tjitter
Thigh
Tlow
-
-
-
-
-
2.0
22.91 (55%)
22.91 (55%)
-
ns
BCLK High Pulse Width
BCLK Low Pulse Width
18.75 (45%)
18.75 (45%)
2.1
ns (%)
ns (%)
ns
SDO Setup Time at Both Rising and
Falling Edge of BCLK
Tsetup
SDO Hold Time at Both Rising and
Falling Edge of BCLK
Thold
Ttco
2.1
-
-
8.0
-
ns
ns
ns
SDI Valid Time After Rising Edge
of BCLK (1:50pF external load)
-
-
7.5
2.0
SDI Flight Time
Tflight
T_cycle
T_high
V
IH
BCLK
SDO
V
V
T
IL
T_low
T_setup T_hold
T_tco
V
OH
SDI
V
OL
T_flight
Figure 17. Link Signals Timing
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
67
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.2.3.
SPDIF Output and Input Timing
Table 83. SPDIF Output and Input Timing
Symbol Minimum Typical
3.072
Parameter
Maximum
Units
MHz
ns
SPDIF-OUT Frequency
SPDIF-OUT Period *1
-
-
-
Tcycle
Tjitter
THigh
TLow
Trise
-
325.6
-
SPDIF-OUT Jitter
-
-
4
ns
SPDIF-OUT High Level Width
SPDIF-OUT Low Level Width
SPDIF-OUT Rising Time
SPDIF-OUT Falling Time
SPDIF-IN Period *2
156.2 (48%)
162.8 (50%)
162.8 (50%)
2.0
169.2 (52%)
ns (%)
ns (%)
ns
156.2 (48%)
169.2 (52%)
-
-
Tfall
-
2.0
-
ns
Tcycle
Tjitter
THigh
TLow
-
325.6
-
ns
SPDIF-IN Jitter
-
-
10
ns
SPDIF-IN High Level Width
SPDIF-IN Low Level Width
146.4 (45%)
146.4 (45%)
162.8 (50%)
162.8 (50%)
179 (55%)
179 (55%)
ns (%)
ns (%)
*1: Bit parameters for 48kHz sample rate of SPDIF-OUT
*2: Bit parameters for 48kHz sample rate of SPDIF-IN
T
cycle
T
T
low
high
V
OH
V
IH
V
t
V
IL
V
OL
T
T
rise
fall
Figure 18. Output and Input Timing
9.2.4.
Test Mode
The ALC888S-VC does not support codec test mode or Automatic Test Equipment (ATE) mode.
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
68
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
9.3. Analog Performance
• Tambient=25 oC, DVDD=3.3V ±5%, AVDD=5.0V±5%
Standard Test Conditions
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz
Table 84. Analog Performance
Parameter
Min
Typical
Max
Units
Full-Scale Input Voltage
All Inputs (gain=0dB)
ADC
-
-
1.6
1.1
-
-
Vrms
Vrms
Full-Scale Output Voltage
DAC
-
-
1.4
1.0
-
-
Vrms
Vrms
Headphone Amplifier Output@32Ω Load
S/N (A Weighted)
ADC
DAC
-
-
-
90
96
95
-
-
-
dB FSA
dB FSA
dB FSA
Headphone Amplifier Output@32Ω Load
THD+N
ADC
DAC
-
-
-
-84
-90
-80
-
-
-
dB FS
dB FS
dB FS
Headphone Amplifier Output@32Ω Load
Frequency Response
ADC
10
0
-
-
-
0.45*Fs
0.45*Fs
Hz
Hz
dB
dB
dB
dB
KΩ
DAC
Power Supply Rejection
Total Out-of-Band Noise (28.8kHz~100kHz)
Amplifier Gain Step
Crosstalk Between Input Channels
Input Impedance (gain=0dB)
Output Impedance
-50
-60
1.5
-80
47
-
-
-
-
-
-
-
-
-
Amplified Output
Non-amplified Output
-
-
1
100
-
-
Ω
Ω
Digital Power Supply Current (normal operation)
DVDD=3.3V
-
-
-
TBD
TBD
TBD
-
-
-
mA
mA
mA
Digital Power Supply Current (power down mode)
DVDD=3.3V
Analog Power Supply Current (normal operation)
AVDD=5.0V
Analog Power Supply Current (power down mode)
AVDD=5.0V
-
2.25
-
TBD
2.50
5
-
3.75
-
mA
V
VREFOUTx Output Voltage
VREFOUTx Output Current
Note: Fs=Sample Rate.
mA
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
69
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
10. Application Circuits
If a digital microphone and GPIO are not used, the ALC888S-VC is pin compatible with the ALC888
series. To get the best compatibility in hardware design and software driver, any modification should be
confirmed by Realtek. Realtek may update the latest application circuits onto our web site
(www.realtek.com.tw) without modifying this datasheet.
10.1. Filter Connection
If analog CD is connected as line level input
(9th port), and Jack Detect is required
MIC1-VREFO-R
LINE2-VREFO
MIC2-VREFO
LINE1-VREFO
MIC1-VREFO-L
R275
39.2K,1%
CD-JD-Jack
SIDESURR-JD
Sense B
R237
5.1K,1%
+5VA
CEN-JD
R238
R239
10K,1%
FRONT-L
FRONT-R
FRONT-IO-SENSE
0
C229 10u
C230
+
+
10u
If analog CD is connected as
line level input(9th port)
U22
+5VA
CD-R-Jack
CD-L-Jack
R257
R272
R273
0
0
0
LINE1-R
LINE1-L
MIC1-R
MIC1-L
37
24
23
22
21
20
19
18
17
16
15
14
13
PIN37-VO
LINE1-R
LINE1-L
MIC1-R
MIC1-L
CD-R
38
39
40
41
42
43
44
45
46
47
48
AVDD2
SURR-L
SURR-OUT-L
JDREF
+
C238
10u
R240
20K,1%
SURR-R
CD-IN Header
C243
1u
1u
1u
SURR-OUT-R
AVSS2
4
3
2
1
C244
C249
CD-GND
CD-L
ALC888S-VC
CEN
LFE
CEN
J23
MIC2-R
LFE
MIC2-R
MIC2-L
LINE2-R
LINE2-L
Sense A
SIDESURR-L
SIDESURR-R
MIC2-L
LINE2-R
LINE2-L
If differential analog CD is used
SIDE-L
SIDE-R
SPDIFI/EAPD
SPDIFO
Sense A
FRONT-JD
LINE1-JD
MIC1-JD
R241
R242
R245
R246
5.1K,1%
10K,1%
20K,1%
39.2K,1%
S/PDIF-IN
Spilt by DGND
SURR-JD
S/PDIF-OUT
+3.3VD
R248 47K
C252
10u
C253 1u
+
Ext. PCBEEP
If secondary S/PDIF-OUT is
connected to HDMI Tx connector
R249
4.7k
RESET#
SYNC
SDIN
R250
22
R274
0
S/PDIF-OUT2
R254 22
JP9
BCLK
DMIC-CLK
DMIC-DATA
Tied at one point only under
the codec or near the codec
4
C260
22P
3
2
1
+3.3VD
Pin
3 and pin 4 are
SDOUT
DMIC Interface
DGND
AGND
not compatible with with
ALC888S version
B
If digital MIC interface
is adapted
Figure 19. Filter Connection
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
70
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
10.2. Onboard Front Panel Header Connection
Option 1 in Figure 20 comes from by Intel’s front panel IO connectivity design guide. A drawback of this
option is that the ports connected to the front panel must use the same jack detection pin. According to the
HD Audio standard specification, ports A/B/C/D use ‘Sense A’ as the jack detect pin; ports E/F/G/H use
‘Sense B’ as the jack detect pin. This is not a good option when the system integrators want to use port-A
(pin 39/41) and port-F (pin 16/17) to be the front panel ports, as ‘Sense A’ and ‘Sense B’ cannot be tied
together.
Option 2 in Figure 20 shows an alternative front panel header design that is also compatible with standard
front panel I/O cable. The option 2 header design lets the two ports use an individual sense pin, and is
compatible with current HD Audio front panel cable.
For the best compatibility with long front panel cable may not follow Intel’s Front Panel I/O Connectivity
standard, the option 2 header design has good ground loop is strongly recommended. The main drawback
of option 2 is not suitable for AC’97 front cable
Option 1: Follow Intel's HD Audio front panle header design
(Two ports must be in the same jack detect group)
MIC2-VREFO
D3
D4
HD Audio Front Panel I/O Cable
1N4148
1N4148
+3.3VD
J2
FIO-PORT1-L
1
3
5
7
9
2
4
6
8
10
R11
4.7K
R12
4.7K
FIO-PORT1-R
FIO-PORT2-R
FIO-SENSE
FIO-PRESENCE#
PORT1-SENSE-RETURN
KEY
R14
FIO-PORT2-L
PORT2-SENSE-RETURN
MIC2-L
MIC2-R
C35
C37
1u
1u
10K
CON10A
J3
1
3
5
7
9
2
4
6
8
10
PRESENCE#
System GPI
LINE2-R
LINE2-L
C38
C39
100u
100u
MIC2-JD
Key
FRONT-IO-JD
FIO-SENSE
LINE2-JD
R18
JACK 7
CON10A
R19
39.2K,1%
Onboard front
panel header
4
3
5
PORT2-SENSE-RETURN
20K,1%
FIO-PORT2-R
FIO-PORT2-L
L14
L15
FERB
FERB
2
1
C41
C42
FIO-PORT2 (Jack-E)
Option 2: A more flexible front panel header
100P
100P
(Each port can be in different jack detect group)
MIC2-VREFO
D5
D6
1N4148
1N4148
FIO-SENSE
+3.3VD
R20
4.7K
R21
4.7K
JACK 8
4
3
5
R23
PORT1-SENSE-RETURN
FIO-PORT1-R
FIO-PORT1-L
L16
L17
FERB
FERB
MIC2-L
MIC2-R
C44
C46
1u
1u
10K
2
1
PRESENCE#
J5
System GPI
1
3
5
7
9
2
4
6
8
10
R25
R26
C49
C50
20K,1%
LINE2-R
LINE2-L
C48
C51
100u
100u
MIC2-JD
LINE2-JD
39.2K,1%
FIO-PORT1 (Jack-F)
Sense B
Sense B
Key
100P
100P
CON10A
Onboard front
panel header
Figure 20. Front Panel Header Connection
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
71
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
10.3. Jack Connection on Rear Panel
MIC1-VREFO-L
MIC1-VREFO-R
R234
4.7K
JACK 30
R235
4.7K
L70
JACK 31
SURR-JD
FERB
FERB
4
3
5
MIC1-JD
4
3
5
SURR-R
SURR-L
C218 1u
C220 1u
L69
L72
MIC1-R
MIC1-L
C219 1u
C221 1u
FERB
FERB
2
1
L73
2
1
C222
C223
100P
C224
100P
C225
100P
MIC-IN (Port-B)
SURROUND (Port-A)
2.2~4.7uF for DA (LF)
frequence response
100P
JACK 32
JACK 33
CEN-JD
4
3
5
FRONT-JD
4
3
5
LFE
C228 1u
C232 1u
L74
L76
FERB
FERB
FRONT-R
FRONT-L
C231
C233
100u
100u
L75
L77
FERB
FERB
CEN
2
1
2
1
C234
C235
100P
C236
100P
C237
100P
CENTER/LFE (Port-G)
2.2~4.7uF for DA (LF)
frequence response
FRONT-OUT (Port-D)
100P
JACK 35
JACK 34
LINE1-JD
SIDESURR-JD
FERB
4
3
5
4
3
5
LINE1-R
LINE1-L
C239 1u
C241 1u
L78
L80
FERB
FERB
SIDE-R
SIDE-L
C240 1u
C242 1u
L79
L81
FERB
2
1
2
1
C245
100P
C246
100P
LINE-IN (Port-C)
C247
100P
C248
100P
SIDESURR (Port-H)
2.2~4.7uF for DA (LF)
frequence response
Figure 21. Jack Connection on Rear Panel
10.4. SPDIF Input/Output Connection
S/PDIF module option 1: Optical S/PDIF option 2: RCA only
S/PDIF option 3: Optical & RCA
U23 TOTX178
U24 TOTX178
U25 TORX178S
Transmitter
S/PDIF-OUT
C261
Transmitter
Receiver
1
R258 100
S/PDIF-OUT
4
5
4
5
4
5
J26
0.01u
C262
100P
R259
220
RCA
R260 10
S/PDIF-OUT
+5VD
L86
C263
0.1u
C264
0.1u
47uH
C265
0.1u
+5VD
+5VD
+3.3VD
+3.3VD
U26 TORX178S
R261
12K@ALC882;NC@ALC888/883
Receiver
R262
12K@ALC882;NC@ALC888/883
S/PDIF-OUT
C266
S/PDIF-IN
S/PDIF-IN
1
R263 100
S/PDIF-OUT
R
4
5
C267
1
C269
100P
0.01u
R264 10
R266
S/PDIF-IN
C268
0.01u
S
0.01u
R270
R265 10
R268
S/PDIF-IN
R271
75
C270
J27
R267
220
J5A3
RCA
J28
RCA
C271
100P
R269 10 S/PDIF-IN
100P
RCA
10K@ALC882,NC@ALC883
10K@ALC882,NC@ALC888/8833
L87
47uH
C272
0.1u
J5A is RCA jack with switch
+5VD
Figure 22. SPDIF Input/Output Connection
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
72
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
10.5. Secondary SPDIF-OUT Connected to HDMI Tx Connector
U3
RCA to HDMI Tx
R69
100 C13
1
S/PDIF-OUT2
C31
0.01u
R70
200
100p
Figure 23. Secondary SPDIF-OUT Connected to HDMI Tx Connector
10.6. Differential Analog CD Used as Line Level Input
JACK 41
CD-JD-Jack
4
3
5
CD-R-Jack
CD-L-Jack
L98
L99
FERB
FERB
2
1
C294
100P
C293
100P
CD-IN (9th Port)
Figure 24. Differential Analog CD Used as Line Level Input
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
73
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
11. Mechanical Dimensions
SYMBOL
MILLIMETER
INCH
MIN TYP MAX MIN
TYP MAX
A
A1
A2
c
-
-
-
1.60
0.15
-
-
-
0.063
0.006
0.05
0.002
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
1.35 1.40 1.45
0.053 0.055 0.057
0.09
-
0.20
0.004
-
0.008
D
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
LEADFRAME MATERIAL
D1
D2
E
APPROVE
CHECK
DOC. NO.
VERSION 02
DWG NO. PKGC-065
DATE
9.00 BSC
7.00BSC
5.50
0.354 BSC
0.276 BSC
0.217
E1
E2
b
REALTEK SEMICONDUCTOR CORP.
0.17 0.20
0.50 BSC
3.5o
0.45 0.60
1.00
0.27 0.007 0.008
0.0196 BSC
3.5o
0.011
7o
e
TH
L
0o
7o
0o
0.75 0.018 0.0236 0.030
0.0393
L1
-
-
-
-
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
74
Track ID: JATR-1076-21 Rev. 1.1
ALC888S-VC2 & ALC888SDD-VC2
Datasheet
12. Ordering Information
Table 85. Ordering Information
Part Number
Description
Status
ALC888S-VC2-GR
ALC888S Version C2, LQFP-48 with ‘Green’ Package
Production
Production
ALC888SDD-VC2-GR ALC888S Version C2 + Dolby® Digital Live + DTS® CONNECT™
(Software Feature)
Note 1: See page 7 for ‘Green’package and version identification.
Note 2: Above parts are tested under AVDD=5.0V. Customers requesting lower AVDD support should contact Realtek
sales representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
7.1+2 Channel High Definition Audio Codec w/Two
Independent SPDIF-OUT
75
Track ID: JATR-1076-21 Rev. 1.1
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