RTL8139C-LF [REALTEK]
3.3V SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT;
| 型号： | RTL8139C-LF |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | 3.3V SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT 以太网：16GBASE-T LTE |
| 文件： | 总67页 (文件大小：730K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8139C
RTL8139C-LF
RTL8139CL
RTL8139CL-LF
3.3V SINGLE-CHIP FAST ETHERNET
CONTROLLER WITH POWER MANAGEMENT
DATASHEET
Rev. 1.6
29 December 2005
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8139C(L)
Datasheet
COPYRIGHT
©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8139C(L) chip.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
Summary
1.5
2005/11/28
Format and layout changes.
Add package ID information (Section 4.1 Package and Version
Identification, page 4).
Add ordering information (Section 14 Ordering Information, page 63).
1.6
2005/12/29
Add sentence “Writing a 1 to any bit will reset that bit, but writing a 0 has no
effect” to section 6.6 Interrupt Status Register (Offset 003Eh-003Fh, R/W),
page 14.
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RTL8139C(L)
Datasheet
Table of Contents
1. General Description .............................................................................................................................................................1
2. Features.................................................................................................................................................................................2
3. Block Diagram......................................................................................................................................................................3
4. Pin Assignments....................................................................................................................................................................4
4.1. Package and Version Identification................................................................................................................................4
5. Pin Descriptions....................................................................................................................................................................5
5.1. Power Management/Isolation Interface..........................................................................................................................5
5.2. PCI Interface ..................................................................................................................................................................5
5.3. FLASH/EEPROM Interface...........................................................................................................................................7
5.4. Power Pins......................................................................................................................................................................8
5.5. LED Interface.................................................................................................................................................................8
5.6. Attachment Unit Interface..............................................................................................................................................8
5.7. Test and Other Pins ........................................................................................................................................................8
6. Register Descriptions ...........................................................................................................................................................9
6.1. Receive Status Register in Rx Packet Header ..............................................................................................................11
6.2. Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) .................................................................................12
6.3. ERSR: Early Rx Status Register (Offset 0036h, R) .....................................................................................................13
6.4. Command Register (Offset 0037h, R/W).....................................................................................................................13
6.5. Interrupt Mask Register (Offset 003Ch-003Dh, R/W).................................................................................................14
6.6. Interrupt Status Register (Offset 003Eh-003Fh, R/W).................................................................................................14
6.7. Transmit Configuration Register (Offset 0040h-0043h, R/W) ....................................................................................15
6.8. Receive Configuration Register (Offset 0044h-0047h, R/W)......................................................................................16
6.9. 9346CR: 93C46 (93C56) Command Register (Offset 0050h, R/W)............................................................................19
6.10.
6.11.
6.12.
6.13.
6.14.
6.15.
6.16.
6.17.
6.18.
6.19.
6.20.
6.21.
6.22.
6.23.
6.24.
6.25.
6.26.
6.27.
6.28.
6.29.
6.30.
6.31.
6.32.
6.33.
CONFIG 0: Configuration Register 0 (Offset 0051h, R/W) ....................................................................................19
CONFIG 1: Configuration Register 1 (Offset 0052h, R/W) ....................................................................................20
Media Status Register (Offset 0058h, R/W).............................................................................................................21
CONFIG 3: Configuration Register3 (Offset 0059h, R/W) .....................................................................................21
CONFIG 4: Configuration Register4 (Offset 005Ah, R/W) ....................................................................................23
Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) .............................................................................24
PCI Revision ID (Offset 005Eh, R)..........................................................................................................................24
Transmit Status of All Descriptors (TSAD) Register (Offset 0060h-0061h, R/W) .................................................24
Basic Mode Control Register (Offset 0062h-0063h, R/W)......................................................................................25
Basic Mode Status Register (Offset 0064h-0065h, R) .............................................................................................25
Auto-Negotiation Advertisement Register (Offset 0066h-0067h, R/W)..................................................................26
Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R)..............................................................27
Auto-Negotiation Expansion Register (Offset 006Ah-006Bh, R)............................................................................27
Disconnect Counter (Offset 006Ch-006Dh, R)........................................................................................................27
False Carrier Sense Counter (Offset 006Eh-006Fh, R)............................................................................................28
NWay Test Register (Offset 0070h-0071h, R/W)....................................................................................................28
RX_ER Counter (Offset 0072h-0073h, R)...............................................................................................................28
CS Configuration Register (Offset 0074h-0075h, R/W)..........................................................................................28
Flash Memory Read/Write Register (Offset 00D4h-00D7h, R/W)..........................................................................29
Config5: Configuration Register 5 (Offset 00D8h, R/W)........................................................................................29
Function Event Register (Offset 00F0h-00F3h, R/W) .............................................................................................30
Function Event Mask Register (Offset 00F4h-00F7h, R/W) ...................................................................................31
Function Present State Register (Offset 00F8h-00FBh, R)......................................................................................31
Function Force Event Register (Offset 00FCh-00FFh, W)......................................................................................32
7. EEPROM Contents (93C46 or 93C56).............................................................................................................................33
7.1. Summary of EEPROM Registers .................................................................................................................................35
7.2. Summary of EEPROM Power Management Registers ................................................................................................35
8. PCI Configuration Space Registers..................................................................................................................................36
8.1. PCI Configuration Space Table....................................................................................................................................36
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8.2. PCI Configuration Space Functions.............................................................................................................................38
8.3. Default Values After Power-on (RSTB asserted) ........................................................................................................42
8.3.1.
PCI Configuration Space Table............................................................................................................................42
8.4. PCI Power Management Functions..............................................................................................................................44
8.5. Vital Product Data (VPD) ............................................................................................................................................46
9. Functional Description.......................................................................................................................................................47
9.1. Transmit Operation.......................................................................................................................................................47
9.2. Receive Operation........................................................................................................................................................47
9.3. Line Quality Monitor....................................................................................................................................................47
9.4. Clock Recovery Module...............................................................................................................................................47
9.5. Loopback Operation.....................................................................................................................................................47
9.6. Tx Encapsulation..........................................................................................................................................................47
9.7. Collision .......................................................................................................................................................................47
9.8. Rx Decapsulation .........................................................................................................................................................48
9.9. Flow Control ................................................................................................................................................................48
9.9.1.
9.9.2.
9.10.
Control Frame Transmission ................................................................................................................................48
Control Frame Reception .....................................................................................................................................48
LED Functions .........................................................................................................................................................49
9.10.1. 10/100Mbps Link Monitor...................................................................................................................................49
9.10.2. LED_RX...............................................................................................................................................................49
9.10.3. LED_TX...............................................................................................................................................................49
9.10.4. LED_TX+LED_RX .............................................................................................................................................50
10. Application Diagram..........................................................................................................................................................51
11. Electrical Characteristics...................................................................................................................................................52
11.1.
11.2.
Temperature Limit Ratings.......................................................................................................................................52
DC Characteristics....................................................................................................................................................52
11.2.1. Supply Voltage.....................................................................................................................................................52
11.3.
AC Characteristics....................................................................................................................................................53
11.3.1. FLASH/BOOT ROM Timing...............................................................................................................................53
11.3.2. PCI Bus Operation Timing...................................................................................................................................55
12. Mechanical Dimensions (128-Pin QFP)............................................................................................................................61
13. Mechanical Dimensions (128-Pin LQFP).........................................................................................................................62
14. Ordering Information........................................................................................................................................................63
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Datasheet
1. General Description
The Realtek RTL8139C(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller
that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u
100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced
Configuration Power management Interface (ACPI), PCI power management for modern operating
systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management possible. The RTL8139CL is suitable for applications such as CardBus or
mobile devices with a built-in network controller. The CIS data can be stored in either a 93C56 EEPROM
or expansion ROM.
In addition to the ACPI feature, the RTL8139C(L) also supports remote wake-up (including AMD Magic
Packet, LinkChg, and Microsoft wake-up frame) in both ACPI and APM environments. The RTL8139C(L)
is capable of performing an internal reset through the application of auxiliary power. When auxiliary power
is on and the main power remains off, the RTL8139C(L) is ready and waiting for the Magic Packet or Link
Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active
high, active low, positive pulse, and negative pulse. The versatility of the RTL8139C(L) LWAKE pin
provides motherboards with the Wake-On-LAN (WOL) function. The RTL8139C(L) also supports Analog
Auto-Power-down, that is, the analog part of the RTL8139C(L) can be shut down temporarily according to
user requirements or when the RTL8139C(L) is in a power down state with the wakeup function disabled.
In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then
both the analog and digital parts stop functioning and power consumption of the RTL8139C(L) will be
negligible. The RTL8139C(L) also supports an auxiliary power auto-detect function, and will
auto-configure related bits of their own PCI power management registers in PCI configuration space.
The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies
hardware (i.e., the RTL8139C(L) LAN card). The information may consist of part number, serial number,
and other detailed information.
To provide cost down support, the RTL8139C(L) is capable of using a 25MHz crystal or OSC as its internal
clock source.
The RTL8139C(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest way
to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps
bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the
RTL8139C(L) is also capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The
RTL8139C(L) is highly integrated and requires no “glue” logic or external memory. It includes an interface
for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of
management.
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2. Features
z
z
128 pin QFP/LQFP
z
z
Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power still remains off
Integrated Fast Ethernet MAC, Physical chip, and
transceiver in one chip
Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space.
z
z
10 Mb/s and 100 Mb/s operation
Supports 10 Mb/s and 100 Mb/s N-way
Auto-negotiation operation
z
z
Includes a programmable, PCI burst size and early
Tx/Rx threshold.
z
PCI local bus single-chip Fast Ethernet controller
Compliant to PCI Revision 2.2
Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
Supports PCI clock 16.75MHz-40MHz
Supports PCI target fast back-to-back transaction
z
z
z
Contains two large (2Kbyte) independent receive and
transmit FIFO’s
Provides PCI bus master data transfers and PCI memory
space or I/O space mapped data transfers of
RTL8139C(L)'s operational registers
Advanced power saving mode when LAN function or
wakeup function is not used
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
application.
z
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports CardBus. The CIS can be stored in 93C56 or
expansion ROM
z
z
Supports LED pins for various network activity
indications
z
z
Supports up to 128K bytes Boot ROM interface for both
EPROM and Flash memory
Supports digital and analog loopback capability on both
ports
Supports 25MHz crystal or 25MHz OSC as the internal
clock source. The frequency deviation of either crystal or
OSC must be within 50 PPM.
z
z
z
Half/Full duplex capability
z
z
Compliant to PC99 standard
Supports Full Duplex Flow Control (IEEE 802.3x)
3.3V power supply with 5V tolerant I/Os.
Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft® wake-up
frame)
* Third-party brands and names are the property of their
respective owners.
z
Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
Note: The model number of the QFP package is RTL8139C. The LQFP package model number is RTL8139CL.
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3. Block Diagram
MAC
Boot ROM
Interface
EEPROM
Interface
LED Driver
Power Control Logic
Early Interrupt
Threshold
Register
Interrupt
Control
Logic
Early Interrupt
Control Logic
PCI
Interface
Transmit/
FIFO
Control
Logic
Receive
Logic
Interface
FIFO
MII
Interface
PHY
100M
5B 4B
Decoder
Data
Alignment
RXD
RXC 25M
Descrambler
10/100
half/full
Switch
Logic
MII
Interface
TXD
TXC 25M
4B 5B
Encoder
Scrambler
10/100M Auto-negotiation
Control Logic
Link pulse
10M
TXC10
TXD10
Manchester coded
waveform
10M Output waveform
shaping
RXC10
RXD10
Data Recovery
Receive low pass filter
Transceiver
TD+
TXC 25M
TXD
3 Level
Driver
TXO+
TXO -
Parrallel
to Serial
Variable Current
Baseline
wander
Correction
Peak
Detect
RXIN+
RXIN-
3 Level
Comparator
MLT-3
to NRZI
Adaptive
Equalizer
ck
data
RXC 25M
RXD
Serial to
Parrallel
Master
PPL
Slave
PLL
Control
Voltage
25M
3
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Datasheet
4. Pin Assignments
Figure 1. Pin Assignments
4.1. Package and Version Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1. The version number is
shown in the location marked ‘V’.
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Datasheet
5. Pin Descriptions
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.
5.1. Power Management/Isolation Interface
Symbol
Type
Pin No
Description
PMEB
(PME#)
O/D
76
Power Management Event: Open drain, active low. Used by the RTL8139C(L) to
request a change in its current power management state and/or to indicate that a
power management event has occurred.
ISOLATEB
(ISOLATE#)
I
95
83
Isolate Pin: Active low. Used to isolate the RTL8139C(L) from the PCI bus. The
RTL8139C(L) does not drive its PCI outputs (excluding PME#) and does not
sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is
asserted.
LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This signal is used
to inform the motherboard to execute the wake-up process. The motherboard must
support Wake-On-LAN (WOL). There are 4 choices of output, including active
high, active low, positive pulse, and negative pulse, that may be asserted from the
LWAKE pin. Please refer to the LWACT bit in the CONFIG1 register and the
LWPTN bit in the CONFIG4 register for the setting of this output signal. The
default output is an active high signal.
LWAKE/
CSTSCHG
O
Once a PME event is received, the LWAKE and PMEB assert at the same time
when the LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the
LWAKE asserts only when the PMEB asserts and the ISOLATEB is low.
CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is used in
CardBus applications only and is used to inform the motherboard to execute the
wake-up process whenever a PME event occurs. This is always an active high
signal, and the setting of LWACT (bit 4, Config1), LWPTN (bit2, Config4), and
LWPME (bit4, Config4) mean nothing in this case.
This pin is a 3.3V signaling output pin.
5.2. PCI Interface
Symbol
AD31-0
Type
T/S
Pin No
Description
120-123, 125-128, 4-6, PCI address and data multiplexed pins.
8-11, 13, 26-29, 31-34,
37-39, 41-45
C/BE3-0
CLK
T/S
I
2, 14, 24, 36
116
PCI bus command and byte enables multiplexed pins.
Clock: This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33MHz.
CLKRUNB
I/O
75
Clock Run: This signal is used by the RTL8139C(L) to request starting
(or speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8139C(L), CLKRUNB is an open drain output as
well as an input. The RTL8139C(L) requests the central resource to
start, speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host system
(central resource) is responsible for maintaining CLKRUNB asserted,
and for driving it high to the negated (deasserted) state.
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Symbol
Type
Pin No
Description
DEVSELB
S/T/S
19
Device Select: As a bus master, the RTL8139C(L) samples this signal
to insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8139C(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
FRAMEB
GNTB
S/T/S
15
Cycle Frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
Grant: This signal is asserted low to indicate to the RTL8139C(L) that
the central arbiter has granted ownership of the bus to the
RTL8139C(L). This input is used when the RTL8139C(L) is acting as a
bus master.
I
117
REQB
IDSEL
INTAB
T/S
I
118
3
Request: The RTL8139C(L) will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization Device Select: This pin allows the RTL8139C(L) to
identify when configuration read/write transactions are intended for it.
Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask and Interrupt Enable registers.
O/D
114
IRDYB
S/T/S
16
Initiator Ready: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the
RTL8139C(L) is ready to complete the current data phase transaction.
This signal is used in conjunction with the TRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and
TRDYB are asserted low. As a target, this signal indicates that the
master has put data on the bus.
TRDYB
S/T/S
17
Target Ready: This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
Parity Error: When the RTL8139C(L) is the bus master and a parity
error is detected, the RTL8139C(L) asserts both SERR bit in ISR and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8139C(L)
continues its operation.
PAR
T/S
23
21
PERRB
S/T/S
When the RTL8139C(L) is the bus target and a parity error is detected,
the RTL8139C(L) asserts this PERRB pin low.
SERRB
O/D
22
System Error: If an address parity error is detected and Configuration
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RTL8139C(L)
Datasheet
Symbol
Type
Pin No
Description
Space Status register bit 15 (detected parity error) is enabled,
RTL8139C(L) asserts both SERRB pin low and bit 14 of Status register
in Configuration Space.
STOPB
RSTB
S/T/S
I
20
Stop: Indicates the current target is requesting the master to stop the
current transaction.
Reset: When RSTB is asserted low, the RTL8139C(L) performs an
internal system hardware reset. RSTB must be held for a minimum of
120 ns.
115
5.3. FLASH/EEPROM Interface
Symbol
MA16-3
Type
Pin No
70-63, 61, 60, 57,
53-51
Description
O
Boot PROM Address Bus: These pins are used to access up to a
128k-byte flash memory or EPROM.
MA8
I/O
61
Output pin as part of Boot PROM (or Flash) address bus after PCI reset.
Input pin as Aux. Power detect pin to detect if Aux. Power exists or not,
when initial power-on or PCI reset is asserted. Besides connecting this
pin to Boot PROM, it should be pulled high to the Aux. Power via a
resistor to detect Aux. power. If this pin is not pulled high to Aux.
Power, the RTL8139C(L) assumes that no Aux. power exists. To
support wakeup from ACPI D3cold or APM power-down, this pin must
be pulled high to Aux. power via a resistor.
MA6/9356SEL
MA2/EESK
I/O
O
57
49
When this pin is pulled high with a 10KΩ resistor, the 93C56 EEPROM
is used to store the resource data and CIS for the RTL8139C(L). The
RTL8139C(L) latches the status of this pin at power-up to determine
what EEPROM (93C46 or 93C56) is used, afterwards, this pin is used
as MA6.
The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46
(93C56) programming or auto-load mode.
MA1/EEDI
MA0/EEDO
EECS
O
O, I
O
48
47
50
93C46 (93C56) chip select
MD0-7
ROMCSB
OEB
I/O
O
O
108, 107, 105-100
Boot PROM data bus
110
88
ROM Chip Select: This is the chip select signal of the Boot PROM.
Output Enable: This enables the output buffer of the Boot PROM or
Flash memory during a read operation.
WEB
O
89
Write Enable: This signal strobes data into the Flash memory during a
write cycle.
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Datasheet
5.4. Power Pins
Symbol
VDD
Type
Pin No
Description
P
1, 12, 25, 35, 46, 58,
59, 106, 109, 119
77, 90, 96
7, 18, 30, 40, 55, 56,
62, 111, 112, 113, 124
74, 80, 85, 93
Digital Power +3.3V
P
P
Analog Power +3.3V
Digital Ground
GND
P
Analog Ground
5.5. LED Interface
Symbol
Type
Pin No
Description
LED0, 1, 2
O
99, 98, 97
LED pins
LEDS1-0
00
01
10
11
Tx/Rx
LINK100
LINK10
Tx/Rx
Tx
LINK10/100
Rx
Tx
LED0
LED1
LED2
LINK10/100
FULL
LINK100
LINK10
During power down mode, the LEDs are OFF.
5.6. Attachment Unit Interface
Symbol
TXD+
TXD-
RXIN+
RXIN-
X1
Type
Pin No
92
91
87
86
79
Description
100/10BASE-T transmit (Tx) Data
O
O
I
I
I
100/10BASE-T receive (Rx) Data
25 MHz Crystal/OSC. Input
X2
O
78
Crystal Feedback Output: This output is used in crystal connection
only. It must be left open when X1 is driven with an external 25 MHz
oscillator.
5.7. Test and Other Pins
Symbol
RTT2-3
Type
TEST
I/O
Pin No
81, 82
Description
Chip test pins.
This pin must be pulled low by a 1.7KΩ resistor.
Reserved
RTSET
NC
84
-
54, 71, 72, 73, 94
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6. Register Descriptions
The RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset
R/W
Tag
Description
0000h
R/W
IDR0
ID Register 0: The ID registers 0-5 are only permitted to read/write
by 4-byte access. Read access can be byte, word, or double word
access. The initial value is autoloaded from the EEPROM EthernetID
field.
0001h
0002h
0003h
0004h
0005h
R/W
R/W
R/W
R/W
R/W
-
IDR1
IDR2
IDR3
IDR4
IDR5
-
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
Reserved
0006h-0007h
0008h
R/W
MAR0
Multicast Register 0: The MAR registers 0-7 are only permitted to
read/write by 4-byte access. Read access can be byte, word, or double
word access. Driver is responsible for initializing these registers.
Multicast Register 1
Multicast Register 2
Multicast Register 3
Multicast Register 4
Multicast Register 5
Multicast Register 6
Multicast Register 7
Transmit Status of Descriptor 0
Transmit Status of Descriptor 1
Transmit Status of Descriptor 2
Transmit Status of Descriptor 3
Transmit Start Address of Descriptor0
Transmit Start Address of Descriptor1
Transmit Start Address of Descriptor2
Transmit Start Address of Descriptor3
Receive (Rx) Buffer Start Address
Early Receive (Rx) Byte Count Register
Early Rx Status Register
0009h
000Ah
000Bh
000Ch
000Dh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
TSD0
000Eh
000Fh
0010h-0013h
0014h-0017h
0018h-001Bh
001Ch-001Fh
0020h-0023h
0024h-0027h
0028h-002Bh
002Ch-002Fh
0030h-0033h
0034h-0035h
0036h
TSD1
TSD2
TSD3
TSAD0
TSAD1
TSAD2
TSAD3
RBSTART
ERBCR
ERSR
R
0037h
0038h-0039h
003Ah-003Bh
R/W
R/W
R
CR
CAPR
CBR
Command Register
Current Address of Packet Read (The initial value is 0FFF0h)
Current Buffer Address: The initial value is 0000h. It reflects total
received byte-count in the rx buffer.
Interrupt Mask Register
Interrupt Status Register
Transmit (Tx) Configuration Register
Receive (Rx) Configuration Register
003Ch-003Dh
003Eh-003Fh
0040h-0043h
0044h-0047h
0048h-004Bh
R/W
R/W
R/W
R/W
R/W
IMR
ISR
TCR
RCR
TCTR
Timer Count Register: This register contains
a
32-bit
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin to count from zero.
004Ch-004Fh
R/W
MPC
Missed Packet Counter: Indicates the number of packets discarded
due to rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written, MPC will be reset also.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Offset
R/W
R/W
R/W
R/W
-
Tag
9346CR
CONFIG0
CONFIG1
-
Description
0050h
0051h
0052h
93C46 (93C56) Command Register
Configuration Register 0
Configuration Register 1
Reserved
0053H
R /W
0054h-0057h
TimerInt
Timer Interrupt Register: Once having written a nonzero value to
this register, the Timeout bit of ISR register will be set whenever the
TCTR reaches to this value. The Timeout bit will never be set as long
as TimerInt register is zero.
0058h
0059h
005Ah
005Bh
R/W
R/W
R/W
-
MSR
CONFIG3
CONFIG4
-
Media Status Register
Configuration register 3
Configuration register 4
Reserved
005Ch-005Dh
005Eh
R/W
R
-
MULINT
RERID
-
Multiple Interrupt Select
PCI Revision ID = 10h
Reserved
005Fh
0060h-0061h
0062h-0063h
0064h-0065h
0066h-0067h
0068h-0069h
006Ah-006Bh
006Ch-006Dh
006Eh-006Fh
0070h-0071h
0072h-0073h
0074h-0075h
0076-0077h
0078h-007Bh
007Ch-007Fh
0080h
R
R/W
R
R/W
R
R
R
R
R/W
R
R/W
-
TSAD
Transmit Status of All Descriptors
Basic Mode Control Register
Basic Mode Status Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Register
Auto-Negotiation Expansion Register
Disconnect Counter
False Carrier Sense Counter
N-way Test Register
RX_ER Counter
CS Configuration Register
Reserved
PHY parameter 1
Twister parameter
PHY parameter 2
BMCR
BMSR
ANAR
ANLPAR
ANER
DIS
FCSC
NWAYTR
REC
CSCR
-
R/W
R/W
R/W
-
PHY1_PARM
TW_PARM
PHY2_PARM
-
0081-0083h
Reserved
0084h
0085h
0086h
0087h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CRC0
CRC1
Power Management CRC Register0 for Wakeup Frame0
Power Management CRC Register1 for Wakeup Frame1
Power Management CRC Register2 for Wakeup Frame2
Power Management CRC Register3 for Wakeup Frame3
Power Management CRC Register4 for Wakeup Frame4
Power Management CRC Register5 for Wakeup Frame5
Power Management CRC Register6 for Wakeup Frame6
Power Management CRC Register7 for Wakeup Frame7
Power Management Wakeup Frame0 (64bit)
Power Management Wakeup Frame1 (64bit)
Power Management Wakeup Frame2 (64bit)
Power Management Wakeup Frame3 (64bit)
Power Management Wakeup Frame4 (64bit)
CRC2
CRC3
0088h
0089h
008Ah
008Bh
CRC4
CRC5
CRC6
CRC7
Wakeup0
Wakeup1
Wakeup2
Wakeup3
Wakeup4
Wakeup5
Wakeup6
Wakeup7
LSBCRC0
008Ch–0093h
0094h–009Bh
009Ch–00A3h
00A4h–00ABh
00ACh–00B3h
00B4h–00BBh
00BCh–00C3h
00C4h–00CBh
00CCh
Power Management Wakeup Frame5 (64bit)
Power Management Wakeup Frame6 (64bit)
Power Management Wakeup Frame7 (64bit)
LSB of the Mask byte of Wakeup Frame0 Within Offset 12 to 75
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Offset
R/W
Tag
Description
00CDh
00CEh
00CFh
00D0h
00D1h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
LSBCRC1
LSBCRC2
LSBCRC3
LSBCRC4
LSBCRC5
LSBCRC6
LSBCRC7
FLASH
Config5
-
LSB of the Mask byte of Wakeup Frame1 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame2 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame3 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame4 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame5 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame6 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame7 Within Offset 12 to 75
Flash Memory Read/Write Register
Configuration Register 5
Reserved
Function Event Register (Cardbus only)
Function Event Mask Register (CardBus only)
Function Present State Register (CardBus only)
Function Force Event Register (CardBus only)
00D2h
00D3h
00D4h-00D7h
00D8h
00D9h-00EFh
00F0h-00F3h
00F4h-00F7h
00F8h-00FBh
00FCh-00FFh
R/W
R/W
R
FER
FEMR
FPSR
FFER
W
6.1. Receive Status Register in Rx Packet Header
Bit
R/W
Symbol
Description
15
R
MAR
Multicast Address Received: This bit set to 1 indicates that a multicast
packet is received.
14
13
R
R
PAM
BAR
Physical Address Matched: This bit set to 1 indicates that the destination
address of this packet matches the value written in ID registers.
Broadcast Address Received: This bit set to 1 indicates that a broadcast
packet is received. BAR, MAR bit will not be set simultaneously.
Reserved
Invalid Symbol Error: (100BASE-TX only) This bit set to 1 indicates
that an invalid symbol was encountered during the reception of this packet.
Runt Packet Received: This bit set to 1 indicates that the received packet
length is smaller than 64 bytes ( i.e. media header + data + CRC < 64
bytes )
12-6
5
-
R
-
ISE
4
R
RUNT
3
2
1
0
R
R
R
R
LONG
CRC
FAE
Long Packet: This bit set to 1 indicates that the size of the received
packet exceeds 4k bytes.
CRC Error: When set, indicates that a CRC error occurred on the
received packet.
Frame Alignment Error: When set, indicates that a frame alignment
error occurred on this received packet.
Receive OK: When set, indicates that a good packet is received.
ROK
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.2. Transmit Status Register (TSD0-3)(Offset
0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139C(L) when the Transmit
Byte Count (bit12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These
registers are only permitted to write by double-word access. After a software reset, all bits except the OWN bit are reset to “0”.
Bit
R/W
Symbol
Description
31
R
CRS
Carrier Sense Lost: This bit is set to 1 when the carrier is lost during
transmission of a packet.
30
29
R
R
TABT
OWC
Transmit Abort: This bit is set to 1 if the transmission of a packet was
aborted. This bit is read only, writing to this bit is not affected.
Out of Window Collision: This bit is set to 1 if the RTL8139C(L)
encountered an "out of window" collision during the transmission of a
packet.
28
R
R
CDH
CD Heart Beat: The same as RTL8139(A/B).
This bit is cleared in the 100 Mbps mode.
Number of Collision Count: Indicates the number of collisions
encountered during the transmission of a packet.
27-24
NCC3-0
23-22
21-16
-
-
Reserved
R/W
ERTXTH5-0
Early Tx Threshold: Specifies the threshold level in the Tx FIFO to
begin the transmission. When the byte count of the data in the Tx FIFO
reaches this level, (or the FIFO contains at least one complete packet)
the RTL8139C(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must be avoided from exceeding 2K byte.
Transmit OK: Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun occurs.
Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted
during the transmission of a packet. The RTL8139C(L) can re-transfer
data if the Tx FIFO underruns and can also transmit the packet to the
wire successfully even though the Tx FIFO underruns. That is, when
TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).
OWN: The RTL8139C(L) sets this bit to 1 when the Tx DMA
operation of this descriptor was completed. The driver must set this bit
to 0 when the Transmit Byte Count (bit0-12) is written. The default
value is 1.
15
14
R
R
TOK
TUN
13
R/W
R/W
OWN
SIZE
12-0
Descriptor Size: The total size in bytes of the data in this descriptor. If
the packet length is more than 1792 byte (0700h), the Tx queue will be
invalid, i.e. the next descriptor will be written only after the OWN bit of
that long packet's descriptor has been set.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.3. ERSR: Early Rx Status Register (Offset 0036h, R)
Bit
7-4
3
R/W
-
R
Symbol
-
ERGood
Description
Reserved
Early Rx Good packet: This bit is set whenever a packet is completely
received and the packet is good. This bit is cleared when writing 1 to it,
Early Rx Bad packet: This bit is set whenever a packet is completely
received and the packet is bad. Writing 1 will clear this bit.
Early Rx OverWrite: This bit is set when the RTL8139C(L)'s local
address pointer is equal to CAPR. In the early mode, this is different
from buffer overflow. It happens that the RTL8139C(L) detected an Rx
error and wanted to fill another packet data from the beginning address
of that error packet. Writing 1 will clear this bit.
2
1
R
R
ERBad
EROVW
0
R
EROK
Early Rx OK: The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8139C(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke a ROK interrupt.
6.4. Command Register (Offset 0037h, R/W)
This register is used for issuing commands to the RTL8139C(L). These commands are issued by setting the corresponding bits for
the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.
Bit
7-5
4
R/W
-
R/W
Symbol
Description
-
Reserved
RST
Reset: Setting to 1 forces the RTL8139C(L) to a software reset state
which disables the transmitter and receiver, reinitializes the FIFOs,
resets the system buffer pointer to the initial value (Tx buffer is at
TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and
PCI configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8139C(L) when the reset
operation is complete.
3
2
R/W
R/W
RE
TE
Receiver Enable: When set to 1, and the receive state machine is idle,
the receive machine becomes active. This bit will read back as a 1
whenever the receive state machine is active. After initial power-up,
software must insure that the receiver has completely reset before
setting this bit.
Transmitter Enable: When set to 1, and the transmit state machine is
idle, then the transmit state machine becomes active. This bit will read
back as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has completely reset
before setting this bit.
1
0
-
R
-
Reserved
BUFE
Buffer Empty: The Rx buffer is empty; There is no packet stored in the
Rx buffer ring.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.5. Interrupt Mask Register (Offset 003Ch-003Dh, R/W)
This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt.
During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt.
ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit.
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error Interrupt: 1 => Enable, 0 => Disable.
14
13
12-7
6
R/W
R/W
-
R/W
R/W
TimeOut
LenChg
-
Time Out Interrupt: 1 => Enable, 0 => Disable.
Cable Length Change Interrupt: 1 => Enable, 0 => Disable.
Reserved
Rx FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.
Packet Underrun/Link Change Interrupt: 1 => Enable, 0 =>
Disable.
FOVW
PUN/LinkChg
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
RXOVW
TER
TOK
RER
ROK
Rx Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.
Transmit Error Interrupt: 1 => Enable, 0 => Disable.
Transmit OK Interrupt: 1 => Enable, 0 => Disable.
Receive Error Interrupt: 1 => Enable, 0 => Disable.
Receive OK Interrupt: 1 => Enable, 0 => Disable.
6.6. Interrupt Status Register (Offset 003Eh-003Fh, R/W)
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt
Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this
register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the
corresponding mask bit in the IMR. Writing a 1 to any bit will reset that bit, but writing a 0 has no effect.
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error: Set to 1 when the RTL8139C(L) signals a system error
on the PCI bus.
14
13
R/W
R/W
TimeOut
LenChg
Time Out: Set to 1 when the TCTR register reaches to the value of the
TimerInt register.
Cable Length Change: Cable length is changed after Receiver is
enabled.
12 - 7
-
-
Reserved
6
5
R/W
R/W
FOVW
PUN/LinkChg
Rx FIFO Overflow: Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change: Set to 1 when CAPR is written but
Rx buffer is empty, or when link status is changed.
Rx Buffer Overflow: Set when receive (Rx) buffer ring storage
resources have been exhausted.
Transmit (Tx) Error: Indicates that a packet transmission was
aborted, due to excessive collisions, according to the TXRR's setting
Transmit (Tx) OK: Indicates that a packet transmission is completed
successfully.
Receive (Rx) Error: Indicates that a packet has either CRC error or
frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.
Receive (Rx) OK: In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.
4
3
2
1
R/W
R/W
R/W
R/W
RXOVW
TER
TOK
RER
0
R/W
ROK
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.7. Transmit Configuration Register (Offset
0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8139C(L). It controls such functions as Loopback, Heartbeat, Auto
Transmit Padding, programmable Inter-frame Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Bit
31
R/W
-
Symbol
-
Description
Reserved
30-26
R
HWVERID
Hardware Version ID:
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23
RTL8139
RTL8139A
RTL8139A-G
RTL8139B
RTL8130
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
RTL8139C
Reserved
All other combination
25-24
R/W
IFG1, 0
Interframe Gap Time: This field allows adjustment of the interframe
gap time below the standards of 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps
100 Mbps
8.4us + 0.4(IFG(1:0)) us
840ns + 40(IFG(1:0)) ns
23
22-19
18, 17
R
-
R/W
8139A-G
-
LBK1, LBK0
RTL8139A rev.G ID = 1. For others, this bit is 0.
Reserved
Loopback test: There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent of
the link state.
00: normal operation
01: Reserved
10: Reserved
11: Loopback mode
16
R/W
CRC
Append CRC:
0: A CRC is appended at the end of a packet
1: No CRC appended at the end of a packet
15-11
10-8
-
-
Reserved
R/W
MXDMA2, 1, 0
Max DMA Burst Size per Tx DMA Burst: This field sets the
maximum size of transmit DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Bit
R/W
Symbol
Description
7-4
R/W
TXRR
Tx Retry Count: These are used to specify additional transmission
retries in multiples of 16 (IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit 16 times before
aborting due to excessive collisions. If the TXRR is set to a value
greater than 0, the transmitter will re-transmit a number of times equal
to the following formula before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set when
the transmission fails and reaches to this specified retry count.
Reserved
Clear Abort: Setting this bit to 1 causes the RTL8139C(L) to
retransmit the packet at the last transmitted descriptor when this
transmission was aborted. Setting this bit is only permitted in the
transmit abort state.
3-1
0
-
W
-
CLRABT
6.8. Receive Configuration Register (Offset 0044h-0047h, R/W)
This register is used to set the receive configuration for the RTL8139C(L). Receive properties such as accepting error packets,
runt packets, setting the receive drain threshold etc. are controlled here.
Bit
31-28
27-24
R/W
-
R/W
Symbol
Description
-
Reserved
ERTH3, 2, 1, 0
Early Rx threshold bits: These bits are used to select the Rx threshold
multiplier of the whole packet that has been transferred to the system
buffer in early mode when the frame protocol is under the
RTL8139C(L)'s definition.
0000 = no early rx threshold
0010 = 2/16
0100 = 4/16
0110 = 6/16
1000 = 8/16
1010 = 10/16
1100 = 12/16
1110 = 14/16
Reserved
0001 = 1/16
0011 = 3/16
0101 = 5/16
0111 = 7/16
1001 = 9/16
1011 = 11/16
1101 = 13/16
1111 = 15/16
23-18
17
-
-
R/W
MulERINT
Multiple early interrupt select: When this bit is set, any received
packet invokes early interrupt according to MULINT<MISR[11:0]>
setting in early mode. When this bit is reset, the packets of familiar
protocol (IPX, IP, NDIS, etc) invoke early interrupt according to
RCR<ERTH[3:0]> setting in early mode. The packets of unfamiliar
protocol will invoke early interrupt according to the setting of
MULINT<MISR[11:0]>.
16
R/W
RER8
The RTL8139C(L) receives the error packet whose length is larger than
8 bytes after setting the RER8 bit to 1.
The RTL8139C(L) receives the error packet larger than 64-byte long
when the RER8 bit is cleared. The power-on default is zero.
If AER or AR is set, the RER will be set when the RTL8139C(L)
receives an error packet whose length is larger than 8 bytes. The RER8
is “ Don’t care “ in this situation.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Bit
R/W
Symbol
Description
15-13
R/W
RXFTH2, 1, 0
Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the
number of the received data bytes from a packet, which is being
received into the RTL8139C(L)'s Rx FIFO, has reached to this level (or
the FIFO has contained a complete packet), the receive PCI bus master
function will begin to transfer the data from the FIFO to the host
memory. This field sets the threshold level according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = no rx threshold. The RTL8139C(L) begins the transfer of data
after having received a whole packet in the FIFO.
12-11
10-8
R/W
R/W
RBLEN1, 0
Rx Buffer Length: This field indicates the size of the Rx ring buffer.
00 = 8k + 16 byte
01 = 16k + 16 byte
10 = 32K + 16 byte
11 = 64K + 16 byte
Max DMA Burst Size per Rx DMA Burst: This field sets the
MXDMA2, 1, 0
maximum size of the receive DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = unlimited
7
R/W
WRAP
0: The RTL8139C(L) will transfer the rest of the packet data into the
beginning of the Rx buffer if this packet has not been completely
moved into the Rx buffer and the transfer has arrived at the end of
the Rx buffer.
1: The RTL8139C(L) will keep moving the rest of the packet data into the
memory immediately after the end of the Rx buffer, if this packet has
not been completely moved into the Rx buffer and the transfer has
arrived at the end of the Rx buffer. The software driver must reserve at
least 1.5K bytes buffer to accept the remainder of the packet. We
assume that the remainder of the packet is X bytes. The next packet will
be moved into the memory from the X byte offset at the top of the Rx
buffer.
This bit is invalid when Rx buffer is selected to 64K bytes.
EEPROM Select: This bit reflects what type of EEPROM is used.
1: The EEPROM used is 9356.
6
5
R
9356SEL
AER
0: The EEPROM used is 9346.
R/W
Accept Error Packets: This bit determines if packets with CRC error,
alignment error and/or collided fragments will be accepted or rejected.
0: Reject error packets
1: Accept error packets
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RTL8139C(L)
Datasheet
Bit
R/W
Symbol
Description
4
R/W
AR
Accept Runt Packets: This bit allows the receiver to accept packets
that are smaller than 64 bytes. The packet must be at least 8 bytes long to
be accepted as a runt.
0: Reject runt packets
1: Accept runt packets
3
2
1
0
R/W
R/W
R/W
R/W
AB
AM
Accept Broadcast Packets: This bit allows the receiver to accept or
reject broadcast packets.
0: Reject broadcast packets
1: Accept broadcast packets
Accept Multicast Packets: This bit allows the receiver to accept or
reject multicast packets.
0: Reject multicast packets
1: Accept multicast packets
Accept Physical Match Packets: This bit allows the receiver to accept
or reject physical match packets.
0: Reject physical match packets
APM
AAP
1: Accept physical match packets
Accept Physical Address Packets: This bit allows the receiver to
accept or reject packets with a physical destination address.
0: Reject packets with a physical destination address
1: Accept packets with a physical destination address
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RTL8139C(L)
Datasheet
6.9. 9346CR: 93C46 (93C56) Command Register (Offset
0050h, R/W)
Bit
R/W
Symbol
Description
7-6
R/W
EEM1-0
Operating Mode: These 2 bits select the RTL8139C(L) operating mode.
EEM1
EEM0
Operating Mode
0
0
Normal (RTL8139C(L) network/host communication
mode)
0
1
Auto-load: Entering this mode will make the
RTL8139C(L) load the contents of 93C46 (93C56) as
when the RSTB signal is asserted. This auto-load
operation will take about 2 ms. After it is completed, the
RTL8139C(L) goes back to the normal mode
automatically (EEM1 = EEM0 = 0) and all the other
registers are reset to default values.
1
1
0
1
93C46 (93C56) programming: In this mode, both network
and host bus master operations are disabled. The 93C46
(93C56) can be directly accessed via bit3-0 which now
reflect the states of EECS, EESK, EEDI, & EEDO pins
respectively.
Config register write enable: Before writing to CONFIG0,
1, 3, 4 registers, and bit13, 12, 8 of BMCR(offset
62h-63h), the RTL8139C(L) must be placed in this mode.
This will prevent RTL8139C(L)'s configurations from
accidental change.
4-5
3
2
1
0
-
-
Reserved
R/W
R/W
R/W
R
EECS
EESK
EEDI
EEDO
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in
auto-load or 93C46 (93C56) programming mode and are valid only
when Flash bit is cleared.
Note: EESK, EEDI and EEDO is valid after boot ROM complete.
6.10. CONFIG 0: Configuration Register 0 (Offset 0051h, R/W)
Bit
7
6
R/W
R
R
Symbol
SCR
PCS
Description
Scrambler Mode: Always 0.
PCS Mode: Always 0.
5
R
T10
10 Mbps Mode: Always 0.
4-3
2-0
R
R
PL1, PL0
BS2, BS1, BS0
Select 10 Mbps medium type: Always (PL1, PL0) = (1, 0)
Select Boot ROM size
BS2
0
BS1
0
BS0
0
Description
No Boot ROM
0
0
1
8K Boot ROM
16K Boot ROM
32K Boot ROM
64K Boot ROM
128K Boot ROM
unused
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
unused
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RTL8139C(L)
Datasheet
6.11. CONFIG 1: Configuration Register 1 (Offset 0052h, R/W)
Bit
7-6
5
R/W
R/W
R/W
Symbol
LEDS1-0
DVRLOAD
Description
Refer to LED PIN definition. These bits’ initial value come from 93C46/93C56.
Driver Load: Software may use this bit to make sure that the driver has been
loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,
MEMEN, and BMEN of the PCI configuration space are written, the
RTL8139C(L) will clear this bit automatically.
4
R/W
LWACT
LWAKE active mode: The LWACT bit and LWPTN bit in the CONFIG4
register are used to program the LWAKE pin’s output signal. According to the
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,
active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150 ms. In CardBus applications, the LWACT and
LWPTN have no meaning.
The default value of each of these two bits is 0, i.e., the default output signal of
the LWAKE pin is an active high signal.
LWAKE output
LWACT
0
1
0
Active high*
Active low
LWPTN
1
Positive pulse
Negative pulse
* Default value.
3
2
1
R
R
R/W
MEMMAP
IOMAP
VPD
Memory Mapping: The operational registers are mapped into PCI memory space.
I/O Mapping: The operational registers are mapped into PCI I/O space.
Vital Product Data: This is used to set to enable Vital Product Data. The VPD
data is stored in 93C46 or 93C56 from within offset 40h-7Fh.
Power Management Enable:
0
R/W
PMEn
Write able only when 93C46CR register EEM1=EEM0=1
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Configuration space offset 06H.
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI Configuration
space offset 50H.
Let D denote the power management registers in the PCI Configuration space
offset from 52H to 57H.
Let E denote the Next_Ptr (power management) register in the PCI
Configuration space offset 51H.
PMEn Description
0
1
A=B=C=E=0, D not valid
A=1, B=50h, C=01h, D valid, E=0
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RTL8139C(L)
Datasheet
6.12. Media Status Register (Offset 0058h, R/W)
This register allows configuration of a variety of device and PHY options, and provides PHY status information.
Bit
7
R/W
R/W
Symbol
TXFCE/
Description
Tx Flow Control Enable: The flow control is valid in full-duplex
LdTXFCE
mode only. This register’s default value comes from 93C46 (93C56).
RTL8139C(L)
ANE = 1
Remote
NWAY FLY mode
NWAY mode only
No NWAY
TXFCE/LdTXFCE
R/O
R/W
R/W
R/W
ANE = 1
ANE = 1
ANE = 0 &
full-duplex mode
ANE = 0 &
half-duplex mode
-
-
invalid
NWAY FLY mode: NWAY with flow control capability
NWAY mode only: NWAY without flow control capability
RX Flow control Enable: The flow control is enabled in full-duplex
mode only. The default value comes from 93C46 (93C56).
Reserved
6
R/W
RXFCE
5
4
-
R
-
Aux_Status
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
Speed: Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
3
R
SPEED_10
2
1
R
R
LINKB
TXPF
Inverse of Link status: 0 = Link OK. 1 = Link Fail.
Transmit Pause Flag: Set when the RTL8139C(L) sends pause packet.
Reset when the RTL8139C(L) sends timer done packet.
Receive Pause Flag: Set when the RTL8139C(L) is in backoff state
because a pause packet received. Reset when pause state is clear.
0
R
RXPF
6.13. CONFIG 3: Configuration Register3 (Offset 0059h, R/W)
Bit
R/W
Symbol
Description
7
R
GNTSel
Gnt Select: Select the Frame’s asserted time after the Grant signal has
been asserted. The Frame and Grant are the PCI signals.
1: Delay one clock from GNT assertion
0: No delay
6
R/W
PARM_En
Parameter Enable: (These parameters are used in 100Mbps mode)
Setting to 0 and 9346CR register EEM1=EEM0=1 enable the
PHY1_PARM, PHY2_PARM, TW_PARM be written via software.
Setting to 1 will allow parameters auto-loaded from 93C46 (93C56)
and disable writing to PHY1_PARM, PHY2_PARM and TW_PARM
registers via software. The PHY1_PARM, PHY2_PARM, and
TW_PARM can be auto-loaded from EEPROM in this mode. The
parameter auto-load process is executed every time when the Link is
OK in 100Mbps mode.
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RTL8139C(L)
Datasheet
Bit
R/W
Symbol
Description
5
R/W
Magic
Magic Packet: This bit is valid when the PWEn bit of CONFIG1
register is set. The RTL8139C(L) will assert the PMEB signal to
wakeup the operating system when the Magic Packet is received.
Once the RTL8139C(L) has been enabled for Magic Packet wakeup
and has been put into adequate state, it scans all incoming packets
addressed to the node for a specific data sequence, which indicates to
the controller that this is a Magic Packet frame. A Magic Packet frame
must also meet the basic requirements: Destination address + Source
address + data + CRC
The destination address may be the node ID of the receiving station or
a multicast address, which includes the broadcast address.
The specific sequence consists of 16 duplications of 6 byte ID registers,
with no breaks or interrupts. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream, 6
bytes of FFh. The device will also accept a multicast address, as long as the
16 duplications of the IEEE address match the address of the ID registers.
If the Node ID is 11h 22h 33h 44h 55h 66h, then the magic frame’s
format is like the following:
Destination address + source address + MISC + FF FF FF FF FF FF +
MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +
11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66
+ 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33
44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC
Link Up: This bit is valid when the PWEn bit of CONFIG1 register is
set. The RTL8139C(L), in adequate power state, will assert the PMEB
signal to wakeup the operating system when the cable connection is
re-established.
4
R/W
LinkUp
3
2
R
R
CardB_En
Card Bus Enable: Set to 1 to enable CardBus related registers and
functions. Set to 0 to disable CardBus related registers and functions.
CLKRUN Enable:
CLKRUN_En
Set to 1 to enable CLKRUN.
Set to 0 to disable CLKRUN.
1
0
R
R
FuncRegEn
FBtBEn
Functions Registers Enable (CardBus only): Set to 1 to enable the 4
Function Registers (Function Event Register, Function Event Mask
Register, Function Present State Register, and Function Force Event
Register) for CardBus application.
Set to 0 to disable the 4 Function Registers for CardBus application.
Fast Back to Back Enable: Set to 1 to enable Fast Back to Back.
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Datasheet
6.14. CONFIG 4: Configuration Register4 (Offset 005Ah, R/W)
Bit
R/W
Symbol
Description
7
R/W
RxFIFOAutoClr
When set to 1, the RTL8139C(L) will clear the Rx FIFO overflow
automatically.
6
5
R/W
R/W
AnaOff
Analog Power Off: This bit can not be auto-loaded from EEPROM
(9346 or 9356).
1: Turn off the analog power of the RTL8139C(L) internally.
0: Normal working state. This is also power-on default value.
Long Wake-up Frame: The initial value comes from EEPROM
autoload.
LongWF
Set to 1: The RTL8139C(L) supports up to 5 wake-up frames, each
with 16-bit CRC algorithm for MS Wakeup Frame, the low byte of
16-bit CRC should be placed at the correspondent CRC register, and
the high byte of 16-bit CRC should be placed at the correspondent
LSBCRC register. The wake-up frame 0 and 1 are the same as above,
except that the masked bytes start from offset 0 to 63. The wake-up
frame 2 and 3 are merged into one long wake-up frame respectively
with masked bytes selected from offset 0 to 127. The wake-up frame 4
and 5, 6 and 7 are merged respectively into another 2 long wake-up
frames. Please refer to 7.4 PCI Power Management functions for a
detailed description.
Set to 0: The RTL8139C(L) supports up to 8 wake-up frames, each
with masked bytes selected from offset 12 to 75.
LANWAKE vs. PMEB:
4
R/W
LWPME
Set to 1: The LWAKE can only be asserted when the PMEB is asserted
and the ISOLATEB is low.
Set to 0: The LWAKE and PMEB are asserted at the same time.
In CardBus application, this bit has no meaning.
Reserved
LWAKE pattern: Please refer to LWACT bit in CONFIG1 register.
Reserved
Pre-Boot Wakeup: The initial value comes from EEPROM autoload.
1: Pre-Boot Wakeup disabled. (suitable for CardBus and MiniPCI
application)
3
2
1
0
-
-
R/W
-
R/W
LWPTN
-
PBWakeup
0: Pre-Boot Wakeup enabled.
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Datasheet
6.15. Multiple Interrupt Select Register (Offset
005Ch-005Dh, R/W)
If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to RTL8139C(L), RCR<ERTH[3:0]> will not be used
to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for
the unfamiliar protocol.
Bit
15-12
11-0
R/W
-
R/W
Symbol
-
MISR11-0
Description
Reserved
Multiple Interrupt Select: Indicates that the RTL8139C(L) makes an
Rx interrupt after RTL8139C(L) has transferred the byte data into the
system memory. If the value of these bits is zero, there will be no early
interrupt as soon as the RTL8139C(L) prepares to execute the first PCI
transaction of the received data. Bit1, 0 must be zero.
The ERTH3-0 bits should not be set to 0 when the multiple interrupt
select register is used.
¾
The above is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet invokes early interrupt
according to MISR[11:0] setting in early mode.
6.16. PCI Revision ID (Offset 005Eh, R)
Bit
R/W
Symbol
Description
7-0
R
Revision ID
The value in PCI Configuration Space offset 08h is 10h.
6.17. Transmit Status of All Descriptors (TSAD) Register (Offset
0060h-0061h, R/W)
Bit
15
14
13
12
11
10
9
8
7
6
5
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Symbol
TOK3
TOK2
TOK1
TOK0
TUN3
TUN2
TUN1
TUN0
TABT3
TABT2
TABT1
TABT0
OWN3
OWN2
OWN1
OWN0
Description
TOK bit of Descriptor 3
TOK bit of Descriptor 2
TOK bit of Descriptor 1
TOK bit of Descriptor 0
TUN bit of Descriptor 3
TUN bit of Descriptor 2
TUN bit of Descriptor 1
TUN bit of Descriptor 0
TABT bit of Descriptor 3
TABT bit of Descriptor 2
TABT bit of Descriptor 1
TABT bit of Descriptor 0
OWN bit of Descriptor 3
OWN bit of Descriptor 2
OWN bit of Descriptor 1
OWN bit of Descriptor 0
4
3
2
1
0
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Datasheet
6.18. Basic Mode Control Register (Offset 0062h-0063h, R/W)
Bit
Name
Description/Usage
Default/
Attribute
0, RW
15
This bit sets the status and control registers of the PHY(register
0062-0074H) in a default state. This bit is self-clearing. 1 = software
reset; 0 = normal operation.
Reset
14
13
Reserved
-
-
This bit sets the network speed. 1 = 100Mbps; 0 = 10Mbps. This bit‘s
initial value comes from 93C46 (93C56).
0, RW
Spd_Set
12
This bit enables/disables the NWay auto-negotiation function. Set to
1 to enable auto-negotiation, bit13 will be ignored.
Set to 0 disables auto-negotiation, bit13 and bit8 will determine the
link speed and the data transfer mode, respectively. This bit‘s initial
value comes from 93C46 (93C56).
0, RW
Auto Negotiation
Enable
(ANE)
11-10
9
Reserved
-
-
This bit allows the NWay auto-negotiation function to be reset.
1 = re-start auto-negotiation; 0 = normal operation.
This bit sets the duplex mode. 1 = full-duplex; 0 = normal operation.
This bit‘s initial value comes from 93C46 (93C56).
If bit12 = 1, read = status write = register value.
If bit12 = 0, read = write = register value.
0, RW
Restart Auto
Negotiation
Duplex Mode
8
0, RW
7-0
Reserved
-
-
6.19. Basic Mode Status Register (Offset 0064h-0065h, R)
Bit
15
14
Name
100Base-T4
100Base_TX_ FD
Description/Usage
1 = enable 100Base-T4 support; 0 = suppress 100Base-T4 support.
1 = enable 100Base-TX full duplex support;
0 = suppress 100Base-TX full duplex support.
1 = enable 100Base-TX half-duplex support;
0 = suppress 100Base-TX half-duplex support.
1 = enable 10Base-T full duplex support;
0 = suppress 10Base-T full duplex support.
1 = enable 10Base-T half-duplex support;
0 = suppress 10Base-T half-duplex support.
Reserved
1 = auto-negotiation process completed;
0 = auto-negotiation process not completed.
1 = remote fault condition detected (cleared on read);
0 = no remote fault condition detected.
1 = Link had not been experienced fail state.
0 = Link had been experienced fail state
1 = valid link established;
Default/ Attribute
0, RO
1, RO
13
12
11
1, RO
1, RO
1, RO
100BASE_TX_H
D
10Base_T_FD
10_Base_T_HD
10-6
5
-
-
0, RO
Auto Negotiation
Complete
Remote Fault
4
3
2
0, RO
1, RD
0, RO
Auto Negotiation
Link Status
0 = no valid link established.
1
0
1 = jabber condition detected; 0 = no jabber condition detected.
1 = extended register capability;
0, RO
1, RO
Jabber Detect
Extended
0 = basic register capability only.
Capability
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RTL8139C(L)
Datasheet
6.20. Auto-Negotiation Advertisement Register (Offset
0066h-0067h, R/W)
Bit
Name
NP
Description/Usage
Default/ Attribute
15
Next Page bit.
0, RO
1 = transmitting the protocol specific data page;
0 = transmitting the primary capability data page
1 = acknowledge reception of link partner capability data word.
1 = advertise remote fault detection capability;
0 = do not advertise remote fault detection capability.
Reserved
14
13
0, RO
0, RW
ACK
RF
12-11
10
-
-
1 = flow control is supported by local node.
0 = flow control is not supported by local mode.
The default value
comes from
EEPROM, RO
0, RO
Pause
9
8
1 = 100Base-T4 is supported by local node;
0 = 100Base-T4 not supported by local node.
1 = 100Base-TX full duplex is supported by local node;
0 = 100Base-TX full duplex not supported by local node.
1 = 100Base-TX is supported by local node;
0 = 100Base-TX not supported by local node.
1 = 10Base-T full duplex supported by local node;
0 = 10Base-T full duplex not supported by local node.
1 = 10Base-T is supported by local node;
T4
TXFD
TX
1, RW
1, RW
7
6
1, RW
10FD
10
5
1, RW
0 = 10Base-T not supported by local node.
4-0
Binary encoded selector supported by this node. Currently only
CSMA/ CD <00001> is specified. No other protocols are
supported.
<00001>, RW
Selector
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Datasheet
6.21. Auto-Negotiation Link Partner Ability Register (Offset
0068h-0069h, R)
Bit
Name
Description/Usage
Default/ Attribute
15
Next Page bit.
0, RO
NP
1 = transmitting the protocol specific data page;
0 = transmitting the primary capability data page
1 = link partner acknowledges reception of local node’s capability
data word.
14
0, RO
ACK
13
12-11
10
1 = link partner is indicating a remote fault.
Reserved
0, RO
-
0, RO
RF
-
Pause
1 = Flow control is supported by link partner,
0 = Flow control is not supported by link partner.
1 = 100Base-T4 is supported by link partner;
0 = 100Base-T4 not supported by link partner.
1 = 100Base-TX full duplex is supported by link partner;
0 = 100Base-TX full duplex not supported by link partner.
1 = 100Base-TX is supported by link partner;
0 = 100Base-TX not supported by link partner.
1 = 10Base-T full duplex is supported by link partner;
0 = 10Base-T full duplex not supported by link partner.
1 = 10Base-T is supported by link partner;
0 = 10Base-T not supported by link partner.
Link Partner's binary encoded node selector. Currently only
CSMA/ CD <00001> is specified.
9
8
0, RO
0, RO
T4
TXFD
TX
7
0, RO
6
0, RO
10FD
10
5
0, RO
4-0
<00000>, RO
Selector
6.22. Auto-Negotiation Expansion Register (Offset
006Ah-006Bh, R)
This register contains additional status for NWay auto-negotiation.
Bit
15-5
4
Name
-
MLF
Description/Usage
Reserved. These bits are always set to 0.
Status indicating if a multiple link fault has occurred.
1 = fault occurred; 0 = no fault occurred.
Default/ Attribute
-
0, RO
3
2
1
Status indicating if the link partner supports Next Page negotiation.
1 = supported; 0 = not supported.
This bit indicates if the local node is able to send additional Next
Pages.
This bit is set when a new Link Code Word Page has been received.
The bit is automatically cleared when the auto-negotiation link
partner’s ability register (register 5) is read by management.
1 = link partner supports NWay auto-negotiation.
0, RO
0, RO
0, RO
LP_NP_ABLE
NP_ABLE
PAGE_RX
0
0, RO
LP_NW_ABLE
6.23. Disconnect Counter (Offset 006Ch-006Dh, R)
Bit
Name
Description/Usage
Default/ Attribute
15-0
This 16-bit counter increments by 1 for every disconnect event. It rolls
over when becomes full. It is cleared to zero by read command.
h'[0000],
R
DCNT
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RTL8139C(L)
Datasheet
6.24. False Carrier Sense Counter (Offset 006Eh-006Fh, R)
This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of
Clause 30 of the IEEE 802.3u specification.
Bit
Name
Description/Usage
Default/ Attribute
15-0
This 16-bit counter increments by 1 for each false carrier event. It is
cleared to zero by read command.
h'[0000],
R
FCSCNT
6.25. NWay Test Register (Offset 0070h-0071h, R/W)
Bit
15-8
7
Name
-
Description/Usage
Default/ Attribute
Reserved
-
1 = set NWay to loopback mode.
Reserved
0, RW
-
0, RW
0, RO
0, RO
0, RO
NWLPBK
-
6-4
3
2
1
0
1 = LED0 Pin indicates linkpulse
ENNWLE
FLAGABD
FLAGPDF
FLAGLSC
1 = Auto-neg experienced ability detect state
1 = Auto-neg experienced parallel detection fault state
1 = Auto-neg experienced link status check state
6.26. RX_ER Counter (Offset 0072h-0073h, R)
Bit
Name
Description/Usage
Default/ Attribute
15-0
This 16-bit counter increments by 1 for each valid packet received.
It is cleared to zero by read command.
h'[0000],
R
RXERCNT
6.27. CS Configuration Register (Offset 0074h-0075h, R/W)
Bit
15
14-10
9
Name
Testfun
-
Description/Usage
1 = Auto-neg speeds up internal timer
Reserved
Active low TPI link disable signal. When low, TPI still transmits
link pulses and TPI stays in good link state.
1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART
BEAT function is only valid in 10Mbps mode.
1 = enable jabber function. 0 = disable jabber function
Used to login force good link in 100Mbps for diagnostic purposes.
1 = DISABLE, 0 = ENABLE.
Default/ Attribute
0,WO
-
1, RW
LD
8
1, RW
HEART BEAT
7
6
1, RW
1, RW
JBEN
F_LINK_100
5
4
3
Assertion of this bit forces the disconnect function to be bypassed.
Reserved
This bit indicates the status of the connection. 1 = valid connected
link detected; 0 = disconnected link detected.
Assertion of this bit configures LED1 pin to indicate connection
status.
0, RW
-
0, RO
F_Connect
-
Con_status
2
0, RW
Con_status_En
1
0
Reserved
Bypass Scramble
-
-
0, RW
PASS_SCR
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.28. Flash Memory Read/Write Register (Offset
00D4h-00D7h, R/W)
Bit
R/W
Symbol
Description
31-24
R/W
MD7-MD0
Flash Memory Data Bus: These bits set and reflect the state of the
MD7 - MD0 pins, during write and read process respectively.
Reserved
Chip Select: This bit sets the state of the ROMCSB pin.
Output Enable: This bit sets the state of the OEB pin.
Write Enable: This bit sets the state of the WEB pin.
Enable software access to flash memory:
23-21
20
19
18
17
-
-
W
W
W
W
ROMCSB
OEB
WEB
SWRWEn
0: Disable read/write access to flash memory via software.
1: Enable read/write access to flash memory via software and disable
the EEPROM access during flash memory access via software.
Flash Memory Address Bus: These bits set the state of the MA16-0
pins.
16-0
W
MA16-MA0
6.29. Config5: Configuration Register 5 (Offset 00D8h, R/W)
This register, unlike other Config registers, is not protected by the 93C46 Command register. Therefore, there is no need to
enable Config register write prior to writing to Config5.
Bit
7
R/W
-
Symbol
-
Description
Reserved
6
R/W
BWF
Broadcast Wakeup Frame:
0: Default value. Disable Broadcast Wakeup Frame with mask bytes
of only DID field = FF FF FF FF FF FF.
1: Enable Broadcast Wakeup Frame with mask bytes of only DID
field = FF FF FF FF FF FF.
The power-on default value of this bit is 0.
5
4
R/W
R/W
MWF
UWF
Mroadcast Wakeup Frame:
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only DID field, which is a multicast address.
1: Enable Multicast Wakeup Frame with mask bytes of only DID
field, which is a multicast address.
The power-on default value of this bit is 0.
Unicast Wakeup Frame:
0: Default value. Disable Unicast Wakeup Frame with mask bytes of
only DID field, which is its own physical address.
1: Enable Unicast Wakeup Frame with mask bytes of only DID field,
which is its own physical address.
The power-on default value of this bit is 0.
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Bit
R/W
Symbol
Description
3
R/W
FIFOAddrPtr
FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM)
0: (Power-on) default value. Both Rx and Tx FIFO address pointers
are updated in ascending way from 0 and upwards. The initial FIFO
address pointer is 0.
1: Both Rx and Tx FIFO address pointers are updated in descending
way from 1FFh and downwards. The initial FIFO address pointer is
1FFh.
Note: This bit does not participate in EEPROM auto-load. The FIFO
address pointers can not be reset, except initial power-on.
The power-on default value of this bit is 0.
2
R/W
LDPS
Link Down Power Saving mode: When cable is disconnected (Link
Down), the analog part will power down itself (PHY Tx part & part of
twister) automatically. However, the PHY Rx part and part of twister
to monitor SD signal will not, in case the cable is re-connected and
Link should be established again.
1: Disable.
0: Enable.
1
0
R/W
R/W
LANWake
PME_STS
LANWake signal enable/disable:
1: Enable LANWake signal.
0: Disable LANWake signal.
PME_Status bit: Always sticky/can be reset by PCI RST# and
software.
1: The PME_Status bit can be reset by PCI reset or by software.
0: The PME_Status bit can only be reset by software.
¾
¾
Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer
supported by RTL8139C.)
The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8139C Config5 register.
6.30. Function Event Register (Offset 00F0h-00F3h, R/W)
Bit
31-16
15
R/W
-
R/W
Symbol
-
INTR
Description
Reserved
Interrupt: This bit is set to 1 when INTR field in the Function Force
Event Register is set. Writing a 1 may clear this bit. Writing a 0 has no
effect. This bit is not affected by the RST# pin and software reset.
Reserved
General Wakeup: This bit is set to 1 when the GWAKE field in the
Function Present State Register changes its state from 0 to 1. This bit
can also be set when the GWAKE bit of the Function Force Register is
set. Writing a 1 may clear this bit. Writing a 0 has no effect. This bit is
not affected by the RST# pin.
14-5
4
-
-
R/W
GWAKE
3-0
-
-
Reserved
¾
¾
This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).
The Function Event (Offset F0h), Function Event Mask (Offset F4h), Function Present State (Offset F8h), and Function
Force Event (Offset FCh) registers have some corresponding fields with the same names. The GWAKE and INTR bits
of these registers reflect the wake-up event signaled on the SCTCSCHG pin. The operation of CSTCSCHG pin is similar
to PME# pin except that the CSTCSCHG pin is asserted high.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.31. Function Event Mask Register (Offset 00F4h-00F7h, R/W)
Bit
31-16
15
R/W
-
R/W
Symbol
-
INTR
Description
Reserved
Interrupt mask: When cleared (0), setting of the INTR bit in either
the Function Present State Register or the Function Event Register
will neither cause assertion of the INT# signal while the CardBus PC
Card interface is powered up, nor the system Wakeup (CSTSCHG)
while the interface is powered off. Setting this bit to 1, enables the
INTR bit in both the Function Present State Register and the Function
Event Register to generate the INT# signal (and the system Wakeup if
the corresponding WKUP field in this Function Event Mask Register
is also set). This bit is not affected by the RST# pin.
14
R/W
WKUP
Wakeup mask: When cleared (0), the Wakeup function is disabled, i.e.,
the setting of this bit in the Function Event Register will not assert the
CSTSCHG signal. Setting this bit to 1, enables the fields in the
Function Event Register to assert the CSTSCHG signal. This bit is not
affected by RST#.
13-5
4
-
-
Reserved
R/W
GWAKE
General Wakeup mask: When cleared (0), setting this bit in the
Function Event Register will not cause the CSTSCHG pin to be
asserted. Setting this bit to 1, enables the GWAKE field in the
Function Event Register to assert CSTSCHG pin if bit14 of this
register is also set. This bit is not affected by RST#.
3-0
-
-
Reserved
¾
This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).
6.32. Function Present State Register (Offset 00F8h-00FBh, R)
Bit
31-16
15
R/W
-
R
Symbol
-
INTR
Description
Reserved
Interrupt: This bit is set when one of the ISR register bits has been set
to 1. This bit remains set (1), until all of the ISR register bits have been
cleared. It is not affected by RST#.
14-5
4
-
R
-
Reserved
GWAKE
General Wakeup: This bit reflects the current state of the Wakeup
event(s), it’s just like the PME_Status bit of the PMCSR register. This
bit remains set (1), until the PME_Status bit of the PMCSR register is
cleared. It is not affected by RST#.
3-0
-
-
Reserved
¾
¾
This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).
This read-only register reflects the current state of the function.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
6.33. Function Force Event Register (Offset 00FCh-00FFh, W)
Bit
31-16
15
R/W
-
W
Symbol
-
INTR
Description
Reserved
Interrupt: Writing a 1 sets the INTR bit in the Function Event
Register. However, the INTR bit in the Function Present State
Register is not affected and continues to reflect the current state of the
ISR register. Writing a 0 to this bit has no effect.
14-5
4
-
W
-
Reserved
GWAKE
General Wakeup: Setting this bit to 1, sets the GWAKE bit in the
Function Event Register. However, the GWAKE bit in the Function
Present State Register is not affected and continues to reflect the current
state of the Wakeup request. Writing a 0 to this bit has no effect.
Reserved
3-0
-
-
¾
This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
7. EEPROM Contents (93C46 or 93C56)
The 93C46 is a 1K-bit EEPROM (the 93C56 is a 2K-bit EEPROM). Although it is actually addressed by words, its contents are
listed below by bytes for convenience. After the valid duration of the RSTB pin or auto-load command in 9346CR, the
RTL8139C(L) performs a series of EEPROM read operations from the 93C46 (93C56) address 00H to 31H.
It is recommended to obtain Realtek approval before changing the default settings of the EEPROM.
Bytes
00h
01h
Contents
29h
Description
These 2 bytes contain the ID code word for the RTL8139C(L). The RTL8139C(L) will
load the contents of the EEPROM into the corresponding location if the ID word (8129h)
is correct, otherwise, the Vendor ID and Device ID of the PCI configuration space are
hex 10EC and 8129 respectively.
81h
02h-03h
04h-05h
06h-07h
08h-09h
0Ah
VID
DID
SVID
PCI Vendor ID, PCI configuration space offset 00h-01h.
PCI Device ID, PCI configuration space offset 02h-03h.
PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh.
PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh.
PCI Minimum Grant Timer, PCI configuration space offset 3Eh.
PCI Maximum Latency Timer, PCI configuration space offset 3Fh.
Bits 7-6 map to bits 7-6 of the Media Status register (MSR); Bits 5, 4, 0 map to bits 13,
12, 8 of the Basic Mode Control register (BMCR); Bits 3-2 are reserved. If the network
speed is set to Auto-Detect mode (i.e. Nway mode), then Bit 1=0 means the local
RTL8139C(L) supports flow control (IEEE 802.3x). In this case, Bit 10=1 in the
Auto-negotiation Advertisement Register (offset 66h-67h). Bit 1=1 means the local
RTL8139C(L) does not support flow control. In this case, Bit 10=0 in Auto-negotiation
Advertisement. This is because there are Nway switch hubs which keep sending flow
control pause packets for no reason, if the link partner supports Nway flow control.
RTL8139C(L) Configuration register 3, operational register offset 59H.
After auto-load command or hardware reset, the RTL8139C(L) loads the Ethernet ID to
IDR0-IDR5 of the RTL8139C(L)'s I/O registers.
SMID
MNGNT
MXLAT
MSRBMCR
0Bh
0Ch
0Dh
0Eh-13h
CONFIG3
Ethernet ID
14h
15h
16h-17h
CONFIG0
CONFIG1
PMC
RTL8139C(L) Configuration register 0, operational registers offset 51h.
RTL8139C(L) Configuration register 1, operational registers offset 52h.
Reserved. Do not change this field without Realtek approval.
Power Management Capabilities. PCI configuration space address 52h and 53h.
18h
19h
-
Reserved. Do not change this field without Realtek approval.
Reserved. Do not change this field without Realtek approval.
CONFIG4
RTL8139C(L) Configuration register 4, operational registers offset 5Ah.
1Ah-1Dh
1Eh
PHY1_PARM_U Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-U for RTL8139C. Operational registers of the RTL8139C(L) are from
78h to 7Bh.
PHY2_PARM_U Reserved. Do not change this field without Realtek approval.
PHY Parameter 2-U for RTL8139C. Operational register of the RTL8139C(L) is 80h.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Bytes
1Fh
Contents
CONFIG_5
Description
Do not change this field without Realtek approval.
Bit7-3: Reserved.
Bit2: Link Down Power Saving mode:
Set to 1: Disable.
Set to 0: Enable. When cable is disconnected(Link Down), the analog part will power
down itself (PHY Tx part & part of twister) automatically except PHY Rx part and
part of twister to monitor SD signal in case that cable is re-connected and Link should
be established again.
Bit1: LANWake signal Enable/Disable
Set to 1: Enable LANWake signal.
Set to 0: Disable LANWake signal.
Bit0: PME_Status bit property
Set to 1: The PME_Status bit can be reset by PCI reset or by software if
D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a
sticky bit.
Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.
20h-23h
24h-27h
28h-2Bh
2Ch
TW_PARM_U
TW_PARM_T
Reserved. Do not change this field without Realtek approval.
Twister Parameter U for RTL8139C. Operational registers of the RTL8139C(L) are
7Ch-7Fh.
Reserved. Do not change this field without Realtek approval.
Twister Parameter T for RTL8139C. Operational registers of the RTL8139C(L) are
7Ch-7Fh.
PHY1_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-T for RTL8139C. Operational registers of the RTL8139C(L) are from
78h to 7Bh.
PHY2_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 2-T for RTL8139C. Operational register of the RTL8139C(L) is 80h.
2Dh-2Fh
30h-31h
-
Reserved.
CISPointer
Reserved. Do not change this field without Realtek approval.
CIS Pointer.
32h-33h
CheckSum
Reserved. Do not change this field without Realtek approval.
Checksum of the EEPROM content.
34h-3Eh
3Fh
-
Reserved. Do not change this field without Realtek approval.
Reserved. Do not change this field without Realtek approval.
PXE ROM code parameter.
PXE_Para
40h-7Fh
80h-FFh
VPD_Data
CIS_Data
VPD data field. Offset 40h is the start address of the VPD data.
CIS data field. Offset 80h is the start address of the CIS data. (93C56 only).
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
7.1. Summary of EEPROM Registers
Offset
Name
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00h-05h IDR0 – IDR5 R/W*
51h
52h
58h
63H
59h
CONFIG0
CONFIG1
R
-
-
-
-
-
-
-
-
BS2
-
BS1
-
BS0
-
*
-
W
R
LEDS1
LEDS1
LEDS0 DVRLOAD LWACT MEMMAP IOMAP
LEDS0 DVRLOAD LWACT
VPD
VPD
PMEN
PMEN
*
-
-
W
R
TxFCE
TxFCE
RxFCE
RxFCE
-
-
-
-
-
-
-
-
*
W
R
MSRBMCR
CONFIG3
-
-
-
-
Spd_Set
Spd_Set
ANE
ANE
-
-
-
-
-
-
FUDUP
FUDUP
*
W
R
GNTDel PARM_EN
Magic
LinkUp CardB_En CLKRU FuncReg FBtBEn
N_En
En
*
-
PARM_EN
AnaOff
Magic
LinkUp
-
-
-
-
-
-
W
5Ah
CONFIG4
* RxFIFO
AutoClr
LongWF LWPME
LWPTN
-
R/W
78h-7Bh PHY1_PARM R/W**
7Ch-7Fh TW1_PARM R/W**
TW2_PARM
32 bit Read Write
32 bit Read Write
32 bit Read Write
8 bit Read Write
80h
PHY2_PARM R/W**
*
*
The registers marked with type = W can be written only if bits EEM1=EEM0=1.
**
** The registers marked with type = W can be written only if bits EEM1=EEM0=1 and CONFIG3<PARM_EN> = 0.
7.2. Summary of EEPROM Power Management Registers
Configuration Name Type
Space offset
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
52h
53h
PMC
R
R
Aux_I_b1 Aux_I_b0
PME_D3cold PME_D3ho PME_D2 PME_D1 PME_D0
DSI
Reserved PMECLK
Version
D1
D2
Aux_I_b2
t
55h
PMCS
R
R
W
PME_Status
PME_Status
-
-
-
-
-
-
-
-
-
-
-
-
PME_En
PME_En
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
8. PCI Configuration Space Registers
8.1. PCI Configuration Space Table
No.
00h
01h
02h
03h
Name
Type
R
Bit7
Bit6
Bit5
Bit4
Bit3
VID3
VID11
DID3
Bit2
VID2
VID10
DID2
DID10
Bit1
VID1
VID9
DID1
DID9
Bit0
VID0
VID8
DID0
DID8
IOEN
IOEN
VID
VID7
VID15
DID7
DID15
VID6
VID14
DID6
DID14
VID5
VID13
DID5
DID13
VID4
VID12
DID4
DID12
R
R
R
DID
DID11
04h Command
R
W
R
W
R
R
0
-
0
-
PERRSP
PERRSP
0
-
0
-
0
-
-
0
-
BMEN MEMEN
BMEN MEMEN
-
05h
0
-
0
0
0
-
0
FBTBEN SERREN
-
-
0
SERREN
06h
07h
Status
FBBC
DPERR
DPERR
0
NewCap
0
0
SSERR
SSERR
RMABT RTABT
RMABT RTABT
STABT
STABT
DST1
-
0
DST0
-
0
DPD
DPD
0
W
R
08h Revision ID
0
0
0
0
0
09h
0Ah
0Bh
0Ch
0Dh
PIFR
SCR
BCR
CLS
LTR
R
R
R
R
R
W
R
R
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
LTR0
LTR0
0
LTR7
LTR7
0
0
0
-
IOAR15
IOAR23
IOAR31
0
LTR6
LTR6
0
0
0
-
IOAR14
IOAR22
IOAR30
0
LTR5
LTR5
0
0
0
-
LTR4
LTR4
0
0
0
-
LTR3
LTR3
0
0
0
-
LTP2
LTP2
0
0
0
-
LTR1
LTR1
0
0
0
-
0Eh
0Fh
10h
HTR
BIST
IOAR
0
IOIN
-
IOAR8
11h
12h
13h
IOAR13 IOAR12 IOAR11 IOAR10
IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16
IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24
IOAR9
14h MEMAR
0
-
0
-
0
-
0
-
0
-
MEMIN
-
MEM8
-
-
15h
16h
17h
18h-2
7h
MEM15
MEM23
MEM31
MEM14
MEM22
MEM30
MEM13 MEM12 MEM11 MEM10
MEM9
MEM21 MEM20 MEM19 MEM18 MEM17 MEM16
MEM29 MEM28 MEM27 MEM26 MEM25 MEM24
RESERVED
28h-2
Bh
CISPtr
SVID
Cardbus CIS Pointer
2Ch
2Dh
2Eh
2Fh
30h
R
R
R
R
R
W
R
W
SVID7
SVID15
SMID7
SMID15
0
SVID6
SVID14
SMID6
SMID14
0
SVID5
SVID13 SVID12 SVID11 SVID10
SMID5 SMID4 SMID3 SMID2
SMID13 SMID12 SMID11 SMID10
SVID4
SVID3
SVID2
SVID1
SVID9
SMID1
SMID9
SVID0
SVID8
SMID0
SMID8
BROMEN
BROMEN
0
SMID
BMAR
0
-
0
-
0
-
0
-
0
-
0
-
0
-
-
-
31h
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
-
32h
33h
34h
R/W BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16
R/W BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24
Cap_Ptr
R
0
1
0
1
0
0
0
0
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
No.
35h-3
Bh
Name
Type
Bit7
Bit6
Bit5
RESERVED
Bit4
Bit3
Bit2
Bit1
Bit0
3Ch
3Dh
3Eh MNGNT
ILR
IPR
R/W
R
R
IRL7
ILR6
ILR5
ILR4
ILR3
ILR2
ILR1
ILR0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
3Fh
40h–
4Fh
50h
51h
52h
53h
54h
MXLAT
R
RESERVED
PMID
NextPtr
PMC
R
R
R
R
R
W
R
W
0
0
0
0
0
0
DSI
0
0
0
0
0
0
0
0
1
0
Aux_I_b1 Aux_I_b0
PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0
Reserved PMECLK
Version
D1
D2
0
-
-
-
Aux_I_b2
PMCSR
0
-
0
-
-
0
-
-
0
-
-
0
-
-
Power State
Power State
-
55h
PME_Status
PME_Status
PME_En
PME_En
-
-
-
-
-
56h–
5Fh
60h
61h
RESERVED
VPDID
NextPtr
R
R
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
62h Flag VPD R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD
Address
7
6
R5
R4
R3
R2
R1
R0
63h
R/W
Flag
VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD
14
R13
R12
R11
R10
R9
R8
64h VPD Data R/W
Data7
Data15
Data23
Data31
Data6
Data14
Data22
Data30
Data5
Data4
Data3
Data2
Data1
Data9
Data17
Data25
Data0
Data8
Data16
Data24
65h
66h
R/W
R/W
R/W
Data13
Data21
Data29
Data12
Data20
Data28
Data11
Data19
Data27
Data10
Data18
Data26
67h
68h-F
Fh
RESERVED
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
8.2. PCI Configuration Space Functions
The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The
functions of RTL8139C(L)'s configuration space are described below.
VID:
Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.
DID:
Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 8129h.
Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and
respond to PCI cycles.
Bit
15-10
9
Symbol
-
FBTBEN
Description
Reserved
Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The
RTL8139C(L) will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This
read/write bit controls whether or not a master can do fast back-to-back transactions to different
devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1
means the master is allowed to generate fast back-to-back transaction to different agents. A value of 0
means fast back-to-back transactions are only allowed to the same agent. This bit’s state after RST# is
0.
8
7
6
SERREN
ADSTEP
PERRSP
System Error Enable: When set to 1, the RTL8139C(L) asserts the SERRB pin when it detects a
parity error on the address phase (AD<31:0> and CBEB<3:0> ).
Address/Data Stepping: Read as 0, write operation has no effect. The RTL8139C(L) never performs
address/data stepping.
Parity Error Response: When set to 1, RTL8139C(L) will assert the PERRB pin on the detection of
a data parity error when acting as the target, and will sample the PERRB pin as the master. When set to
0, any detected parity error is ignored and the RTL8139C(L) continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
5
VGASNOO
P
VGA palette SNOOP: Read as 0, write operation has no effect.
4
3
MWIEN
SCYCEN
Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect.
Special Cycle Enable: Read as 0, write operation has no effect. The RTL8139C(L) ignores all special
cycle operation.
2
BMEN
Bus Master Enable: When set to 1, the RTL8139C(L) is capable of acting as a bus master. When set
to 0, it is prohibited from acting as a PCI bus master.
For the normal operation, this bit must be set by the system BIOS.
1
0
MEMEN
IOEN
Memory Space Access: When set to 1, the RTL8139C(L) responds to memory space accesses. When
set to 0, the RTL8139C(L) ignores memory space accesses.
I/O Space Access: When set to 1, the RTL8139C(L) responds to IO space access. When set to 0, the
RTL8139C(L) ignores I/O space accesses.
Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register
behave normally. Writes are slightly different in that bits can be reset, but not set.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
Bit
Symbol
Description
15
DPERR
Detected Parity Error: When set indicates that the RTL8139C(L) detected a parity error, even if parity
error handling is disabled in command register PERRSP bit.
Signaled System Error: When set indicates that the RTL8139C(L) asserted the system error pin,
SERRB. Writing a 1 clears this bit to 0.
Received Master Abort: When set indicates that the RTL8139C(L) terminated a master transaction
with master abort. Writing a 1 clears this bit to 0.
Received Target Abort: When set indicates that the RTL8139C(L) master transaction was terminated
due to a target abort. Writing a 1 clears this bit to 0.
Signaled Target Abort: Set to 1 whenever the RTL8139C(L) terminates a transaction with target abort.
Writing a 1 clears this bit to 0.
14
13
SSERR
RMABT
RTABT
STABT
DST1-0
DPD
12
11
10-9
8
Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),
indicating the RTL8139C(L) will assert DEVSELB two clocks after FRAMEB is asserted.
Data Parity error Detected:
This bit sets when the following conditions are met:
• The RTL8139C(L) asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by
another device.
• The RTL8139C(L) operates as a bus master for the operation that caused the error.
• The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
7
6
FBBC
UDF
Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
User Definable Features Supported: Read as 0, write operation has no effect. The RTL8139C(L) does
not support UDF.
5
66MHz
NewCap
-
66 MHz Capable: Read as 0, write operation has no effect. The RTL8139C(L) has no 66MHz
capability.
New Capability: Config3<PMEn>=0, Read as 0, write operation has no effect. Config3<PMEn>=1, Read
as 1.
4
0-3
Reserved
RID: Revision ID Register
The Revision ID register is an 8-bit register that specifies the RTL8139C(L) controller revision number.
PIFR: Programming Interface Register
The programming interface register is an 8-bit register that identifies the programming interface of the RTL8139C(L)
controller. Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h.
SCR: Sub-Class Register
The Sub-class register is an 8-bit register that identifies the function of the RTL8139C(L). SCR = 00h indicates that the
RTL8139C(L) is an Ethernet controller.
BCR: Base-Class Register
The Base-class register is an 8-bit register that broadly classifies the function of the RTL8139C(L). BCR = 02h indicates
that the RTL8139C(L) is a network controller.
CLS: Cache Line Size
Reads will return a 0, writes are ignored.
LTR: Latency Timer Register
Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8139C(L).
When the RTL8139C(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8139C(L) deasserts FRAMEB
prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8139C(L)
initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is
00H.
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
HTR: Header Type Register
Reads will return a 0, writes are ignored.
BIST: Built-in Self Test
Reads will return a 0, writes are ignored.
IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also
specifies the number of bytes required as well as an indication that it can be mapped into IO space.
Bit
Symbol
Description
31-8 IOAR31-8
BASE IO Address: This is set by software to the Base IO address for the operational register map.
7-2
IOSIZE
Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8139C(L)
requires 256 bytes of IO space.
1
0
-
Reserved
IOIN
IO Space Indicator: Read only. Set to 1 by the RTL8139C(L) to indicate that it is capable of being
mapped into IO space.
MEMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L) operational registers. This
register must be initialized prior to accessing any of the RTL8139C(L)'s register with memory access.
Bit
31-8
7-4
Symbol
MEM31-8
MEMSIZE
Description
Base Memory Address: This is set by software to the base address for the operational register map.
Memory Size: These bits return 0, which indicates that the RTL8139C(L) requires 256 bytes of
Memory Space.
3
MEMPF
Memory Prefetchable: Read only. Set to 0 by the RTL8139C(L).
2-1
MEMLOC
Memory Location Select: Read only. Set to 0 by the RTL8139C(L). This indicates that the base
register is 32-bit wide and can be placed anywhere in the 32-bit memory space.
Memory Space Indicator: Read only. Set to 0 by the RTL8139C(L) to indicate that it is capable of
being mapped into memory space.
0
MEMIN
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
CISPtr: CardBus CIS Pointer. This field is valid only when CardB_En (bit3, Config3) = 1. The value of this register is
auto-loaded from 93C46 or 93C56 (from offset 30h-31h).
-
Bit 2-0: Address Space Indicator
Bit2-0
0
1-6
Meaning
Not supported. (CIS begins in device-dependent configuration space.)
The CIS begins in the memory address governed by one of the six Base
Address Registers. Ex., if the value is 2, then the CIS begins in the memory
address space governed by Base Address Register 2.
The CIS begins in the Expansion ROM space.
7
-
-
Bit27-3: Address Space Offset
Bit31-28: ROM Image number
Bit2-0
Space Type
Address Space Offset Values
0
Configuration space
Memory space
Not supported.
X; 1≤X≤6
0h≤value≤FFFF FFF8h. This is the offset into the memory address space
governed by Base Address Register X. Adding this value to the value in the
Base Address Register gives the location of the start of the CIS. For
RTL8139C(L), the value is 100h.
7
Expansion ROM
0≤image number≤Fh, 0h≤value≤0FFF FFF8h. This is the offset into the
expansion ROM address space governed by the Expansion ROM Base
Register. The image number is in the uppermost nibble of the CISPtr
register. The value consists of the remaining bytes. For RTL8139C(L), the
image number is 0h.
This read-only register points to where the CIS begins, in one of the following spaces:
i.
Memory space --- The CIS may be in any of the memory spaces from offset 100h and up after being
auto-loaded from 93C56. The CIS is stored in 93C56 EEPROM physically from offset 80h-FFh.
Expansion ROM space --- The CIS is stored in expansion ROM physically within the 128KB max.
ii.
SVID: Subsystem Vendor ID. This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external
EEPROM. If there is no EEPROM, this field will default to a value of 11ECh which is Realtek Semiconductor's PCI
Subsystem Vendor ID.
SMID: Subsystem ID. This field will be set to a value corresponding to the PCI Subsystem ID in the external EEPROM. If there
is no EEPROM, this field will default to a value of 8129h.
BMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L) operational registers. This
register must be initialized prior to accessing any of the RTL8139C(L)'s registers with memory access.
Bit
Symbol
Description
31-18 BMAR31-18 Boot ROM Base Address
17-11
ROMSIZE
These bits indicate how many Boot ROM spaces to be supported.
The Relationship between Config 0 <BS2:0> and BMAR17-11 is the following:
BS2 BS1 BS0 Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Boot ROM, BROMEN=0 (R)
8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W)
16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W)
32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W)
64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W)
128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W)
unused
unused
10-1
0
-
Reserved (read back 0)
Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM.
BROMEN
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
ILR: Interrupt Line Register
The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the
POST software to set interrupt line for the RTL8139C(L).
IPR: Interrupt Pin Register
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8139C(L). The
RTL8139C(L) uses INTA interrupt pin. Read only. IPR = 01H.
MNGNT: Minimum Grant Timer: Read only
Specifies how long a burst period the RTL8139C(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This
field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
MXLAT: Maximum Latency Timer: Read only
Specifies how often the RTL8139C(L) needs to gain access to the PCI bus in units of 1/4 microseconds. This field
will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
8.3. Default Values After Power-on (RSTB asserted)
8.3.1. PCI Configuration Space Table
No.
00h
01h
02h
03h
04h
Name
Type
R
Bit7
Bit6
Bit5
Bit4
0
1
0
0
0
-
0
Bit3
1
0
1
0
0
-
0
Bit2
Bit1
Bit0
VID
1
0
0
1
0
-
0
-
1
0
0
0
1
0
1
0
0
-
0
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
R
R
R
R
W
R
W
R
DID
Command
0
PERRSP
BMEN MEMEN IOEN
05h
0
-
0
0
0
-
0
0
0
-
0
1
0
-
NewCap
0
-
0
0
SERREN
06h
07h
Status
0
0
0
R
0
W
R
R
R
R
DPERR
SSERR RMABT RTABT
STABT
-
0
0
0
0
0
0
-
0
0
0
1
0
0
DPD
0
0
0
0
0
0
08h
09h
0Ah
0Bh
0Ch
0Dh
Revision ID
PIFR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCR
BCR
CLS
LTR
0
0
0
0
0
0
R
R
0
0
0
0
0
0
W
R
R
LTR7
LTR6
LTR5
LTR4
LTR3
LTP2
LTR1
LTR0
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
HTR
BIST
IOAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R
R/W
R/W
R/W
MEMAR
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
No.
18h
|
Name
Type
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESERVED(ALL 0)
-
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
R
R
R
R
R
R
R
R
R
W
R
W
R/W
R/W
R
0
0
0
0
1
0
0
1
0
-
0
0
0
0
1
0
0
0
0
-
0
0
0
0
1
0
1
0
0
-
0
0
0
0
0
1
0
0
0
-
0
0
0
0
1
0
1
0
0
-
0
0
0
0
1
0
0
0
0
-
0
-
0
0
Ptr2
0
0
0
0
0
0
0
0
0
-
0
-
0
0
Ptr1
0
0
0
0
0
1
1
1
CISPtr
SVID
SMID
BMAR
0
BROMEN
31h
0
0
0
0
0
0
-
0
0
Ptr0
BMAR15 BMAR14 BMAR13 BMAR12 BMAR11
32h
33h
34h
35h
|
0
0
Ptr7
0
0
Ptr6
0
0
Ptr5
0
0
Ptr4
0
0
Ptr3
Cap-Ptr
-
RESERVED(ALL 0)
3Bh
3Ch
3Dh
3Eh
3Fh
40h
|
ILR
IPR
MNGNT
MXLAT
R/W
R
R
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R
RESERVED(ALL 0)
-
FFh
3.3V Single-Chip Fast Ethernet Controller w/Power Management
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Track ID: JATR-1076-21 Rev. 1.6
RTL8139C(L)
Datasheet
8.4. PCI Power Management Functions
The RTL8139C(L) is compliant to ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class
Power Management Reference Specification (V1.0, 1.0a, 2.0), such as to support OS Directed Power Management (OSPM)
environment. To support this, the RTL8139C(L) provides the following capabilities:
¾
The RTL8139C(L) can monitor the network for a Wakeup Frame, a Magic Packet, or a Link Change, and notify the
system via PME# when such a packet or event arrives. Then, the whole system can be restored to a working state to
process the incoming jobs.
¾
The RTL8139C(L) can be isolated from the PCI bus automatically with the auxiliary power circuit when the PCI bus is
in B3 state, i.e. when the power on the PCI bus is removed. When the motherboard includes a built-in RTL8139C(L)
single-chip fast Ethernet controller, the RTL8139C(L) can be disabled when needed by pulling the isolate pin low to 0V.
When the RTL8139C(L) is in power down mode (D1 ~ D3):
♦
The Rx state machine is stopped, and the RTL8139C(L) keeps monitoring the network for wakeup events such as Magic
Packet, Wakeup Frame, and/or Link Change, in order to wake up the system. When in power down mode, the
RTL8139C(L) will not reflect the status of any incoming packets in the ISR register and will not receive any packets into
the Rx FIFO.
♦
The FIFO status and the packets which are already contained in the Rx FIFO before entering power down mode are kept
by the RTL8139C(L) during power down mode.
♦
♦
The transmission is stopped. The action of PCI bus master mode is stopped, as well. The Tx FIFO is kept.
After restoration to a D0 state, the PCI bus master mode continues to transfer the data, which is not yet moved into the Tx
FIFO from the last break. The packet that was not transmitted completely last time is transmitted again.
D3cold_support_PME bit(bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space.
If 9346 D3cold_support_PME bit(bit15, PMC) = 1, the above 4 bits depend on the existence of Aux. power.
If 9346 D3cold_support_PME bit(bit15, PMC) = 0, the above 4 bits are all 0's.
Examples:
1. If 9346 D3c_support_PME = 1,
¾
If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC, i.e. if 9346 PMC = C2 F7,
then PCI PMC = C2 F7.
¾
If Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits
are all 0’s. I.e. if 9346 PMC = C2 F7, the PCI PMC = 02 76.
In this case, if wakeup support is desired when the main power is off, it is suggested that the 9346
PMC be set to: C2 F7 (RT 9346 default value). It is not recommended to set the D0_support_PME
bit to “1”.
2. If 9346 D3c_support_PME = 0,
¾
If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC. I.e. if 9346 PMC = C2 77,
then PCI PMC = C2 77.
¾
If Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits
are all 0’s. I.e. if 9346 PMC = C2 77, the PCI PMC = 02 76.
In this case, if wakeup support is not desired when the main power is off, it is suggested that the
9346 PMC to be 02 76. It is not recommended to set the D0_support_PME bit to “1”.
A Link Wakeup occurs only when the following conditions are met:
♦
The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8139C(L) is in an
isolation state, or the PME# can be asserted in current power state.
♦
The Link status is re-established.
A Magic Packet Wakeup occurs only when the following conditions are met:
The destination address of the received Magic Packet matches.
♦
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RTL8139C(L)
Datasheet
♦
♦
The received Magic Packet does not contain a CRC error.
The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8139C(L) is in isolation
state, or the PME# can be asserted in current power state.
♦
The Magic Packet pattern matches, i.e. 6 * FFh + MISC(can be none)+ 16 * DID(Destination ID) in any part of a valid
(Fast) Ethernet packet.
A Wakeup Frame event occurs only when the following conditions are met:
♦
♦
♦
The destination address of the received Wakeup Frame matches.
The received Wakeup Frame does not contain a CRC error.
The PMEn bit (CONFIG1#0) is set to 1.
The 8-bit CRC* (or 16-bit CRC) of the received Wakeup Frame matches with the 8-bit CRC* (or 16-bit CRC) of the
sample Wakeup Frame pattern received from the local machine’s OS.
The last masked byte** of the received Wakeup Frame matches with the last masked byte of the sample Wakeup Frame
pattern provided by the local machine’s OS. (In Long Wakeup Frame mode, the last masked byte field is replaced with
the high byte of the 16-bit CRC.)
* 8-bit CRC:
This 8-bit CRC logic is used to generate an 8-bit CRC from the masked bytes of the received Wakeup Frame packet within offset
12 to 75. Software should calculate the 8-bit Power Management CRC for each specific sample wakeup frame and store the
calculated CRC in the corresponding CRC register for the RTL8139C(L) to check if there is a Wakeup Frame packet coming in.
* 16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127):
Long Wakeup Frame: The RTL8139C(L) also supports 3 long Wakeup Frames. If the range of the mask bytes of the sample
Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75, the related registers of wakeup
frames 2 and 3 can be merged to support one long wakeup frame by setting the LongWF (bit0, CONFIG4). Thus, the range
of effective mask bytes extends from offset 0 to 127. The low byte and high byte of the calculated 16-bit CRC should be put
into register CRC2 and LSBCRC2 respectively. The mask bytes (16 bytes) should be stored to register Wakeup2 and
Wakeup3. The CRC3 and LSBCRC3 have no meaning in this case and should be reset to 0. The long Wakeup Frame pairs
are wakeup frames 4 and 5, wakeup frames 6 and 7. The CRC5, CRC7, LSBCRC5, and LSBCRC7 have no meaning in this
case and should be reset to 0, if the RTL8139C(L) is set to support long Wakeup Frames. In this case, the RTL8139C(L)
supports 5 wakeup frames, that are 2 normal wakeup frames and 3 long wakeup frames.
** last masked byte:
The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC mode) should
match the last byte of the masked bytes of the sample Wakeup Frame provided by the local machine’s OS.
The PME# signal is asserted only when the following conditions are met:
The PMEn bit (bit0, CONFIG1) is set to 1.
The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
The RTL8139C(L) may assert PME# in current power state, or the RTL8139C(L) is in isolation state. Refer to
PME_Support(bit15-11) of the PMC register in PCI Configuration Space.
Magic Packet, LinkUp, or Wakeup Frame has occurred.
Note: Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space will clear this bit
and cause the RTL8139C(L) to stop asserting a PME# (if enabled).
When the RTL8139C(L) is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM space are all disabled. After RST#
is asserted, the power state must be changed to D0 if the original power state is D3cold. There is no hardware enforced delays at
RTL8139C(L)’s power state. When in ACPI mode, the RTL8139C(L) does not support PME from D0, due to the setting of the
PMC register. This setting comes from EEPROM.
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The RTL8139C(L) also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute
the wake-up process whenever the RTL8139C(L) receives a wakeup event, such as Magic Packet.
The LWAKE signal is asserted according the following setting.
LWPME bit (bit4, CONFIG4):
0: The LWAKE is asserted whenever there is wakeup event occurs.
1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.
Bit1 of DELAY byte(offset 1Fh, EEPROM):
0: LWAKE signal is disabled.
1: LWAKE signal is enabled
8.5. Vital Product Data (VPD)
Bit 31 of the VPD is used to issue the VPD read/write command and is also a flag used to indicate if the transfer of data between
the VPD data register and the 93C46/93C56 has been completed or not.
1.
Write VPD register: (write data to 93C46/93C56)Write the flag bit to a one at the same time the VPD address is written.
When the flag bit is set to zero by the RTL8139C(L), the VPD data (all 4 bytes) has been transferred from the VPD data
register to 93C46/93C56.
2.
Read VPD register: (read data from 93C46/93C56) Write the flag bit to a zero at the same time the VPD address is written.
When the flag bit is set to one by the RTL8139C(L), the VPD data (all 4 bytes) has been transferred from the 93C46/93C56
to the VPD data register.
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9. Functional Description
9.1. Transmit Operation
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the
entire packet has been transferred to the Tx buffer, the RTL8139C(L) is instructed to move the data from the Tx buffer to the
internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the
programmed threshold level, the RTL8139C(L) begins packet transmission.
9.2. Receive Operation
The incoming packet is placed in the RTL8139C(L)'s Rx FIFO. Concurrently, the RTL8139C(L) performs address filtering of
multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the
Receive Configuration Register, the RTL8139C(L) requests the PCI bus to begin transferring the data to the Rx buffer in PCI bus
master mode.
9.3. Line Quality Monitor
The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount of Equalization being used
by accessing certain test registers with the DSP engine. This provides a crude indication of connected cable length. This function
allows for a quick and simple verification of the line quality in that any significant deviation from an expected register value (based on
a known cable length) would indicate that the signal quality has deviated from the expected nominal case.
9.4. Clock Recovery Module
The Clock Recovery Module (CRM) is supported in both 10Base-T and 100Base-TX mode. The CRM accepts 125Mb/s MLT3 data
from the equalizer. The DPLL locks onto the 125Mb/s data stream and extracts a 125MHz recovered clock. The extracted and
synchronized clock and data are used as required by the synchronous receive operations.
9.5. Loopback Operation
Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function correctly. In loopback mode for
100Mbps, the RTL8139C(L) takes frames from the transmit descriptor and transmits them up to internal Twister logic.
9.6. Tx Encapsulation
While operating in 100Base-TX mode, the RTL8139C(L) encapsulates the frames that it transmits according to the 4B/5B
code-groups table. The changes of the original packet data are listed as follows:
1. The first byte of the preamble in the MAC frame is replaced with the JK symbol pair.
2. After the CRC, the TR symbol pair is inserted.
9.7. Collision
If the RTL8139C(L) is not in full-duplex mode, a collision event occurs when the receive input is not idle while the
RTL8139C(L) transmits. If the collision was detected during the preamble transmission, the jam pattern is transmitted after
completing the preamble (including the JK symbol pair).
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9.8. Rx Decapsulation
The RTL8139C(L) continuously monitors the network when reception is enabled. When activity is recognized it starts to process
the incoming data.
After detecting receive activity on the line, the RTL8139C(L) starts to process the preamble bytes based on the mode of
operation.
While operating in 100Base-TX mode, the RTL8139C(L) expects the frame to start with the symbol pair JK in the first bye of the
8-byte preamble.
The RTL8139C(L) checks the CRC bytes and checks if the packet data ends with the TR symbol pair, if not, the RTL8139C(L)
reports a CRC error RSR.
The RTL8139C(L) reports a RSR<CRC> error in the following case:
In 100Base-TX mode, one of the following occur.
a. An invalid symbol (4B/5B Table) is received in the middle of the frame.
The RSR<ISE> bit also sets.
b. The frame does not end with the TR symbol pair.
9.9. Flow Control
The RTL8139C(L) supports IEEE802.3X flow control to improve performance in full-duplex mode. It detects PAUSE packets
to achieve flow control tasks.
9.9.1. Control Frame Transmission
When the RTL8139C(L) detects that its free receive buffer is less than 3K bytes, it sends a PAUSE packet with
pause_time(=FFFFh) to inform the source station to stop transmission for the specified period of time. After the driver has
processed the packets in the receive buffer and updated the boundary pointer, the RTL8139C(L) sends the other PAUSE packet
with pause_time(=0000h) to wake up the source station to restart transmission.
9.9.2. Control Frame Reception
The RTL8139C(L) enters a back off state for a specified period of time when it receives a valid PAUSE packet with
pause_time(=n). If the PAUSE packet is received while the RTL8139C(L) is transmitting, the RTL8139C(L) starts to back off
after current transmission completes. The RTL8139C(L) is free to transmit the next packets when it receives a valid PAUSE
packet with pause_time(=0000h) or the backoff timer(=n*512 bit time) elapses.
Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. a PAUSE packet). The N-way
flow control capability can be disabled. Please refer to Section 7, “EEPROM (93C46 or 93C56) Contents” for a detailed
description.
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Datasheet
9.10. LED Functions
9.10.1. 10/100Mbps Link Monitor
The Link Monitor senses the link integrity or if a station is down.
9.10.2. LED_RX
In 10/100 Mbps mode, the LED function is as follows:
Power On
LED = Low
No
Receiving Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
9.10.3. LED_TX
Power On
LED = Low
No
Transmitting Packet
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
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Datasheet
9.10.4. LED_TX+LED_RX
Power On
LED = Low
No
Tx or Rx Packet?
Yes
LED = High for (100 +- 10) ms
LED = Low for (12 +- 2) ms
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Datasheet
10. Application Diagram
EEPROM
LED
CLK
DATA
BOOT
ROM
RTL8139C(L)
RJ45
Magetics
Address
Auxiliary Power
PCI INTERFACE
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Datasheet
11. Electrical Characteristics
11.1. Temperature Limit Ratings
Parameter
Storage temperature
Minimum
Maximum
+125
Units
°C
°C
-55
0
Operating temperature
70
11.2. DC Characteristics
11.2.1. Supply Voltage
Vcc = 3.0V min. to 3.6V max.
Symbol
Parameter
Conditions
Minimum
Maximum
Units
V
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Input Current
I
0.9 * Vcc
Vcc
V
OH
OH= -8mA
V
I
0.1 * Vcc
Vcc+0.5
0.3 * Vcc
1.0
V
V
OL
OL= 8mA
V
0.5 * Vcc
-0.5
IH
V
V
IL
I
V
V
-1.0
uA
IN
IN= CC or
GND
I
Tri-State Output Leakage Current
Average Operating Supply Current
V
V
-10
10
uA
OZ
OUT= CC or
GND
I
I
0mA,
150
mA
CC
OUT=
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Datasheet
11.3. AC Characteristics
11.3.1. FLASH/BOOT ROM Timing
FLASH/BOOT ROM - Read
MA17-0
TRC
ROMCSB
OEB
TWRBR
TOES
TCE
TOOLZ
WEB
TOHZ
TOH
TCOLZ
MD7-0
TACC
Symbol
TRC
TCE
TACC
TOES
TCOLZ
TOOLZ
TOHZ
TOH
Description
Minimum
Typical
Maximum
Units
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle
135
-
-
-
-
-
-
-
-
-
-
-
200
200
60
-
-
40
0
Chip Enable Access Time
Address Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address, ROMCSB, or
OEB
-
0
0
-
0
TWRBR
Write Recovery time Before Read
6
-
-
us
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Datasheet
FLASH MEMORY - Write
SETUPMPROGRAM
COMMAND
PROGRAM COMMAND
LATCH ADDRESS
STANDBY/VCC
POWER-DOWN
PROGRAM
VERIFICATION
VERIFY
COMMAND
VCC POWER-UP
& STANDBY
PROGRAMMING
& DATA
MA17-0
ROMCSB
OEB
tWC
tWC
tAS
tRC
tAH
tCH
tAH
tCS
tCH
tCS
tWHWH1
tWHGL
tWPH
tGHWL
tDF
tWP
tDS
tWP
tWP
tDS
tOH
tOE
WEB
tDS
tDH
tDH
tOOLZ
VALID
DATA
IN
DATAOUT
=40H
DATAOUT
=C0H
DATAO
MD7-0
tCOLZ
tCE
Symbol
TWC
TAS
TAH
TDS
Description
Minimum
Typical
Maximum
Units
ns
ns
ns
ns
ns
us
us
ns
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Recovery Time before Read
Read Recovery Time before Write
Chip Enable Set-up Time before
Write
135
0
60
50
10
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TDH
TWHGL
TGHWL
TCS
0
20
TCH
TWP
TWPH
Chip Enable Hold Time
Write Pulse Width
Write Pulse Width High
0
-
-
-
-
-
-
-
us
ns
ns
us
50
20
10
TWHWH1
Duration of Programming Operation
25
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Datasheet
11.3.2. PCI Bus Operation Timing
Target Read
Target Write
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Datasheet
Configuration Read
Configuration Write
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BUS Arbitration
Memory Read
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Memory Write
Target Initiated Termination - Retry
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Datasheet
Target Initiated Termination - Disconnect
Target Initiated Termination - Abort
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Master Initiated Termination - Abort
Parity Operation - One Example
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Datasheet
12. Mechanical Dimensions (128-Pin QFP)
Note:
Symbol Dimension in inch Dimension in mm
1. Dimension D & E do not include interlead flash.
Typical
Typical
Min
Max Min
Max
2. Dimension b does not include dambar
protrusion/intrusion.
-
0.134
-
-
3.40
0.91
3.10
0.32
0.25
3. Controlling dimension: Millimeter
4. General appearance spec. should be based on final visual
inspection spec.
A
A1
A2
B
C
D
0.004 0.010 0.036 0.10
0.102 0.112 0.122 2.60
0.005 0.009 0.013 0.12
0.002 0.006 0.010 0.05
0.541 0.551 0.561 13.75
0.778 0.787 0.797 19.75
0.020 BSC
0.25
2.85
0.22
0.15
14.00
20.00
14.25
20.25
TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE
-CU L/F, FOOTPRINT 3.2 mm
E
LEADFRAME MATERIAL:
0.50 BSC
0.665 0.677 0.689 16.90
0.902 0.913 0.925 22.90
0.027 0.035 0.043 0.68
0.053 0.063 0.073 1.35
17.50
APPROVE
CHECK
DOC. NO. 530-ASS-P004
HD
HE
L
L1
y
17.20
23.20
0.88
1.60
-
23.50
1.08
1.85
0.10
12°
VERSION
PAGE
1
OF
DWG NO.
DATE
Q128 - 1
Nov. 4 1999
-
-
0.004
-
-
-
REALTEK SEMICONDUCTOR CO., LTD
θ
0°
12°
0°
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Datasheet
13. Mechanical Dimensions (128-Pin LQFP)
Note:
Symbol Dimension in inch
Dimension in mm
1.Dimension b does not include dambar protrusion/intrusion.
2.Controlling dimension: Millimeter
Min Typical Max Min Typical Max
-
-
0.067
-
-
-
1.70
0.25
1.50
0.29
0.20
3.General appearance spec. should be based on final visual
A
A1
A2
b
c
D
0.000 0.004 0.008 0.00
0.051 0.055 0.059 1.30
0.006 0.009 0.011 0.15
1.40
0.22
-
0.004
-
0.006 0.09
TITLE: 128LD
APPROVE
CHECK
LQFP
( 14x20x1.4 mm*2 ) PACKAGE
-CU L/F, FOOTPRINT 2.0 mm
LEADFRAME MATERIAL:
0.541 0.551 0.561 13.75
0.778 0.787 0.797 19.75
0.020 BSC
0.620 0.630 0.640 15.90
0.855 0.866 0.877 21.70
0.016 0.024 0.031 0.45
0.039 REF
14.25
20.25
14.00
20.00
0.50 BSC
16.00
22.00
0.60
1.00
3.5°
E
DOC. NO.
VERSION
PAGE
530-ASS-P004
16.30
23.30
0.75
REF
9°
1
OF
HD
HE
L
L1
θ
DWG NO.
DATE
LQ128 - 1
Nov. 4.1999
REALTEK SEMICONDUCTOR CORP.
0°
3.5°
9°
0°
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RTL8139C(L)
Datasheet
14. Ordering Information
Table 1. Ordering Information
Part Number
RTL8139C
Package
128-pin QFP
Status
RTL8139C-LF
RTL8139CL
128-pin QFP Lead (Pb)-Free
128-pin LQFP
RTL8139CL-LF
128-pin LQFP Lead (Pb)-Free
Note: See page 4 for Lead (Pb)-Free package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
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