89HPES5T5ZBBCG [RENESAS]

5-Lane 5-Port PCI ExpressÂ® Switch;


型号：	89HPES5T5ZBBCG
厂家：	RENESAS TECHNOLOGY CORP
描述：	5-Lane 5-Port PCI ExpressÂ® Switch 时钟 PC 外围集成电路
文件：	总29页 (文件大小：385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

89PES5T5

Data Sheet

5-Lane 5-Port PCI Express®

Switch

Highly Integrated Solution

– Requires no external components

Device Overview

The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI

Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral

chip that performs PCI Express Base switching. It provides connectivity

and switching functions between a PCI Express upstream port and up to

four downstream ports and supports switching between downstream

ports.

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates five 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC and Advanced Error Reporting

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC mother-

boards

Features

High Performance PCI Express Switch

– Five 2.5Gbps PCI Express lanes

– Five switch ports

– Upstream port is x1

– Downstream ports are x1

Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Low-latency cut-through switch architecture

– Support for Max Payload Sizes up to 256 bytes

– One virtual channel

– Supports PCI Power Management Interface specification (PCI-

– Eight traffic classes

PM 1.2)

– PCI Express Base Specification Revision 1.1 compliant

Flexible Architecture with Numerous Configuration Options

– Unused SerDes are disabled.

– Supports Advanced Configuration and Power Interface Speci-

fication, Revision 2.0 (ACPI) supporting active link state

– Automatic lane reversal on all ports

– Automatic polarity inversion

Testability and Debug Features

– Ability to load device configuration from serial EEPROM

Legacy Support

– Built in Pseudo-Random Bit Stream (PRBS) generator

– Numerous SerDes test modes

– Ability to read and write any internal register via the SMBus

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

– PCI compatible INTx emulation

– Bus locking

Block Diagram

5-Port Switch Core / 5 PCI Express Lanes

Port

Frame Buffer

Route Table

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Mux / Demux

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

Logical

Layer

Logical

Layer

Logical

Layer

Logical

Layer

SerDes

(Port 2)

(Port 4)

(Port 5)

(Port 0)

(Port 3)

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

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IDT 89PES5T5 Data Sheet

11 General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output

– Each pin may be individually configured as an interrupt input

– Some pins have selectable alternate functions

Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high

throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex

switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc-

tions and is fully compliant with PCI Express Base specification revision 1.1.

The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-

tion layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through

switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated

resource management to allow efficient switching for applications requiring additional narrow port connectivity.

Processor

Memory

North

Bridge

South

Bridge

PES5T5

LOM

1394

Figure 2 I/O Expansion Application

SMBus Interface

The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every

configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of

the PES5T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an

external Hot-Plug I/O expander.

Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In

the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these

address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up

on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in

Table 1.

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IDT 89PES5T5 Data Sheet

Slave

SMBus

Address

Master

SMBus

Address

Bit

SSMBADDR[1]

MSMBADDR[1]

SSMBADDR[2]

MSMBADDR[2]

SSMBADDR[3]

MSMBADDR[3]

MSMBADDR[4]

SSMBADDR[5]

Table 1 Master and Slave SMBus Address Assignment

As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure

3(a), the master and slave SMBuses are tied together and the PES5T5 acts both as a SMBus master as well as a SMBus slave on this bus. This

requires that the SMBus master or processor that has access to PES5T5 registers supports SMBus arbitration. In some systems, this SMBus master

interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support

these systems, the PES5T5 may be configured to operate in a split configuration as shown in Figure 3(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.

The PES5T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the

serial EEPROM.

Processor

SMBus

Master

Other

... SMBus

Devices

Processor

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

...

PES5T5

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

MSMBCLK

MSMBDAT

Serial

EEPROM

(b) Split Configuration and Management Buses

Figure 3 SMBus Interface Configuration Examples

(a) Unified Configuration and Management Bus

Hot-Plug Interface

The PES5T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES5T5 utilizes

an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-

ever the state of a Hot-Plug output needs to be modified, the PES5T5 generates an SMBus transaction to the I/O expander with the new value of all of

the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate

function of GPIO) of the PES5T5. In response to an I/O expander interrupt, the PES5T5 generates an SMBus transaction to read the state of all of the

Hot-Plug inputs from the I/O expander.

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IDT 89PES5T5 Data Sheet

General Purpose Input/Output

The PES5T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may

be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate

functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

Pin Description

The following tables lists the functions of the pins provided on the PES5T5. Some of the functions listed may be multiplexed onto the same pin. The

active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.

All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal

Type

Name/Description

PE0RP[0]

PE0RN[0]

PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pair for port 0.

PE0TP[0]

PE0TN[0]

PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 0.

PE2RP[0]

PE2RN[0]

PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pair for port 2.

PE2TP[0]

PE2TN[0]

PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 2.

PE3RP[0]

PE3RN[0]

PCI Express Port 3 Serial Data Receive. Differential PCI Express receive

pair for port 3.

PE3TP[0]

PE3TN[0]

PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 3.

PE4RP[0]

PE4RN[0]

PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pair for port 4.

PE4TP[0]

PE4TN[0]

PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 4.

PE5RP[0]

PE5RN[0]

PCI Express Port 5 Serial Data Receive. Differential PCI Express receive

pair for port 5.

PE5TP[0]

PE5TN[0]

PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-

mit pair for port 5.

PEREFCLKP

PEREFCLKN

PCI Express Reference Clock. Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

REFCLKM

PCI Express Reference Clock Mode Select. This signal selects the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

Table 2 PCI Express Interface Pins

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IDT 89PES5T5 Data Sheet

Signal

Type

Name/Description

MSMBADDR[4:1]

Master SMBus Address. These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

MSMBCLK

I/O

Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT

Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[5,3:1]

SSMBCLK

Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

I/O

Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT

Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 3 SMBus Interface Pins

Signal

Type

Name/Description

GPIO[0]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P4RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 4

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN1

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 1 input

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN2

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 2 input

GPIO[5]

GPIO[6]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Table 4 General Purpose I/O Pins (Part 1 of 2)

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IDT 89PES5T5 Data Sheet

Signal

Type

Name/Description

GPIO[7]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

GPIO[8]

GPIO[9]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P3RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 3

GPIO[10]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P5RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 5

Table 4 General Purpose I/O Pins (Part 2 of 2)

Signal

Type

Name/Description

APWRDISN

Auxiliary Power Disable Input. When this pin is active, it disables the

device from using auxiliary power supply.

CCLKDS

Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be override by modifying the SCLK bit in the downstream

port’s PCIELSTS register.

CCLKUS

Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the PA_PCIELSTS register.

MSMBSMODE

PERSTN

Master SMBus Slow Mode. The assertion of this pin indicates that the

master SMBus should operate at 100 KHz instead of 400 kHz. This value

may not be overridden.

Fundamental Reset. Assertion of this signal resets all logic inside the

PES5T5 and initiates a PCI Express fundamental reset.

Table 5 System Pins (Part 1 of 2)

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IDT 89PES5T5 Data Sheet

Signal

Type

Name/Description

RSTHALT

Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, the PES5T5 executes the reset procedure and remains in a reset

state with the Master and Slave SMBuses active. This allows software to

read and write registers internal to the device before normal device opera-

tion begins. The device exits the reset state when the RSTHALT bit is

cleared in the PA_SWCTL register by an SMBus master.

SWMODE[2:0]

WAKEN

Switch Mode. These configuration pins determine the PES5T5 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0xF Reserved

I/O

Wake Input/Output. The WAKEN signal is an input or output. The WAKEN

signal input/output selection can be made through the WAKEDIR bit setting

in the WAKEUPCNTL register.

Table 5 System Pins (Part 2 of 2)

Signal

Type

Name/Description

JTAG_TCK

JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI

JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO

JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS

JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N

JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 6 Test Pins

Signal

Type

Name/Description

V_DDCORE

Core VDD. Power supply for core logic.

I/O VDD. LVTTL I/O buffer power supply.

V_DDIO

V_DDPE

PCI Express Digital Power. PCI Express digital power used by the digital

power of the SerDes.

V_DDAPE

PCI Express Analog Power. PCI Express analog power used by the PLL

and bias generator.

V_TTPE

V_SS

PCI Express Termination Power.

Ground.

Table 7 Power and Ground Pins

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IDT 89PES5T5 Data Sheet

Pin Characteristics

Note: Some input pads of the PES5T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.

This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left

floating can cause a slight increase in power consumption.

I/O

Internal

Resistor

Function

Pin Name

PE0RN[0]

Type

Buffer

Notes

Type

PCI Express Inter-

face

CML

Serial Link

PE0RP[0]

PE0TN[0]

PE0TP[0]

PE2RN[0]

PE2RP[0]

PE2TN[0]

PE2TP[0]

PE3RN[0]

PE3RP[0]

PE3TN[0]

PE3TP[0]

PE4RN[0]

PE4RP[0]

PE4TN[0]

PE4TP[0]

PE5RN[0]

PE5RP[0]

PE5TN[0]

PE5TP[0]

PEREFCLKN

PEREFCLKP

REFCLKM

MSMBADDR[4:1]

MSMBCLK

MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK

SSMBDAT

LVPECL/

CML

Diff. Clock

Input

Refer toTable 9

LVTTL

Input

STI¹

pull-down

pull-up

SMBus

I/O

STI

Input

STI

pull-up

I/O

STI

General Purpose I/O GPIO[10:0]

LVTTL

High Drive

Table 8 Pin Characteristics (Part 1 of 2)

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IDT 89PES5T5 Data Sheet

I/O

Type

Internal

Resistor

Function

Pin Name

Type

Buffer

Notes

System Pins

APWRDISN

CCLKDS

LVTTL

Input

pull-down

pull-up

CCLKUS

pull-up

MSMBSMODE

PERSTN

pull-down

RSTHALT

pull-down

open-drain

pull-up

SWMODE[2:0]

WAKEN

I/O

EJTAG / JTAG

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

LVTTL

STI

pull-up

STI

pull-up

Table 8 Pin Characteristics (Part 2 of 2)

Schmitt Trigger Input (STI).

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IDT 89PES5T5 Data Sheet

Logic Diagram — PES5T5

PCI Express

Switch

SerDes Output

Port 0

PEREFCLKP

PE0TP[0]

PE0TN[0]

Reference

PEREFCLKN

Clock

REFCLKM

PCI Express

PE0RP[0]

Switch

PCI Express

Switch

SerDes Output

Port 2

PE2TP[0]

PE2TN[0]

SerDes Input

Port 0

PE0RN[0]

PCI Express

Switch

SerDes Input

Port 2

PE2RP[0]

PE2RN[0]

PCI Express

Switch

SerDes Output

Port 3

PE3TP[0]

PE3TN[0]

PCI Express

Switch

SerDes Input

Port 3

PE3RP[0]

PE3RN[0]

PCI Express

Switch

SerDes Output

Port 4

PE4TP[0]

PE4TN[0]

PES5T5

PCI Express

Switch

SerDes Input

Port 4

PE4RP[0]

PE4RN[0]

PCI Express

Switch

SerDes Output

Port 5

PE5TP[0]

PE5TN[0]

PCI Express

Switch

SerDes Input

Port 5

PE5RP[0]

PE5RN[0]

General Purpose

I/O

GPIO[10:0]

JTAG_TCK

JTAG_TDI

MSMBADDR[4:1]

MSMBCLK

Master

SMBus Interface

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

JTAG Pins

MSMBDAT

SSMBADDR[5,3:1]

SSMBCLK

Slave

SMBus Interface

CORE

SSMBDAT

APE

MSMBSMODE

CCLKDS

Power/Ground

System

Pins

CCLKUS

RSTHALT

PERSTN

SWMODE[2:0]

WAKEN

APWRDISN

Figure 4 PES5T5 Logic Diagram

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IDT 89PES5T5 Data Sheet

System Clock Parameters

Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.

Parameter

Description

Min

Typical

Max

Unit

PEREFCLK

Refclk_FREQ

Input reference clock frequency range

Duty cycle of input clock

100

125¹

MHz

Refclk_DC

T_R, T_F

V_SW

Rise/Fall time of input clocks

Differential input voltage swing⁴

Input clock jitter (cycle-to-cycle)

0.2*RCUI

1.6

RCUI³

0.6

T_jitter

125

Table 9 Input Clock Requirements

^1.The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.

^2.ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.

^3.RCUI (Reference Clock Unit Interval) refers to the reference clock period.

^4.AC coupling required.

AC Timing Characteristics

Parameter

Description

Min¹

Typical¹

Max¹

Units

PCIe Transmit

Unit Interval

Minimum Tx Eye Width

399.88

0.7

400

400.12

0.15

T_TX-EYE

T_{TX-EYE-MEDIAN-to-}Maximum time between the jitter median and maximum

deviation from the median

MAX-JITTER

_TX-RISE,T_TX-FALLD+ / D- Tx output rise/fall time

T_{TX- IDLE-MIN}

Minimum time in idle

T_{TX-IDLE-SET-TO-}

Maximum time to transition to a valid Idle after sending

an Idle ordered set

IDLE

T_{TX-IDLE-TO-DIFF-}

Maximum time to transition from valid idle to diff data

DATA

T_TX-SKEW

T_BTEn

Transmitter data skew between any 2 lanes

500

1300

Time from asserting Beacon TxEn to beacon being trans-

mitted on the lane

PCIe Receive

Unit Interval

399.88

0.4

400

400.12

T_{RX-EYE (with jitter)}

Minimum Receiver Eye Width (jitter tolerance)

Table 10 PCIe AC Timing Characteristics (Part 1 of 2)

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IDT 89PES5T5 Data Sheet

Parameter

Description

Min¹

Typical¹

Max¹

Units

T_{RX-EYE-MEDIUM TO}Max time between jitter median & max deviation

0.3

MAX JITTER

T_{RX-IDLE-DET-DIFF-}

Unexpected Idle Enter Detect Threshold Integration Time

ENTER TIME

T_RX-SKEW

Lane to lane input skew

Table 10 PCIe AC Timing Characteristics (Part 2 of 2)

^1.Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1

Timing

Reference

Signal

Symbol

Min Max Unit

Diagram

Edge

Reference

GPIO

GPIO[10:0]¹

Tpw_13b²

None

—

See Figure 5.

Table 11 GPIO AC Timing Characteristics

^1.GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if

they are asynchronous.

^2.The values for this symbol were determined by calculation, not by testing.

EXTCLK

Tdo_13a

GPIO (synchronous output)

GPIO (asynchronous input)

Tpw_13b

Figure 5 GPIO AC Timing Waveform

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IDT 89PES5T5 Data Sheet

Timing

Diagram

Reference

Edge

Signal

Symbol

Min

Max

Unit

JTAG

JTAG_TCK

Tper_16a

none

25.0

10.0

50.0

25.0

See Figure 6.

Thigh_16a,

Tlow_16a

JTAG_TMS¹,

JTAG_TDI

Tsu_16b

Thld_16b

Tdo_16c

Tdz_16c²

Tpw_16d²

JTAG_TCK rising

JTAG_TCK falling

none

2.4

1.0

—

JTAG_TDO

11.3

—

JTAG_TRST_N

25.0

Table 12 JTAG AC Timing Characteristics

^1.The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N

changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK

when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.

^2.The values for this symbol were determined by calculation, not by testing.

Tlow_16a

Tper_16a

Thigh_16a

JTAG_TCK

Thld_16b

Tsu_16b

JTAG_TDI

Thld_16b

Tsu_16b

JTAG_TMS

Tdo_16c

Tdz_16c

JTAG_TDO

Tpw_16d

JTAG_TRST_N

Figure 6 JTAG AC Timing Waveform

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IDT 89PES5T5 Data Sheet

Recommended Operating Supply Voltages

Symbol

Parameter

Internal logic supply

Minimum

Typical

Maximum

Unit

V_DDCORE

V_DDI/O

0.9

3.135

0.9

1.0

3.3

1.0

1.5

1.1

3.465

1.1

I/O supply except for SerDes LVPECL/CML

PCI Express Digital Power

V_DDPE

_DDAPE

PCI Express Analog Power

0.9

1.1

V_TTPE

PCI Express Serial Data Transmit

Termination Voltage

1.425

1.575

V_SS

Common ground

Table 13 PES5T5 Operating Voltages

Power-Up/Power-Down Sequence

This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the

PES5T5, the power-up sequence must be as follows:

I/O — 3.3V

Core, V PE, V APE — 1.0V

PE — 1.5V

When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues

are avoided. There are no maximum time limitations in ramping to valid power levels.

The power-down sequence must be in the reverse order of the power-up sequence.

Recommended Operating Temperature

Grade

Temperature

Commercial

Industrial

0C to +70C Ambient

-40C to +85C Ambient

Table 14 PES5T5 Operating Temperatures

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June 18, 2014

IDT 89PES5T5 Data Sheet

Power Consumption

Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13.

Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in

Table 13.

All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow.

PCIe Digital

Supply

PCIe Analog

Supply

PCIe Termin-

ation Supply

Core Supply

I/O Supply

Total

Typ Max

Number of

Connected

Lanes

Typ

Max

1.1V

Typ

Max

1.1V

Typ

Max

1.1V

Typ

Max

1.575V

Typ

Max

1.0V

1.5V

3.3V

3.465V Power Power

1/1/1/1/1

290

385

250

308

124

143

115

141

3.3

Watts

0.29

0.42

0.25

0.34

0.12

0.16

0.17

0.22

0.01

0.85

1.15

Table 15 PES5T5 Power Consumption

Thermal Considerations

This section describes thermal considerations for the PES5T5 (15mm BCG196 package). The data in Table 16 below contains information that is

relevant to the thermal performance of the PES5T5 switch.

Symbol

Parameter

Value

Units

Conditions

T_J(max)

T_A(max)

Junction Temperature

Ambient Temperature

125

^oC

^oC/W

Watts

Maximum

Maximum for commercial-rated products

Maximum for industrial-rated products

Zero air flow

33.3



Effective Thermal Resistance, Junction-to-Ambient

1 m/S air flow

JA(effective)

26.6

18.7

9.8

2 m/S air flow



Thermal Resistance, Junction-to-Board

Thermal Resistance, Junction-to-Case

Power Dissipation of the Device



1.15

Maximum

Table 16 Thermal Specifications for PES5T5, 15x15mm BCG196 Package

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June 18, 2014

IDT 89PES5T5 Data Sheet

DC Electrical Characteristics

Values based on systems running at recommended supply voltages, as shown in Table 13.

Note: See Table 8, Pin Characteristics, for a complete I/O listing.

I/O Type Parameter

Description

Min¹

Typ¹

Max¹Unit

Conditions

Serial Link

PCIe Transmit

V_TX-DIFFp-p

Differential peak-to-peak output voltage

800

-3

1200

-4

V_TX-DE-RATIODe-emphasized differential output voltage

V_TX-DC-CM

DC Common mode voltage

-0.1

3.7

V_TX-CM-ACP

RMS AC peak common mode output volt-

age

V_TX-CM-DC-

Abs delta of DC common mode voltage

between L0 and idle

100

active-idle-delta

V_{TX-CM-DC-line-}Abs delta of DC common mode voltage

between D+ and D-

delta

V_{TX-Idle-DiffP}

Electrical idle diff peak output



V_{TX-RCV-Detect}Voltage change during receiver detection

600

RL_TX-DIFF

RL_TX-CM

Z_TX-DEFF-DC

Z_OSE

Transmitter Differential Return loss

Transmitter Common Mode Return loss

DC Differential TX impedance

505

100

120

Single ended TX Impedance



Transmitter Eye TX Eye Height (De-emphasized bits)

Diagram

650

Transmitter Eye TX Eye Height (Transition bits)

Diagram

800

175

950

PCIe Receive

V_RX-DIFFp-p

V_RX-CM-AC

Differential input voltage (peak-to-peak)

1200

150

Receiver common-mode voltage for AC

coupling

RL_RX-DIFF

RL_RX-CM

Receiver Differential Return Loss

Receiver Common Mode Return Loss

Differential input impedance (DC)



Z_RX-DIFF-DC

100

120

Z_RX-COMM-DCSingle-ended input impedance



Z_{RX-COMM-HIGH-}Powered down input common mode

200k

350k



impedance (DC)

Z-DC

V_RX-IDLE-DET-Electrical idle detect threshold

175

DIFFp-p

PCIe REFCLK

C_IN

Input Capacitance

1.5

—

Table 17 DC Electrical Characteristics (Part 1 of 2)

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June 18, 2014

IDT 89PES5T5 Data Sheet

I/O Type Parameter

Description

Min¹

Typ¹

Max¹Unit

Conditions

Other I/Os

LOW Drive

Output

I_OL

I_OH

I_OL

I_OH

V_IL

V_IH

—

2.5

-5.5

12.0

-20.0

—

V_OL= 0.4v

V_OH= 1.5V

V_OL= 0.4v

V_OH= 1.5V

—

High Drive

Output

—

Schmitt Trig-

ger Input

(STI)

-0.3

2.0

0.8

—

V_DDIO+

0.5

—

Input

V_IL

V_IH

-0.3

2.0

—

0.8

—

V_DDIO+

0.5

Capacitance

Leakage

C_IN

—

8.5

A

—

Inputs

+ 10

V_DDI/O (max)

I/O_{LEAK W/O}

Pull-ups/downs

I/O_{LEAK WITH}

Pull-ups/downs

—

+ 80

A

V_DDI/O (max)

Table 17 DC Electrical Characteristics (Part 2 of 2)

^1.Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.

17 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

Package Pinout — 196-BGA Signal Pinout for PES5T5

The following table lists the pin numbers and signal names for the PES5T5 device.

Function

Alt Pin

Function

V_DDAPE

_DDAPE

Alt Pin

Function

V_DDCORE

Alt Pin

Function

Alt

V_SS

E13

E14

V_SS

V_DDCORE

V_SS

V_TTPE

MSMBDAT

SSMBADDR_2

SSMBADDR_5

V_DDIO

C10

C11

C12

C13

C14

CCLKDS

V_SS

V_DDIO

H10

H11

H12

H13

H14

V_DDCORE

GPIO_05

GPIO_03

GPIO_02

JTAG_TDO

JTAG_TRST_N

JTAG_TMS

V_DDCORE

V_SS

SWMODE_0

SSMBCLK

SSMBDAT

V_SS

V_DDCORE

V_SS

A10

A11

A12

A13

A14

PE0TN00

V_SS

V_DDCORE

V_DDIO

F10

F11

F12

F13

F14

G10

G11

G12

G13

G14

PE0RP00

V_SS

_DDCORE

V_DDCORE

V_DDPE

GPIO_00

PERSTN

V_SS

_DDPE

V_DDCORE

V_SS

MSMBADDR_4

MSMBCLK

V_DDIO

D10

D11

D12

D13

D14

_DDIO

V_DDCORE

V_SS

_DDCORE

V_SS

J10

J11

J12

J13

J14

K10

SWMODE_2

SWMODE_1

SSMBADDR_1

SSMBADDR_3

_DDCORE

V_DDIO

V_SS

V_DDIO

V_SS

GPIO_06

GPIO_04

JTAG_TDI

V_DDIO

B10

B11

B12

B13

B14

_DDCORE

PE0TP00

V_SS

_DDIO

V_SS

V_DDCORE

V_SS

PE0RN00

V_SS

V_DDAPE

V_SS

V_DDIO

WAKEN

APWRDISN

CCLKUS

V_SS

GPIO_01

RSTHALT

MSMBADDR_1

MSMBADDR_2

MSMBADDR_3

V_DDCORE

V_SS

E10

E11

E12

V_DDCORE

V_SS

V_TTPE

V_DDIO

V_SS

Table 18 PES5T5 196-pin Signal Pin-Out (Part 1 of 2)

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June 18, 2014

IDT 89PES5T5 Data Sheet

Function

V_DDCORE

Alt Pin

Function

Alt Pin

Function

Alt Pin

Function

PE5RN00

Alt

K11

K12

K13

K14

L12

L13

L14

V_SS

M13

MSMBSMODE

V_SS

N14

V_SS

GPIO_10

GPIO_09

V_SS

M14

PEREFCLKP

V_SS

GPIO_08

GPIO_07

JTAG_TCK

V_SS

PEREFCLKN

V_SS

PE2RP00

V_SS

_DDCORE

PE2RN00

V_SS

V_DDCORE

V_SS

PE2TN00

PE3TP00

V_SS

PE2TP00

PE3TN00

V_SS

_DDIO

V_DDIO

_DDCORE

V_TTPE

PE3RP00

PE4RN00

V_SS

V_DDCORE

V_DDAPE

V_TTPE

PE3RN00

PE4RP00

V_SS

_DDPE

M10

M11

M12

P10

P11

P12

P13

P14

_DDPE

N10

N11

N12

N13

PE4TP00

PE5TN00

V_SS

_DDCORE

V_DDIO

PE4TN00

PE5TP00

V_SS

L10

L11

V_DDIO

V_SS

REFCLKM

PE5RP00

Table 18 PES5T5 196-pin Signal Pin-Out (Part 2 of 2)

Alternate Signal Functions

GPIO

Alternate

F12

G13

H14

H13

J14

K14

L14

L13

GPIO_00

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_07

GPIO_09

GPIO_10

P2RSTN

P4RSTN

IOEXPINTN0

IOEXPINTN1

IOEXPINTN2

GPEN

P3RSTN

P5RSTN

Table 19 PES5T5 Alternate Signal Functions

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June 18, 2014

IDT 89PES5T5 Data Sheet

Power Pins

V_DDCore

V_DDIO

V_DDPE

V_DDAPE

V_TTPE

H10

H11

C12

D10

D11

E12

E10

E13

K11

F11

G12

J11

J12

F10

L10

M10

M11

Table 20 PES5T5 Power Pins

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June 18, 2014

IDT 89PES5T5 Data Sheet

Ground Pins

V_ss

D12

G10

G11

L11

L12

M14

A12

A14

E11

E14

J10

N10

N13

B12

B14

F14

K10

K12

C11

C13

P10

P13

Table 21 PES5T5 Ground Pins

No Connection Pins

A10

B10

Table 22 PES5T5 No Connection Pins

21 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

Signals Listed Alphabetically

Signal Name I/O Type

Location

Signal Category

APWRDISN

CCLKDS

C10

System

CCLKUS

GPIO_00

I/O

F12

G13

H14

H13

J14

H12

J13

K14

K13

L14

L13

General Purpose Input/Output

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_05

GPIO_06

GPIO_07

GPIO_08

GPIO_09

GPIO_10

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

MSMBADDR_1

MSMBADDR_2

MSMBADDR_3

MSMBADDR_4

MSMBCLK

MSMBDAT

MSMBSMODE

JTAG

SMBus

I/O

M13

System

See Table 22 for a listing of No Connection pins.

PE0RN00

PE0RP00

PE0TN00

B13

A13

A11

B11

PCI Express

PE0TP00

PE2RN00

PE2RP00

PE2TN00

Table 23 PES5T5 Alphabetical Signal List (Part 1 of 2)

22 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

Signal Name I/O Type

Location

Signal Category

PE2TP00

PCI Express (cont.)

PE3RN00

PE3RP00

PE3TN00

PE3TP00

PE4RN00

PE4RP00

PE4TN00

N11

P11

N14

P14

P12

N12

PE4TP00

PE5RN00

PE5RP00

PE5TN00

PE5TP00

PEREFCLKN

PEREFCLKP

PERSTN

F13

M12

G14

System

PCI Express

System

REFCLKM

RSTHALT

SSMBADDR_1

SSMBADDR_2

SSMBADDR_3

SSMBADDR_5

SSMBCLK

SSMBDAT

SWMODE_0

SWMODE_1

SWMODE_2

WAKEN

SMBus

I/O

SMBus

System

C14

D14

D13

I/O

V_DDCORE,

See Table 20 for a listing of power pins.

V_DDAPE, V_DDIO,

V_DDPE_,V_TTPE

V_SS

See Table 21 for a listing of ground pins.

Table 23 PES5T5 Alphabetical Signal List (Part 2 of 2)

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June 18, 2014

IDT 89PES5T5 Data Sheet

PES5T5 Pinout — Top View

Signals

V_TTPE (Power)

V_DDPE (Power)

V_DDCore (Power)

Vss (Ground)

No Connect

V_DDI/O (Power)

V_DDAPE (Power)

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June 18, 2014

IDT 89PES5T5 Data Sheet

PES5T5 Package Drawing — 196-Pin BC196/BCG196

25 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

PES5T5 Package Drawing — Page Two

26 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

Revision History

March 31, 2008: Publication of final data sheet.

August 6, 2008: Added industrial temperature information to Tables 14 and 16 and to Ordering Information section.

May 7, 2009: Revised labels in Table 15, Power Consumption, for greater clarification.

June 18, 2014: Changed the height dimension for the side view in PES5T5 Package Drawing — 196-Pin BC196/BCG196 to match the package’s

characteristics.

27 of 28

June 18, 2014

IDT 89PES5T5 Data Sheet

Ordering Information

Legend

A = Alpha Character

N = Numeric Character

AAA

NNAN

Product

Family

Operating

Voltage

Device

Family

Temp Range

Package

Product

Detail

Device

Revision

Commercial Temperature

(0°C to +70°C Ambient)

Blank

Industrial Temperature

(-40° C to +85° C Ambient)

BC196 196-ball CABGA

BCG196 196-ball CABGA, Green

BCG

ZB revision

5-lane, 5-port

5T5

PCI Express Switch

PES

1.0V +/- 0.1V Core Voltage

Serial Switching Product

Valid Combinations

89HPES5T5ZBBC

89HPES5T5ZBBCG

89HPES5T5ZBBCI

89HPES5T5ZBBCGI

196-pin BC196 package, Commercial Temperature

196-pin Green BCG196 package, Commercial Temperature

196-pin BC196 package, Industrial Temperature

196-pin Green BCG196 package, Industrial Temperature

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28 of 28

June 18, 2014

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