CD4044BMS [RENESAS]
R-S Latch;
| 型号： | CD4044BMS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | R-S Latch 逻辑集成电路 |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4043BMS
CD4044BMS
CMOS Quad 3 State R/S Latches
December 1992
Features
Pinout
• High Voltage Types (20V Rating)
CD4043BMS
TOP VIEW
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
Q4
Q1
1
2
3
4
5
6
7
8
16 VDD
15 R4
14 S4
13 NC
12 S3
11 R3
10 Q3
R1
S1
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
ENABLE
S2
R2
• Maximum Input Current of 1µa at 18V Over Full Pack-
9
Q2
VSS
age-Temperature Range;
- 100nA at 18V and 25oC
NC = NO CONNECTION
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
CD4044BMS
TOP VIEW
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Q4
NC
1
2
3
4
5
6
7
8
16 VDD
15 S4
14 R4
13 Q1
12 R3
11 S3
10 Q3
S1
Applications
R1
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
ENABLE
R2
S2
• General Digital Logic
9
Q2
VSS
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
NC = NO CONNECTION
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP
Frit Seal DIP
*H4T
*H1C
†H4T
†HIE
Ceramic Flatpack
*CD4043B Only
*H3X †H6W
†CD4044B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3311
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-876
Specifications CD4043BMS, CD4044BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
2
200
2
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
-
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
o
Tri-State Output
Leakage
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-0.4
-
-
µA
µA
µA
µA
µA
µA
o
+125 C
-12
o
VDD = 18V
VDD = 20V
-55 C
-0.4
-
o
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
0.4
12
0.4
o
+125 C
o
VDD = 18V
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-877
Specifications CD4043BMS, CD4044BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS
MAX
300
405
230
311
180
243
200
270
UNITS
ns
o
Propagation Delay
Set or Reset to Q
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
9
10, 11
9
+25 C
-
-
-
-
-
-
-
-
o
o
+125 C, -55 C
ns
o
Propagation Delay
3 - State Enable to Q
TPHZ
TPZH
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
3 - State Enable to Q
TPLZ
TPZL
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
1
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
30
2
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
60
2
µA
o
o
-55 C, +25 C
µA
o
+125 C
120
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
7-878
Specifications CD4043BMS, CD4044BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
o
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
-
3
V
o
-55 C
o
o
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25 C, +125 C,
7
-
V
o
-55 C
o
Propagation Delay
Set or Reset to Q
TPLH
TPHL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
140
100
110
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
o
+25 C
o
Propagation Delay
3 State Enable to Q
TPHZ
TPZH
+25 C
o
+25 C
o
Propagation Delay
3 State Enable to Q
TPLZ
TPZL
+25 C
100
70
o
+25 C
o
Transition Time
TTHL
TTLH
+25 C
100
80
o
+25 C
o
Minimum Set or Reset
Pulse Width
TW
+25 C
160
80
o
+25 C
o
+25 C
40
o
Input Capacitance
NOTES:
CIN
+25 C
7.5
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
7.5
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 0.2µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-879
Specifications CD4043BMS, CD4044BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4043BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
1, 2, 9, 10, 13
13
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
8
8
8
3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1
5, 16
1, 2, 9, 12
4, 6, 12, 14
3, 7, 11, 15
Irradiation
Note 2
1, 2, 9, 10, 13
3 - 7, 11, 12,
14 - 16
PART NUMBER CD4044BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
1, 2, 9, 10, 13
2
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
8
8
8
3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1
5, 16
1, 9, 10, 13
4, 6, 12, 14
3, 7, 11, 15
Irradiation
Note 2
1, 2, 9, 10, 13
3 - 7, 11, 12,
14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-880
Specifications CD4043BMS, CD4044BMS
Functional Diagram
VDD
VDD
16
16
R1
S1
4
3
S1
R1
4
3
LATCH
1
LATCH
1
13 Q1
2
9
Q1
Q2
R2
S2
6
7
S2
R2
6
7
LATCH
2
LATCH
2
9
Q2
R3
S3
12
11
S3
R3
12
11
LATCH
3
LATCH
3
10 Q3
10 Q3
R4
S4
14
15
5
S4
R4
14
15
5
LATCH
4
LATCH
4
1
2
Q4
NC
1
Q4
ENABLE
ENABLE
13 NC
8
8
VSS
VSS
CD4043BMS
CD4044BMS
Logic Diagram
EQUIVALENT
NOR LATCH
EQUIVALENT
NAND LATCH
E
VDD
E
VDD
S1
S1
3
4
*
*
Q1
2
Q1
13
R1
R1
4
3
*
*
*
E
VSS
E
E
5
E
VSS
5
E
E
E
E
*
VDD
VDD
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
VSS
CD4043BMS
CD4044BMS
TRUTH TABLE
CD4043BMS
CD4044BMS
S
X
O
1
R
X
O
O
1
E
O
1
Q
OC*
NC**
1
S
X
1
R
X
1
E
O
1
Q
OC*
NC**
1
1
O
1
1
1
O
1
1
O
O
O
1
O
1
1
∆
O
1
∆∆
* Open Circuit
** No Change
* Open Circuit
** No Change
∆ Dominated by S = 1 input
∆∆ Dominated by R = O input
7-881
CD4043BMS, CD4044BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
175
AMBIENT TEMPERATURE (TA) = +25oC
150
SUPPLY VOLTAGE (VDD) = 5V
125
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
15V
75
50
25
100
10V
15V
50
0
0
10 20
30 40
50 60
70 80
90 100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - SET, RESET, to Q, Q
7-882
CD4043BMS, CD4044BMS
Typical Performance Characteristics (Continued)
106
105
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
104
103
10V
102
10
1
10V
5V
CL =15pF
CL = 50pF
103
104
105
106
107
INPUT FREQUENCY (fI) (kHz)
FIGURE 7. TYPICAL POWER DISSIPATION vs FREQUENCY
VDD
1MΩ
1MΩ
VDD
S
Q
OUTPUT
S
Q
OUTPUT
LATCH
LATCH
R
R
1MΩ
1MΩ
VDD
CD4044BMS
CD4043BMS
FIGURE 8. SWITCH BOUNCE ELIMINATOR
TEST
IN
IN
A
VDD
tPHZ VDD VSS VSS
tPLZ VSS VDD VDD
tPZH VDD VSS VSS
tPZL VSS VDD VDD
Z = HIGH IMPEDANCE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
50%
50%
ENABLE
POINT A
VSS
≈ 2/3 VDD
90%
tPZH
ENABLE
IN
tPHZ
10%
≈ 1/3 VDD
(IN = VDD, IN = VSS)
IN
POINT A
≈ 2/3 VDD
≈ 1/3 VDD
1KΩ
90%
10%
(IN = VSS, IN = VDD)
A
tPZL
tPLZ
CL = 50pF
VSS
FIGURE 9. ENABLE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORM
7-883
CD4043BMS
CD4001
1 OF 4
1
2
3
4
10
11
4
6
12
14
2
5
6
9
BUS A
8
CD4043
3
10
1
9
12
13
7
11
15
LOAD A
5
ENABLE A
CD4001
1
2
3
4
4
6
2
5
6
10
11
12
14
9
BUS B
8
CD4043
3
10
1
9
12
13
7
11
15
LOAD B
3
5
7
9
2
4
5
ENABLE B
OUTPUT
DATA
BUS
6
CD4001
10
1
2
3
4
4
6
2
5
6
10
11
12
14
9
2/3 CD4009
BUS C
8
CD4043
3
10
1
9
12
13
7
11
15
LOAD C
5
ENABLE C
CD4001
1
2
3
4
4
6
2
5
6
10
11
12
14
9
BUS D
8
CD4043
3
10
1
9
12
13
7
11
15
LOAD D
5
ENABLE D
RESET
FIGURE 10. MULTIPLE BUS STORAGE
7-884
CD4043BMS
Chip Dimensions and Pad Layouts
CD4043BMSH
CD4044BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (321) 724-7000
FAX: (321) 724-7240
885
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