EL5205IY-T7 [RENESAS]
1 CHANNEL, VIDEO AMPLIFIER, PDSO8, 3 MM, MSOP-8;
| 型号： | EL5205IY-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1 CHANNEL, VIDEO AMPLIFIER, PDSO8, 3 MM, MSOP-8 放大器 光电二极管 商用集成电路 |
| 文件： | 总18页 (文件大小：2014K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL5104, EL5105, EL5204, EL5205, EL5304
700MHz Slew-Enhanced VFAs
FN7332
Rev 8.00
May 25, 2016
The EL5104, EL5105, EL5204, EL5205, and EL5304
represent high speed voltage feedback amplifiers based on
the current feedback amplifier architecture. This gives the
typical high slew rate benefits of a CFA family along with the
stability and ease of use associated with the VFA type
architecture. This family is available in single, dual, and triple
versions, with 200MHz, 400MHz, and 700MHz versions.
This family operates on single 5V or ±5V supplies from
minimum supply current. The EL5104 and EL5204 also
feature an output enable function, which can be used to put
the output in to a high-impedance mode. This enables the
outputs of multiple amplifiers to be tied together for use in
multiplexing applications.
Features
• Specified for 5V or ±5V applications
• Power-down to 17µA
• -3dB bandwidth = 700MHz
• ±0.1dB bandwidth = 45MHz
• Low supply current = 9.5mA
• Slew rate = 7000V/µs
• Low offset voltage = 10mV max
• Output current = 160mA
• A
VOL
= 1400
• Diff gain/phase = 0.01%/0.02°
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High speed communications
• RGB applications
• Broadcast equipment
• Active filtering
FN7332 Rev 8.00
May 25, 2016
Page 1 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Pinouts
EL5104
(6 LD SOT-23)
TOP VIEW
EL5104
(8 LD SOIC)
TOP VIEW
EL5105
(5 LD SOT-23, SC-70)
TOP VIEW
OUT
VS-
IN+
1
2
3
6
5
4
VS+
NC
IN-
1
2
3
4
8
7
6
5
ABLE
VS+
OUT
VS-
IN+
1
2
3
5
VS+
ENABLE
IN-
-
+
+
-
+ -
IN+
VS-
OUT
4
IN-
NC
EL5204
(10 LD MSOP)
TOP VIEW
EL5205
(8 LD SOIC, MSOP)
EL5304
(16 LD QSOP)
TOP VIEW
TOP VIEW
OUTA
INA-
INA+
VS-
OUT
IN-
1
2
3
4
5
10 VS+
1
2
3
4
8
7
6
5
VS+
INA+
CEA
VS-
1
2
3
4
5
6
7
8
16 INA-
15 TA
14 VS+
-
+
9
8
7
6
OUT
IN-
-
+
OUTB
INB-
-
+
IN+
VS-
CE
-
+
-
+
-
IN+
CE
INB+
CEB
INB+
N
13 OUTB
12 INB-
11 NC
+
-
CEC
INC+
10 OUTC
9
INC-
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
MDP0027
EL5104ISZ (Note) (No longer
available, recommended
replacement: EL5104IWZ-T7)
5104ISZ
5104ISZ
5104ISZ
-
8 Ld SOIC (150 mil) (Pb-Free)
8 Ld SOIC (150 mil) (Pb-Free)
8 Ld SOIC (150 mil) (Pb-Free)
EL5104ISZ-T7 (Note) (No longer
available, recommended
replacement: EL5104IWZ-T7)
7”
MDP0027
MDP0027
EL5104ISZ-T13 (Note) (No longer
available, recommended
13”
replacement: EL5104IWZ-T7)
EL5104IWZ-T7 (Note)
EL5104IWZ-T7A (Note)
BAEA
BAEA
C
7” (3k pcs)
7” (250 pcs)
-
6 Ld SOT-23 (Pb-Free)
6 Ld SOT-23 (Pb-Free)
5 Ld SC-70 (1.25mm)
P5.064A
P5.064A
P5.049
EL5105IC (No longer available or
supported)
EL5105IWZ-T7 (Note)
EL5105IWZ-T7A (Note)
EL5204IYZ (Note)
BBMA
BBMA
BAAAF
BAAAF
BAAAF
7” (3k pcs)
5 Ld SOT-23 (Pb-Free)
P5.064A
P5.064A
MDP0043
MDP0043
MDP0043
7” (250 pcs)
5 Ld SOT-23 (Pb-Free)
-
10 Ld MSOP (3.0mm) (Pb-Free)
10 Ld MSOP (3.0mm) (Pb-Free)
10 Ld MSOP (3.0mm) (Pb-Free)
EL5204IYZ-T7 (Note)
EL5204IYZ-T13 (Note)
7”
13”
FN7332 Rev 8.00
May 25, 2016
Page 2 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Ordering Information (Continued)
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
MDP0027
EL5205ISZ (Note)
5205ISZ
-
7”
13”
-
8 Ld SOIC (150 mil) (Pb-Free)
8 Ld SOIC (150 mil) (Pb-Free)
8 Ld SOIC (150 mil) (Pb-Free)
16 Ld QSOP (150 mil)
EL5205ISZ-T7 (Note)
EL5205ISZ-T13 (Note)
5205ISZ
MDP0027
MDP0027
MDP0040
5205ISZ
EL5304IU (No longer available or 5304IU
supported)
EL5304IU-T7 (No longer available 5304IU
or supported)
7”
13”
-
16 Ld QSOP (150 mil)
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
EL5304IU-T13 (No longer available 5304IU
or supported)
16 Ld QSOP (150 mil)
EL5304IUZ (Note) (No longer
available or supported)
5304IUZ
5304IUZ
5304IUZ
16 Ld QSOP (150 mil) (Pb-Free)
16 Ld QSOP (150 mil) (Pb-Free)
16 Ld QSOP (150 mil) (Pb-Free)
EL5304IUZ-T7 (Note) (No longer
available or supported)
7”
EL5304IUZ-T13 (Note) (No longer
13”
available or supported)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7332 Rev 8.00
May 25, 2016
Page 3 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and GND. . . . . . . . . . . . . . . . . . 13.2V
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
V + to V - Maximum Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
S
S
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
V
= ±5V, GND = 0V, T = +25°C, V
= 0V, V
= 0V, V
= GND or OPEN, Unless Otherwise
ENABLE
S
A
CM
OUT
Specified.
DESCRIPTION
Offset Voltage
PARAMETER
CONDITIONS
MIN
-10
-18
TYP
3
MAX
10
UNIT
mV
V
EL5104, EL5105, EL5204, EL5205
EL5304
OS
5
18
mV
TCV
IB
Offset Voltage Temperature Coefficient
Input Bias Current
Measured from T
to T
10
8
µV/°C
µA
OS
MIN
MAX
MAX
V
V
= 0V
= 0V
30
15
IN
IN
I
Input Offset Current
4
µA
OS
TCI
Input Bias Current Temperature
Coefficient
Measured from T
to T
50
nA/°C
OS
MIN
PSRR
CMRR
CMIR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Common Mode Input Range
Input Resistance
60
56
-3
70
62
dB
dB
V
V
from -3V to +3V
CM
Guaranteed by CMRR test
Common mode
SO package
+3
R
C
50
120
1
k
pF
mA
µA
µA
V
IN
Input Capacitance
IN
I
I
Supply Current - Enabled
Supply Current - Shut Down
Per amplifier
8.5
+1
-25
4
9.5
0
11
+25
-1
S,ON
S,OFF
V +, per amplifier
S
V -, per amplifier
17
S
PSOR
AVOL
Power Supply Operating Range
Open Loop Gain
13.2
R = 1k to GND
55
65
60
dB
dB
V
L
R = 150 to GND
L
V
V
Positive Output Voltage Swing
Negative Output Voltage Swing
Output Current
R = 150 to 0V
3.6
3.8
OP
ON
L
R = 150 to 0V
-3.8
±160
-3.6
V
L
I
R = 10 to 0V
±90
mA
V
OUT
L
V
ENABLE Pin Voltage for Power Up
(V +)
S
(V +)
S
IH-EN
-5
-3
V
ENABLE Pin Voltage for Shut Down
(V +)
S
V +
V
IL-EN
S
-1
FN7332 Rev 8.00
May 25, 2016
Page 4 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Closed Loop AC Electrical Specifications V = +5V, GND = 0V, T = +25°C, V
= +1.5V, V
= +1.5V, V
= +5V,
CLAMP
S
A
CM
OUT
V
= 0V, A = +1, R = 0, R = 150 to GND pin, unless otherwise specified.
ENABLE
V
F
L
PARAMETER
BW
SR
DESCRIPTION
-3dB Bandwidth (V = 200mV
CONDITIONS
MIN
TYP
700
3000
0.4
10
MAX
UNIT
MHz
V/µs
ns
)
V
= ±5V, A = 1, R = 0
OUT
P-P
S
V
F
Slew Rate
R = 100, V
= -3V to +3V
OUT
2000
7000
L
t , t
R
Rise Time, Fall Time
Overshoot
±0.1V step
±0.1V step
±0.1V step
F
OS
%
t
t
Propagation Delay
0.1% Settling Time
Differential Gain
Differential Phase
Input Noise Voltage
Input Noise Current
Disable Time
0.4
7
ns
PD
S
V
= ±5V, R = 500, A = 1, V
= ±2.5V
ns
S
L
V
OUT
dG
dP
A
= 2, R = 150, V
= -1 to +1V
= -1 to +1V
0.01
0.02
10
%
V
L
INDC
INDC
A
= 2, R = 150, V
°
V
L
e
f = 10kHz
f = 10kHz
nV/Hz
pA/Hz
ns
N
i
54
N
t
t
I
180
650
DIS
EN
EN
Enable Time
ns
Enable Pin Current
Enabled, V
= 0V
= 5V
-1
1
1
µA
EN
Disabled, V
25
µA
EN
FN7332 Rev 8.00
May 25, 2016
Page 5 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves
5
240
180
120
60
V =±5V
S
V =±5V
S
4
3
A =+1
V
A =+1
V
R =0
F
R =0
F
R =500
L
R =500
L
2
1
0
0
-1
-2
-3
-4
-5
-60
-3dB BW @ 925MHz
-120
-180
-240
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH)
FIGURE 2. PHASE vs FREQUENCY
70
60
50
40
30
20
0.5
V =±5V
S
0.4
0.3
0.2
0.1
0
A =+1
GAIN=40dB or 100
FREQ.=2.64MHz
GAIN BW PRODUCT=2.64x100=264MHz
V
R =0
F
R =500
L
0.1dB BW @ 39MHz
-0.1
-0.2
-0.3
-0.4
-0.5
V =±5V
S
R =500
L
1
10
FREQUENCY (MHz)
100
0
1
10
100
FREQUENCY (MHz)
FIGURE 3. 0.1dB BANDWIDTH
FIGURE 4. GAIN BANDWIDTH PRODUCT
300
250
200
150
100
50
5
4
V =±5V
S
R =500
L
3
A =+1
V
R =0
2
F
1
0
-1
-2
-3
-4
-5
A =+5
V
R =1.6k, R =402
F
G
V =±5V
S
A =+2
V
R =500
L
R =R =255
F
G
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
100k
1M
10M
100M
1G
SUPPLY VOLTAGES (±V)
FREQUENCY (Hz)
FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGES
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +A
V
FN7332 Rev 8.00
May 25, 2016
Page 6 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
5
4
5
V =±5
S
A =+1
V
4
A =+1
R =0
V
F
3
3
R =0
F
R =500
L
V =±6V
S
R =1k
L
2
2
1
V =±5V
S
1
R =500
L
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
V =±4V
S
R =150
L
V =±3V
S
R =75
L
V =±2V
S
R =50
L
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±Vs
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS R (A =+1)
L
V
5
5
4
V =±5
S
V =±5
4
3
S
A =+2
V
A =+5
V
R =255
F
3
R =1600
F
C =12pF
2
L
2
R =1k
R =500
L
L
R =1k
1
L
1
R =500
0
L
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R =50
L
R =50
L
R =75
L
R =75
L
R =150
L
R =150
L
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS R (A =+2)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS R (A =+5)
L
V
L
V
5
4
5
4
C =22pF
L
C =33pF
L
V =±5
S
V =±5
S
C =22pF
L
A =+2
A =+1
V
V
C =5.6pF
L
3
3
R =255
R =0
F
C =12pF
F
L
2
R =500
2
C =15pF
L
R =500
L
L
C =3.3pF
L
1
1
C =8.2pF
L
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C =0pF
L
C =0pF
L
100k
1M
10M
100M
1G
10G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS C (A =+1)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS C (A =+2)
L V
L
V
FN7332 Rev 8.00
May 25, 2016
Page 7 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
5
5
4
R =100
V =±5
S
F
V =±5
S
4
3
C =100pF
L
A =+1
A =+5
V
V
R =500
R =50
R =1600
3
L
F
F
C =68pF
L
R =500
L
2
2
C =39pF
L
R =25
F
1
1
0
0
C =22pF
L
-1
-2
-3
-4
-5
-1
-2
-3
R =0
F
C =0pF
L
-4
-5
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS C (A =+5)
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS R (A =+1)
L
V
F
V
5
4
3
2
1
5
4
V =±5
S
V =±5
S
R =604
F
A =+5
A =+2
V
R =6k
V
F
R =500
R =500
L
R =511
L
3
F
R =4k
F
2
R =402
F
1
R =2k
F
0
0
-1
-1
-2
-3
-4
-5
R =255
F
R =1k
F
-2
-3
-4
-5
R =50
F
R =100
F
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS R (A = +2)
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS R (A = +5)
F V
F
V
5
4
5
4
V =±5
S
V =±5
S
C
=3.9pF
IN
A =+5
C
=4.7pF
IN
A =+2
V
V
C
=2.7pF
3
IN
3
R =402
G
R =R =255
C
=3.3pF
F
G
IN
R =1600
R =500
L
L
2
2
C
=2.2pF
IN
C
=2.2pF
C =15pF
IN
L
1
1
0
0
C
=1pF
IN
C =1.5pF
IN
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C
=0pF
IN
C
=0pF
IN
100k
1M
10M
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS C
FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS C
IN(-)
IN(-)
(A = +2)
V
(A = +5)
V
FN7332 Rev 8.00
May 25, 2016
Page 8 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
70
100
10
A =+2
V
V =±5V
S
50
30
10
1
0.1
-10
-30
0.01
1k
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 20. Z
OUT
vs FREQUENCY
-10
10
-10
-30
-50
A =+5
V
S
A =+1
V
V =±5V
V =±5V
S
-30
-50
-70
V +
S
-90
-70
-90
V -
S
-110
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. CMRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
10
9
8
7
6
5
4
3
2
1
0
30
25
20
15
10
5
V =±5V
S
R =500
L
A =+1
V
R =0
F
R =500
L
R =150
L
0
-5
-10
-15
-20
-25
-30
V =±5V
S
A =+2
V
R =R =402
F
G
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100M
1G
FREQUENCY (Hz)
FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 24. GROUP DELAY vs FREQUENCY
FN7332 Rev 8.00
May 25, 2016
Page 9 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
0
-10
-10
V =±5V
S
V =±5V
S
OUTPUT TO INPUT
-20
A =+1
A =+1
V
V
-20
R =0
R =0
F
F
-30
-30
-40
-50
-60
-70
-80
-90
-100
CHIP DISABLED
R =500
L
-40
A IN TO B OUT
-50
-60
-70
INPUT TO OUTPUT
-80
-90
B IN TO A OUT
-100
-110
-120
-130
-140
NOTE:
This was done on the
EL5205 (dual op amp).
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 25. INPUT AND OUTPUT ISOLATION
FIGURE 26. CHANNEL TO CHANNEL ISOLATION
-20
-40
-50
-60
-70
-80
-90
V
=±5V
S
V
=±5V
S
A =+5
A =+1
V
-30
-40
V
R
=402
R =0
G
F
R =1600
R =500
F
R =500
V
L
L
=2V
OUT
P-P
T.H.D
-50 C =15pF
L
F
= 10MHz
IN
-60
-70
-80
-90
nd
H.D.
2
F
= 1MHz
rd
IN
3
H.D.
-100
-110
-100
0
1
2
3
4
5
6
7
8
100k
1M
10M
100M
OUTPUT VOLTAGES (V
)
P-P
FUNDAMENTAL FREQUENCY (Hz)
FIGURE 27. HARMONIC DISTORTION vs FREQUENCY
FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT
VOLTAGES
6
6
Vs =±5V
Vs =±5V
A =+1
5
4
A =+1
V
V
5
4
ENABLE SIGNAL
R =0
R =0
F
F
R =500
R =500
L
L
DISABLE SIGNAL
OUTPUT SIGNAL
V
=2V
V
=2V
3
OUT P-P
OUT
P-P
3
2
2
OUTPUT SIGNAL
1
1
0
0
-1
-2
-3
-1
-2
-3
-600 -400 -200
0
200 400 600 800 1000 1200 1400 1600
TIME (ns)
-600 -400 -200
0
200 400 600 800 1000 1200 1400 1600
TIME (ns)
FIGURE 29. TURN-ON TIME
FIGURE 30. TURN-OFF TIME
FN7332 Rev 8.00
May 25, 2016
Page 10 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
1K
0.5
0.4
V =±5V
S
Vs =±5V
A =+1
V
R =0
F
R =500
L
0.3
V
=400mV
OUT
100
10
1
0.2
0.1
T
= 860ps
FALL
0.0
T
=852ps
RISE
-0.1
-0.2
-0.3
10
100
1k
10k
100k
-20
0
20 40 60 80 100 120 140 160 180
TIME (ns)
FREQUENCY (Hz)
FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
FIGURE 32. SMALL SIGNAL STEP RESPONSE_RISE & FALL
TIME
5
12
Vs =±5V
A =+1
V
A =+1
V
4
3
R =0
F
R =0
F
10
8
R =500
L
R =500
L
V
=4.0V
OUT
P-P
2
1
6
T
= 944ps
FALL
0
4
T
=958ps
RISE
-1
-2
-3
NOTE:
2
The curve showed positive current.
The negative current was the same.
0
-20
0
20 40 60 80 100 120 140 160 180
TIME (ns)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
FIGURE 33. LARGE SIGNAL STEP RESPONSE_RISE & FALL
TIME
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
5000
10
Vs =±5V
V
A =+2
V
NEGATIVE SLEW RATE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
A =+5
R =R =255
4500
4000
F
G
Delta IM=(4)-(-73)=77dB
IP3=4+(77/2)=42.5dBm
R =1600
F
R =500
L
R =100
L
V
=4V
OUT P-P
C =15pF
L
f2=4.1dBm
@ 1.05MHz
3500
3000
2500
2000
1500
1000
f1=4dBm
@ 0.95MHz
POSITIVE SLEW RATE
2f2-f1=-73dBm
@ 1.15MHz
2f1-f2=-72.7dBm
@ 0.85MHz
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.8
0.9
1.0
1.1
1.2
SUPPLY VOLTAGES (±V)
FREQUENCY (MHz)
FIGURE 35. SLEW RATE vs SUPPLY VOLTAGES
FIGURE 36. THIRD ORDER IMD INTERCEPT (IP3)
FN7332 Rev 8.00
May 25, 2016
Page 11 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Typical Performance Curves (Continued)
60
55
50
45
40
35
30
Vs =±5V
25
A =+5
V
20 R =1600
F
R =100
L
15
10
C =15pF
L
1
10
100
FREQUENCY (MHz)
FIGURE 37. THIRD ORDER IMD INTERCEPT vs FREQUENCY
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1
0.8
0.6
0.4
0.2
0
1.2 1.136W
791mW
1.116W
QSOP16
SO8
=110°C/W
=158°C/W
1.087W
1
781mW
JA
JA
SO8
QSOP16
=160°C/W
0.8
JA
607mW
488mW
=112°C/W
JA
MSOP8/10
543mW
0.6
0.4
0.2
0
=206°C/W
JA
MSOP8/10
SOT23-5/6
=115°C/W
125
=256°C/W
JA
JA
SOT23-5/6
=230°C/W
JA
0
25
50
75 85 100
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7332 Rev 8.00
May 25, 2016
Page 12 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
FN7332.8
FN7332.7
CHANGE
May 25, 2016
October 20, 2015
- Updated Ordering Information Table on page 2.
- Updated Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
- POD MDP0038 obsoleted and replaced by P5.064A latest revision.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2004-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7332 Rev 8.00
May 25, 2016
Page 13 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
FN7332 Rev 8.00
May 25, 2016
Page 14 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7332 Rev 8.00
May 25, 2016
Page 15 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.08-0.20
D
A
5
4
PIN 1
INDEX AREA
2.80
3
1.60
5
3
0.15 C D
2x
(0.60)
2
0.20 C
2x
0.95
SEE DETAIL X
END VIEW
B
0.40 ±0.05
3
0.20 M C A-B D
TOP VIEW
10° TYP
(2 PLCS)
H
5
0.15 C A-B
2x
2.90
1.45 MAX
C
1.14 ±0.15
GAUGE
PLANE
(0.25)
SEATING PLANE
0.10
C
0.45±0.1
4
SIDE VIEW
0.05-0.15
(0.60)
DETAIL "X"
(1.20)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
(2.40)
2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3. Dimension is exclusive of mold flash, protrusions or gate burrs.
4. Foot length is measured at reference to guage plane.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
5.
6.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN7332 Rev 8.00
May 25, 2016
Page 16 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Quarter Size Outline Plastic Packages Family (QSOP)
A
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
A
A1
A2
b
0.068
0.006
0.056
0.010
0.008
0.193
0.236
0.154
0.025
0.025
0.041
16
0.068
0.006
0.056
0.010
0.008
0.341
0.236
0.154
0.025
0.025
0.041
24
0.068
0.006
0.056
0.010
0.008
0.390
0.236
0.154
0.025
0.025
0.041
28
Max.
±0.002
±0.004
±0.002
±0.001
±0.004
±0.008
±0.004
Basic
-
PIN #1
I.D. MARK
E
E1
-
-
-
1
(N/2)
c
-
B
D
1, 3
0.010 C A B
E
-
e
E1
e
2, 3
H
-
C
SEATING
L
±0.009
Basic
-
PLANE
L1
N
-
0.007 C A B
b
0.004 C
Reference
-
Rev. F 2/07
L1
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
FN7332 Rev 8.00
May 25, 2016
Page 17 of 18
EL5104, EL5105, EL5204, EL5205, EL5304
Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
e1
SYMBOL
MAX
0.043
0.004
0.039
0.012
0.010
0.009
0.009
0.085
0.094
0.053
MIN
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.85
1.80
1.15
MAX
1.10
0.10
1.00
0.30
0.25
0.22
0.20
2.15
2.40
1.35
NOTES
5
1
4
A
A1
A2
b
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.073
0.071
0.045
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0256 Ref
0.0512 Ref
0.010 0.018
0.65 Ref
1.30 Ref
0.26 0.46
A2
A1
A
e1
L
-
-C-
4
-
L1
L2
0.017 Ref.
0.420 Ref.
0.15 BSC
0.10 (0.004)
C
0.006 BSC
o
o
o
o
0
8
0
8
-
N
b
WITH
5
5
5
PLATING
b1
R
0.004
0.004
-
0.10
0.15
-
R1
0.010
0.25
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
L2
L1
4X 1
VIEW C
FN7332 Rev 8.00
May 25, 2016
Page 18 of 18
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