EL5306ISZ [RENESAS]
350MHz Fixed Gain Amplifiers with Enable; QSOP16, SOIC16; Temp Range: -40° to 85°C;
| 型号： | EL5306ISZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 350MHz Fixed Gain Amplifiers with Enable; QSOP16, SOIC16; Temp Range: -40° to 85°C 放大器 光电二极管 商用集成电路 |
| 文件： | 总13页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5106, EL5306
Data Sheet
June 6, 2012
FN7357.7
350MHz Fixed Gain Amplifiers with Enable
Features
The EL5106 and EL5306 are fixed gain amplifiers with a
bandwidth of 350MHz. This makes these amplifiers ideal for
today’s high speed video and monitor applications. They
feature internal gain setting resistors and can be configured
in a gain of +1, -1 or +2.
• Pb-free available (RoHS compliant)
• Gain selectable (+1, -1, +2)
• 350MHz -3dB BW (A = 2)
V
• 1.5mA supply current per amplifier
• Fast enable/disable
With a supply current of just 1.5mA and the ability to run
from a single supply voltage from 5V to 12V, these amplifiers
are also ideal for handheld, portable or battery powered
equipment.
• Single and dual supply operation, from 5V to 12V
• Available in SOT-23 packages
The EL5106 and EL5306 also incorporate an enable and
disable function to reduce the supply current to 25µA typical
per amplifier. Allowing the CE pin to float or applying a low
logic level will enable the amplifier.
• 450MHz, 3.5mA product available (EL5108 and EL5308)
Applications
• Battery powered equipment
• Handheld, portable devices
• Video amplifiers
The EL5106 is offered in the 6 Ld SOT-23 and the
industry-standard 8 Ld SOIC packages and the EL5306 is
available in the 16 Ld SOIC and 16 Ld QSOP packages. All
operate over the industrial temperature range of -40°C to
+85°C.
• Cable drivers
• RGB amplifiers
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
EL5106IWZ-T7 (Notes 1, 2)
EL5106IWZ-T7A (Notes 1, 2)
EL5106ISZ (Note 2)
BAFA (Note 3)
6 Ld SOT-23
6 Ld SOT-23
P6.064A
BAFA (Note 3)
5106ISZ
P6.064A
M8.15E
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil)
8 Ld SOIC (150 mil)
16 Ld SOIC (150 mil)
16 Ld SOIC (150 mil)
16 Ld SOIC (150 mil)
16 Ld QSOP (150 mil)
16 Ld QSOP (150 mil)
16 Ld QSOP (150 mil)
EL5106ISZ-T7 (Notes 1, 2)
EL5106ISZ-T13 (Notes 1, 2)
EL5306ISZ (Note 2)
5106ISZ
M8.15E
5106ISZ
M8.15E
EL5306ISZ
EL5306ISZ
EL5306ISZ
5306IUZ
MDP0027
MDP0027
MDP0027
MDP0040
MDP0040
MDP0040
EL5306ISZ-T7 (Notes 1, 2)
EL5306ISZ-T13 (Notes 1, 2)
EL5306IUZ (Note 2)
EL5306IUZ-T7 (Notes 1, 2)
EL5306IUZ-T13 (Notes 1, 2)
NOTES:
5306IUZ
5306IUZ
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. The part marking is located on the bottom of the part.
4. For Moisture Sensitivity Level (MSL), please see device information page for EL5106, EL5306. For more information on MSL please see tech
brief TB363.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2002-2005, 2007, 2010, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
EL5106, EL5306
Pinouts
EL5106
(8 LD SOIC)
TOP VIEW
EL5306
(16 LD SOIC, QSOP)
TOP VIEW
INA+
CEA
VS-
1
2
3
4
5
6
7
8
16 INA-
NC
IN-
CE
1
2
3
4
8
7
6
5
-
+
15 OUTA
14 VS+
VS+
OUT
NC
-
+
IN+
VS-
+
-
CEB
INB+
NC
13 OUTB
12 INB-
11 NC
EL5106
(6 LD SOT-23)
TOP VIEW
+
-
CEC
INC+
10 OUTC
9
INC-
OUT
VS-
IN+
VS+
CE
1
2
3
6
5
4
+
-
IN-
FN7357.7
June 6, 2012
2
EL5106, EL5306
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . 13.2V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
S
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . V - -0.5V to V + +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 150Ω, T = +25°C Unless Otherwise Specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
= +1
= -1
= +2
250
380
350
20
MHz
MHz
MHz
MHz
V/µs
ns
V
A
V
A
V
BW1
SR
0.1dB Bandwidth
Slew Rate
V
V
= -2.5V to +2.5V, A = +2
3000
4500
16
O
V
t
0.1% Settling Time
Input Voltage Noise
IN+ Input Current Noise
= -2.5V to +2.5V, A = 2
OUT V
S
e
2.8
nV/√Hz
pA/√Hz
%
N
i +
N
6
dG
dP
Differential Gain Error (Note 5)
Differential Phase Error (Note 5)
A
= +2
0.02
0.04
V
A
= +2
°
V
DC PERFORMANCE
V
Specified Offset Voltage
Output offset voltage including I *R term
-15
15
mV
OS
b
F
T V
Input Offset Voltage Temperature
Coefficient
Measured from T
MIN
to T
MAX
5
µV/°C
C
OS
A
Gain Error
V
= -3V to +3V, R = 150Ω
1
2.5
%
E
O
L
R , R
Internal R and R
G
325
Ω
F
G
F
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
+ Input Current
±3
±3.3
1.5
2
V
+I
7
µA
MΩ
pF
IN
IN
IN
R
C
Input Resistance
at I +
N
Input Capacitance
1
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
R = 150Ω to GND
±3.4
±3.7
60
±3.6
±3.85
100
V
V
O
L
R = 1kΩ to GND
L
I
Output Current
R = 10Ω to GND
mA
OUT
L
SUPPLY
I
I
Supply Current - Enabled (per amplifier) No load, V = 0V
IN
1.35
1.5
12
75
1.82
25
mA
µA
dB
SON
Supply Current - Disabled (per amplifier) No load, V = 0V
IN
SOFF
PSRR
Power Supply Rejection Ratio
DC, V = ±4.75V to ±5.25V
S
FN7357.7
June 6, 2012
3
EL5106, EL5306
Electrical Specifications V + = +5V, V - = -5V, R = 150Ω, T = +25°C Unless Otherwise Specified. (Continued)
S
S
L
A
PARAMETER
ENABLE
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
t
t
I
I
Enable Time
Disable Time
280
400
5
ns
ns
µA
µA
V
EN
DIS
CE Pin Input High Current
CE Pin Input Low Current
CE = V +
1
25
-1
IHCE
ILCE
S
CE = V -
+1
0
S
V
V
CE Input High Voltage for Power-down
CE Input Low Voltage for Enable
V + -1
S
IHCE
ILCE
V + -3
V
S
NOTE:
5. Standard NTSC test, AC signal amplitude = 286mV , f = 3.58MHz
P-P
Pin Descriptions
EL5306
EL5106
(SO8)
EL5106
(SOT23-6)
(SO16,
QSOP16)
PIN
NAME
FUNCTION
Not connected
EQUIVALENT CIRCUIT
1, 5
2
6, 11
NC
4
9, 12, 16
IN-
INC-, INB-,
INA-
Inverting input
R
G
IN+
IN-
R
F
CIRCUIT 1
3
3
1, 5, 8
IN+
INA+, INB+,
INC+
Non-inverting input
(Reference Circuit 1)
4
6
2
1
3
VS-
Negative supply
Output
10, 13, 15
OUT
OUTC,
OUTB,
OUTA
OUT
R
F
CIRCUIT 2
7
8
6
5
14
VS+
Positive supply
Chip enable
2, 4, 7
CE,
CEA,
CEB,
CEC
V +
S
CE
V -
S
CIRCUIT 3
FN7357.7
June 6, 2012
4
EL5106, EL5306
Typical Performance Curves
5
11
9
A
= +2
= ±5V
= 150Ω
V
R
= ±5V
= 150Ω
V
S
L
C
= 10pF
L
V
S
R
L
3
1
C
= 6.8pF
L
7
5
3
1
A
= -1
V
C
= 2.2pF
L
-1
-3
-5
A = 2
V
C
= 0pF
L
A
= 1
V
100k
1M
10M
FREQUENCY (Hz)
1G
100k
1M
10M
FREQUENCY (Hz)
1G
100M
100M
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS C
L
FIGURE 1. FREQUENCY RESPONSE
1.6
1.2
0.8
0.4
0
450
R
= 150Ω
L
R
= 150Ω
L
A
= -1
V
A
= -1
= 2
V
350
250
150
A
= 1, 2
V
A
V
A
= 1
V
1
10
100
1k
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. GROUP DELAY vs FREQUENCY
FIGURE 4. BANDWIDTH vs SUPPLY VOLTAGE
0
-10
-20
1
R
= 150Ω
L
0.8
0.6
0.4
0.2
0
A
= -1
= 2
V
-30
-40
-50
-60
-70
-80
PSRR+
A
V
PSRR-
A
= 1
V
1k
10k
100k
1M
10M
100M
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0
FREQUENCY (Hz)
V
(V)
S
FIGURE 5. PEAKING vs SUPPLY VOLTAGE
FIGURE 6. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FN7357.7
June 6, 2012
5
EL5106, EL5306
Typical Performance Curves (Continued)
100
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
I -
S
10
I +
S
1
0.1
10k
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0
100k
1M
100M
10M
FREQUENCY (Hz)
V
S
(V)
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE (PER
AMPLIFIER)
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
0
V
= ±5V
= 2
= 150Ω
S
-10
-20
-30
-40
-50
-60
-70
-80
-90
A
M=100ns
V
R
V
L
= 2V
OP-P
HD3
HD2
CH1 2.00V/DIV
CH2 1.00V/DIV
0M
10M
20M
30M
40M
50M
60M
FREQUENCY (Hz)
FIGURE 9. HARMONIC DISTORTION vs FREQUENCY
FIGURE 10. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0
909mW
0.9
SO16 (0.150”)
M=100ns
θ
= +110°C/W
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
JA
CH1 2.00V/DIV
625mW
633mW
SO8
θ
= +160°C/W
JA
391mW
QSOP16
SOT23-6
= +256°C/W
CH2 1.00V/DIV
θ
= +158°C/W
JA
θ
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 11. DISABLED RESPONSE
FN7357.7
June 6, 2012
6
EL5106, EL5306
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1.0
0.8
0.6
0.4
1.250W
SO16 (0.150”)
θ
= +80°C/W
JA
909mW
893mW
SO8
θ
θ
= +110°C/W
JA
435mW
SOT23-6
= +230°C/W
QSOP16
= +112°C/W
θ
0.2
0.1
0
JA
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
the positive supply. For ±5V supply, this means that the
Applications Information
amplifier will be enabled when CE is 2V or less, and disabled
when CE is above 4V. Although the logic levels are not
standard TTL, this choice of logic voltages allow the EL5106
and EL5306 to be enabled by tying CE to ground, even in 5V
single supply applications. The CE pin can be driven from
CMOS outputs.
Product Description
The EL5106 and EL5306 are fixed gain amplifier that offers
a wide -3dB bandwidth of 350MHz and a low supply current
of 1.5mA. They work with supply voltages ranging from a
single 5V to 12V and they are also capable of swinging to
within 1.2V of either supply on the output. These
combinations of high bandwidth and low power make the
EL5106 and EL5306 the ideal choice for many
low-power/high-bandwidth applications such as portable,
handheld, or battery-powered equipment.
Gain Setting
The EL5106 and EL5306 are built with internal feedback and
gain resistors. The internal feedback resistors have equal
value; as a result, the amplifier can be configured into gain of
+1, -1, and +2 without any external resistors. Figure 14
shows the amplifier in gain of +2 configuration. The gain
error is ±2% maximum. Figure 15 shows the amplifier in gain
of -1 configuration. For gain of +1, IN+ and IN- should be
connected together as shown in Figure 16. This
configuration avoids the effects of any parasitic capacitance
on the IN- pin. Since the internal feedback and gain resistors
change with temperature and process, external resistor
should not be used to adjust the gain settings.
For varying bandwidth and higher gains, consider the
EL5191 with 1GHz on a 9mA supply current or the EL5162
with 300MHz on a 4mA supply current. Versions include
single, dual, and triple amp packages with 5 Ld SOT-23,
16 Ld QSOP, and 8 Ld SOIC or 16 Ld SOIC outlines.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Low
impedance ground plane construction is essential. Surface
mount components are recommended, but if leaded
components are used, lead lengths should be as short as
possible. The power supply pins must be well bypassed to
reduce the risk of oscillation. The combination of a 4.7µF
tantalum capacitor in parallel with a 0.01µF capacitor has
been shown to work well when placed at each supply pin.
325Ω
325Ω
IN-
-
IN+
+
FIGURE 14. A = +2
V
Disable/Power-Down
The EL5106 and EL5306 amplifiers can be disabled placing
their output in a high impedance state. When disabled, the
amplifier supply current is reduced to <25µA. The EL5106
and EL5306 are disabled when its CE pin is pulled up to
within 1V of the positive supply. Similarly, the amplifier is
enabled by floating or pulling the CE pin to at least 3V below
FN7357.7
June 6, 2012
7
EL5106, EL5306
325Ω
325Ω
325Ω
+5
IN-
-
IN+
+
325Ω
FIGURE 15. A = -1
V
-
V
OUT
+5
+
0.1µF
1k
1k
325Ω
0.1µF
IN- 325Ω
V
IN
-
+
IN+
FIGURE 17.
FIGURE 16. A = +1
V
Video Performance
Supply Voltage Range and Single-Supply
Operation
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. Previously, good differential gain could only be
achieved by running high idle currents through the output
transistors (to reduce variations in output impedance).
Special circuitries have been incorporated in the EL5106 and
EL5306 to reduce the variation of output impedance with
current output. This results in dG and dP specifications of
0.02% and 0.04°, while driving 150Ω at a gain of 2.
The EL5106 and EL5306 have been designed to operate
with supply voltages having a span of greater than or equal
to 5V and less than 11V. In practical terms, this means that
the EL5106 and EL5306 will operate on dual supplies
ranging from ±2.5V to ±5V. With single-supply, the EL5106
and EL5306 will operate from 5V to 10V.
As supply voltages continue to decrease, it becomes
necessary to provide input and output voltage ranges that
can get as close as possible to the supply voltages. The
EL5106 and EL5306 have an input range which extends to
within 2V of either supply. So, for example, on ±5V supplies,
the EL5106 and EL5306 have an input range which spans
±3V. The output range is also quite large, extending to within
1V of the supply rail. On a ±5V supply, the output is therefore
capable of swinging from -4V to +4V. Single-supply output
range is larger because of the increased negative swing due
to the external pull-down resistor to ground. Figure 16 shows
an AC-coupled, gain of +2, +5V single supply circuit
configuration.
Output Drive Capability
In spite of its low 1.5mA of supply current per amplifier, the
EL5106 and EL5306 are capable of providing a maximum of
±125mA of output current.
Driving Cables and Capacitive Loads
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, the back-termination series resistor will
decouple the EL5106 and EL5306 from the cable and allow
extensive capacitive drive. However, other applications may
have high capacitive loads without a back-termination
resistor. In these applications, a small series resistor (usually
between 5Ω and 50Ω) can be placed in series with the
output to eliminate most peaking.
FN7357.7
June 6, 2012
8
EL5106, EL5306
where:
Current Limiting
The EL5106 and EL5306 have no internal current-limiting
circuitry. If the output is shorted, it is possible to exceed the
Absolute Maximum Rating for output current or power
dissipation, potentially resulting in the destruction of the
device.
T
= Maximum ambient temperature
MAX
θ
= Thermal resistance of the package
JA
n = Number of amplifiers in the package
PD = Maximum power dissipation of each amplifier in
MAX
the package
Power Dissipation
With the high output drive capability of the EL5106 and
EL5306, it is possible to exceed the +125°C Absolute
Maximum junction temperature under certain very high load
PD
Equation 2:
for each amplifier can be calculated as shown in
MAX
current conditions. Generally speaking when R falls below
about 25Ω, it is important to calculate the maximum junction
V
L
OUTMAX
R
L
----------------------------
PD
= (2 × V × I
) + (V - V ) ×
OUTMAX
MAX
S
SMAX
S
temperature (T
) for the application to determine if
JMAX
(EQ. 2)
power supply voltages, load conditions, or package type
need to be modified for the EL5106 and EL5306 to remain in
the safe operating area. These parameters are calculated as
shown in Equation 1:
where:
V = Supply voltage
S
I
= Maximum bias supply current
SMAX
(EQ. 1)
T
= T
+ (θ × n × PD
)
MAX
JMAX
MAX
JA
V
= Maximum output voltage (required)
OUTMAX
R = Load resistance
L
Revision History
DATE
REVISION
CHANGE
April 25, 2012
FN7357.7
Removed obsolete part EL5106IS from “Order Information” page 1.
Corrected Pkg Dwg # in “Order Information” page 1 for EL5306ISZ parts from M8.15E to
MDP0027.
Added MSL note (Note 4 on page 1).
Changed Min/Max limits for “VOS” on page 3 from -10/10mV to -15/15mV. Added “Output
offset voltage including I *R term” to conditions column. Changed Description from “Offset
b
F
Voltage” to “Specified Offset Voltage”.
Added package outline drawing MDP0027 to page 13.
June 4, 2009
FN7357.6
Removed obsolete, leaded devices EL5106IW-T7, EL5106IW-T7A; EL5106IS-T7, EL5106IS-
T13; EL5306IS, EL5306IS-T7, EL5306IS-T13; EL5306IU, EL5306IU-T7, EL5306IU-T13
Corrected Figure references in “Gain Setting” on page 7 (Fig 14 callout was referencing Fig
13; Fig 15 callout was referencing Fig 14; Fig 16 callout was referencing Fig 15) .
Updated pin descriptions to match pin names of EL5306.
Applied Intersil Standards: Updated Pb-free bullet in Features, Updated ordering information
by removing tape and reel column and adding standard reference note and updating note to
match lead finish, updated caution statement to legal's suggested verbiage. Changed date
and Rev'd to 6.
Updated Package Outline Drawing MDP0038 toP6.064A - P6.064A replaces 6 Ld SOT-23
(same dimensions, just MDP0038 had both 5 & 6 Ld SOT23s w/dimensions listed in table)
Updated Package Outline Drawing MDP0027 to M8.15E - M8.15E replaces MDP0027 8 Ld
SOIC (same dimensions, just MDP0027 had 8, 14, 16, 20, 24, 28 Ld SOICS with dimensions
listed in table)
P1, added Note 3 "The part marking is located on the bottom of the part" for SOT-23 package
Added Revision History table.
FN7357.7
June 6, 2012
9
EL5106, EL5306
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN7357.7
June 6, 2012
10
EL5106, EL5306
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.08-0.20
0.95
D
A
6
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
5
0.15 C D
2x
(0.60)
1
2
3
0.20
2x
C
SEE DETAIL X
END VIEW
0.40 ±0.05
0.20 M
3
A-B
B
C
D
TOP VIEW
10° TYP
(2 PLCS)
5
0.15 C A-B
2x
2.90
H
1.14 ±0.15
1.45 MAX
C
GAUGE
PLANE
(0.25)
0.10
C
SEATING PLANE
0.05-0.15
(0.60)
SIDE VIEW
DETAIL "X"
0.45±0.1
4
(1.20)
NOTES:
(2.40)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3. Dimension is exclusive of mold flash, protrusions or gate burrs.
4. Foot length is measured at reference to guage plane.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
5.
6.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN7357.7
June 6, 2012
11
EL5106, EL5306
Quarter Size Outline Plastic Packages Family (QSOP)
A
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
A
A1
A2
b
0.068
0.006
0.056
0.010
0.008
0.193
0.236
0.154
0.025
0.025
0.041
16
0.068
0.006
0.056
0.010
0.008
0.341
0.236
0.154
0.025
0.025
0.041
24
0.068
0.006
0.056
0.010
0.008
0.390
0.236
0.154
0.025
0.025
0.041
28
Max.
±0.002
±0.004
±0.002
±0.001
±0.004
±0.008
±0.004
Basic
-
PIN #1
I.D. MARK
E
E1
-
-
-
1
(N/2)
c
-
B
D
1, 3
0.010 C A B
E
-
e
E1
e
2, 3
H
-
C
SEATING
L
±0.009
Basic
-
PLANE
L1
N
-
0.007 C A B
b
0.004 C
Reference
-
Rev. F 2/07
L1
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7357.7
June 6, 2012
12
EL5106, EL5306
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24 (SOL- SO28 (SOL-
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
24)
28)
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
-
±0.002
-
±0.003
-
c
±0.001
-
D
E
±0.004
1, 3
±0.008
-
E1
e
±0.004
2, 3
Basic
-
L
±0.009
-
L1
h
Basic
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7357.7
June 6, 2012
13
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