F0440NBGI8 [RENESAS]
Dual Matched Broadband RF DVGA 450MHz to 2700MHz;
| 型号： | F0440NBGI8 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Matched Broadband RF DVGA 450MHz to 2700MHz |
| 文件： | 总31页 (文件大小：2991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
F0440
Dual Matched Broadband RF
DVGA 450MHz to 2700MHz
Datasheet
Description
Features
This document describes the specifications for the F0440
450MHz to 2700MHz Dual RF Digital Variable Gain Amplifier
designed for use in receivers.
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Dual Path RF amp & DSAs for Diversity / MIMO Receivers
RF: 450MHz to 2700MHz
< 2dB overshoot between DSA transitions
11.6dB typical max gain @ 900MHz
DSA0 is a single 6dB coarse step
DSA1 has 23dB total gain range in 1dB steps
DSA2 has 18dB gain range in 6dB steps
+41dBm OIP3 @ 2000MHz
4.7dB Noise Figure @ 900MHz
+5V Supply Voltage
ICC = 245mA
F0440 Dual RF DVGA provides two independent receiver paths
each with 11.6dB typical maximum gain and 4.7dB noise figure in
the low-band configuration designed to operate with a single +5V
supply. For each path Gain control is split into 3 separate
attenuators; DSA0 is a single 6dB step using a single control pin,
DSA1 includes 23dB SPI-controlled gain adjustment in 1dB steps,
and DSA2 includes 18dB attenuation in 6dB steps controlled
using two control pins. F0440 offers +40dBm nominal output IP3
using 245mA total ICC.
Independent standby: 7mA standby current
SPI interface for DSA1
1-bit control for DSA0
This device is packaged in a 6mm x 6mm, 36-pin TQFN with 50
ohm single-ended RF input and RF output impedances for ease
of integration into the signal-path lineup for each of the two paths.
2-bit control for DSA2
Competitive Advantage
50 Ω input and output impedance
Broadband, Internally Matched
6mm x 6mm, 36-pin TQFN package
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High Reliability
High Linearity
Low DC current
Zero DistortionTM technology
GlitchFreeTM technology
Block Diagram
Figure 1. Block Diagram
Typical Applications
F0440
6dB
23dB
18dB
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Multi-mode, Multi-carrier Receivers
PCS1900 Base Stations
RFOUT_A
RFIN_A
SPI Data
SPI CSb
DSA0
DSA1
DSA2
RF AMP
DCS1800 Base Stations
2
SPI CLK
Decode
Logic / Bias
WiMAX and LTE Base Stations
UMTS/WCDMA 3G Base Stations
PHS/PAS Base Stations
Distributed Antenna Systems
Digital Radio
VCTRL0
VCTRL1
VCTRL2
2
2
2
2
STBY
RFIN_B
RFOUT_B
6mm x 6mm
Table 1. Typical Band Performance Summary
RF Frequency (MHz)
900
2000
2700
Max Gain (dB)
NF @ max gain (dB)
OIP3 @ max gain (dBm)
OP1dB @ max gain (dBm)
DC current (mA)
11.6
4.7
+40
+20.2
245
11.4
4.9
+41
+19.8
245
11.6
5.2
+38
+18.9
245
Power Dissipation (mW)
1225
1225
1225
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Pin Assignments
Figure 2. Pin Assignments for 6 x 6 mm 36-TQFN Package – Top View
36
35
34
33
32
31
30
29
28
F0440
DSA0_A
DSA1_A
DSA2_A
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
RFout_A
RFin_A
GND
NC
VCTRL0_A
VCC
Rset
SPI Data
SPI Clk
Decode
Logic
Bias
Control
VCC
RDset
VCC
VCC
VCTRL0_B
GND
NC
RFin_B
RFout_B
DSA2_B
DSA0_B
DSA1_B
10
11
12
13
14
15
16
17
18
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Pin Descriptions
Table 2. Pin Descriptions
Number
Name
Description
1
RFin_A
RF Path A input internally matched to 50 Ω. Must use external DC block.
2, 8, 15, 16,
17, 29, 30,
31
GND
Ground these pins.
3
VCTRL0_A 1bit DSA0 6dB attenuator control for path A
SPI Data[a] Data input: 3.3V or 1.8V CMOS compatible.
4
5
SPI Clk[a]
VCC
Clock input: 3.3V or 1.8V CMOS compatible.
6, 21, 23, 25
+5V Power Supply. Use bypass capacitors as close to pin as possible.
7
9
VCTRL0_B 1bit DSA0 6dB attenuator control for path B
RFin_B
NC
RF Path B input internally matched to 50 Ω. Must use external DC block.
No internal connection. Can be either left open or connected to GND (recommended)
10, 18, 20,
26, 28, 36
11
SPI CSb_B[a] Chip Select bar input path B: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data.
Standby (Low/Open = device power ON, High = device power OFF with SPI still powered ON). A pull-
down resistor connects between input and GND.
12
STBY_B
13
14
19
22
24
27
32
33
VCTRL1_B See separate attenuation logic table for Path B DSA2.
VCTRL2_B See separate attenuation logic table for Path B DSA2.
RFout_B
RDset
RF output Path B. Use external DC block as close to the pin as possible.
Connect external resistor to GND to optimize amplifier bias. Used with pin 24.
Connect external resistor to GND to optimize amplifier bias. Used with pin 22.
RF output Path A. Use external DC block as close to the pin as possible.
Rset
RFout_A
VCTRL2_A See separate attenuation logic table for Path A DSA2.
VCTRL1_A See separate attenuation logic table for Path A DSA2.
Standby (Low/Open = device power ON, High = device power OFF with SPI still powered ON). A pull-
down resistor connects between input and GND.
SPI CSb_A[a] Chip Select bar input path A: 3.3V or 1.8V CMOS compatible. Logic LOW shifts data.
34
35
STBY_A
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple
ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground
— EP
vias are also required to achieve the noted RF performance.
a. See Serial Control Word section for description.
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F0440 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VCC to GND
VCC
-0.3
+5.5
V
SPI Data, SPI CSb_A, CSb_B, SPI Clk, VCTRL0_A,
VCTRL0_B
Minimum
( VCC, 3.6 )
VCtrl1
VCtrl2
-0.3
-0.3
V
V
STBY_A, STBY_B, VCTRL1_A, VCTRL1_B,
VCTRL2_A, VCTRL2_B
VCC + 0.25
RDset
IR1
IR2
+1.5
+0.8
+3.6
+3.6
mA
mA
V
Rset
RFin_A, RFin_B externally applied DC voltage
RFout_A, RFout_B, externally applied DC voltage
VRFin
VRFout
+1.4
+1.4
V
RF Input Power (RFin_A, RFin_B) applied for 24 hours
maximum[a]
Pin1
+22
dBm
Continuous Power Dissipation
Junction Temperature
Pdiss
Tj
1.5
150
150
260
W
°C
°C
°C
Storage Temperature Range
Lead Temperature (soldering, 10s)
Tst
-65
ElectroStatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
Class 1C
(1500 V)
ElectroStatic Discharge – CDM
(JEDEC 22-C101F)
Class C3
(1000 V)
a. Exposure to these maximum RF levels can result in significant Vcc current draw due to
overdriving the amplifier stages.
Recommended Operating Conditions
Table 4. Recommended Operating Conditions
Parameter
Supply Voltage(s)
Symbol
VCC
Condition
All VCC pins
Minimum
4.75
Typical
Maximum
5.25
Units
V
Operating Temperature Range
RF Frequency Range
TCASE
FRF
Exposed Paddle Temperature
Operating Range
Single Ended
-40
+105
°C
MHz
Ω
450
2700
RF Source Impedance
RF Load Impedance
ZRFI
50
50
ZRFO
Single Ended
Ω
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Electrical Characteristics
Table 5. Electrical Characteristics
See F0440 Typical Application Circuit. VCC = +5V, TC = +25 °C, Specifications apply operated as a dual-path RF DVGA unless otherwise
noted, Max gain setting, output power = 0dBm, ZRFI = ZRFO = 50 Ω, unless otherwise noted.
Parameter
Logic Input High
Symbol
VIH
Condition
Minimum
Typical
Maximum
Units
1.1 [a]
These apply for 5V, 3.3V, and 1.8V
logic levels
V
Logic Input Low
VIL
0.63
127[b]
87
5V logic
-5
-5
-5
-5
-5
STBY_A, STBY_B
3.3V logic
1.8V logic
3.3V logic
1.8V logic
Logic Current (per pin)
IIH, IIL
47
μA
5
SPI_, VCTRL0,
VCTRL1, VCTRL2
5
ICC_LB
ICC_MB
ICC_HB
Low Band Configuration
Mid Band Configuration
High Band Configuration
Standby Mode[c]
245
245
245
7
270
14
Supply Current
Startup time
mA
ns
ICC_STBY
50% of STBY going low to Gain
within ± 1 dB with no attenuation.
Tstart
74
DSA0 adjust range / step
DSA1 adjustment range
DSA1 step
GSTEP0
GADJ1
6
23
1
dB
dB
dB
dB
dB
dB
GSTEP1
GADJ2
DSA2 adjustment range
DSA2 step
18
6
GSTEP2
ATTNG
Max Attenuation Glitch
2
50% CTL to within 0.1dB final value,
0 dB state to 6 dB state
ATT0_SW_0to6
ATT0_SW_6to1
ATT2_SW_0to18
ATT2_SW_18to0
DSA1ST
24
18
35
35
35
35
ns
ns
ns
ns
ns
ns
DSA0 Gain Settling Time [d]
50% CTL to within 0.1dB final value,
6 dB state to 0 dB state
50% CTL to within 0.1dB final value,
0 dB state to 18 dB state
16
DSA2 Gain Settling Time
DSA1 Gain Settling Time
50% CTL to within 0.1dB final value,
18 dB state to 0 dB state
15
50% of CSb to within 0.1dB final
value
300
16
50% CTL to within 1 degree of final
value, 0 dB state to 18 dB state
ATT2_PH_0to18
35
35
DSA2 Phase Settling Time
Stability K factor
50% CTL to within 1 degree of final
value, 18 dB state to 0 dB state
ATT2_PH_18to0
KFACT
15
ns
Over entire temperature range
1.4
unit
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Serial Clock Speed
SPICLK
10
MHz
CSb_A, CSb_B to first serial
clock rising edge
SPI 3 wire Bus. 50% of CSb falling
edge to 50% of CLK rising edge.
A
10
10
10
ns
ns
ns
ns
ns
SPI 3 wire Bus. 50% of CLK rising
edge to 50% of Data falling edge.
Serial Data Hold Time
B
Final serial clock rising edge to
CSb
SPI 3 wire Bus. 50% of CLK rising
edge to 50% of CSb rising edge.
C
50% CTL to within 1 degree of final
value, 0 dB state to 6 dB state
ATT0_PH_0to6
ATT0_PH_6to0
24
18
35
35
DSA0 Phase Settling Time
50% CTL to within 1 degree of final
value, 6 dB state to 0 dB state
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up.
d. Time for the gain to settle within ± 0.1 dB and relative to SPI command latch.
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Table 6. Electrical Characteristics – 450MHz Performance
See F0440 Typical Application Circuit. Specifications apply operated as a dual-path RF DVGA unless otherwise noted, VCC = +5V,
TC = +25 °C, FRF = 450MHz, Max gain setting, output power = 0dBm / tone, ZRFI = ZRFO = 50 Ω, the evaluation board and connector losses
are de-embedded, unless otherwise noted.
Parameter
RF input return loss
Symbol
RLIN_450
RLOut_450
GMAX_450
GMIN_450
GTEMP_450
Condition
Minimum
Typical
11
Maximum
Units
dB
RF output return loss
14.5
11
dB
Gain
Maximum attenuation
-35
dB
Variation over Temperature
0.7
DSA0 Absolute Error
DSA1 Step Error
GDSA0SE_450 Relative to maximum gain
GDSA1SE_450 Between adjacent states
GDSA1ABS_450 Relative to maximum gain
GDSA2SE_450 Between adjacent states
GDSA2ABS_450 Relative to maximum gain
GPH_DSA0_450
± 0.07
± 0.05
± 0.15
± 0.11
± 0.25
1.7
dB
dB
DSA1 Absolute Error
DSA2 Step Error
dB
dB
DSA2 Absolute Error
Relative Phase DSA0
Phase Deviation DSA1
Relative Phase DSA2
dB
Deg
Deg
Deg
GPH_DSA1_450 Between adjacent states
GPH_ DSA2_450 Between any two states
NF450
0.16
7.7
5
Noise Figure
NF450_HOT
NF450_RG
Tcase = +105 °C
5.7
dB
DSA1 22dB attenuation
27.7
38
OIP3_450-1 1 MHz tone separation
1 MHz tone separation
OIP3_450-2
35
38
37
Pout = -10dBm/tone
1 MHz tone separation
OIP3_450-6dB
dBm
DSA0 full attenuation
Output Third Order Intercept Point
1 MHz tone separation
OIP3_450-3
Worst case over temp range
Pout = -18dBm / tone
OIP3_450_18dB 1 MHz tone separation
DSA2 full 18dB attenuation
20
Input 1dB Compression d
Output 1dB Compression
IP1dB_450
Full attenuation
30
dBm
dBm
OP1dB_450
19.4
OP1dB_DEG450
=
Output 1dB Compression
Degradation
OP1dB450(DSA2 =0dB atten)
- ATTN450_DSA2_MAX
OP1_DEG_450
0.4
dB
- OP1dB450(DSA2=max atten)
Output 0.2dB Compression
Output Saturated Power
OP0.2dB_450
PSAT_450
18.2
20.1
dBm
dBm
3 dB compression
7
© 2020 Renesas Electronics Corporation
August 13, 2020
F0440 Datasheet
Parameter
Reverse Isolation
Symbol
Condition
Minimum
Typical
Maximum
Units
REVISO_450
21
dB
RFOUT_B vs. RFOUT_A w/
signal applied to RFIN_A
39
39
Path Isolation
PATHISO_450
dB
Same gain settings over PVT
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Including frequency and ripple variations valid within each individual 3GPP band
d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Table 7. Electrical Characteristics – Lowband Performance
See F0440 Typical Application Circuit. Specifications apply operated as a dual-path RF DVGA unless otherwise noted, VCC = +5V,
TC = +25 °C, FRF = 900MHz, Max gain setting, output power = 0dBm / tone, ZRFI = ZRFO = 50 Ω, the evaluation board and connector losses
are de-embedded, unless otherwise noted.
Parameter
RF input return loss
Symbol
RLIN_LB
Condition
Minimum
Typical
16
Maximum
Units
dB
RF output return loss
RLOut_LB
GMAX_LB
GMIN_LB
GTEMP_LB
GVAR_LB
20
dB
10.9
11.6
-34.9
0.6
12.2
Maximum attenuation
-36.4
-33.4
Gain
dB
Variation over Temperature
Variation over frequency[c]
0.1
DSA0 Absolute Error
DSA1 Step Error
GDSA0SE_LB Relative to maximum gain
GDSA1SE_LB Between adjacent states
GDSA1ABS_LB Relative to maximum gain
GDSA2SE_LB Between adjacent states
GDSA2ABS_LB Relative to maximum gain
GPH_DSA0_LB
± 0.2
± 0.03
± 0.35
± 0.03
± 0.06
0.7
dB
dB
DSA1 Absolute Error
DSA2 Step Error
dB
dB
DSA2 Absolute Error
Relative Phase DSA0
Phase Deviation DSA1
Relative Phase DSA2
dB
Deg
Deg
Deg
GPH_DSA1_LB Between adjacent states
GPH_ DSA2_LB Between any two states
NFLB
0.26
2.5
4.7
Noise Figure
NFLB_HOT
NFLB_RG
OIP3_LB-1
Tcase = +105 °C
5.4
dB
DSA1 22dB attenuation
1 MHz tone separation
27
38.5
38
40
1 MHz tone separation
Pout = -10dBm/tone
OIP3_LB-2
OIP3_LB-6dB
OIP3_LB-3
39
40
39
1 MHz tone separation
DSA0 full attenuation
dBm
Output Third Order Intercept Point
1 MHz tone separation
Worst case over temp range
Pout = -18dBm / tone
OIP3_LB_18dB 1 MHz tone separation
22
DSA2 full 18dB attenuation
Input 1dB Compression d
Output 1dB Compression
IP1dB_LB
Full attenuation
27
dBm
dBm
OP1dB_LB
18.4
20.2
OP1dB_DEGLB=
Output 1dB Compression
Degradation
OP1dBLB(DSA2 =0dB atten)
- ATTNLB_DSA2_MAX
OP1_DEG_LB
0.05
0.5
dB
- OP1dBLB(DSA2=max atten)
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Parameter
Output 0.2dB Compression
Output Saturated Power
Reverse Isolation
Symbol
OP0.2dB_LB
PSAT_LB
Condition
Minimum
Typical
18.7
Maximum
Units
dBm
dBm
dB
3 dB compression
20.9
REVISO_LB
20
43
20.5
RFOUT_B vs. RFOUT_A w/
signal applied to RFIN_A
45
45
Path Isolation
PATHISO_LB
dB
Same gain settings over PVT
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Including frequency and ripple variations valid within each individual 3GPP band
d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Table 8. Electrical Characteristics – Midband Performance
See F0440 Typical Application Circuit. Specifications apply operated as a dual-path RF DVGA unless otherwise noted, VCC = +5V, TC =
+25 °C, FRF = 2000MHz, Max gain setting, output power = 0dBm / tone, ZRFI = ZRFO = 50 Ω, the evaluation board and connector losses are
de-embedded, unless otherwise noted.
Parameter
RF input return loss
Symbol
RLIN_MB
RLOut_MB
GMAX_MB
GMIN_MB
GTEMP_MB
GVAR_MB
Condition
Minimum
Typical
20
Maximum
Units
dB
RF output return loss
20
dB
10.6
11.6
-35.3
0.4
12.3
Maximum attenuation
-37.0
-33.5
Gain
dB
Variation over Temperature
Variation over frequency[c]
0.02
± 0.05
± 0.03
± 0.1
± 0.075
± 0.15
2.9
DSA0 Absolute Error
DSA1 Step Error
GDSA0SE_MB Relative to maximum gain
GDSA1SE_MB Between adjacent states
GDSA1ABS_MB Relative to maximum gain
GDSA2SE_MB Between adjacent states
GDSA2ABS_MB Relative to maximum gain
GPH_DSA0_MB
dB
dB
DSA1 Absolute Error
DSA2 Step Error
-0.6
0.6
dB
dB
DSA2 Absolute Error
Relative Phase DSA0
Phase Deviation DSA1
Relative Phase DSA2
dB
Deg
Deg
Deg
GPH_DSA1_MB Between adjacent states
GPH_ DSA2_MB Any State
0.88
10
NFMB
4.9
Noise Figure
NFMB_HOT
NFMB_RG
OIP3_MB-1
Tcase = +105 °C
5.6
dB
DSA1 22dB attenuation
1 MHz tone separation
27
37.5
37.5
41
1 MHz tone separation
Pout = -10dBm/tone
OIP3_MB-2
OIP3_MB-6dB
OIP3_MB-3
40.5
41
1 MHz tone separation
DSA0 full attenuation
dBm
Output Third Order Intercept Point
1 MHz tone separation
Worst case over temp range
39.5
Pout = -18dBm / tone
OIP3_MB_18dB 1 MHz tone separation
21
DSA2 full 18dB attenuation
Input 1dB Compression d
Output 1dB Compression
IP1dB_MB
Full attenuation
29
dBm
dBm
OP1dB_MB
19.8
OP1dB_DEGMB=
Output 1dB Compression
Degradation
OP1dBMB(DSA2 =0dB atten)
- ATTNMB_DSA2_MAX
OP1_DEG_MB
0.1
0.5
dB
- OP1dBMB(DSA2=max atten)
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Parameter
Output 0.2dB Compression
Output Saturated Power
Reverse Isolation
Symbol
OP0.2dB_MB
PSAT_MB
Condition
Minimum
Typical
18.8
Maximum
Units
dBm
dBm
dB
3 dB compression
20.5
REVISO_MB
20
44
20.5
RFOUT_B vs. RFOUT_A w/
signal applied to RFIN_A
45
45
Path Isolation
PATHISO_MB
dB
Same gain settings over PVT
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Including frequency and ripple variations valid within each individual 3GPP band
d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Table 9. Electrical Characteristics – Highband Performance
See F0440 Typical Application Circuit. Specifications apply operated as a dual-path RF DVGA unless otherwise noted, VCC = +5V, TC =
+25 °C, FRF = 2700MHz, Max gain setting, output power = 0dBm / tone, ZRFI = ZRFO = 50 Ω, the evaluation board and connector losses are
de-embedded, unless otherwise noted.
Parameter
RF input return loss
Symbol
RLIN_HB
RLOut_HB
GMAX_HB
GMIN_HB
GTEMP_HB
GVAR_HB
Condition
Minimum
Typical
20
Maximum
Units
dB
RF output return loss
20
dB
10.6
11.6
-35.4
0.32
0.05
± 0.2
± 0.04
± 0.23
± 0.11
± 0.24
4.1
12.6
Maximum attenuation
-37.0
-33.7
Gain
dB
Variation over Temperature
Variation over frequency[c]
DSA0 Absolute Error
DSA1 Step Error
GDSA0SE_HB Relative to maximum gain
GDSA1SE_HB Between adjacent states
GDSA1ABS_HB Relative to maximum gain
GDSA2SE_HB Between adjacent states
GDSA2ABS_HB Relative to maximum gain
GPH_DSA0_HB
dB
dB
DSA1 Absolute Error
DSA2 Step Error
dB
dB
DSA2 Absolute Error
Relative Phase DSA0
Phase Deviation DSA1
Relative Phase DSA2
dB
Deg
Deg
Deg
GPH_DSA1_HB Between adjacent states
GPH_ DSA2_HB Any State
1.27
16
NFHB
5.2
Noise Figure
NFHB_HOT
NFHB_RG
OIP3_HB-1
Tcase = +105 °C
5.9
dB
DSA1 22dB attenuation
1 MHz tone separation
28
35.2
34
38
1 MHz tone separation
Pout = -10dBm/tone
OIP3_HB-2
OIP3_HB-6dB
OIP3_HB-3
37
38
37
1 MHz tone separation
DSA0 full attenuation
dBm
Output Third Order Intercept Point
1 MHz tone separation
Worst case over temp range
34
Pout = -18dBm / tone
OIP3_HB_18dB 1 MHz tone separation
19
DSA2 full 18dB attenuation
Input 1dB Compression d
Output 1dB Compression
IP1dB_HB
Full attenuation
24
dBm
dBm
OP1dB_HB
18.9
OP1dB_DEGHB=
Output 1dB Compression
Degradation
OP1dBHB(DSA2 =0dB atten)
- ATTNHB_DSA2_MAX
OP1_DEG_HB
0.3
0.5
dB
- OP1dBHB(DSA2=max atten)
© 2020 Renesas Electronics Corporation
13
August 13, 2020
F0440 Datasheet
Parameter
Output 0.2dB Compression
Output Saturated Power
Reverse Isolation
Symbol
OP0.2dB_HB
PSAT_HB
Condition
Minimum
Typical
18.2
Maximum
Units
dBm
dBm
dB
3 dB compression
19.4
REVISO_HB
19
42
20.5
RFOUT_B vs. RFOUT_A w/
signal applied to RFIN_A
44
43
Path Isolation
PATHISO_HB
dB
Same gain settings over PVT
a. Items in min/max columns in bold italics are Guaranteed by Test.
b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.
c. Including frequency and ripple variations valid within each individual 3GPP band
d. Input 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power
Thermal Characteristics
Table 10. Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance.
θJA
40
°C/W
Junction to Case Thermal Resistance.
(Case is defined as the exposed Paddle)
θJC
4
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
Vcc = +5V
Pout = 0dBm / Tone
1 MHz Tone Spacing
TCASE = +25 °C
ATTN setting = 0 dB (Max Gain)
EVkit losses (traces and connectors) fully de-embedded
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Typical Performance Characteristics [Output IP3, EVkit Losses]
Figure 3. Output IP3 for Pout=0dBm/tone
Figure 4. Output IP3 for Pout=-10dBm/tone
44
44
42
40
38
36
34
32
30
42
40
38
36
34
-40C case / 4.75V
+25C case / 4.75V
+105C case / 4.75V
-40C case / 5V
+25C case / 5V
+105C case / 5V
-40C case / 5.25V
+25C case / 5.25V
+105C case / 5.25V
-40C case / 4.75V
+25C case / 4.75V
+105C case / 4.75V
-40C case / 5V
+25C case / 5V
+105C case / 5V
-40C case / 5.25V
+25C case / 5.25V
+105C case / 5.25V
32
30
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
Frequency (GHz)
Frequency (GHz)
Figure 5. Output IP3 for DSA0=6dB, DSA1=0dB,
DSA2=0dB, and Pout=0dBm/tone
Figure 6. Output IP3 for DSA0=0dB, DSA1=0dB,
DSA2=18dB, and Pout=-18dBm/tone
44
42
40
38
36
34
24
22
20
18
16
14
-40C case / 4.75V
+25C case / 4.75V
+105C case / 4.75V
-40C case / 5V
+25C case / 5V
+105C case / 5V
-40C case / 5.25V
+25C case / 5.25V
+105C case / 5.25V
-40C case / 4.75V
+25C case / 4.75V
+105C case / 4.75V
-40C case / 5V
+25C case / 5V
+105C case / 5V
-40C case / 5.25V
+25C case / 5.25V
+105C case / 5.25V
32
30
12
10
0.5
1
1.5
2
2.5
3
0.5
1
1.5
2
2.5
3
Frequency (GHz)
Frequency (GHz)
Figure 8. EVkit Losses [connectors and
traces])
Figure 7. Output IP3 Versus Tone Spacing
44
0
-0.05
-0.1
-0.15
42
40
38
36
34
-40 C
+25 C
+105 C
-0.2
-0.25
-0.3
-0.35
-0.4
0.9 GHz / ChA
2.0 GHz / ChA
2.7 GHz / ChA
0.9 GHz / ChB
2.0 GHz / ChB
2.7 GHz / ChB
32
30
-0.45
0
5
10
15
20
25
30
0
0.5
1
1.5
2
2.5
3
Tone Spacing (MHz)
Frequency (GHz)
© 2020 Renesas Electronics Corporation
15
August 13, 2020
F0440 Datasheet
Typical Performance Characteristics [Compression]
Figure 9. Gain Compression [900 MHz]
Figure 10. Phase Compression [900 MHz]
1
10
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
0.5
0
5
0
-0.5
-1
-5
-1.5
-2
-10
-15
-20
-25
-30
-2.5
-3
-3.5
-4
10
12
14
16
18
20
22
22
22
10
12
14
16
18
20
22
22
22
Output Power (dBm)
Output Power (dBm)
Figure 11. Gain Compression [2000 MHz]
Figure 12. Phase Compression [2000 MHz ]
1
10
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
0.5
0
5
0
-0.5
-1
-5
-1.5
-2
-10
-15
-20
-25
-30
-2.5
-3
-3.5
-4
10
12
14
16
18
20
10
12
14
16
18
20
Output Power (dBm)
Output Power (dBm)
Figure 13. Gain Compression [2700 MHz ]
Figure 14. Phase Compression [2700 MHz]
1
10
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
0.5
0
5
0
-0.5
-1
-5
-1.5
-2
-10
-15
-20
-25
-30
-2.5
-3
-3.5
-4
10
12
14
16
18
20
10
12
14
16
18
20
Output Power (dBm)
Output Power (dBm)
© 2020 Renesas Electronics Corporation
16
August 13, 2020
F0440 Datasheet
Typical Performance Characteristics [Output IP2, Stability, Noise Figure]
Table 11. Wideband OIP2 [Tcase = 25C,
Pout = -10dBm/Tone]
Table 12. Wideband OIP2 [Tcase = 25C,
Pout = 0dBm/Tone]
Figure 15. Stability Versus Temperature and
Voltage [DSA1=0dB]
Figure 16. Stability Versus DSA1 Attenuation
5
12
DSA1=0dB
DSA1=4dB
DSA1=1dB
DSA1=5dB
DSA1=2dB
DSA1=6dB
DSA1=3dB
DSA1=7dB
4.5
4
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
10
8
3.5
3
2.5
2
6
4
1.5
1
2
0.5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
Figure 17. Noise Figure versus Voltage and
Temperature
Figure 18. Noise Figure with DSA1=22 dB
7
6
5
4
3
2
30
28
26
24
22
20
18
16
-40C case / 4.75V
25C case / 4.75V
105C case / 4.75V
-40C case / 5.00V
25C case / 5.00V
105C case / 5.00V
-40C case / 5.25V
25C case / 5.25V
105C case / 5.25V
1
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Typical Performance Characteristics [Gain, S-Parameters, Phase Change]
Figure 19. Maximum Gain [S21, DSA0=0dB,
DSA1=0dB, DSA2=0dB]
Figure 20. S21 [DSA0=0dB, DSA1 varied,
DSA2=0dB]
13
15
10
5
-40C case/ 4.75V
+25C case/ 4.75V
+105C case/ 4.75V
-40C case/ 5.00V
+25C case/ 5.00V
+105C case/ 5.00V
-40C case/ 5.25V
+25C case/ 5.25V
+105C case/ 5.25V
12.5
12
11.5
11
0
-5
10.5
10
-10
DSA1=0dB
DSA1=4dB
DSA1=8dB
DSA1=12dB
DSA1=16dB
DSA1=20dB
DSA1=1dB
DSA1=5dB
DSA1=9dB
DSA1=13dB
DSA1=17dB
DSA1=21dB
DSA1=2dB
DSA1=6dB
DSA1=10dB
DSA1=14dB
DSA1=18dB
DSA1=22dB
DSA1=3dB
DSA1=7dB
DSA1=11dB
DSA1=15dB
DSA1=19dB
DSA1=23dB
-15
-20
-25
9.5
9
0
0.5
1
1.5
2
2.5
3
3.5
4
4
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
Figure 21. S11 [DSA0=0dB, DSA1 varied,
DSA2=0dB]
Figure 22. S22 [DSA0=0dB, DSA1 varied,
DSA2=0dB]
0
0
DSA1=0dB
DSA1=4dB
DSA1=8dB
DSA1=12dB
DSA1=16dB
DSA1=20dB
DSA1=1dB
DSA1=5dB
DSA1=9dB
DSA1=13dB
DSA1=17dB
DSA1=21dB
DSA1=2dB
DSA1=6dB
DSA1=10dB
DSA1=14dB
DSA1=18dB
DSA1=22dB
DSA1=3dB
DSA1=7dB
DSA1=11dB
DSA1=15dB
DSA1=19dB
DSA1=23dB
DSA1=0dB
DSA1=4dB
DSA1=8dB
DSA1=12dB
DSA1=16dB
DSA1=20dB
DSA1=1dB
DSA1=5dB
DSA1=9dB
DSA1=13dB
DSA1=17dB
DSA1=21dB
DSA1=2dB
DSA1=6dB
DSA1=10dB
DSA1=14dB
DSA1=18dB
DSA1=22dB
DSA1=3dB
DSA1=7dB
DSA1=11dB
DSA1=15dB
DSA1=19dB
DSA1=23dB
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
Figure 23. S12 [DSA0=0dB, DSA1 varied,
DSA2=0dB]
Figure 24. Phase Change as DSA1 varied
[DSA0=0dB, DSA2=0dB]
0
30
DSA1=0dB
DSA1=4dB
DSA1=8dB
DSA1=12dB
DSA1=16dB
DSA1=20dB
DSA1=1dB
DSA1=5dB
DSA1=9dB
DSA1=13dB
DSA1=17dB
DSA1=21dB
DSA1=2dB
DSA1=6dB
DSA1=10dB
DSA1=14dB
DSA1=18dB
DSA1=22dB
DSA1=3dB
DSA1=7dB
DSA1=11dB
DSA1=15dB
DSA1=19dB
DSA1=23dB
0.9 GHz
2.0 GHz
2.7 GHz
-5
-10
-15
-20
-25
-30
-35
-40
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
Frequency (GHz)
DSA1 Attenuation (dB)
© 2020 Renesas Electronics Corporation
18
August 13, 2020
F0440 Datasheet
Typical Performance [DSA1 Errors, S-parameters with varied DSA2]
Figure 25. DSA1 Absolute Attenuation Error
[DSA0=0dB, DSA2=0dB]
Figure 26. DSA1 Attenuator Step Error
[DSA0=0dB, DSA2=0dB]
0.500
0.25
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
0.400
0.300
0.200
0.100
0.000
-0.100
-0.200
-0.300
-0.400
-0.500
0.2
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
0
2
4
6
8
10 12 14 16 18 20 22 24
0
2
4
6
8
10
12
14
16
18
20
22
24
DSA1 Attenuation (dB)
DSA1 Attenuation (dB)
Figure 27. S21 [DSA0=0dB, DSA1=0dB, DSA2
varied]
Figure 28. S12 [DSA0=0dB, DSA1=0dB, DSA2
varied]
15
10
5
-20
-25
-30
-35
-40
-45
0
-5
-10
DSA2=0dB
DSA2=6dB
1.5
DSA2=12dB
2.5
DSA2=18dB
DSA2=0dB
DSA2=6dB
1.5
DSA2=12dB
2.5
DSA2=18dB
-15
-50
0
0.5
1
2
3
3.5
4
0
0.5
1
2
3
3.5
4
Frequency (GHz)
Frequency (GHz)
Figure 29. S11 [DSA0=0dB, DSA1=0dB, DSA2
varied]
Figure 30. S22 [DSA0=0dB, DSA1=0dB, DSA2
varied]
0
0
DSA2=0dB
DSA2=6dB
DSA2=12dB
DSA2=18dB
DSA2=0dB
DSA2=6dB
DSA2=12dB
DSA2=18dB
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
© 2020 Renesas Electronics Corporation
19
August 13, 2020
F0440 Datasheet
Typical Performance [Phase vs. DSA2, DSA2 Errors, S-Param. vs. DSA0]
Figure 31. Phase Change as DSA2 varied
[DSA0=0dB, DSA1=0dB]
Figure 32. DSA2 Absolute Attenuation Error
[DSA0=0dB, DSA1=0dB]
20
0.600
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
0.9 GHz
2.0 GHz
2.7 GHz
0.400
0.200
0.000
-0.200
-0.400
-0.600
15
10
5
0
-5
0
6
12
18
18
4
0
6
12
18
DSA2 Attenuation (dB)
DSA2 Attenuation (dB)
Figure 33. DSA2 Attenuator Step Error
[DSA0=0dB, DSA1=0dB]
Figure 34. S21 [DSA0=0, 6dB, DSA1=0dB,
DSA2=0dB]
0.250
0.200
0.150
0.100
0.050
0.000
-0.050
-0.100
-0.150
12
10
8
6
4
2
-40C / 0.9GHz
+25C / 0.9GHz
+105C / 0.9GHz
-40C / 2.0GHz
+25C / 2.0GHz
+105C / 2.0GHz
-40C / 2.7GHz
+25C / 2.7GHz
+105C / 2.7GHz
-0.200
-0.250
DSA0=0dB
1.5
DSA0=6dB
2.5
0
0
6
12
0
0.5
1
2
3
3.5
4
DSA2 Attenuation (dB)
Frequency (GHz)
Figure 35. S12 [DSA0=0, 6dB, DSA1=0dB,
DSA2=0dB]
Figure 36. S11 [DSA0=0, 6dB, DSA1=0dB,
DSA2=0dB]
0
0
DSA0=0dB
DSA0=6dB
-5
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
DSA0=0dB
1.5
DSA0=6dB
-40
0
0.5
1
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
Frequency (GHz)
© 2020 Renesas Electronics Corporation
20
August 13, 2020
F0440 Datasheet
Typical Performance [S22 versus DSA0, OIP3 with Swept Pout]
Figure 37. S22 [DSA0=0, 6dB, DSA1=0dB,
DSA2=0dB]
Figure 38. Output IP3 with Swept Pout
[DSA0 = 0 dB]
0
44.00
42.00
40.00
38.00
36.00
34.00
32.00
DSA0=0dB
DSA0=6dB
-5
-10
-15
-20
-25
-30
-35
-40
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
0
0.5
1
1.5
2
2.5
3
3.5
4
-10
-7.5
-5
-2.5
0
2.5
5
Frequency (GHz)
Output Power (dBm/tone)
Figure 39. Output IP3 with Swept Pout
[DSA0 = 6dB]
Figure 40. Output IP3 with Swept Pout
[DSA2 = 18 dB]
44.00
42.00
40.00
38.00
36.00
24.00
22.00
20.00
18.00
16.00
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
34.00
32.00
-40C case/ 0.9GHz
+25C case/ 0.9GHz
+105C case/ 0.9GHz
-40C case/ 2.0GHz
+25C case/ 2.0GHz
+105C case/ 2.0GHz
-40C case/ 2.7GHz
+25C case/ 2.7GHz
+105C case/ 2.7GHz
14.00
-10
-7.5
-5
-2.5
0
2.5
5
-30
-25
-20
-15
-10
Output Power (dBm/tone)
Output Power (dBm/tone)
© 2020 Renesas Electronics Corporation
21
August 13, 2020
F0440 Datasheet
Programming
Serial Control Mode
Figure 41. Serial Register Timing Diagram (LSB-FIRST)
1
2
3
4
5
6
7
8
9
CLK
Data Word
Latched into
Active Register
CSb
Data Word 8 bits
X
X
1 dB
2 dB
4 dB
8 dB 16 dB
X
DATA
D0
LSB
D1
D2
D3 D4
D5 D6
D7
MSB
X - don’t care
Table 13. DSA1 Serial Mode Default Condition
When the device is first powered up, DS1 will default to the Maximum Attenuation setting as shown.
Default Register Setting
x
x
1
1
1
1
1
x
D0
LSB
D1
D2
D3
D4
D5
D6
D7
MSB
Note – F0440 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being
programmed. When CSb is high (> VIH), the CLK input is disabled and serial data (DATA) is not clocked into the shift register. It
is recommended that CSb be pulled high (>VIH) when the device is not being programmed.
© 2020 Renesas Electronics Corporation
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August 13, 2020
F0440 Datasheet
Table 14. DSA1 Attenuation Word Truth Table (LSB = first in)
DON’T
CARE
ATTENUATION WORD
DON’T CARE
ATTENUATION
SETTING
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
High
Low
Low
Low
High
High
High
High
High
High
High
High
Low
Low
Low
High
Low
Low
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
High
Low
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
Low
Low
Low
Low
High
Low
High
Low
High
Low
High
Low
High
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0 dB
1 dB
2 dB
4 dB
8 dB
16 dB
22 dB
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
23 dB (max)
Table 15. DSA0 ATTENUATOR TRUTH TABLE
VCTRL0_A, VCTRL0_B
ATTENUATION SETTING (DB)
0
1
0 (Reference IL)
6
Table 16. DSA2 TRUTH TABLE
VCTRL1_A, VCTRL1_B
VCTRL2_A, VCTRL2_B
ATTENUATION SETTING (DB)
0
0
0 (Reference IL)
1 (NC)
0
0
6
1 (NC)
1 (NC)
12
18
1 (NC)
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Table 17. STANDBY TRUTH TABLE
PARAMETER
LOGIC LEVEL
FUNCTION
Low or NC
High
Power On
Power Off
STBY
Evaluation Kit Picture
Figure 42. Top View
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Evaluation Kit / Applications Circuit
Figure 43. Schematic
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Table 18. Bill of Material (BOM)
Part Reference
QTY
DESCRIPTION
Mfr. Part #
Mfr.
C1, C2, C21, C28
4
47pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H470J
Murata
C3, C4, C6, C10, C11,
C16, C22, C24, C26, C27
10 2pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H2R0B
Murata
C12, C14, C17, C20
C13, C15, C18, C19
4
4
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
0.1uF ±10%, 16V, X7R Ceramic Capacitor (0402)
GRM1555C1H102J
GRM155R71C104K
Murata
Murata
R1, R3, R4, R6, R10,
R11, R13, R17, R18, R19
10 5.11kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF5111X
Panasonic
R21, R22, R23, R24
R25
4
1
1
5
0Ω Resistors (0402)
ERJ-2GE0R00X
ERJ-2RKF6041X
ERJ-2RKF2371X
142-0701-851
Panasonic
Panasonic
6.04kΩ ±1%, 1/10W, Resistor (0402)
2.37kΩ ±1%, 1/10W, Resistor (0402)
Edge Launch SMA (0.375 inch pitch ground tabs)
R26
Panasonic
J1, J3, J5, J9, J14
Emerson Johnson
CONN HEADER VERT SGL 3 X 1 POS GOLD,
Mount jumpers to GND
J4, J11
2
4
961103-6404-AR
961102-6404-AR
3M
3M
CONN HEADER VERT SGL 2 X 1 POS GOLD
Mount jumpers
J6, J10, J12, J15
J7, J8
J13
2
1
DNP
67997-106HLF
67997-122HLF
FCI
FCI
CONN HEADER VERT SGL 11 X 2 POS GOLD
C5, C7, C8, C9, C23,
C25, C29, C30, R2, R5,
R15, R20, R7, R8, R9,
R12, R14, R16
DNP
U1
1
1
1
DVGA
F0440NGBI
IDT
IDT
IDT
Printed Circuit Board
PCB Schematic (Rev 01)
F0440 EVKIT REV 01
Applications Information
F0440 has been optimized for use in high performance RF applications from 450MHz to 2700MHz.
Power Supplies
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.
Supply voltage change or transients should have a slew rate smaller than 1V/20µS. In addition, all control pins should remain at 0V (+/-0.3V)
while the supply voltage ramps or while it returns to zero.
GND Jumpers
Jumpers J6 and J10 must be grounded (header in place) for optimum RF performance.
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Figure 44. Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to all SPI and control pins as shown below. Note the recommended resistor
and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity.
5Kohm
VCTRL1_A
2pf
5Kohm
5Kohm
STBY_A
VCTRL2_A
2pf
2pf
5Kohm
SPI CSb_A
2pf
35
34
33
32
31
30
29
28
36
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
5Kohm
VCTRL0_A
SPI Data
2pf
2pf
IDTF0440
Exposed pad (GND)
5Kohm
SPI Clk
2pf
VCTRL0_B
5Kohm
2pf
18
10
11
12
13
14
15
16
17
5Kohm
SPI CSb_B
2pf
5Kohm
2pf
5Kohm
2pf
VCTRL1_B
VCTRL2_B
STBY_B
5Kohm
2pf
© 2020 Renesas Electronics Corporation
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F0440 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/us/en/document/psc/nbnbg36-package-outline-60-x-60-mm-body-epad-410-mm-sq-050-mm-pitch-qfn
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F0440NBGI
F0440NBGI8
F0440EVBI
6 x 6 x 0.75 mm 36-TQFN
6 x 6 x 0.75 mm 36-TQFN
Evaluation Board
1
1
Tray
-40° to +105°C
-40° to +105°C
Tape and Reel
Marking Diagram
Assembler
Code
Part Number
IDTF0440
NBGI
ZW1607L
Date Code
(Week 7 of 2016)
ASM Test
Step
Q86A034MY
Lot Number
Revision History
Revision Date
Description of Change
August 13, 2020
May 13, 2020
July 27, 2016
Added Spec Table at 450MHz
Rebranded datasheet.
First release (Rev O) of the F0440 datasheet
© 2020 Renesas Electronics Corporation
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