F0448NBGK8 [RENESAS]
Dual Matched Broadband RF DVGA 3.4GHz to 3.8GHz;
| 型号： | F0448NBGK8 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Matched Broadband RF DVGA 3.4GHz to 3.8GHz |
| 文件： | 总35页 (文件大小：3665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Matched Broadband RF DVGA
3.4GHz to 3.8GHz
F0448
Datasheet
Description
Features
The F0448 is a 3.4GHz to 3.8GHz dual RF digital variable gain
amplifier (DVGA) designed for use in receivers.
.
RF Frequency Range: 3.4GHz to 3.8GHz
.
Dual Channel RF amp and DSAs for Diversity / MIMO
Receivers
This dual RF DVGA provides two independent receiver channels
each with 13dB typical maximum gain and 6dB noise figure
designed to operate with a single +5V supply. For each channel,
gain control is split into three separate attenuators: DSA0, a single
6dB step using a single control pin; DSA1, a 23dB SPI-controlled
gain adjustment in 1dB steps; and DSA2, includes 18dB
attenuation in 6dB steps controlled using two control pins. The
F0448 offers +37dBm nominal output IP3 using 220mA total ICC.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
< 2dB overshoot between DSA transitions
13dB typical maximum gain at 3.6GHz
DSA0: Single 6dB coarse step
DSA1: 23dB total gain range in 1dB steps
DSA2: 18dB gain range in 6dB steps
+37dBm OIP3 at 3.6GHz
6dB Noise figure at 3.6GHz
+5V Supply voltage
This device is packaged in a 6 × 6 mm, 36-QFN with 50Ω single-
ended RF input and RF output impedances for ease of integration
into the signal-channel lineup for each of the two channels.
ICC = 220mA
Independent standby: 7mA standby current
SPI interface for DSA1
Competitive Advantage
1-bit control for DSA0
.
.
.
.
.
High reliability
2-bit control for DSA2
High linearity
50Ω input and output impedance
Internally matched
Low DC current
Zero DistortionTM technology
GlitchFreeTM technology
Temperature range: -40°C to +105°C
6 × 6 × 0.75 mm 36-QFN package
Typical Applications
Block Diagram
.
.
.
.
Multi-mode, Multi-carrier Receivers
PHS/PAS Base Stations
Distributed Antenna Systems
Digital Radio
F0448
DSA0A
DSA1A
23dB
RF AMP A
DSA2A
18dB
RFIN_A
RFOUT_A
DATA
6dB
CSb
2
CLK
TM
Free TM
lit
Glitch
-
Decode
Logic / Bias
VCTRL0
2
VCTRL1
2
VCTRL2
2
TM
TM
6dB
23dB
18dB
STBY
i
t
ti
Zero
-
Distortion
2
RFIN_B
RFOUT_B
DSA0B
DSA1B
RF AMP B
DSA2B
1
October 24, 2018
Contents
Pin Assignments....................................................................................................................................................................................................5
Pin Descriptions.....................................................................................................................................................................................................6
Absolute Maximum Ratings...................................................................................................................................................................................7
Recommended Operating Conditions ...................................................................................................................................................................7
Electrical Characteristics .......................................................................................................................................................................................8
Thermal Characteristics.......................................................................................................................................................................................11
Typical Operating Conditions (TOC) ...................................................................................................................................................................11
Typical Performance Characteristics...................................................................................................................................................................12
Programming.......................................................................................................................................................................................................18
Serial Control – DSA1 ................................................................................................................................................................................18
Parallel Control Mode – DSA0, DSA2, STBY......................................................................................................................................................21
Typical Application Circuit ...................................................................................................................................................................................22
Evaluation Kit Picture ..........................................................................................................................................................................................23
Evaluation Kit / Applications Circuit.....................................................................................................................................................................24
Evaluation Kit Operation......................................................................................................................................................................................26
Power Supply Setup...................................................................................................................................................................................26
GND Jumpers.............................................................................................................................................................................................26
Standby (STBY) Pin ...................................................................................................................................................................................27
Serial Control..............................................................................................................................................................................................28
Parallel Control Pins...................................................................................................................................................................................29
Power-On Procedure..................................................................................................................................................................................29
Power-Off Procedure..................................................................................................................................................................................29
Application Information........................................................................................................................................................................................30
Power Supplies...........................................................................................................................................................................................30
RSET and RDSET......................................................................................................................................................................................30
Control Pin Interface...................................................................................................................................................................................30
Package Outline Drawings ..................................................................................................................................................................................31
Marking Diagram .................................................................................................................................................................................................31
Ordering Information............................................................................................................................................................................................31
Revision History...................................................................................................................................................................................................32
2
October 24, 2018
List of Figures
Figure 1. Pin Assignments for 6 × 6 mm 32-QFN – Top View............................................................................................................................5
Figure 2. Maximum Gain vs. Frequency...........................................................................................................................................................12
Figure 3. Gain vs. Frequency for DSA0 Settings..............................................................................................................................................12
Figure 4. Gain vs. Frequency for DSA1 Settings..............................................................................................................................................12
Figure 5. Gain vs. Frequency for DSA2 Settings..............................................................................................................................................12
Figure 6. Stability vs. Frequency as a Function of Voltage and Temperature ..................................................................................................12
Figure 7. Input Return Loss for DSA0 Settings.................................................................................................................................................13
Figure 8. Output Return Loss for DSA0 Settings..............................................................................................................................................13
Figure 9. Input Return Loss for DSA1 Settings.................................................................................................................................................13
Figure 10. Output Return Loss for DSA1 Settings..............................................................................................................................................13
Figure 11. Input Return Loss for DSA2 Settings.................................................................................................................................................13
Figure 12. Output Return Loss for DSA2 Settings..............................................................................................................................................13
Figure 13. Reverse Location for DSA0 Settings.................................................................................................................................................14
Figure 14. Phase Deviation Between Adjacent States vs. DSA0 Setting ...........................................................................................................14
Figure 15. Reverse Location for DSA1 Settings.................................................................................................................................................14
Figure 16. Phase Deviation Between Adjacent States vs. DSA1 Setting ...........................................................................................................14
Figure 17. Reverse Location for DSA2 Settings.................................................................................................................................................14
Figure 18. Phase Deviation Between Adjacent States vs. DSA2 Setting ...........................................................................................................14
Figure 19. DSA0 Absolute Attenuation Error (INL).............................................................................................................................................15
Figure 20. DSA0 Attenuator Step Error (DNL)...................................................................................................................................................15
Figure 21. DSA1 Absolute Attenuation Error (INL).............................................................................................................................................15
Figure 22. DSA1 Attenuator Step Error (DNL)....................................................................................................................................................15
Figure 23. DSA2 Absolute Attenuation Error (INL).............................................................................................................................................15
Figure 24. DSA2 Attenuator Step Error (DNL)....................................................................................................................................................15
Figure 25. OIP3 vs. Frequency with POUT = 0dBm/Tone and Max Gain.............................................................................................................16
Figure 26. OIP3 vs. Frequency with POUT = -10dBm/Tone and Max Gain..........................................................................................................16
Figure 27. OIP3 vs. Frequency with POUT = -18dBm/Tone and DSA2 = 18dB....................................................................................................16
Figure 28. OIP3 vs. Frequency as a Function of Tone Spacing with POUT = 0dBm/Tone...................................................................................16
Figure 29. OIP3 vs. Frequency with POUT = 0dBm/Tone and DSA0 = 6dB.........................................................................................................16
Figure 30. Wideband OIP2 vs. Frequency with POUT = -10dBm/Tone................................................................................................................17
Figure 31. Wideband OIP2 vs. Frequency with POUT = 0dBm/Tone ...................................................................................................................17
Figure 32. NF vs. Frequency as a Function of Temperature at Max Gain..........................................................................................................17
Figure 33. NF vs. Frequency as a Function of Temperature with DSA1 = 22dB................................................................................................17
Figure 34. Gain Compression at fRF = 3.6GHz ...................................................................................................................................................17
Figure 35. EVKit Connector and Trace Losses ..................................................................................................................................................17
Figure 36. Serial Register Data Flow Diagram (LSB Clock in First) ...................................................................................................................18
Figure 37. DSA1 Default Condition.....................................................................................................................................................................18
Figure 38. Serial Timing Diagram.......................................................................................................................................................................20
Figure 39. Electrical Schematic ..........................................................................................................................................................................22
Figure 40. Top View............................................................................................................................................................................................23
3
October 24, 2018
Figure 41. Bottom View ......................................................................................................................................................................................23
Figure 42. Electrical Schematic ..........................................................................................................................................................................24
Figure 43. Power Supply Connections – Top View.............................................................................................................................................26
Figure 44. Power Supply Connections – Bottom View .......................................................................................................................................26
Figure 45. Two Ground Jumper Connections.....................................................................................................................................................26
Figure 46. Two Standby Pin Connections ..........................................................................................................................................................27
Figure 47. Two Jumpers for Serial Programming Connections ..........................................................................................................................28
Figure 48. Parallel Pin Connections ...................................................................................................................................................................29
Figure 49. Control Pin Interface..........................................................................................................................................................................30
List of Tables
Table 1. Pin Descriptions...................................................................................................................................................................................6
Table 2. Absolute Maximum Ratings.................................................................................................................................................................7
Table 3. Recommended Operating Conditions .................................................................................................................................................7
Table 4. Electrical Characteristics .....................................................................................................................................................................8
Table 5. Package Thermal Characteristics......................................................................................................................................................11
Table 6. DSA1 Attenuation Word Truth Table (LSB = First In)........................................................................................................................19
Table 7. SPI Timing Diagram Values for Figure 38.........................................................................................................................................20
Table 8. DSA0 Truth Table..............................................................................................................................................................................21
Table 9. DSA2 Truth Table..............................................................................................................................................................................21
Table 10. STANDBY Truth Table ......................................................................................................................................................................21
Table 11. Bill of Material (BOM) ........................................................................................................................................................................25
Table 12. J13 Header Pins................................................................................................................................................................................28
Table 13. Attenuator Control Using One Latch Signal.......................................................................................................................................29
4
October 24, 2018
Pin Assignments
Figure 1. Pin Assignments for 6 × 6 mm 32-QFN – Top View
F0448
35
34
33
32
31
30
29
28
36
DSA0_A
DSA1_A
DSA2_A
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
RFout_A
RFin_A
GND
GND
VCC
Rset
VCTRL0_A
SPI Data
SPI Clk
Decode Logic
VCC
Bias Control
RDset
VCC
VCC
VCTRL0_B
GND
GND
RFin_B
RFout_B
DSA0_B
DSA1_B
DSA2_B
10
11
12
13
14
15
16
17
18
5
October 24, 2018
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1
RFIN_A
GND
Input RF port for channel A which is internally matched to 50Ω. Must use external DC block.
2, 8, 15, 16,
17, 29, 30, 31
Internally grounded. This pin must be grounded with a via as close to the pin as possible.
1-bit DSA0 6dB attenuator control for channel A. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB
attenuated.
3
VCTRL0_A
4
DATA
CLK
VCC
Data input: 3.3V or 1.8V CMOS compatible.
5
Clock input: 3.3V or 1.8V CMOS compatible.
6, 21, 23, 25
Power Supply. Use bypass capacitors as close to pin as possible.
1-bit DSA0 6dB attenuator control for channel B. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB
attenuated.
7
9
VCTRL0_B
RFIN_B
NC
Input RF port for channel B that is internally matched to 50Ω. Must use external DC block.
10, 18, 20, 26,
28, 36
No internal connection. These pins can be left unconnected or be connected to ground (recommended). Use a via as
close to the pin as possible if grounded.
11
12
CSb_B
STBY_B
Chip Select bar input for channel B: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.
Standby pin for channel B (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An
internal pull-down resistor of 57kΩ connects between this pin and GND.
13
14
19
22
24
27
32
33
VCTRL1_B
VCTRL2_B
RFOUT_B
RDSET
Bit 0 for DSA2 channel B attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.
Bit 1 for DSA2 channel B attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.
Output RF port for channel B. Use external DC block as close to the pin as possible.
Connect external resistor to GND to optimize amplifier bias. Used with pin 24.
RSET
Connect external resistor to GND to optimize amplifier bias. Used with pin 22.
RFOUT_A
VCTRL2_A
VCTRL1_A
Output RF port for channel A. Use external DC block as close to the pin as possible.
Bit 1 for DSA2 channel A attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.
Bit 0 for DSA2 channel A attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.
Standby pin for channel A (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An
internal pull-down resistor of 57kΩ connects between this pin and GND.
34
35
STBY_A
CSb_A
Chip Select bar input for channel A: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that
uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground
vias are also required to achieve the specified RF performance.
— EPAD
6
October 24, 2018
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F0448 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VCC to GND
VCC
-0.3
+5.5
V
Lower of
(VCC, 3.6)
DATA, CSb_A, CSb_B, CLK, VCTRL0_A, VCTRL0_B
VLOGIC1
-0.3
V
STBY_A, STBY_B, VCTRL1_A, VCTRL1_B, VCTRL2_A, VCTRL2_B
RFIN_A, RFIN_B externally applied DC voltage
RFOUT_A, RFOUT_B, externally applied DC voltage
RF Input Power (RFIN_A or RFIN_B) applied for 24 hours maximum [a]
Continuous Power Dissipation
VLOGIC2
VRFIN
VRFOUT
PMAX
-0.3
+1.4
+1.4
VCC + 0.25
+3.6
+3.6
+22
V
V
V
dBm
W
PDISS
TST
1.5
Storage Temperature Range
-65
150
°C
°C
Lead Temperature (soldering, 10s)
260
2000
Class 2
ElectroStatic Discharge – HBM (JEDEC/ESDA JS-001-2012)
ElectroStatic Discharge – CDM (JEDEC 22-C101F)
V
V
1000
Class C3
[a] Exposure to these maximum RF levels can result in significant VCC current draw due to overdriving the amplifier stage.
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
VCC
Condition
All VCC pins
Minimum
4.75
Typical
Maximum
5.25
Units
V
Supply Voltage
5.00
Operating Temperature Range
Junction Temperature
RF Frequency Range
Maximum RF Input Power
RF Source Impedance
RF Load Impedance
TEPAD
TJ
Exposed paddle
-40
+105
+125
3.8
°C
°C
fRF
3.4
GHz
dBm
Ω
PIP
DSA0 = DSA1 = 0dB
Single ended
0
ZRFI
50
50
ZRFO
Single ended
Ω
7
October 24, 2018
Electrical Characteristics
See F0448 Typical Application Circuit. VCC = +5V, TC = +25°C, fRF = 3.6GHz specifications apply when operated as a dual-channel RF DVGA,
maximum gain setting, POUT = 0dBm, ZRFI = ZRFO = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise
stated.
Table 4.
Electrical Characteristics
Parameter
Symbol
VIH
Condition
Applies for all logic levels.
Applies for all logic levels.
Minimum
Typical
Maximum
Units
Logic Input High
Logic Input Low
1.07 [a]
V
V
VIL
0.63
5
Logic Current
(CLK, DATA, CSb_A, CSb_B,
VCTRL0_A, VCTRL1_A, VCTRL2_A,
VCTRL0_B, VCTRL1_B, VCTRL2_B)
IIH, IIL
-5
μA
μA
5V logic
-5
-5
-5
127
87
Logic Current for Standby
(STBY_A, STBY_B) [b]
I
IH-SB, IIL-SB 3.3V logic
1.8V logic
47
ICC_2
ICC_1
Both channels on
220
110
7
270
142
14
Supply Current
Startup Time
One channel on
Standby Mode
mA
ns
ICC_STBY
50% of STBY going LOW to Gain
within ± 1dB with no attenuation.
tSTART
74
DSA0 Adjustment Range
DSA1 Adjustment Range
DSA2 Adjustment Range
Maximum Attenuation Glitch
AADJ0
AADJ1
6dB step size
1dB step size
6dB step size
6
23
18
2
dB
dB
dB
dB
AADJ2
ATTNG
50% CTRL to within 0.1dB final value,
0dB state to 6dB state
tDSA0_1
24
35
35
DSA0 Gain Settling Time
DSA1 Gain Settling Time
DSA2 Gain Settling Time
ns
ns
ns
50% CTRL to within 0.1dB final value,
6dB state to 0dB state
tDSA0_2
tDSA1
18
300
16
50% of CSb to within 0.1dB final value
50% CTRL to within 0.1dB final value,
0dB state to 18dB state
tDSA2_1
35
35
35
35
50% CTRL to within 0.1dB final value,
18dB state to 0dB state
tDSA2_2
15
24
18
50% CTRL to within 1 degree of final
value, 0dB state to 6dB state
tDSA0_1_PH
tDSA0_2_PH
DSA0 Phase Settling Time
ns
50% CTRL to within 1 degree of final
value, 6dB state to 0dB state
8
October 24, 2018
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
50% CTRL to within 1 degree of final
value, 0dB state to 18dB state
tDSA2_1_PH
16
35
35
DSA2 Phase Settling Time
ns
50% CTRL to within 1 degree of final
value, 18dB state to 0dB state
tDSA0_1_PH
15
Stability K factor
KFACT
Over entire temperature range
1.4
unit
Serial Clock Speed
SPICLK
10
MHz
CSb_A, CSb_B to first serial clock
rising edge
SPI 3 wire bus. 50% of CSb falling
edge to 50% of CLK rising edge.
tLS
tH
10
10
10
ns
ns
ns
SPI 3 wire bus. 50% of CLK rising
edge to 50% of Data falling edge.
Serial Data Hold Time
SPI 3 wire bus. 50% of CLK rising
edge to 50% of CSb rising edge.
Final serial clock rising edge to CSb
tLC
RF Input Return Loss
RF Output Return Loss
RLIN
RLOUT
15
20
dB
dB
GMAX
12
13
13.5
GMIN
Maximum attenuation
-38.1
-32
-26.4
Gain
dB
GTEMP
Variation over temperature
Variation over frequency [c]
±0.15
±0.2
0.52
0.16
0.55
0.32
0.43
6.6
GVAR
DSA0 Absolute Accuracy
DSA1 Step Error
INLDSA0
DNLDSA1
INLDSA1
DNLDSA2
INLDSA2
ΦPH_DSA0
dB
dB
DSA1 Absolute Accuracy
DSA2 Step Error
dB
dB
DSA2 Absolute Accuracy
Relative Phase DSA0
Phase Deviation DSA1
Relative Phase DSA2
dB
deg
deg
deg
ΦPH_DSA1 Between adjacent states
3
ΦPH_ DSA2 Any State
6.6
NF
5.9
Noise Figure
NFHOT
NF22
TEPAD = +105°C
6.6
dB
DSA1 22dB attenuation
27.7
9
October 24, 2018
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
OIP31
1MHz tone separation
34
37
1MHz tone separation
POUT = -10dBm/tone
OIP32
OIP36dB
OIP33
33
35
37
36
1MHz tone separation
DSA0 full attenuation
dBm
Output Third Order Intercept Point
1MHz tone separation
Worst case over temp range
33
POUT = -18dBm/tone
OIP318dB 1MHz tone separation
DSA2 full 18dB attenuation
21
Input 1dB Compression [d]
Output 1dB Compression
Reverse Isolation
IP1dB
OP1dB
REVISO
Full attenuation
24
18
22
39
39
dBm
dBm
dB
19
35
Channel Isolation [e]
CHISO
dB
Over voltage and temperature
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that
are not shown in bold italics are guaranteed by design characterization.
[b] During standby mode, SPI is to be left ON and previous state is maintained when device is powered up.
[c] Including frequency and ripple variations valid within each individual 3GPP band.
[d] Input 1dB compression point is a linearity figure of merit. For maximum RF input power, see Absolute Maximum Ratings.
[e] Signal applied to RFIN_A (RFIN_B), measure desired signal at RFOUT_A (RFOUT_B) and compare to signal level at RFOUT_B (RFOUT_A).
Maximum gain setting.
10
October 24, 2018
Thermal Characteristics
Table 5.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance.
θJA
37.1
°C/W
Junction to Case Thermal Resistance.
(Case is defined as the exposed paddle)
θJC-BOT
9.1
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 1
Typical Operating Conditions (TOC)
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
.
.
.
.
.
Vcc = 5.0V
ZL = ZS = 50Ω Single ended
fRF = 3.6GHz
TEPAD = +25°C
Gain setting = Maximum gain
STBY = LOW
POUT = 0dBm/tone
1MHz Tone Spacing
ATTN setting = 0dB (Maximum gain; DSA0 = DSA1 = DSA2 = 0dB)
All temperatures are referenced to the exposed paddle
Evaluation Kit traces and connector losses are de-embedded
11
October 24, 2018
Typical Performance Characteristics
Figure 2. Maximum Gain vs. Frequency
Figure 3. Gain vs. Frequency for DSA0 Settings
15.0
15
+4.75 V / -40 C
+5.00 V / -40 C
+5.25 V / -40 C
+4.75 V / +25 C
+5.00 V / +25 C
+5.25 V / +25 C
+4.75 V / +105 C
+5.00 V / +105 C
+5.25 V / +105 C
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
10
5
0
-5
-10
DSA0=0dB
DSA0=6dB
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
Frequency (GHz)
Figure 4. Gain vs. Frequency for DSA1 Settings
Figure 5. Gain vs. Frequency for DSA2 Settings
15
15
10
5
10
5
0
0
-5
-10
-5
-10
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
DSA2=0 dB
DSA2=6 dB
DSA2=12 dB
DSA2=18 dB
6 dB
7 dB
8 dB
9 dB
10 dB
16 dB
22 dB
11 dB
17 dB
23 dB
12 dB
18 dB
13 dB
19 dB
14 dB
20 dB
15 dB
21 dB
-15
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
Frequency (GHz)
Figure 6. Stability vs. Frequency as a Function
of Voltage and Temperature
5.0
+4.75 V / -40 C
+5.00 V / -40 C
+5.25 V / -40 C
+4.75 V / +25 C
+5.00 V / +25 C
+5.00 V / +25 C
+4.75 V / +105 C
+5.25 V / +105 C
+5.25 V / +105 C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
12
October 24, 2018
Figure 7. Input Return Loss for DSA0 Settings
Figure 8. Output Return Loss for DSA0
Settings
0
0
DSA0=0 dB
DSA0=6 dB
-5
-10
-15
-20
-25
-30
-35
-5
DSA0=0 dB
DSA0=6 dB
-10
-15
-20
-25
-30
-35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
Frequency (GHz)
Figure 9. Input Return Loss for DSA1 Settings
Figure 10. Output Return Loss for DSA1
Settings
0
-5
0
0 dB
6 dB
12 dB
18 dB
1 dB
7 dB
13 dB
19 dB
2 dB
8 dB
14 dB
20 dB
3 dB
9 dB
15 dB
21 dB
4 dB
5 dB
10 dB
16 dB
22 dB
11 dB
17 dB
23 dB
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
0 dB
6 dB
12 dB
18 dB
1 dB
7 dB
13 dB
19 dB
2 dB
8 dB
14 dB
20 dB
3 dB
9 dB
15 dB
21 dB
4 dB
5 dB
10 dB
16 dB
22 dB
11 dB
17 dB
23 dB
-35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
Frequency (GHz)
Figure 11. Input Return Loss for DSA2 Settings
Figure 12. Output Return Loss for DSA2
Settings
0
0
DSA2=00 dB
DSA2=12 dB
DSA2=06 dB
DSA2=18 dB
-5
-10
-15
-20
-25
-30
-35
-5
-10
-15
-20
-25
-30
-35
DSA2=00 dB
DSA2=06 dB
DSA2=12 dB
DSA2=18 dB
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Frequency (GHz)
Frequency (GHz)
13
October 24, 2018
Figure 13. Reverse Isolation for DSA0 Settings
Figure 14. Phase Deviation Between Adjacent
States vs. DSA0 Setting
0
0
-5
-1
-2
-3
-4
-5
-6
-7
DSA0=0 dB
DSA0=6 dB
-10
-15
-20
-25
-30
-35
-40
-45
-50
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-8
-9
-10
0
6
0.0
1.0
2.0
3.0
4.0
5.0
6.0
DSA0 Setting (dB)
Frequency (GHz)
Figure 15. Reverse Isolation for DSA1 Settings
Figure 16. Phase Deviation Between Adjacent
States vs. DSA1 Setting
0
0
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-1
-2
-3
-4
-5
-6
-7
6 dB
7 dB
8 dB
9 dB
10 dB
16 dB
22 dB
11 dB
17 dB
23 dB
12 dB
18 dB
13 dB
19 dB
14 dB
20 dB
15 dB
21 dB
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-8
-9
-10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
5
10
15
20
Frequency (GHz)
DSA1 Setting (dB)
Figure 17. Reverse Isolation for DSA2 Settings
Figure 18. Phase Deviation Between Adjacent
States vs. DSA2 Setting
0
0
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
DSA2=0 dB
-5
-1
-2
DSA2=6 dB
-10
DSA2=12 dB
DSA2=18 dB
-15
-3
-20
-25
-30
-35
-40
-45
-50
-4
-5
-6
-7
-8
-9
-10
0
6
12
18
0.0
1.0
2.0
3.0
4.0
5.0
6.0
DSA2 Setting (dB)
Frequency (GHz)
14
October 24, 2018
Figure 19. DSA0 Absolute Attenuation Error
Figure 20. DSA0 Attenuator Step Error (DNL)
(INL)
1.0
1.0
0.9
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
6
0
6
DSA0 Setting (dB)
DSA0 Setting (dB)
Figure 21. DSA1 Absolute Attenuation Error
Figure 22. DSA1 Attenuator Step Error (DNL)
(INL)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.8
0.7
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.2
0.1
0.0
0
5
10
15
20
0
5
10
15
20
DSA1 Setting (dB)
DSA1 Setting (dB)
Figure 23. DSA2 Absolute Attenuation Error
Figure 24. DSA2 Attenuator Step Error (DNL)
1.0
0.8
0.7
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
0
6
12
18
0
6
12
18
DSA2 Setting (dB)
DSA2 Setting (dB)
15
October 24, 2018
Figure 25. OIP3 vs. Frequency with
Figure 26. OIP3 vs. Frequency with
POUT = -10dBm/Tone and Max Gain
POUT = 0dBm/Tone and Max Gain
50
50
48
46
44
42
40
38
36
34
32
30
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
48
46
44
42
40
38
36
34
32
30
3
3.2
3.4
3.6
3.8
4
3
3.2
3.4
3.6
3.8
4
Frequency (GHz)
Frequency (GHz)
Figure 27. OIP3 vs. Frequency with
POUT = -18dBm/Tone and DSA2 = 18dB
Figure 28. OIP3 vs. Frequency as a Function of
Tone Spacing with POUT = 0dBm/Tone
25
24
23
22
21
20
19
18
17
16
15
50
48
46
44
42
40
38
36
34
32
30
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-40 C
+25 C
+105 C
3
3.2
3.4
3.6
3.8
4
0
10
20
30
40
50
Frequency (GHz)
Tone Spacing Frequency (MHz)
Figure 29. OIP3 vs. Frequency with
POUT = 0dBm/Tone and DSA0 = 6dB
50
48
46
44
42
40
38
36
34
32
30
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
3
3.2
3.4
3.6
3.8
4
Frequency (GHz)
16
October 24, 2018
Figure 30. Wideband OIP2 vs. Frequency with
POUT = -10dBm/Tone
Figure 31. Wideband OIP2 vs. Frequency with
POUT = 0dBm/Tone
0
0
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Frequency (GHz)
Frequency (GHz)
Figure 32. NF vs. Frequency as a Function of
Figure 33. NF vs. Frequency as a Function of
Temperature at Max Gain
Temperature with DSA1 = 22dB
7
32
31
30
29
28
27
26
25
24
6.5
6
5.5
5
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
4.5
4
23
22
3
3.2
3.4
3.6
3.8
4
3
3.2
3.4
3.6
3.8
4
Frequency (GHz)
Frequency (GHz)
Figure 34. Gain Compression at fRF = 3.6GHz
Figure 35. EVKit Connector and Trace Losses
14
13
12
11
10
0.0
-40 C
-0.1
+25 C
+105 C
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-40 C, +4.75 V
+25 C, +4.75 V
+105 C, +4.75 V
-40 C, +5.00 V
+25 C, +5.00 V
+105 C, +5.00 V
-40 C, +5.25 V
+25 C, +5.25 V
+105 C, +5.25 V
9
8
0
1
2
3
4
5
6
8
10
12
14
16
18
20
Frequency (GHz)
Output Power (dBm)
17
October 24, 2018
Programming
The F0448 is programmed in both the serial and parallel. The 23dB attenuator (DSA1) is programmed using a three-wire serial control line. You
choose which channel is programmed by using either or both CSb lines. Parallel pins are used for the one-bit 6dB attenuator ((DSA0_A,
DSA0_B) and two-bit 18dB (6dB step) attenuator (DSA2_A, DSA2_B). The standby pins are also controlled by the parallel pin. All logic is both
1.8V and 3.3V compatible.
Serial Control – DSA1
The serial interface uses an 8-bit word with only 5 bits used. The serial word is shifted in LSB (D0) first.
Figure 36. Serial Register Data Flow Diagram (LSB Clock in First)
1
2
3
4
5
6
7
8
9
CLK
Data Word
Latched into
Active Register
CSb
Data Word 8 bits
X
X
1 dB
2 dB
4 dB
8 dB 16 dB
X
DATA
D0
LSB
D1
D2
D3 D4
D5 D6
D7
MSB
Figure 37. DSA1 Default Condition
When the device is first powered up, DSA1 will default to the Maximum Attenuation setting as shown.
Default Register Setting
x
x
1
1
1
1
1
x
D0
LSB
D1
D2
D3
D4
D5
D6
D7
MSB
The F0448 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed. When
CSb is high (> VIH), the CLK input is disabled and serial data (DATA) is not clocked into the shift register. It is recommended that CSb be pulled
high (> VIH) when the device is not being programmed.
18
October 24, 2018
Table 6.
DSA1 Attenuation Word Truth Table (LSB = First In)
Attenuation word
Attenuation
Setting (dB)
D7 (MSB)
D6
D5
D4
D3
D2
D1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D0 (LSB)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
2
4
8
16
22
23 (max)
23 (max)
23 (max)
23 (max)
23 (max)
23 (max)
23 (max)
23 (max)
23 (max)
19
October 24, 2018
Figure 38. Serial Timing Diagram
tH
tP
tLC
tS
tCH
tCL
CLK
DATA
tLS
CSb
tL
tL
Table 7.
SPI Timing Diagram Values for Figure 38
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
10
Units
MHz
ns
CLK Frequency
fC
tCH
tCL
tS
CLK High Duration Time
CLK Low Duration Time
DATA to CLK Setup Time
CLK Period [a]
50
50
10
100
10
10
10
10
ns
ns
tP
ns
CLK to DATA Hold Time
CSb to CLK Setup Time
CSb Trigger Pulse Width
CSb Trigger to CLK Setup Time [b]
tH
ns
tLS
tL
ns
ns
tLC
ns
[a] (tCH + tCL) ≥ 1/fC
[b] Once all desired DATA is clocked in, tLC represents the time a CSb high needs to occur before any subsequent CLK signals.
20
October 24, 2018
Parallel Control Mode – DSA0, DSA2, STBY
Externally set the parallel control pins either logic LOW or HIGH.
Table 8.
DSA0 Truth Table
VCTRL0_A (VCTRL0_B)
ATTENUATION SETTING (dB)
DSA0_A or DSA0_B
LOW
HIGH
0 (Reference IL)
6
Table 9.
DSA2 Truth Table
ATTENUATION SETTING (dB)
VCTRL1_A (VCTRL1_B)
VCTRL2_A (VCTRL2_B)
DSA2_A or DSA2_B
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
0 (Reference IL)
6
12
18
Table 10. STANDBY Truth Table
Control Pins
Logic Level
LOW (or open)
HIGH
Function
Channel Powered On
Channel Powered OFF
STBY_A, STBY_B
21
October 24, 2018
Typical Application Circuit
Figure 39 is a typical circuit that can be used in a design for the F0448.
Figure 39. Electrical Schematic
CSB_A
R3
R1
R4
C6
C4
C3
STBY_A
U1
RFOUT_A
RFIN_A
C1
C2
J1
1
27
26
25
24
23
22
21
20
19
J3
RFIN_A
RFOUT_A
NC
VCTRL0_A
R6
2
3
4
5
6
7
8
9
C11
GND
C10
C12
C13
VCC2A
VCTRL0_A
SPI_DATA
SPI_CLK
VCC
VCC
SPI_DATA
SPI_CLK
R10
R11
R26
R25
RSET
VCC
VCC2AB
F0448
C16
C14
C15
RDSET
VCC
R13
VCC1
C19
VCC2B
VCTRL0_B
GND
C22
C17
C16
C28
C20
NC
VCTRL0_B
C21
RFOUT_B
RFIN_B
RFOUT_B
RFIN_B
J4
J2
STBY_B
C24
C27
R19
C26
R18
R17
CSB_B
22
October 24, 2018
Evaluation Kit Picture
Figure 40. Top View
Figure 41. Bottom View
23
October 24, 2018
Evaluation Kit / Applications Circuit
Figure 42 is the evaluation board schematic.
Figure 42. Electrical Schematic
1
2
N C
8 2
N C
G N
G N
G N
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
D
D
D
G N
G N
G N
D
D
D
9 2
0 3
1 3
2 3
3 3
4 3
5 3
6 3
7 3
A 2 _ L R T C V
A 1 _ L R T C V
B 2 _ L R T C V
B 1 _ L R T C V
3
2
1
3
2
1
A
B Y S _ T
S B C _ A
B
B Y S _ T
S B C _ B
N C
N C
E P A D
24
October 24, 2018
Table 11. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1, C2, C21, C28
4
47pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H470J
Murata
C3, C4, C6, C10, C11,
C16, C22, C24, C26,
C27
10 2pF ±0.1pF, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H2R0B
Murata
C12, C14, C17, C20
C13, C15, C18, C19
4
4
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
0.1µF ±10%, 16V, X7R Ceramic Capacitor (0402)
GRM1555C1H102J
GRM155R71C104K
Murata
Murata
R1, R3, R4, R6, R10,
R11, R13, R17, R18,
R19
10 5.11kΩ ±1%, 1/10W, Resistor (0402)
ERJ-2RKF5111X
Panasonic
R21, R22, R23, R24
R25, R26
4
2
5
2
4
1
1
1
0Ω Resistor (0402)
ERJ-2GE0R00X
ERJ-3EKF4421V
142-0701-851
Panasonic
4.42kΩ ±1%, 1/10W, Resistor (0402)
Edge Launch SMA (0.375 inch pitch ground tabs)
CONN HEADER VERT SGL 3 X 1 POS GOLD
CONN HEADER VERT SGL 2 X 1 POS
CONN HEADER VERT SGL 11 X 2 POS GOLD
Dual DVGA
Panasonic
J1, J3, J5, J9, J14
J4, J11
Emerson Johnson
961103-6404-AR
961102-6404-AR
67997-122HLF
3M
3M
J6, J10, J12, J15
J13
FCI
IDT
IDT
U1
F0448NBGK
Printed Circuit Board
F0440 EVKIT REV 01
C5, C7, C8, C9, C23,
C25, C29, C30, R2,
R5, R15, R20, R7, R8,
R9, R12, R14, R16, J7,
J8
DNP
25
October 24, 2018
Evaluation Kit Operation
Power Supply Setup
Set up a power supply in the voltage range of 4.75V to 5.25V with the power supply output disabled. The voltage is applied via the SMA
connector, J1, show in Figure 43 and Figure 44.
Figure 43. Power Supply Connections – Top View
Figure 44. Power Supply Connections – Bottom View
GND Jumpers
Headers J6 and J10 must be jumped (grounded) for optimum RF performance. Figure 45 shows the header locations.
Figure 45. Two Ground Jumper Connections
26
October 24, 2018
Standby (STBY) Pin
The Evaluation Board can control the F0448 for standby operation. The standby pin is the center pin of the J4 and J11 header as shown in
Figure 46. VCC (logic HIGH) and ground (logic LOW) pins are available to make a connection with a jumper.
Figure 46. Two Standby Pin Connections
To place channel A in the normal operation mode (on), use one of these options:
.
.
.
Make no connections on J4.
Apply a logic LOW signal to STBY (pin 2 of J4 or the middle pin).
Make a connection between pin 1 (GND) and pin 2 (STBY, the middle pin) of J4.
To place channel A in the standby mode (off), use one of these options:
.
.
Apply a logic HIGH signal to the STBY (pin 2 of J4 or the middle pin).
Make a connection between pin 3 (VCC) and pin 2 (STBY, the middle pin) of J4.
To place channel B in the normal operation mode (on), use one of these options:
.
.
.
Make no connections on J11.
Apply a logic LOW signal to STBY (pin 2 of J11 or the middle pin).
Make a connection between pin 1 (GND) and pin 2 (STBY, the middle pin) of J11.
To place channel B in the standby mode (off), use one of these options:
.
.
Apply a logic HIGH signal to the STBY (pin 2 of J11 or the middle pin).
Make a connection between pin 3 (VCC) and pin 2 (STBY, the middle pin) of J11.
27
October 24, 2018
Serial Control
Both channels have a digital controlled attenuator, DSA1_A and DSA1_B, which share the serial control word. The serial control pins are on
header J13 and are shown in Figure 47. Table 12 lists the pin functions on header J13.
Figure 47. Two Jumpers for Serial Programming Connections
Table 12. J13 Header Pins
Pin
1
Label
GND
Pin
2
Label
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
DATA
4
5
CLK
6
7
CSb_A
8
9
CSb_B
10
12
14
16
18
20
22
11
13
15
17
19
21
VCTRL0_A
VCTRL0_B
VCTRL1_A
VCTRL1_B
VCTRL2_A
VCTRL2_B
Each channel has its own latch pins, CSB_A and CSB_B (pin 7 of J13 and pin 9 of J13) so each channel attenuator can be independently
controlled. If you only have one latch signal, the ability to control each channel attenuator achieved using headers J12 and J15. The latch signal
must be applied to CSb_A (pin 7 of J13). Table 13 lists the operation for the connections on these headers.
28
October 24, 2018
Table 13. Attenuator Control Using One Latch Signal
J12
CSb_B
OPEN
Function
OPEN
No control of attenuators
OPEN
CLOSED
OPEN
DSA1_B attenuator is controlled
DSA1_A attenuator is controlled
CLOSED
CLOSED
CLOSED
DSA1_A attenuator is controlled DSA1_B attenuator is controlled
Parallel Control Pins
Both channels have two other attenuators, DSA0 and DSA1, which are parallel controlled. These parallel pins are located on header J13 shown
in Figure 48. Table 12 lists the pin functions on header J13.
Figure 48. Parallel Pin Connections
See Table 8 and Table 9 for the attenuation control.
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in “Power Supply Setup” with the “Standby Pin” set for logic LOW, then enable
the power supply.
Power-Off Procedure
Disable the power supply.
29
October 24, 2018
Application Information
The F0448 is optimized for use in high-performance RF applications from 3.4GHz to 3.6GHz.
Power Supplies
Bypass supply pins with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients
can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V/20µS. In
addition, all control pins should remain at 0V (±0.3V) while the supply voltage ramps or while it returns to zero.
RSET and RDSET
The F0448 is optimized for gain and intermodulation products by adjusting the bias resistors RSET and RDSET. For the optimized setting,
RSET (R26) and RDSET (R25) are 4.42kΩ.
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to control pins 3-7, 11-14, and 32-35 as shown below. Note the recommended
resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity.
Figure 49. Control Pin Interface
5kΩ
VCTRL1_A
2pF
5kΩ
5kΩ
STBY_A
VCTRL2_A
2pF
2pF
5kΩ
CSb_A
2pF
35
34
33
32
31
30
29
28
36
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
5kΩ
VCTRL0_A
2pF
5kΩ
5kΩ
DATA
CLK
2pF
2pF
F0448
Exposed pad (GND)
5kΩ
VCTRL0_B
2pF
18
10
11
12
13
14
15
16
17
5kΩ
CSb_B
2pF
5kΩ
5kΩ
VCTRL2_B
STBY_B
2pF
2pF
5kΩ
VCTRL1_B
2pF
30
October 24, 2018
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
https://www.idt.com/document/psc/nbnbg36-package-outline-60-x-60-mm-body-epad-410-mm-sq-050-mm-pitch-qfn
Marking Diagram
.
.
.
.
.
Line 1 and 2 are the part number.
Line 3 “ZW” is for die version.
IDTF0448
NBGK
ZW1707L
Q86A034MY
Line 3 “yyww = 1707 has two digits for the year and week that the part was assembled.
Line 3 “L” denotes Assembly Site.
Line 4 “Q86A034MY” is the Assembly Lot number.
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Tray
Temperature
-40°C to +105°C
-40°C to +105°C
F0448NBGK
F0448NBGK8
F0448EVB
1
6 × 6 × 0.75 mm 36-QFN
6 × 6 × 0.75 mm 36-QFN
1
Tape and Reel
Evaluation Board
Evaluation Solution
F0448EVS
31
October 24, 2018
Revision History
Revision Date
Description of Change
Removed “or pin open” from Pin Descriptions
.
.
.
October 24, 2018
October 18, 2018
Removed “or open” from Table 8 and Table 9
Updated Figure 47
.
.
.
Updated various logic levels.
Update Typical Performance Characteristics
Completed other minor improvements.
August 29, 2018
August 8, 2018
Added θJA and θJC-BOT values to Table 5.
Initial release.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明