F0452BLEGK [RENESAS]
Dual Path RF Switch with LNA and DVGA 2.3GHz to 2.7GHz;
| 型号： | F0452BLEGK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Path RF Switch with LNA and DVGA 2.3GHz to 2.7GHz |
| 文件： | 总29页 (文件大小：3489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Path RF Switch with LNA and
DVGA 2.3GHz to 2.7GHz
F0452B
Datasheet
Description
Features
The F0452B is an integrated dual-path RF front-end consisting of
an RF switch and two gain stages with 6dB gain control used in the
analog front-end receiver of an Active Antenna System (AAS). The
F0452B supports frequencies from 2.3GHz to 2.7GHz.
.
Gain at 2.6GHz
34dB typical in High Gain Mode
28dB typical in Low Gain Mode
1.5dB NF at 2.6GHz
+23dBm OIP3 at 2.6GHz
OP1dB at 2.6GHz
.
.
.
The F0452B provides 34dB gain with +23dBm OIP3, +15dBm
output P1dB, and 1.5dB noise figure (NF) at 2.6GHz. Gain is
reduced 6dB in a single step with a maximum settling time of 31ns.
The device uses a single 3.3V supply and 130mA of IDD.
+15dBm in High Gain Mode
+14dBm in Low Gain Mode
The F0452B is offered in a 5 5 0.8 mm, 32-LGA package with
50Ω input and output amplifier impedances for ease of integration
into the signal path.
.
.
.
.
.
.
50Ω single-ended input / output amplifier impedances
IDD = 130mA
Independent Standby Mode for power savings
Supply voltage: +3.15V to +3.45V
5 5 mm, 32-LGA package
-40°C to +105°C exposed pad operating temperature range
Competitive Advantage
.
.
.
.
High integration
Low noise and high linearity
On-chip matching and bias
Extremely low current consumption
Block Diagram
Typical Applications
.
.
.
Multi-mode, multi-carrier receivers
4.5G (LTE Advanced)
5G band 42
SW1_IN
STBY1
ATT1_CTRL
SW1_CTRL
SW2_CTRL
ATT2_CTRL
STBY2
SW2_IN
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May 7, 2019
Contents
Pin Assignments....................................................................................................................................................................................................5
Pin Descriptions.....................................................................................................................................................................................................6
Absolute Maximum Ratings...................................................................................................................................................................................7
Recommended Operating Conditions ...................................................................................................................................................................8
Electrical Characteristics .......................................................................................................................................................................................9
Thermal Characteristics.......................................................................................................................................................................................13
Typical Operating Conditions ..............................................................................................................................................................................13
Programming.......................................................................................................................................................................................................18
Evaluation Kit Picture ..........................................................................................................................................................................................20
Evaluation Kit / Applications Circuit .....................................................................................................................................................................21
Evaluation Kit Operation......................................................................................................................................................................................23
Mode Control Setup....................................................................................................................................................................................23
Power-On Procedure..................................................................................................................................................................................23
Power-Off Procedure..................................................................................................................................................................................23
Application Information........................................................................................................................................................................................24
Power Supplies...........................................................................................................................................................................................24
Control Pin Interface...................................................................................................................................................................................24
Package Outline Drawings ..................................................................................................................................................................................25
Ordering Information............................................................................................................................................................................................25
Marking Diagram .................................................................................................................................................................................................25
Revision History...................................................................................................................................................................................................26
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May 7, 2019
List of Figures
Figure 1. Pin Assignments for 5 5 0.8 mm 32-LGA – Top View...................................................................................................................5
Figure 2. Typical TX Input Power and Reduced Exposed Pad Temperature Profile ..........................................................................................8
Figure 3. RX Mode Gain (High Gain)................................................................................................................................................................14
Figure 4. RX Mode Gain (Low Gain) ................................................................................................................................................................14
Figure 5. RX Mode Channel Isolation (High Gain)............................................................................................................................................14
Figure 6. RX Mode Channel Isolation (Low Gain) ............................................................................................................................................14
Figure 7. RX Mode Input Return Loss (High Gain)...........................................................................................................................................14
Figure 8. RX Mode Input Return Loss (Low Gain)............................................................................................................................................14
Figure 9. RX Mode Output Return Loss (High Gain)........................................................................................................................................15
Figure 10. RX Mode Output Return Loss (Low Gain).........................................................................................................................................15
Figure 11. RX Mode OP1dB vs. Frequency (High Gain) ....................................................................................................................................15
Figure 12. RX Mode OP1dB vs. Frequency (Low Gain).....................................................................................................................................15
Figure 13. RX Mode OIP3 vs. Frequency (High Gain)........................................................................................................................................15
Figure 14. RX Mode OIP3 vs. Frequency (Low Gain) ........................................................................................................................................15
Figure 15. TX Mode Switch Isolation (SWx_IN to RXx_OUT) ............................................................................................................................16
Figure 16. TX Mode Channel Isolation (Switch Inputs).......................................................................................................................................16
Figure 17. TX Mode Input Return Loss...............................................................................................................................................................16
Figure 18. Stability Factor...................................................................................................................................................................................16
Figure 19. RX Mode Noise Figure (High Gain)...................................................................................................................................................16
Figure 20. RX Mode Noise Figure (Low Gain)....................................................................................................................................................16
Figure 21. Switching Time from TX to RX Mode ................................................................................................................................................17
Figure 22. Switching Time from RX to TX Mode ................................................................................................................................................17
Figure 23. Standby to RX Mode Transient Time ................................................................................................................................................17
Figure 24. RX Mode to Standby Transient Time ................................................................................................................................................17
Figure 25. 6dB Gain Reduction Transient Time .................................................................................................................................................17
Figure 26. 6dB Gain Increase Transient Time....................................................................................................................................................17
Figure 27. Electrical Schematic ..........................................................................................................................................................................19
Figure 28. Evaluation Kit: Top View....................................................................................................................................................................20
Figure 29. Evaluation Kit: Bottom View ..............................................................................................................................................................20
Figure 30. Electrical Schematic ..........................................................................................................................................................................21
Figure 31. Standby and Switch Control Logic.....................................................................................................................................................23
Figure 32. Control Pin Interface Schematic........................................................................................................................................................24
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May 7, 2019
List of Tables
Table 1. Pin Descriptions...................................................................................................................................................................................6
Table 2. Absolute Maximum Ratings.................................................................................................................................................................7
Table 3. Recommended Operating Conditions .................................................................................................................................................8
Table 4. Electrical Characteristics .....................................................................................................................................................................9
Table 5. Electrical Characteristics: RX Path in RX Mode Cascaded Performance .........................................................................................11
Table 6. Electrical Characteristics: RX Path in RX Mode Cascaded Performance and TX Performance .......................................................12
Table 7. Thermal Characteristics.....................................................................................................................................................................13
Table 8. Gain Step Truth Table .......................................................................................................................................................................18
Table 9. Standby and RF Switch Truth Table..................................................................................................................................................18
Table 10. Bill of Material (BOM) ........................................................................................................................................................................22
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May 7, 2019
Pin Assignments
Figure 1. Pin Assignments for 5 5 0.8 mm 32-LGA – Top View
ATT1_CTRL
1
GND
SW1_IN
GND
NC
24
23
22
21
20
19
18
17
STBY1
2
SW1_CTRL
GND
3
4
5
6
7
8
GND
NC
SW2_CTRL
STBY2
GND
SW2_IN
GND
ATT2_CTRL
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May 7, 2019
Pin Descriptions
Table 1.
Pin Descriptions
Number
Name
Description
1-bit 6dB gain control for path 1. (LOW/open = no attenuation; HIGH = 6dB attenuation). A 500kΩ pull-down
resistor is connected between this input and GND.
1
2
ATT1_CTRL
STBY1
Standby (LOW/open = path 1 power ON; HIGH = path 1 power OFF). A 500kΩ pull-down resistor is connected
between this input and GND.
RF SWITCH 1 control (LOW/open = select main RX PATH 1; HIGH = switch output). SW1_CTRL also puts path
3
SW1_CTRL 1 into Standby Mode for minimum current consumption. A 500kΩ pull-down resistor is connected between this
input and GND.
4, 5, 9, 11,
13, 15, 17,
19, 22, 24,
GND
Ground these pins.
26, 28, 30, 32
RF SWITCH 2 control (LOW/open = select main RX PATH 2; HIGH = switch output). SW2_CTRL also puts path
6
7
SW2_CTRL 2 into Standby Mode for minimum current consumption. A 500kΩ pull-down resistor is connected between this
input and GND.
Standby (LOW/open = path 2 power ON; HIGH = path 2 power OFF). A 500kΩ pull-down resistor is connected
between this input and GND.
STBY2
1-bit 6dB gain control for path 2. (LOW/open = no attenuation; HIGH = 6dB attenuation). A 500kΩ pull-down
resistor connects between this input and GND.
8
10
ATT2_CTRL
RX2_OUT
VDD
RF output path 2 matched to 50Ω. Use external DC block as close to the pin as possible.
Power supply. Bypass to GND with capacitors shown in the F0452B Application Circuit (see Figure 30) as close
as possible to the pins.
12, 14, 27, 29
RF2 switch output matched to 50Ω. Use external 50Ω terminating resistor with proper power rating as required
for the application.
16
SW2_OUT
18
23
SW2_IN
SW1_IN
RF2 switch input matched to 50Ω. Use an external DC block as close to the pin as possible.
RF1 switch input matched to 50Ω. Use an external DC block as close to the pin as possible.
RF1 switch output matched to 50Ω. Use an external 50Ω terminating resistor with proper power rating as
required for the application.
25
SW1_OUT
31
RX1_OUT
NC
RF output path 1 matched to 50Ω. Use an external DC block as close to the pin as possible.
20, 21
Not internally connected.
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground
vias to provide heat transfer out of the device into the PCB ground planes. These multiple via grounds are also
required to achieve the specified RF performance.
— EPAD
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May 7, 2019
Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
VDD
Minimum
-0.3
Maximum
+3.6
Units
VDD to GND
V
V
STBY1, STBY2, ATT1_CTRL, ATT2_CTRL, SW1_CTRL, SW2_CTRL to GND
VCTRL
-0.3
VDD + 0.25
SW1_IN, SW2_IN, RX1_OUT, RX2_OUT, SW1_OUT, SW2_OUT to GND
Externally Applied DC Voltage
VSW
-50
50
mV
TX Mode CW Average Input Power +7.5dB PAR at SW1_IN, SW2_IN Ports,
10s, 89% Duty Cycle
PABS_TX
+31
+33 [b]
dBm
50Ω, TEPAD = 105°C [a], VDD = +3.3V
RX Mode Average Input Power +7.5dB PAR at SW1_IN, SW2_IN Ports,
1 Hour Single Event, 50% Duty Cycle
PABS_RX
+8
dBm
50Ω, TEPAD = 105°C [a], VDD = +3.3V
Storage Temperature Range
TST
-65
+150
+260
°C
°C
Lead Temperature (soldering, 10s)
TLEAD
Electrostatic Discharge – HBM
1500
VESDHBM
V
V
(JEDEC/ESDA JS-001-2012)
(Class 1C)
Electrostatic Discharge – CDM
(JEDEC JS-002-2014)
500
VESDCDM
(Class C2A)
ALL pins except pins 16, 18, 23, 25
Electrostatic Discharge – CDM
(JEDEC JS-002-2014)
Pins 16, 18, 23, 25
125
VESDCDM
V
(Class C0B)
[a] TEPAD = Temperature of the exposed paddle.
[b] RF input exposures greater than +31dBm and up to +33dBm for multiple extended periods will affect device reliability and lifetime if the maximum
recommended input junction temperature is exceeded.
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May 7, 2019
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Minimum
3.15
Typical
Maximum
3.45
Units
V
Power Supply Voltage
VDD
3.3
Operating Temperature Range
RF Frequency Range
TEPAD
fRF
Exposed Paddle
-40
+105
°C
2.3
2.7
GHz
TX Mode CW Average Input Power,
+7.5dB PAR, Full Life Time [a]
PMAX_TX
89% Duty Cycle
89% Duty Cycle
+30[b]
-25
dBm
dBm
50Ω, VDD = +3.3V
RX Mode CW Average Input Power,
+7.5dB PAR, Full Life Time [a]
PMAX_RX
50Ω, VDD = +3.3V
Port Impedance (SW1_IN, SW2_IN,
RX1_OUT, RX2_OUT)
ZRF
TJ
50
Ω
Junction Temperature
+125
°C
[a] Assumes device environmental temperature cycling within the specified exposed pad operating temperature range of -40°C and 105°C and a
maximum junction temperature of 125°C.
[b] Operation beyond the maximum recommended operating input power level should be limited and have reduced exposed pad temperatures to
maintain device reliability per foundry guidelines (see Figure 2). Electrical characteristics and lifetime are not guaranteed for RF input power
levels beyond what is specified in this table.
Figure 2. Typical TX Input Power and Reduced Exposed Pad Temperature Profile
Note: This graph estimates the maximum input power without exceeding the maximum junction temperature of 125°C using an IDT-specific evaluation board
and test environment.
Average Input Power +7.5dB PAR
35
34
33
32
31
30
29
28
27
26
25
60
65
70
75
80
85
90
95 100 105 110 115
Exposed Pad Temperature (°C)
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May 7, 2019
Electrical Characteristics
Table 4.
Electrical Characteristics
See F0452B Application Circuit in Figure 30. Specifications apply when operated as an RX RF amplifier with VDD = +3.3V, TEPAD = +25°C,
STBYx = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Lower of
(VDD, 3.3)
Logic Input High Threshold
VIH
1.17[a]
V
Logic Input Low Threshold
Logic Current
VIL
-0.3
0.63
10
V
IIH, IIL
For each control pin
2 paths in RX Mode
-10
µA
130
70
180
1 path in RX Mode
1 path in TX Mode
100
1 path in RX Mode
DC Current
IDD
67
5
mA
1 path in Standby Mode
1 path in TX Mode
1 path in Standby Mode
2 paths in Standby Mode
5
6
Gain Step
GSTEP
dB
dB
Relative to maximum gain,
over-voltage, and temperature
Gain Step Absolute Error
Relative Phase Gain Step
Gain Step Settling Time [b]
GSTEP_ERR
GSTEP_PH
GSTEP_SET
±0.5
28
deg
ns
50% control logic to RF output
within ±0.1dB of final value
20
31
30
50% control logic to RF output
within ±1 degree of final value
Gain Step Phase Settling Time [b]
Power ON Switching Time [b]
GSTEP_PHSET
16
ns
To RX Mode from TX Mode
50% control logic to RF output
settled to within ±0.1dB of final
value
SWON
1
µs
To TX Mode from RX Mode
50% control logic to RF input
settled within ±0.1dB of final
value
Power OFF Switching Time [b]
SWOFF
0.5
µs
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May 7, 2019
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
To RX Mode from Standby
Mode
Power ON from Standby Mode [b]
SWON_STANDBY
1
1
µs
50% STBYx to RF output
settled within ±0.1dB of final
value
To Standby Mode from RX
Mode
Power OFF to Standby Mode [b]
SWOFF_STANDBY
µs
50% STBYx to gain below
-25dB from maximum gain
[a] Items in the “Minimum”/“Maximum” columns in bold italics are guaranteed by test. Items in the “Minimum”/“Maximum” columns not in bold italics
are guaranteed by design characterization.
[b] fRF = 2.6GHz. Assumes the control signal is clean and no external RC circuitry is required on the pin. Adding RC circuitry increases switching
time. Timing tests performed with a control logic signal of +3.3V and a rise/fall time ≤ 30ns.
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May 7, 2019
Table 5.
Electrical Characteristics: RX Path in RX Mode Cascaded Performance
See the F0452B Application Circuit in Figure 30. Specifications apply when operated as an RX RF amplifier with VDD = +3.3V, fRF = 2.6GHz,
TEPAD = +25°C, STBYx = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless
otherwise noted.
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Measured at SW1_IN, SW2_IN,
High/Low Gain Mode,
12 [a]
fRF = 2.4GHz
Measured at SW1_IN, SW2_IN,
High/Low Gain Mode,
Input Return Loss
RLIN
20
dB
fRF = 2.6GHz
Measured at SW1_IN, SW2_IN,
High/Low Gain Mode,
6
fRF = 2.3GHz to 2.7GHz
Measured at RX1_OUT,
RX2_OUT,
Output Return Loss
RLOUT
7
dB
dB
High/Low Gain Modes,
fRF = 2.3GHz to 2.7GHz
Reverse Isolation, RX1_OUT to
SW1_IN, or RX2_OUT to SW2_IN
ISOREV
fRF = 2.3GHz to 2.7GHz
50
58
34
GHG
GHG_TEMP
GLG
High Gain Mode
32
31
37
38
Gain
dB
dB
TEPAD = -40°C to 105°C
Low Gain Mode
Gain Attenuated
25.5
28
31.5
fRF = 2.3GHz to 2.7GHz
(Difference between maximum
and minimum gain in each
100MHz subrange within the
specified frequency range)
Gain Ripple
Noise Figure
GRIPPLE
±0.75
dB
dB
Measured at antenna port
ideally matched to LNA
1.5
1.5
1.7
2.3
NF
TEPAD = 105°C
Low Gain Mode
[a] Items in the “Minimum”/“Maximum” columns in bold italics are guaranteed by test. Items in the “Minimum”/“Maximum” columns NOT in bold italics
are guaranteed by design characterization.
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May 7, 2019
Table 6.
Electrical Characteristics: RX Path in RX Mode Cascaded Performance and TX Performance
See the F0452B Application Circuit in Figure 30. Specifications apply when operated as an RX RF amplifier with VDD = +3.3V, fRF = 2.6GHz,
TEPAD = +25°C, STBYx = LOW, RX output power = -10dBm, ZS = ZL = 50Ω, and EVKit trace and connector losses are de-embedded unless
otherwise noted.
Parameter
Symbol
Condition
Pout = 0dBm/tone
Minimum
Typical
Maximum
Units
OIP31
23[a]
5MHz tone separation
Pout = 0dBm/tone
OIP32
OIP33
5MHz tone separation
TEPAD = -40°C to 105°C
20
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
Output Third-Order Intercept Point
dBm
23
Pout = 0dBm/tone
5MHz tone separation
Low Gain Mode
OIP34
18
TEPAD = -40°C to 105°C
OP1dB1
OP1dB2
OP1dB3
OP1dB4
High Gain Mode [b]
13
11
15
14
High Gain Mode
TEPAD = -40°C to 105°C
Output 1dB Compression
dBm
Low Gain Mode
Low Gain Mode
10
40
TEPAD = -40°C to 105°C
RFISO1 = (푅푋1_푂푈푇
)
푅푋2_푂푈푇
푑퐵
with -60 ≤ SW1_IN ≤ -30dBm
Channel Isolation
ISOCH
50
65
dB
dB
RFISO2 = (푅푋2_푂푈푇
)
푅푋1_푂푈푇
푑퐵
with -60 ≤ SW2_IN ≤ -30dBm
TX Mode
RF Switch Isolation
ISOSW
55
Measured at SW_IN to
RX_OUT of the same channel
[a] Items in the “Minimum”/“Maximum” columns in bold italics are guaranteed by test. Items in the “Minimum”/“Maximum” columns not in bold italics
are guaranteed by design characterization.
[b] In the OP1dB calculation formula, “G” denotes the gain of each part instance at the frequency of interest and appropriate HIGH / LOW gain state.
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May 7, 2019
Thermal Characteristics
Table 7.
Thermal Characteristics
Parameter
Symbol
Value
Units
θJA
Junction-to-Ambient Thermal Resistance
43
°C/W
Junction-to-Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC_BOT
11.7
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL3
Typical Operating Conditions
Unless otherwise noted:
.
.
.
.
.
.
VDD = +3.3V
TEPAD = 25°C
ZL = ZS = 50Ω single-ended with matching networks
STBY1 = STBY2 = LOW or open
SW_CTRL = LOW or open
Gain Setting = High Gain Mode
.
PIN ≤ -30dBm
.
.
All temperatures are referenced to the exposed paddle
Evaluation kit traces and connector losses are de-embedded
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May 7, 2019
Typical Performance Characteristics: Part 1
Figure 3. RX Mode Gain (High Gain)
Figure 4. RX Mode Gain (Low Gain)
40
38
36
34
32
30
28
26
40
38
36
34
32
30
28
26
24
22
20
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
24
22
20
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Frequency(GHz)
Frequency(GHz)
Figure 5. RX Mode Channel Isolation
Figure 6. RX Mode Channel Isolation
(High Gain)
(Low Gain)
70
70
65
60
55
50
45
40
65
60
55
50
45
40
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
35
30
35
30
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Frequency(GHz)
Frequency(GHz)
Figure 7.
RX Mode Input Return Loss (High Gain)
Figure 8.
RX Mode Input Return Loss (Low Gain)
0
-5
0
-5
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
-40
2
-40
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Frequency(GHz)
Frequency(GHz)
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May 7, 2019
Typical Performance Characteristics: Part 2
Figure 9.
RX Mode Output Return Loss
(High Gain)
Figure 10. RX Mode Output Return Loss
(Low Gain)
0
-5
0
-5
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
+25 C, +3.15 V
+105 C, +3.15 V
-10
-15
-20
-25
-10
-15
-20
-25
-30
-30
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2.8
2.8
Frequency(GHz)
Frequency(GHz)
Figure 11. RX Mode OP1dB vs. Frequency
(High Gain)
Figure 12. RX Mode OP1dB vs. Frequency
(Low Gain)
20
20
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
19
18
17
16
15
14
13
12
11
10
19
18
17
16
15
14
13
12
11
10
2.3
2.4
2.5
2.6
2.7
2.8
2.3
2.4
2.5
2.6
2.7
Frequency(GHz)
Frequency(GHz)
Figure 13. RX Mode OIP3 vs. Frequency
(High Gain)
Figure 14. RX Mode OIP3 vs. Frequency
(Low Gain)
30
30
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
29
28
27
26
25
24
23
22
21
20
29
28
27
26
25
24
23
22
21
20
2.3
2.4
2.5
2.6
2.7
2.8
2.3
2.4
2.5
2.6
2.7
Frequency(GHz)
Frequency(GHz)
15
May 7, 2019
Typical Performance Characteristics: Part 3
Figure 15. TX Mode Switch Isolation
(SWx_IN to RXx_OUT)
Figure 16. TX Mode Channel Isolation
(Switch Inputs)
100
90
100
90
80
70
60
50
40
80
70
60
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
50
40
+25 C, +3.30 V
+105 C, +3.30 V
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3
3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
10
3
Frequency(GHz)
Frequency(GHz)
Figure 17. TX Mode Input Return Loss
Figure 18. Stability Factor
0
1000
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-5
-10
-15
-20
-25
-30
100
10
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
+25 C, +3.30 V
+105 C, +3.30 V
1
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
0
1
2
3
4
5
6
7
8
9
Frequency(GHz)
Frequency(GHz)
Figure 19. RX Mode Noise Figure (High Gain)
Figure 20. RX Mode Noise Figure (Low Gain)
4
4
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
-40 C, +3.15 V
+25 C, +3.15 V
+105 C, +3.15 V
-40 C, +3.30 V
+25 C, +3.30 V
+105 C, +3.30 V
-40 C, +3.45 V
+25 C, +3.45 V
+105 C, +3.45 V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
2
2.2
2.4
2.6
2.8
2
2.2
2.4
2.6
2.8
Frequency(GHz)
Frequency(GHz)
16
May 7, 2019
Typical Performance Characteristics: Part 4
Figure 21. Switching Time from TX to RX Mode
Figure 23. Standby to RX Mode Transient Time
Figure 25. 6dB Gain Reduction Transient Time
Figure 22. Switching Time from RX to TX Mode
Figure 24. RX Mode to Standby Transient Time
Figure 26. 6dB Gain Increase Transient Time
17
May 7, 2019
Programming
Table 8.
Gain Step Truth Table
ATT1_CTRL, ATT2_CTRL
Attenuation Setting
LOW or Open
0dB
6dB
HIGH
Table 9.
Standby and RF Switch Truth Table
In TX Mode, the amplifiers are OFF but the bias will remain ON for fast turn-on recovery time.
STBY1, STBY2
LOW or Open
LOW or Open
HIGH
SW1_CTRL, SW2_CTRL
LOW or Open
MODE
RX
Amplifier State
ON
OFF
OFF
HIGH
TX
HIGH or LOW or Open
STANDBY
18
May 7, 2019
Typical Application Circuit
Figure 27 is a typical circuit (minimum components) that can be used in a design for the F0452B by the customer.
Figure 27. Electrical Schematic
VDD
C12
C14
C13
C18
C11
C17
J2
J3
RX1_OUT
SW1_OUT
GND
J1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SW1_IN
ATT1_CTRL
STBY1
SW1_CTRL
ATT1_CTRL
STBY1
SW1_CTRL
GND
GND
SW2_CTRL
STBY2
ATT2_CTRL
GND
SW1_IN
GND
U1
GND
GND
GND
SW1_CTRL
STBY2
ATT2_CTRL
SW2_IN
GND
J4
GND
SW2_IN
J5
J6
C19
C7
C20
C9
SW2_OUT
RX2_OUT
C8
C10
VDD
19
May 7, 2019
Evaluation Kit Picture
Figure 28. Evaluation Kit: Top View
TBD
TBD
Figure 29. Evaluation Kit: Bottom View
20
May 7, 2019
Evaluation Kit / Applications Circuit
Figure 30. Electrical Schematic
VDD
R8
J9
TP1
VDD
VDD
VDD
C14
C15
R7
C12
C16
SW1
TP2
C13
C18
C11
C17
GND
SW DIP-8
J2
J3
RX1_OUT
SW1_OUT
J10
R1
R2
R3
R4
R5
R6
C1
C2
C3
C4
C5
C6
GND
J7
J1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SW1_IN
ATT1_CTRL
STBY1
SW1_CTRL
GND
GND
SW2_CTRL
STBY2
GND
SW1_IN
GND
GND
GND
GND
SW2_IN
GND
U1
J4
ATT2_CTRL
HEADER 8
GND
SW2_IN
J11
J5
J6
C19
C7
C20
C9
SW2_OUT
RX2_OUT
C8
C10
VDD
21
May 7, 2019
Table 10. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1, C6
0
4
4
4
1
1
1
4
1
1
8
1
1
DNP
C2 - C5
CAP CER 100pF 50V 5% NP0 (0402)
CAP CER 10000pF 50V 10% X7R (0402)
CAP CER 1µF 10V 10% X5R (0402)
CAP CER 10000pF 50V 5% C0G/NP0 (0603)
CAP CER 8.0pF ±0.1pF 50V NP0 (0402)
0Ω ±1%, 1/10W, Resistor (0402)
GRM1555C1H101JA01D
GRM155R71H103KA88D
GRM155R61A105KE15D
GRM1885C1H103JA01D
GJM1555C1H8R0BB01D
ERJ-2RKF0000X
Murata
Murata
C7, C9, C11, C13
C8, C10, C12, C14
Murata
C15
C17-C20
R1, R6
R2-R5
R7
Murata
Murata
Panasonic
Panasonic
Panasonic
Panasonic
Cinch Connectivity
3M
100Ω ±1%, 1/10W, Resistor (0402)
1kΩ ±1%, 1/10W, Resistor (0402)
1.3kΩ ±1%, 1/10W, Resistor (0402)
SMA Edge Mount
ERJ-2RKF1000X
ERJ-2RKF1001X
R8
ERJ-2RKF1301X
J1- J6, J10, J11
J7
142-0761-881
CONN HEADER VERT SGL 8POS GOLD
CONN SMA JACK STR 50OHM EDGE MNT
961108-6404-AR
J9
142-0701-851
Cinch Connectivity
TP1, TP2
SW1
1
1
1
8 Pin DIP Switch (3 POS)
Dual Path RF Switch + LNA + DVGA 5X5 LGA
Printed Circuit Board
KAT1108E
F0452BLEGK
E-Switch
IDT
U1
F0453 EVKIT Stripline R2
22
May 7, 2019
Evaluation Kit Operation
TBD
Mode Control Setup
There are three operation modes as described in Table 9: RX Mode, TX Mode, and Standby Mode. Based on each mode, set up the standby
pins and switch control pins as described in Table 9. The standby and switch control logic are shown in Figure 31.
Figure 31. Standby and Switch Control Logic
Power-On Procedure
Set up the voltage supplies and Evaluation Board so that the STBY1 and STBY2 pins are either open or connected to logic LOW, and then
enable the power supply.
Power-Off Procedure
Disable the power supply.
23
May 7, 2019
Application Information
Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to
fail. Supply voltage change or transients should have a slew rate smaller than 1V / 20µs. In addition, all control pins should remain at
0V (±0.3V) while the supply voltage ramps up or while it returns to zero.
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to control pins 1, 2, 3, 6, 7, and 8 shown in Figure 32.
Figure 32. Control Pin Interface Schematic
5 k
ATT1_CTRL
2 pF
5 k
STBY1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
2 pF
5 k
SW1_CTRL
2 pF
5 k
SW2_CTRL
2 pF
5 k
STBY2
2 pF
5 k
ATT2_CTRL
2 pF
24
May 7, 2019
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/leg32-package-outline-50-x-50-mm-body-08-mm-thick-05mm-pitch-lga
Ordering Information
Orderable Part Number
Package
MSL Rating
MSL3
Shipping Packaging
Temperature
-40° to +105°C
-40° to +105°C
F0452BLEGK
Tray
Reel
5.0 5.0 0.8 mm 32-LGA
5.0 5.0 0.8 mm 32-LGA
F0452BLEGK8
F0452BEVB
MSL3
Evaluation Board
Marking Diagram
.
Lines 1 and 2 indicate the part number
Line 3 indicates the following:
“#” denotes stepping
IDTF04
52BLEGK
#YYWW$
.
“YY” is the last two digits of the year; “WW” is the work week number when the part was assembled.
“$” denotes the mark code.
.
Line 4 is the lot number
LOT
25
May 7, 2019
Revision History
Revision Date
Description of Change
May 7, 2019
Initial release.
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