F2911NBGP8 [RENESAS]
75Ω SPST RF Switch 1MHz to 3500MHz;
| 型号： | F2911NBGP8 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 75Ω SPST RF Switch 1MHz to 3500MHz |
| 文件： | 总19页 (文件大小：1461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
75Ω SPST RF Switch
1MHz to 3500MHz
F2911
Datasheet
Description
Features
.
.
.
.
.
.
Low insertion loss: 0.33dB at 1200MHz
The F2911 is a high reliability, low insertion loss, 75Ω SPST RF
switch designed for a multitude of wireless and RF applications.
This device covers a broad frequency range from 1MHz to
3500MHz. In addition to providing low insertion loss, the F2911
also delivers excellent linearity and isolation performance while
providing a 75Ω termination on one port in the isolation mode.
High isolation: 53dB at 1200MHz
Supply voltage: +2.7V to +5.5V
1.8V and 3.3V compatible control logic
-40°C to +105°C operating temperature range
2mm x 2mm, 8-pin DFN package
The F2911 uses a single positive supply voltage supporting either
3.3V or 1.8V control logic.
Block Diagram
Figure 1. Block Diagram
Competitive Advantage
The F2911 provides broadband RF performance to support the
CATV market along with high power handling, and high isolation.
V1
VDD
.
.
.
.
Low insertion loss
High isolation
Excellent linearity
Control
Circuit
Extended temperature range
RF2
RF1
Typical Applications
.
.
.
.
.
CATV Infrastructure
CATV Set-Top Boxes
CATV Satellite Modems
Data Network Equipment
Fiber Networks
75Ω
1
Rev O, September 21, 2017
Pin Assignments
Figure 2. Pin Assignments for 2mm x 2mm x 0.9mm 8-DFN – Top View
VDD
V1
RF1
RF2
8
7
6
5
EP
F2911
1
2
3
4
GND
GND
NC
NC
Pin Descriptions
Table 1.
Pin Descriptions
Pin
Name
Function
1, 4
NC
No internal connection. This pin may be connected to the exposed paddle and can be grounded.
Ground. This pin is internally connected to the ground paddle. Ground this pin as close to the device as
possible.
2, 3
5
GND
RF1
RF1 port. This pin is matched to 75 in the insertion loss state only. If this pin is not 0V DC, then an
external coupling capacitor must be used.
6
7
8
VDD
V1
Power supply. Bypass to GND with capacitors as shown in the Figure 16 as close as possible to pin.
Logic control pin. See Table 7 for proper logic setting.
RF2
RF2 port. Matched to 75Ω. If this pin is not 0V DC, then an external coupling capacitor must be used.
Exposed pad. This pad is internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to provide heat transfer out of the device and into the PCB ground planes. These
multiple ground vias are also required to achieve the specified RF performance.
EP
2
Rev O, September 21, 2017
Absolute Maximum Ratings
Stresses beyond those listed below may cause permanent damage to the device. Functional operation of the device at these or any other
conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 2.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
VDD to GND
V1 to GND
VDD
-0.3
+6.0
V
Lower of
(VDD + 0.3V, 3.6V)
VLOGIC
VRF
-0.3
-0.3
V
V
RF1, RF2 to GND
+0.3
RF1 or RF2 as input
(Insertion loss state)
PRFCW12
31
RF Input Power, CW
ZS = ZL = 75Ω
TEP = 25°C [a]
RF1 as input
(Isolation state)
PRF1CW_ISO
PRF2CW_ISO
PRFPK12
21
28
34
24
31
dBm
dBm
VDD = +3.3V
RF2 as input
(Isolation state)
RF1 or RF2 as input
(Insertion loss state)
RF Input Power, Peak
ZS = ZL = 75Ω
TEP = 25°C [a], [b]
VDD = +3.3V
RF1 as input
(Isolation state)
PRF1PK_ISO
PRF2PK_ISO
RF2 as input
(Isolation state)
Maximum Junction Temperature
Storage Temperature Range
TJMAX
TSTOR
TLEAD
+140
+150
+260
°C
°C
°C
-65
Lead Temperature (soldering, 10s)
ElectroStatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
2000
(Class 2)
VESDHBM
VESDCDM
V
V
ElectroStatic Discharge – CDM
(JEDEC 22-C101F)
1000
(Class C3)
a. TEP = Temperature at the exposed paddle (see Table 3).
b. 5% duty cycle of a 4.6ms period.
3
Rev O, September 21, 2017
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
Condition
Min
Typical
Max
Units
Power Supply Voltage
Operating Temperature Range
RF Frequency Range
VDD
TEP
fRF
2.7
-40
1
5.5
+105
3500
28
25
18
15
25
22
31
V
Exposed paddle temperature
OC
MHz
RF1 or RF2 as the input
(Insertion loss state)
TEP = 85ºC
TEP = 105ºC
TEP = 85ºC
TEP = 105ºC
TEP = 85ºC
TEP = 105ºC
TEP = 85ºC
TEP = 105ºC
TEP = 85ºC
TEP = 105ºC
TEP = 85ºC
TEP = 105ºC
RF1 as the input
(Isolation state)
RF Input CW Power
(Non-Switched) [a]
PRFCW
dBm
RF2 as the input
(Isolation state)
RF1 or RF2 as the input
(Insertion loss state)
RF1 as the input
(Isolation state)
28
21
18
28
RF Input Peak Power
(Non-Switched) [a] , [b]
PRFPK
dBm
dBm
RF2 as the input
(Isolation state)
Applied to RF2 and
switching between
insertion loss to isolation
state
25
TEP = 85ºC
22
RF Continuous
Input Power
(RF Hot Switching CW) [a]
PRFSW
TEP = 105ºC
19
RF1/2 Port Impedance
RF2 Port Impedance
ZRFx
ZRFx
Insertion loss state
Isolation state
75
75
Ω
Ω
a. Levels based on: VDD = +2.7V to +5.5V, 1MHz ≤ fRF ≤ 3500MHz, ZS = ZL = 75Ω. See Figure 3 for power handling derating vs.
RF frequency.
b. 5% duty cycle of a 4.6ms period.
Figure 3. Maximum RF Input Operating Power vs. RF Frequency (ZS = ZL = 75Ω)
40
Cond 1: Maximum Continuous Operating CW Power, RF1 or RF2 Port, I.L. State ,TEP = 105 C
Cond 2: Maximum Continuous Operating CW Power, RF2 Port, Isolation State, TEP = 105 C
Cond 3: Maximum Continuous Operating Hot Switching CW Power, RF2 Port, TEP = 105 C
35
30
25
20
15
10
5
Cond 1
Cond 2
Cond 3
0
-5
0.01
0.1
1
10
100
1000
Frequency (MHz)
4
Rev O, September 21, 2017
Electrical Characteristics
Table 4.
Electrical Characteristics
See the F2911 Typical Application Circuit. Specifications apply when operated with VDD = +3.3V, TEP = +25°C, fRF = 1000MHz,
driven port = RF2, PIN = 0dBm, ZS = ZL = 75Ω. PCB board trace and connector losses are de-embedded unless otherwise noted.
Parameter
Logic Input High
Symbol
Condition
+2.7V ≤ VDD ≤ +5.5V
Min
Typical
Max
Units
Lower of
(VDD, 3.6)
0.6
VIH
1.1 [a]
V
Logic Input Low
Logic Current
VIL
IIH, IIL
-0.3 [b]
-1
V
µA
+1
VDD = 3.3V
VDD = 5.0V
190
230
0.24
0.26
0.29
0.31
0.33
0.39
0.39
0.89
84
304
DC Current
IDD
µA
1MHz ≤ fRF ≤ 50MHz [c]
50MHz < fRF ≤ 250MHz
250MHz < fRF ≤ 750MHz
750MHz < fRF ≤ 1000MHz
1000MHz < fRF ≤ 1200MHz
1200MHz < fRF ≤ 1800MHz [c]
1800MHz < fRF ≤ 2000MHz
2000MHz < fRF ≤ 3500MHz
1MHz ≤ fRF ≤ 50MHz
0.44
0.55
Insertion Loss
IL
dB
75
50MHz < fRF ≤ 250MHz
250MHz < fRF ≤ 750MHz
750MHz < fRF ≤ 1000MHz
1000MHz < fRF ≤ 1200MHz
1200MHz < fRF ≤ 1800MHz
1800MHz < fRF ≤ 2000MHz
2000MHz < fRF ≤ 3500MHz
1MHz ≤ fRF ≤ 50MHz
50MHz < fRF ≤ 250MHz
250MHz < fRF ≤ 750MHz
750MHz < fRF ≤ 1000MHz
1000MHz < fRF ≤ 1200MHz
1200MHz < fRF ≤ 1800MHz
1800MHz < fRF ≤ 2000MHz
2000MHz < fRF ≤ 3500MHz
1MHz ≤ fRF ≤ 50MHz
50MHz < fRF ≤ 250MHz
250MHz < fRF ≤ 750MHz
750MHz < fRF ≤ 1000MHz
1000MHz < fRF ≤ 1200MHz
1200MHz < fRF ≤ 1800MHz
1800MHz < fRF ≤ 2000MHz
2000MHz < fRF ≤ 3500MHz
70
59
55
53
46
45
35
33
32
27
25
23
20
20
10
27
27
25
23
22
20
20
11
Isolation
ISO
dB
dB
dB
RF1, RF2 Return Loss [d]
(Insertion Loss State)
RFRL
RF2 Return Loss [d]
(Isolation State)
RFRLISO
a. Items in min/max columns in bold italics are guaranteed by test (GBT).
b. Items in min/max columns that are not bold italics are guaranteed by design characterization (GBDC).
c. Maximum specification limit is GBT at 50MHz and 1.8GHz, and it is GBDC over the whole frequency range.
d. Return loss includes mismatch effects of the Evaluation Kit PCB and RF connectors.
5
Rev O, September 21, 2017
Electrical Characteristics
Table 5.
Electrical Characteristics
See the F2911 Typical Application Circuit. Specifications apply when operated with VDD = +3.3V, TEP = +25°C, fRF = 1000MHz,
driven port = RF2, PIN = 0dBm, ZS = ZL = 75Ω. PCB board trace and connector losses are de-embedded unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
fRF =1MHz
33
34
34
34
30
33
33
33
fRF = 10MHz
fRF = 2000MHz
fRF = 3500MHz
fRF = 1MHz
fRF = 10MHz
fRF = 2000MHz
fRF = 3500MHz
Input 1dB Compression [c]
ICP1dB
dBm
Input 0.1dB Compression [c]
ICP0.1dB
dBm
dBm
f1 = 5MHz
f2 = 6MHz
86
120
121
117
52
f1 = 185MHz
f2 = 190MHz
f1 = 895MHz
f2 = 900MHz
f1 = 1745MHz
f2 = 1750MHz
f1 = 5MHz
PIN = 13dBm/tone
f1+ f2 frequency
Input IP2 [d]
IIP2
f2 = 6MHz
f1 = 185MHz
f2 = 190MHz
f1 = 1790MHz
f2 = 1795MHz
f1 = 3490MHz
f2 = 3495MHz
64
Input IP3 [d]
IIP3
PIN = 13dBm/tone
dBm
66
64
-95
CTB / CSO
77 and 110 channels, POUT = 44dBmV
dBc
Out any RF port when externally
terminated into 75Ω
Non-RF Driven Spurious [e]
SpurMAX
-100
dBm
50% control to 90% RF
50% control to 10% RF
1.0
1.0
Switching Time [f]
TSW
µs
50% control to RF settled to within
+/- 0.1dB of I.L. value
1.1
25
Maximum Switching Rate
SWRATE
VIDFT
kHz
Peak transients during switching
Measured with 20ns rise time
0 to +3.3V control pulse
Maximum Video Feed-
Through on RF Ports
10
mVpp
a. Items in min/max columns in bold italics are guaranteed by test.
b. Items in min/max columns not in bold italics are guaranteed by design characterization.
c. The input 0.1dB and 1dB compression points are linearity figures of merit. Refer to the “Recommended Operating Conditions”
section and Figure 3 for the maximum operating power levels.
d. RF1 or RF2 driven IIP2 and IIP3 results when in the insertion loss state.
e. Spurious due to on-chip negative voltage generator. Spurious fundamental = approximately 5.7MHz.
f. fRF = 1GHz.
6
Rev O, September 21, 2017
Thermal Characteristics
Table 6.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
Junction to Ambient Thermal Resistance
θJA
160
°C/W
Junction to Case Thermal Resistance
(Case is defined as the exposed paddle)
θJC_BOT
15.1
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL1
Typical Operating Conditions (TOCs)
Unless otherwise noted:
.
.
.
.
.
.
.
.
VDD = +3.3V
TEP = 25°C
ZS = ZL = 75Ω
fRF = 1GHz
Small signal tests done at 0dBm input power.
RF2 is the driven port.
All temperatures are referenced to the exposed paddle.
Evaluation Kit (EVKit) traces and connector losses are de-embedded for the insertion loss and isolation plots. All other plots include the
loss and effects of the PCB.
7
Rev O, September 21, 2017
Typical Performance Characteristics [1]
Figure 4. RF2 to RF1 Insertion Loss vs.
Figure 5. RF2 to RF1 Isolation vs. Frequency
Frequency over Temp. and Voltage
over Temperature and Voltage
0
0
2.7V, -40C
2.7V, 25C
2.7V, 105C
3.3V, -40C
3.3V, 25C
3.3V, 105C
5.5V, -40C
5.5V, 25C
5.5V, 105C
-0.2
-0.4
-0.6
-0.8
-1
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-1.2
-1.4
-1.6
2.7V, -40C
2.7V, 25C
2.7V, 105C
3.3V, -40C
3.3V, 25C
3.3V, 105C
5.5V, -40C
5.5V, 25C
5.5V, 105C
-1.8
-2
0
1
2
3
4
4
4
0
1
2
3
4
Frequency (GHz)
Frequency (GHz)
Figure 6. RF1 Port On State Return Loss vs.
Figure 7. RF2 Port On State Return Loss vs.
Frequency over Temp. and Voltage
Frequency over Temp. and Voltage
0
0
2.7V, -40C
2.7V, 25C
2.7V, 105C
3.3V, -40C
3.3V, 25C
3.3V, 105C
5.5V, -40C
5.5V, 25C
5.5V, 105C
2.7V, -40C
2.7V, 25C
2.7V, 105C
3.3V, -40C
3.3V, 25C
3.3V, 105C
5.5V, -40C
5.5V, 25C
5.5V, 105C
-5
-10
-15
-20
-25
-30
-35
-40
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
0
1
2
3
4
Frequency (GHz)
Frequency (GHz)
Figure 8. RF2 Port Off State Return Loss vs.
Frequency over Temp. and Voltage
0
2.7V, -40C
2.7V, 25C
2.7V, 105C
3.3V, -40C
3.3V, 25C
3.3V, 105C
5.5V, -40C
5.5V, 25C
5.5V, 105C
-5
-10
-15
-20
-25
-30
-35
-40
0
1
2
3
Frequency (GHz)
8
Rev O, September 21, 2017
Typical Performance Characteristics [2]
Figure 9. Switching Time Isolation to Insertion
Loss State
Figure 10. Switching Time Insertion Loss to
Isolation State
Figure 11. EVKit PCB and Connector Thru Loss
Figure 12. EVKit PCB and Connector Return
vs. Frequency over Temperature
Loss vs. Frequency over Temp.
0
0
-40C
25C
105C
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-0.1
-0.2
-0.3
-0.4
-40C
25C
105C
-0.5
0
1
2
3
4
0
1
2
3
4
Frequency (GHz)
Frequency (GHz)
9
Rev O, September 21, 2017
Control Mode
Table 7.
Switch Control Truth Table
V1
LOW
HIGH
State
Isolation
Insertion Loss
RFC to RF2
RF1 port reflective, RF2 port matched to 75Ω
RF1 and RF2 port matched to 75Ω
Application Information
Default Start-up
The V1 control pin includes no internal pull-down resistors to logic LOW or pull-up resistors to logic HIGH.
Power Supplies
A common VDD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade the noise figure, and fast transients can trigger ESD clamps and cause them to
fail. Supply voltage change or transients should have a slew rate slower than 1V/20µs. In addition, all control pins should remain at 0V
(± 0.3V) while the supply voltage ramps up or while it returns to zero.
Control Pin Interface
If a clean control signal cannot be guaranteed due to overshoot, undershoot, or ringing, etc., the following circuit at the input of the control pin
is recommended.
Figure 13. Control Pin Signal Integrity Improvement Circuit
5kΩ
V1
2pF
EP
F2911
10
Rev O, September 21, 2017
Evaluation Kit Pictures
Figure 14. Top View
Figure 15. Bottom View
11
Rev O, September 21, 2017
Evaluation Kit / Applications Circuit
Figure 16. Electrical Schematic
12
Rev O, September 21, 2017
Table 8.
Bill of Material (BOM)
Part Reference
C1
QTY
Description
Manufacturer Part #
Manufacturer
1
4
1
1
2
4
1
0
0
1
1
0.1µF ±10%, 16V, X7R, Ceramic Capacitor (0402)
Not Installed (0402)
GRM155R71C104K
Murata
C2 – C5
R1
15kΩ ±1%, 1/10W, Resistor (0402)
18kΩ ±1%, 1/10W, Resistor (0402)
0Ω, 1/10W, Resistor (0402)
ERJ-2RKF1502X
ERJ-2RKF1802X
ERJ-2GE0R00X
531-40039
Panasonic
Panasonic
R2
R3, R4
J1 – J4
J5
Panasonic
F-Type Edge Mount
Amphenol
CONN HEADER VERT 4x2 POS GOLD
Not Installed (Red Test Point Loop)
Not Installed (Black Test Point Loop)
SPST Switch 2mm x 2mm 8-pin DFN
Printed Circuit Board
67997-108HLF
Amphenol FCI
TP1
TP2, TP3
U1
F2911NBGP
F2911EVBI
IDT
IDT
13
Rev O, September 21, 2017
Evaluation Kit (EVKit) Operation
External Supply Setup
Set up a main power supply in the voltage range of 2.7V to 5.5V with the power supply output disabled.
Connect the disabled power supply to J5 pin 1 (VCC) and ground to J5 pin 8 (GND).
Logic Control Setup
Using the EVKIT to set the control logic:
On connector J5, connect a 2-pin shunt from pin 3 (VCC) to pin 4 (VLOGIC). This connection allows the main power supply to power the
EVKit logic control network (R1 and R2). Resistors R1 and R2 form a voltage divider to set the VIH level over the 2.7V to 5.5V supply range for
manual logic control.
See Table 7 for Switch Control Truth Table states. With the logic control network enabled (as noted above), pin 5 can be left open to provide
a logic HIGH through pull-up resistor R1. To set a logic LOW for V1, connect a 2-pin shunt on J5 from pin 5 (V1) to pin 6 (GND).
Note that when using the on-board R1/R2 voltage divider, the current draw from the power supply will be higher by approximately the main
power supply voltage divided by 33kΩ.
Using external control logic:
Remove any jumpers from connector J5. Connect the disabled external logic control to V1 (pin 5) of connector J5. See Table 7 for the Switch
Control Truth Table settings. Note that even with the R1/R2 divider network disabled, R2 will still be a load (18kΩ to GND) for an external
control signal applied to V1.
Turn On Procedure / Operation
Setup the supplies and EVKit as noted in the External Supply Setup and Logic Control Setup sections above.
Enable the power supply.
If using the EVKIT to manually set the control logic: Set the logic setting to achieve the desired Table 7 configuration by placing a shunt
between J5 pins 5 and 6 for a logic LOW or leave pins 5 and 6 open for a logic HIGH.
If using the external control logic setup above: Enable the logic control signal. Set the logic signal level to achieve the desired Table 7
configuration. Note that external control logic should not be applied without the main power supply being present.
Turn Off Procedure
Set any external logic control to 0V.
Disable the main power supply.
14
Rev O, September 21, 2017
Package Drawings
Figure 17. Package Outline Drawing – NBG8P3 Package
15
Rev O, September 21, 2017
Recommended Land Pattern
Figure 18. Recommended Land Pattern – NBG8P3 Package
16
Rev O, September 21, 2017
Marking Diagram
Line 1 and 2 are the part number.
Line 3 - “Z” are for die version.
Line 3 - “412” is one digit for the year and week that the part was assembled.
Line 3 - “AKG” denotes the production process.
IDTF29
11NBGP
Z412AKG
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
F2911NBGP
F2911NBGP8
F2911EVBI
2mm x 2mm x 0.9mm 8-VFQFP-N
2mm x 2mm x 0.9mm 8-VFQFP-N
Evaluation Board
MSL1
MSL1
Cut Tape
Reel
-40°C to +105°C
-40°C to +105°C
17
Rev O, September 21, 2017
Revision History
Revision
Revision Date
Description of Change
Rev O
2017-Sept-21
Initial release.
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