HA1-2420-2/883 [RENESAS]
IC SAMPLE AND HOLD AMPLIFIER, 3.2 us ACQUISITION TIME, CDIP14, FRIT SEALED, CERAMIC, DIP-14, Sample and Hold Circuit;
| 型号： | HA1-2420-2/883 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC SAMPLE AND HOLD AMPLIFIER, 3.2 us ACQUISITION TIME, CDIP14, FRIT SEALED, CERAMIC, DIP-14, Sample and Hold Circuit 放大器 CD |
| 文件： | 总12页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-2420, HA-2425
®
Data Sheet
November 19, 2004
FN2856.6
3.2µs Sample and Hold Amplifiers
Features
The HA-2420 and HA-2425 is a monolithic circuit consisting
of a high performance operational amplifier with its output in
series with an ultra-low leakage analog switch and JFET
input unity gain amplifier.
• Maximum Acquisition Time
- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . 4µs (Max)
- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . 6µs (Max)
• Low Droop Rate (C = 1000pF). . . . . . . . . . 5µV/ms (Typ)
H
With an external hold capacitor connected to the switch
output, a versatile, high performance sample-and-hold or
track-and-hold circuit is formed. When the switch is closed,
the device behaves as an operational amplifier, and any of
the standard op amp feedback networks may be connected
around the device to control gain, frequency response, etc.
When the switch is opened the output will remain at its last
level.
• Gain Bandwidth Product . . . . . . . . . . . . . . . 2.5MHz (Typ)
• Low Effective Aperture Delay Time . . . . . . . . . 30ns (Typ)
• TTL Compatible Control Input
• ±12V to ±15V Operation
Applications
• 12-Bit Data Acquisition
• Digital to Analog Deglitcher
• Auto Zero Systems
• Peak Detector
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
• Gated Operational Amplifier
Pinout
HA-2420 (CERDIP)
HA-2425 (PDIP)
TOP VIEW
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc. For more information,
please see Application Note AN517..
-IN
+IN
1
2
3
4
5
6
7
14 S/H CONTROL
13 GND
Ordering Information
OFFSET ADJ.
OFFSET ADJ.
V-
12 NC
TEMP.
PKG.
DWG. #
11 HOLD CAP.
10 NC
o
PART NUMBER RANGE ( C)
PACKAGE
-55 to 125 14 Ld CERDIP
0 to 75 14 Ld PDIP
HA1-2420-2
HA3-2425-5
F14.3
E14.3
NC
9
8
V+
NC
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-2420, HA-2425
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
Digital Input Voltage (Sample and Hold Pin) . . . . . . . . . . +8V, -15V
Output Current . . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
75
95
20
N/A
o
Maximum Junction Temperature (Ceramic Packages). . . . . . . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
Operating Conditions
o
Temperature Range
HA-2420-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HA-2425-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
o
o
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±12V to ±15V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test Conditions (Unless Otherwise Specified) V
= ±15.0V; C = 1000pF; Digital Input: V = +0.8V
(Sample), V = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input)
SUPPLY
H
IL
IH
HA-2420-2
TYP
HA-2425-5
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Input Voltage Range
Offset Voltage
MIN
MAX
MIN
TYP
MAX
UNITS
Full
25
±10
-
2
-
4
±10
-
3
-
6
V
-
-
mV
mV
nA
nA
nA
nA
MΩ
V
Full
25
-
3
6
-
4
8
Bias Current
-
40
-
200
400
50
100
-
-
40
-
200
400
50
100
-
Full
25
-
-
Offset Current
-
-
10
-
-
-
10
-
Full
25
Input Resistance
5
10
-
5
10
-
Common Mode Range
Full
±10
-
±10
-
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Common Mode Rejection
R
= 2kΩ, V = 20V
P-P
Full
Full
Full
25
80
-
50
90
-
-
-
25
74
-
50
90
-
-
-
kV/V
dB
L
O
V
= ±10V
CM
Hold Mode Feedthrough Attenuation
(Note 2)
f
≤ 100kHz
-76
-76
dB
IN
Gain Bandwidth Product (Note 2)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
25
-
2.5
-
-
2.5
-
MHz
R
= 2kΩ
Full
25
±10
-
-
-
-
-
±10
-
-
-
-
-
V
mA
kHz
Ω
L
±15
-
±15
-
Full Power Bandwidth (Note 2)
Output Resistance
V
= 20V
25
-
-
100
0.15
-
-
100
0.15
O
P-P
DC
25
TRANSIENT RESPONSE
Rise Time (Note 2)
V
V
V
= 200mV
= 200mV
25
25
25
-
-
75
25
5
100
40
-
-
-
75
25
5
100
40
-
ns
%
O
O
O
P-P
P-P
Overshoot (Note 2)
Slew Rate (Note 2)
= 10V
3.5
3.5
V/µs
P-P
FN2856.6
2
November 19, 2004
HA-2420, HA-2425
Electrical Specifications Test Conditions (Unless Otherwise Specified) V
= ±15.0V; C = 1000pF; Digital Input: V = +0.8V
IL
(Sample), V = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued)
SUPPLY
H
IH
HA-2420-2
TYP
HA-2425-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
DIGITAL INPUT CHARACTERISTICS
Digital Input Current
MIN
MAX
MIN
MAX
UNITS
V
V
= 0V
Full
Full
Full
Full
-
-
-
-
-
-
-0.8
20
0.8
-
-
-
-
-
-
-
-0.8
20
0.8
-
mA
µA
V
IN
IN
= 5V
Digital Input Voltage
Low
High
SAMPLE AND HOLD CHARACTERISTICS
-
-
2.0
2.0
V
Acquisition Time (Note 2)
Acquisition Time (Note 2)
Hold Step Error
To 0.1% 10V Step
To 0.01% 10V Step
= 0V
25
25
-
-
-
-
-
-
-
-
-
-
-
2.3
3.2
10
860
30
30
5
4
6
20
-
-
-
-
-
-
-
-
-
-
-
-
2.3
3.2
10
860
30
30
5
4
µs
µs
6
V
25
20
mV
ns
IN
Hold Mode Settling Time
Aperture Time (Note 3)
Effective Aperture Delay Time
Aperture Uncertainty
Drift Current (Note 2)
HA1-2420
To ±1mV
25
-
25
-
-
ns
25
-
-
ns
25
-
-
-
ns
V
= 0V
25
5
-
5
pA
nA
nA
nA
IN
Full
Full
Full
1.8
-
10
-
-
-
HA1-2425
0.1
7.5
1.0
10.0
HA3-2425, HA4P2425,
HA9P2425
-
-
POWER SUPPLY CHARACTERISTICS
Supply Current (+)
25
25
-
-
3.5
2.5
90
5.5
3.5
-
-
-
3.5
2.5
90
5.5
3.5
-
mA
mA
dB
Supply Current (-)
Power Supply Rejection
NOTES:
Full
80
74
2. A = ±1, R = 2kΩ, C = 50pF.
V
L
L
3. Derived from computer simulation only; not tested.
Functional Diagram
OFFSET
ADJUST
V+
9
3
4
1
7
-
-INPUT
OUT
-
+
+
2
+INPUT
HA-2420/2425
14
S/H
CONTROL
11
13
GND
5
V-
HOLD
CAPACITOR
FN2856.6
3
November 19, 2004
HA-2420, HA-2425
Test Circuits and Waveforms
-IN
OUTPUT
HOLD
INPUT
S/H
CONTROL
S/H
CONTROL
HOLD
CAP
SAMPLE
+IN
GND
OUTPUT
C
H
V
STEP
S/H CONTROL
INPUT
NOTE: Set rise/fall times of S/H Control to approximately 20ns.
FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT
FIGURE 2. HOLD STEP ERROR TEST
+5V
EN
HI-508A
MUX
SINE WAVE
INPUT
IN2
IN1
IN3
IN4
IN5
IN6
IN7
IN8
A2
HA-2420/2425
-IN
V
O
OUT
GND
+IN
OUT
S/H
HOLD
HOLD
S/H
CONTROL CAP
CONTROL
SAMPLE
C
V
H
INP-P
OUTPUT
A0
A1
∆V
S/H CONTROL INPUT
∆t
NOTE: Compute hold mode feedthrough attenuation from the formula:
V
HOLD
OUT
----------------------------------
Feedthrough Attenuation = 20log
V
HOLD
IN
NOTE: Measure the slope of the output during hold, ∆V/∆t,
and compute drift current from: I = C ∆V/∆t.
Where V
sinewave during the hold mode.
HOLD = Peak-to-Peak value of output
OUT
D
H
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
FIGURE 3. DRIFT CURRENT TEST
FN2856.6
November 19, 2004
4
HA-2420, HA-2425
Schematic Diagram
OFFSET ADJ.
V+
R
R
Q
Q
1
2
64
Q
89
J
63
Q
Q
58
Q
29
Q
Q
30
65
Q
Q
17
23
Q
5
Q
Q
106
90
Q
66
Q
2
Q
72
Q
4
82
59
Q
Q
Q
R
74
45
46
J
R
61
Q
P
73
Q
Q
Q
7
9
Q
91
Q
105
Q
87
Q
51
Q
Q
52
Q
15
Q
Q
6
C
7
Q
H
47
Q
Q
48
11
Q
53
Q
54
49
Q
50
27
D
1
Q
75
Q
19
Q
20
21
Q
8
Q
31
C
3
Q
R
32
15pF
9
Q
Q
100
R
8
OUT
Q
101
Q
Q
3
24
Q Q
33 34
Q
R
18
10
56
Q
25
Q
10
Q
Q
38
13
Q
77
S/H
Q
Q
35
76
CONTROL
Q
Q
55
22
Q
C
26
4
Q
Q
83
Q
69
67
GND
J
60
Q
68
R
121
Q
12
Q
14
GND
Q
78
J
86
R
11
Q
83
Q
Q
Q
39
40
Q
Q
79
70
J
Q
57
41
Q
103
Q
42
43
Q
102
Q
44
Q
Q
71
Q
80
62
Q
16
R
14
R
13
Q
81
-IN
+IN
V-
FN2856.6
November 19, 2004
5
HA-2420, HA-2425
Application Information
R
0.002R
OUT
F
F
INPUT
HOLD STEP VOLTAGE (mV)
+10
R
OUTPUT
I
-IN
S/H
CONTROL
5
+IN
-10
-5
+5
+10
–R
F
0
----------
NOTE: GAIN ∼
R
DC INPUT VOLTAGE (V)
S/H CONTROL INPUT
I
-5
C
= 0.1µF
H
FIGURE 6. INVERTING CONFIGURATION
-10
C
C
= 10,000pF
= 1000pF
H
H
-15
-20
-25
-30
-35
INPUT
OUTPUT
+IN
-IN
OUT
S/H
CONTROL
C
= 100pF
H
R
F
S/H CONTROL
INPUT
R
I
R
F
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
NOTE: GAIN ~ 1 + -------
0.002R
I
R
I
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100kΩ trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
FIGURE 7. NON-INVERTING CONFIGURATION
Figure 8 shows a typical unity gain circuit, with Offset
Zeroing. All of the other normal op amp feedback
configurations may be used with the HA-2420, HA-2425. The
input amplifier may be used as a gated amplifier by utilizing
Pin 11 as the output. This amplifier has excellent drive
capabilities along with exceptionally low switch leakage.
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
CONTROL
The linear variation in pedestal voltage with sample-and-hold
V+
input voltage causes a -0.06% gain error (C = 1000pF). In
H
C
H
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain
error at the sample-and-hold.
-
+
-
+
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
OUT
IN
100kΩ
V-
3. Adjust the trim pot for +10V output in the hold mode.
OFFSET TRIM (±25mV RANGE)
4. Apply the nominal input voltage that should produce a
-10V output.
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
5. Measure the output hold voltage (V
). Adjust
-10NOMINAL
the trim pot for an output hold voltage of
(V
) + (-10V)
–10NOMINAL
-----------------------------------------------------------------
2
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
o
85 C), Teflon, or Parlene types are recommended.
For more applications, consult Intersil Application Note
AN517, or the factory applications group.
FN2856.6
6
November 19, 2004
HA-2420, HA-2425
Effective Aperture Delay Time (EADT)
CONTROL
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
GND
-IN
HOLD
CAPACITOR
+IN
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to V at the instant the
IN
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will correspond to
a value of V that occurred before the Hold command.
IN
V-
OUT
Aperture Uncertainty
V+
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
Drift Current
Glossary of Terms
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
Acquisition Time
The time required following a “sample” command, for the output
to reach its final value within ±0.1% or ±0.01%. This is the
minimum sample time required to obtain a given accuracy, and
includes switch delay time, slewing time and settling time.
∆V
-------
(V ⁄ s)
I
(pA) = C (pF) ×
D
H
∆t
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
FN2856.6
7
November 19, 2004
HA-2420, HA-2425
Typical Performance Curves
1000
1000
MIN. SAMPLE TIME
DRIFT DURING HOLD
AT 25 C (mV/s)
EQUIV. INPUT NOISE
o
FOR 0.1% ACCURACY
“SAMPLE” MODE - 100kΩ
SOURCE RESISTANCE
10V SWINGS (µs)
100
10
OUTPUT NOISE
“HOLD” MODE
UNITY GAIN PHASE
MARGIN (DEGREES)
HOLD STEP
100
10
1
OFFSET
ERROR (mV)
1.0
UNITY GAIN
BANDWIDTH
(MHz)
EQUIV. INPUT NOISE
“SAMPLE” MODE - 0Ω
SOURCE RESISTANCE
0.1
SLEW RATE
(V/µs)
0.01
10pF
100pF
1000pF
0.01µF
0.1µF
1.0µF
10
100
1K
10K
100K
1M
C
VALUE
H
BANDWIDTH (LOWER 3dB FREQUENCY = 10Hz)
FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLDING CAPACITOR
FIGURE 11. BROADBAND NOISE CHARACTERISTICS
1000
100
10
100
90
C
C
C
= 100pF
= 1000pF
= 0.01µF
H
H
H
80
70
60
50
40
30
20
10
0
C
C
= 1.0µF
= 0.1µF
H
H
-10
-20
-30
1
10
100
1K
10K
100K
1M
10M
100M
-50
-25
0
25
50
75
100
125
o
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 12. DRIFT CURRENT vs TEMPERATURE
FIGURE 13. OPEN LOOP FREQUENCY RESPONSE
0
20
C
= 0.01µF
H
-30
-40
-50
-60
-70
-80
-90
C
= 1.0µF
H
C
= 1000pF
H
C
= 1000pF
H
C
≤ 100pF
H
40
60
80
100
120
140
160
180
200
220
240
C
= 0.1µF
H
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
100M
±10V SINUSOIDAL INPUT FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 14. HOLD MODE FEED THROUGH ATTENUATION
FIGURE 15. OPEN LOOP PHASE RESPONSE
4V
S/H
SAMPLE
HOLD
CONTROL
0V
FN2856.6
8
November 19, 2004
HA-2420, HA-2425
Typical Performance Curves (Continued)
S/H
S/H
(5V/DIV.)
(5V/DIV.)
+10V
0V
V
OUT
(2V/DIV.)
V
OUT
(2V/DIV.)
0V
-10V
TIME (1µs/DIV)
TIME (1µs/DIV)
FIGURE 16. ACQUISITION TIME (C = 1000pF)
FIGURE 17. ACQUISITION TIME (C = 1000pF)
H
H
S/H
(5V/DIV.)
S/H
(5V/DIV.)
+1V
OUT
0V
V
(0.5V/DIV.)
V
OUT
(0.5V/DIV.)
-1V
0V
TIME (1µs/DIV)
TIME (1µs/DIV)
FIGURE 18. ACQUISITION TIME (C = 1000pF)
H
FIGURE 19. ACQUISITION TIME (C = 1000pF)
H
S/H
(5V/DIV.)
S/H
(5V/DIV.)
0.1V
0V
0V
V
OUT
(50mV/DIV.)
-0.1V
V
OUT
(50mV/DIV.)
TIME (500ns/DIV)
TIME (500ns/DIV)
FIGURE 20. ACQUISITION TIME (C = 1000pF)
H
FIGURE 21. ACQUISITION TIME (C = 1000pF)
H
FN2856.6
November 19, 2004
9
HA-2420, HA-2425
Die Characteristics
DIE DIMENSIONS:
102 mils x 61 mils x 19 mils
2590µm x 1550µm x 483µm
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
3
4
2
Nitride Thickness: 3.5kÅ ±1.5kÅ
METALLIZATION:
Type: Al, 1% Cu
TRANSISTOR COUNT:
Thickness: 16kÅ ±2kÅ
78
SUBSTRATE POTENTIAL:
PROCESS:
V-
Bipolar Dielectric Isolation
BACKSIDE FINISH:
Gold, Nickel, Silicon, etc.
Metallization Mask Layout
HA-2420, HA-2425
GND
VOS ADJ
VOS ADJ
HOLD CAP
V-
V+
OUTPUT
FN2856.6
10
November 19, 2004
HA-2420, HA-2425
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
INCHES MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8
D1
B1
-
eA
A1
A
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
14
14
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
FN2856.6
11
November 19, 2004
HA-2420, HA-2425
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2856.6
12
November 19, 2004
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