HCS373K/SAMPLE [RENESAS]
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20;
| 型号： | HCS373K/SAMPLE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20 驱动 CD 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
September 1995
Features
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
1
2
3
4
5
6
7
8
9
VCC
Q7
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-
Day (Typ)
18 D7
17 D6
16 Q6
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
15
Q5
14 D5
13 D4
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
12
Q4
GND 10
11 LE
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
Description
The Intersil HCS373MS is a Radiation Hardened octal transpar-
ent three-state latch with an active-low output enable. The
HCS373MS utilizes advanced CMOS/SOS technology. The out-
puts are transparent to the inputs when the Latch Enable (LE) is
HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
OE
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
D0
D1
Q1
Q2
D2
D3
The HCS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Q3
GND
The HCS373MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS373DMSR
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
o
o
-55 C to +125 C
20 Lead SBDIP
o
o
HCS373KMSR
-55 C to +125 C
20 Lead Ceramic Flatpack
20 Lead SBDIP
o
HCS373D/Sample
HCS373K/Sample
HCS373HMSR
+25 C
o
+25 C
Sample
20 Lead Ceramic Flatpack
Die
o
+25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518845
File Number 2135.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
346
HCS373MS
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
LATCH
OE
D
D
Q
Q
(2, 5, 6, 9, 12,
15, 16, 19)
LE
COMMON CONTROLS
LE
(11)
OE
(1)
TRUTH TABLE
OE
L
LE
H
H
L
D
H
L
I
Q
H
L
L
L
L
L
L
h
X
H
Z
H
X
H = High Level, L = Low Level
X = Immaterial, Z = High Impedance
I = Low voltage level prior to the high-to-low latch enable transition
h = High voltage level prior to the high-to-low latch enable transition
Spec Number 518845
347
Specifications HCS373MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 107 C/W 28 C/W
Maximum Package Power Dissipation at +125 C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/ C
θ
θ
JA
JC
o
o
72 C/W
24 C/W
o
o
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . .100ns Max
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
40
o
o
+125 C, -55 C
-
750
µA
o
Output Current
(Sink)
IOL
IOH
VOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25 C
7.2
6.0
-7.2
-6.0
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
-
-
o
Output Current
(Source)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-
o
o
o
Output Voltage Low
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
0.1
IOL = 50µA, VIL = 1.35V
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
0.1
V
V
V
o
o
o
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
+25 C, +125 C, -55 C
VCC
-0.1
-
-
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
+25 C, +125 C, -55 C
VCC
-0.1
o
Input Leakage
Current
IIN
IOZ
FN
VCC = 5.5V, VIN = VCC or
GND
1
2, 3
+25 C
-
-
-
±0.5
±5.0
±1.0
±50
-
µA
µA
µA
µA
-
o
o
+125 C, -55 C
o
Output Three-State
Leakage
VCC = 5.5V, VO = 0V or
VCC
1
+25 C
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 2)
7, 8A, 8B
+25 C, +125 C, -55 C
-
NOTES:
1. All voltages reference to device GND.
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518845
348
Specifications HCS373MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
MIN
(NOTES 1, 2)
A SUB-
PARAMETER
Data to Qn
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MAX
20
24
24
29
25
31
20
24
25
30
UNITS
ns
o
TPLH,
TPHL
VCC = 4.5V
9
10, 11
9
+25 C
2
2
2
2
2
2
2
2
2
2
o
o
+125 C, -55 C
ns
o
LE to Qn
TPLH,
TPHL
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Enable to Output
TPZL
TPZH
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Disable to Output
NOTES:
TPLZ,
TPHZ
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
MIN
-
MAX
UNITS
pF
pF
pF
pF
ns
o
Capacitance Power Dissipation
CPD
VCC = 5.0V, f = 1MHz
+25 C
57
60
10
10
12
18
-
o
o
+125 C, -55 C
-
o
Input Capacitance
Output Transition Time
Setup Time Data to LE
Hold Time Data to LE
Pulse Width LE
CIN
VCC = 5.0V, f = 1MHz
VCC = 4.5V
+25 C
-
o
o
+125 C, -55 C
-
o
TTHL
TTLH
+25 C
-
o
o
+125 C, -55 C
-
ns
o
TSU
TH
VCC = 4.5V
+25 C
10
15
5
ns
o
o
+125 C, -55 C
-
ns
o
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
5
-
ns
o
TW
VCC = 4.5V
+25 C
16
24
-
ns
o
o
+125 C, -55 C
-
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 518845
349
Specifications HCS373MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
MAX
0.75
-
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
-
o
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25 C
6.0
mA
o
Output Current (Source)
Output Voltage Low
Output Voltage High
Input Leakage Current
IOH
VOL
VOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25 C
-6.0
-
-
0.1
-
mA
V
o
VCC = 4.5V and 5.5V, VIH = 0.70(VCC)
VIL = 0.30(VCC), IOL = 50µA
+25 C
o
VCC = 4.5V and 5.5V, VIH = 0.70(VCC)
VIL = 0.30(VCC), IOH = -50µA
+25 C
VCC
-0.1
V
o
IIN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
µA
o
Three-State Output
Leakage Current
IOZ
Applied Voltage = 0V or VCC,
VCC = 5.5V
+25 C
±50
o
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
+25 C
-
-
-
o
Data to Qn
TPLH,
TPHL
VCC = 4.5V
+25 C
2
2
24
29
ns
ns
o
LE to Qn
TPLH,
TPHL
VCC = 4.5V
+25 C
o
Enable to Output
TPZL
TPZH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
2
31
24
30
ns
ns
ns
o
+25 C
o
Disable to Output
NOTES:
TPLZ,
TPHZ
+25 C
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
o
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)
GROUP B
PARAMETER
SUBGROUP
DELTA LIMIT
12µA
ICC
5
5
5
IOL/IOH
-15% of 0 Hour
±200nA
IOZL/IOZH
Spec Number 518845
350
Specifications HCS373MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H
1, 7, 9
1, 7, 9
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
ICC, IOL/H
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
Interim Test III (Postburn-In)
PDA
1, 7, 9
ICC, IOL/H
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Group A (Note 1)
Group B
Subgroup B-5
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
Subgroup B-6
Sample/5005
Sample/5005
1, 7, 9
1, 7, 9
Group D
NOTES:
1. Alternate Group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
2, 5, 6, 9, 12, 15, 16,
19
1, 3, 4, 7, 8, 10, 11,
13, 14, 17, 18
-
-
20
-
-
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
2, 5, 6, 9, 12, 15, 16,
19
10
1, 3, 4, 7, 8, 11, 13,
14, 17, 18, 20
-
-
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
1, 10
2, 5, 6, 9, 12, 15, 16,
19
20
11
3, 4, 7, 8, 13,
14, 17, 18
NOTES:
1. Each pin except VCC and GND will have a resistor of 10kΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 680Ω ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
2, 5, 6, 9, 12, 15, 16, 19
10
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group
E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518845
351
HCS373MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518845
352
HCS373MS
AC Timing Diagrams
INPUT
LEVEL
VS
LE
DATA
Qn
VS
VS
TW
INPUT
LEVEL
VS
VS
VS
TSU(L)
VS
DATA
VS
VS
TH(H)
TPLH
TPHL
TH(L)
LE
TSU(H)
TPHL
TPLH
VS
VS
VS
VS
FIGURE 1. LATCH ENABLE PROPAGATION DELAYS
FIGURE 2. LATCH ENABLE PREREQUISITE TIMES (DATA
SET-UP AND HOLD)
AC VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
VIH
VS
TTLH
TTHL
VOH
VOL
80%
80%
20%
20%
OUTPUT
VIL
GND
0
FIGURE 3. OUTPUT TRANSITION TIMES
AC Load Circuit
DUT
TEST
POINT
CL
RL
CL = 50pF
RL = 500Ω
Spec Number 518845
353
HCS373MS
Three-State Load Circuit
Three-State Low Timing Diagram
VCC
VIH
INPUT
VS
OE
VIL
RL
CL
TPZL
TEST
POINT
DUT
TPLZ
VOZ
VOL
CL = 50pF
RL = 500Ω
VT
VW
OUTPUT
THREE-STATE LOW VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
2.25
0.90
0
UNITS
V
V
V
V
V
V
V
VIH
VS
VT
VW
GND
VIL
0
Three-State High Timing Diagram
Three-State Load Circuit
DUT
TEST
POINT
VIH
OE
VIL
INPUT
VS
CL
RL
TPHZ
TPZH
VOH
VOZ
CL = 50pF
VW
VT
OUTPUT
RL = 500Ω
THREE-STATE HIGH VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
2.25
3.60
0
UNITS
V
V
V
V
V
V
V
VIH
VS
VT
VW
GND
VIL
0
Spec Number 518845
354
HCS373MS
Die Characteristics
DIE DIMENSIONS:
2747 x 2693µm
METALLIZATION:
Type: SiAl
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS373MS
D0
(3)
Q0
(2)
OE
(1)
Q7
(19)
VCC
(20)
(18) D7
(17) D6
D1 (4)
Q1 (5)
(16) Q6
Q2 (6)
(15) Q5
(14) D5
D2 (7)
(12)
Q4
(13)
D4
(8)
D3
(9)
Q3
(10)
GND
(11)
LE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCS373 is TA14303A.
Spec Number 518845
355
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