HD3-6408-9 [RENESAS]
CMOS Asynchronous Serial Manchester Adapter (ASMA); CERDIP24, PDIP24; Temp Range: -40° to 85°C;
| 型号： | HD3-6408-9 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CMOS Asynchronous Serial Manchester Adapter (ASMA); CERDIP24, PDIP24; Temp Range: -40° to 85°C 编码器 电信 光电二极管 电信集成电路 |
| 文件： | 总11页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD-6408
CMOS Asynchronous Serial
Manchester Adapter (ASMA)
March 1997
Features
Description
• Low Bit Error Rate
The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder
for creating a very high speed asynchronous serial data bus.
The Encoder converts serial NRZ data (typically from a shift
register) to Manchester II encoded data, adding a sync pulse
and parity bit. The Decoder recognizes this sync pulse and
identifies it as a Command Sync or a Data Sync. The data is
then decoded and shifted out in NRZ code (typically into a
shift register). Finally, the parity bit is checked. If there were
no Manchester or parity errors the Decoder responds with a
valid word signal. The Decoder puts the Manchester code to
full use to provide clock recovery and excellent noise immu-
nity at these very high speeds.
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encoder, Decoder
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
• Single Power Supply
• 24 Lead Package
The HD-6408 can be used in many commercial applications
such as security systems, environmental control systems,
serial data links and many others. It utilizes a single 12 x
clock and achieves data rates of up to one million bits per
second with a very minimum overhead of only 4 bits out of
20, leaving 16 bits for data.
Ordering Information
PART
NUMBER
PKG.
NO.
PACKAGE
PDIP
TEMP. RANGE
o
o
-40 C to +85 C
HD3-6408-9
HD1-6408-9
E24.6
E24.6
o
o
CERDIP
-40 C to +85 C
Pinout
HD-6408 (DIP)
TOP VIEW
VW
ESC
TD
1
2
3
4
5
6
7
8
9
24
V
CC
23 EC
22 SCI
21 SD
20 SS
SDO
DC
BZI
19 EE
BOI
UDI
DSC
18 SDI
17 BOO
16 OI
CDS 10
DR 11
15 BZO
14 DBS
13 MR
GND 12
d
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2952.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19995-1
HD-6408
Block Diagrams
ENCODER
DECODER
11
1
DR
BIT COUNTER
23
14
13
EC
DBS
÷ 6
VALID
WORD
TEST
MR
VALID
WORD
LATCH
PARITY
CHECK
VW
22
BIT COUNTER
SCI
÷ 2
CIRCUIT
2
3
ESC
TD
SYNC
LATCH
10
CDS
21
SD
COUNT
DECODER
RESET
20
5
SS
SYNC
4
NRZ
OUTPUT
PORT
CLOCK
SYNCHRO-
NIZER
DC
CHARACTER
IDENTIFIER
SDO
9
15
16
17
BZO
OI
BOO
DSC
CHARACTER
FORMER
PARITY
6
7
BZI
18
DATA
19
SDI
TRANSITION
FINDER
BOI
EE
8
UDI
5-2
HD-6408
Pin Description
PIN
1
TYPE
O
SYMBOL
VW
SECTION
Decoder
Encoder
DESCRIPTION
Output high indicates receipt of a VALID WORD.
2
O
ESC
ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The En-
coder samples SDI on the low-to-high transition of ESC.
3
O
TD
Decoder
TAKE DATA output is high during receipt of data after identification of a sync pulse
and two valid Manchester data bits.
4
5
O
I
SDO
DC
Decoder
Decoder
SERIAL DATA OUT delivers received data in correct NRZ format.
DECODER CLOCK input drives the transition finder, and the synchronizer which
in turn supplies the clock to the balance of the Decoder. Input a frequency equal to
12X the data rate.
6
7
I
I
BZI
BOI
Decoder
Decoder
Decoder
Decoder
Decoder
A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative
state. This pin must be held high when the Unipolar input is used.
A high input should be applied to BIPOLAR ONE IN when the bus is in its positive
state, this pin must be held low when the Unipolar input is used.
8
I
UDI
With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition
finder circuit. If not used this input must be held low.
9
O
O
DSC
CDS
DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ÷ 12),
synchronized by the recovered serial data stream.
10
COMMAND/DATA SYNC output high occurs during output of decoded data which
was preceded by a Command synchronizing character. A low output indicates a
Data synchronizing character.
11
I
DR
Decoder
A high input to DECODER RESET during a rising edge of DECODER SHIFT
CLOCK resets the decoder bit counting logic to a condition ready for a new word.
12
13
I
I
GND
MR
Both
Both
GROUND supply pin.
A high on MASTER RESET clears the 2:1 counters in both the encoder and decod-
er and the ÷ 6 counter.
14
15
O
O
DBS
BZO
Encoder
Encoder
DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER
CLOCK.
BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative
sense of a bipolar line driver.
16
17
I
OI
Encoder
Encoder
A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.
O
BOO
BIPOLAR ONE OUT is an active low output designed to drive the one or positive
sense of a bipolar line driver.
18
19
20
21
I
I
SDI
EE
SS
SD
Encoder
Encoder
Encoder
Encoder
SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER
SHIFT CLOCK.
A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preced-
ing cycle being completed).
I
SYNC SELECT actuates a Command sync for an input high and data sync for an
input low.
O
SEND DATA is an active high output which enables the external source of serial
data.
22
23
24
I
I
I
SCI
EC
Encoder
Encoder
Both
SEND CLOCK IN is 2X the Encoder data rate.
ENCODER CLOCK is the input to the 6:1 divider.
V
V
is the +5V power supply pin. A 0.1µF decoupling capacitor from V
(pin 24)
CC
CC
CC
to GND (pin 12) is recommended.
5-3
HD-6408
Encoder Operation
The Encoder requires a single clock with a frequency of During these sixteen periods the data should be clocked into
twice the desired data rate applied at the SClock input. An the SD Input with every high-to-low transition of the ESC (3)
auxiliary divide by six counter is provided on chip which can - (4). After the sync and Manchester II encoded data are
be utilized to produce the SClock by dividing the DClock.
transmitted through the BOO and BZO outputs, the Encoder
adds on an additional bit which is the (odd) parity for that
word (5). If ENCODER ENABLE is held high continuously,
consecutive words will be encoded without an interframe
gap. ENCODER ENABLE must go low by time (5) as shown
to prevent a consecutive word from being encoded. At any
time a low on OI will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
The Encoder’s cycle begins when EE is high during a falling
edge of ESC (1). This cycle lasts for one word length or
twenty ESC periods. At the next low-to-high transition of the
ESC, a high at SS input actuates a Command sync or a low
will produce a Data sync for that word (2). When the Encoder
is ready to accept data, the SD output will go high and
remain high for sixteen ESC periods (3) - (4).
To Abort the Encoder transmission a positive pulse must be
applied at MR. Any time after or during this pulse, a low-to-
high transition on SCI clears the internal counters and initial-
izes the Encoder for a new word.
0
1
2
3
4
5
6
7
15
16
17
18
19
TIMING
SCI
ESC
EE
DON’T CARE
SS
VALID
DON’T CARE
SD
SDI
15
14
13
12
11
10
3
2
1
0
BOO
1ST HALF 2ND HALF 15
14
14
13
13
12
12
11
11
3
3
2
2
1
1
0
0
4
P
P
BZO
SYNC
SYNC
3
15
1
2
5
5-4
HD-6408
Decoder Operation
The Decoder requires a single clock with a frequency of 12 The decoded data available at SDO is in a NRZ format. The
times the desired data rate applied at the DClock input. The DSC is provided so that the decoded bits can be shifted into
Manchester II coded data can be presented to the Decoder an external register on every low-to-high transition of this
in one of two ways. The BOI and BZI inputs will accept data clock (2) - (3). Note that DECODER SHIFT CLOCK may
from a differential output comparator. The UDI input can only adjust its phase up until the time that TAKE DATA goes high.
accept noninverted Manchester II coded data (e.g. from
After all sixteen decoded bits have been transmitted (3) the
BOO of an Encoder through an inverter to UDI).
data is checked for odd parity. A high on VW output (4) indi-
The Decoder is free running and continuously monitors its cates a successful reception of a word without any
data input lines for a valid sync character and two valid Manchester or parity errors. At this time the Decoder is look-
Manchester data bits to start an output cycle. When a valid ing for a new sync character to start another output
sync is recognized (1), the type of sync is indicated by the sequence. VALID WORD will go low approximately 20
CDS output. If the sync character was a command, this out- DECODER SHIFT CLOCK periods after it goes high if not
put will go high (2) and remain high for sixteen DSC periods reset low sooner by a valid sync and two valid Manchester
(3), otherwise it will remain low. The TD output will go high bits as shown (1).
and remain high (2) - (3) while the Decoder is transmitting
At any time in the above sequence a high input on DR during
the decoded data through SDO.
a low-to-high transition of DSC will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
0
1
2
3
4
5
6
7
8
16
17
18
19
TIMING
DSC
1ST HALF 2ND HALF
15
15
14
14
13
13
12
12
11
11
10
10
2
2
1
1
0
0
P
P
BOI
BZI
SYNC
SYNC
TD
CDS
SDO
VW
UNDEFINED
15
14
13
12
4
3
2
1
0
FROM PREVIOUS RECEPTION
1
2
3
4
5-5
HD-6408
Thermal Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance (Typical)
θ
o
θ
JC
JA
o
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
+0.3V
CC
CERDIP Package . . . . . . . . . . . . . . . . 50 C/W
PDIP Package . . . . . . . . . . . . . . . . . . . 60 C/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates
11 C/W
N/A
o
o
o
o
o
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HD-6408-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
o
o
o
o
DC Electrical Specifications V = 5.0V ±10%, T = -40 C to +85 C
CC
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
V
V
V
V
II
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Voltage (Clock)
Logical “0” Input Voltage (Clock)
Input Leakage
70% V
-
-
-
V
IH
CC
20% V
-
-
V
V
IL
CC
V
-0.5
CC
-
-
IHC
ILC
-
GND +0.5
-
V
-1.0
+1.0
µA
V
= V
or GND, DIP Pins
IN
CC
5-8, 11, 13, 16, 18, 19, 20, 22, 23
V
Logical “1” Output Voltage
Logical “0” Output Voltage
Supply Current Standby
2.4
-
-
V
V
I
I
= -3mA
OH
OH
V
-
-
-
-
0.4
2
= 1.8mA
OL
OL
I
I
0.5
8.0
mA
mA
V
V
= V = 5.5V Outputs Open
CC
CCSB
CCOP
IN
Supply Current Operating (Note 1)
10.0
= 5.5V, f = 15MHz
CC
NOTE:
1. Guaranteed but not 100% tested.
o
o
AC Electrical Specifications V = 5.0V ±10%, T = -40 C to +85 C
CC
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
ENCODER TIMING
(1)
(2)
F
F
T
T
F
T
T
T
T
T
T
Encoder Clock Frequency
Send Clock Frequency
Encoder Clock Rise Time
Encoder Clock Fall Time
Data Rate
0
0
-
-
-
-
-
-
-
-
-
-
-
12
MHz
MHz
ns
C = 50pF
L
EC
ESC
ECR
ECF
ED
MR
E1
2.0
C = 50pF
L
(3)
-
8
C = 50pF
L
(4)
-
8
ns
C = 50pF
L
(5)
0
1.0
MHz
ns
C = 50pF
L
(6)
Master Reset Pulse Width
Shift Clock Delay
150
-
-
C = 50pF
L
(7)
125
ns
C = 50pF
L
(8)
Serial Data Setup
75
75
90
100
-
-
-
-
ns
C = 50pF
L
E2
(9)
Serial Data Hold
ns
C = 50pF
L
E3
(10)
(11)
Enable Setup
ns
C = 50pF
L
E4
Enable Pulse Width
ns
C = 50pF
L
E5
5-6
HD-6408
o
o
AC Electrical Specifications V = 5.0V ±10%, T = -40 C to +85 C (Continued)
CC
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
C = 50pF
(12)
(13)
(14)
(15)
(16)
(17)
T
T
T
T
T
T
Sync Setup
55
-
-
ns
E6
L
Sync Pulse Width
Send Data Delay
Bipolar Output Delay
Enable Hold
150
0
-
-
-
-
-
-
50
130
-
ns
ns
ns
ns
ns
C = 50pF
L
E7
C = 50pF
E8
L
-
C = 50pF
L
E9
10
95
C = 50pF
L
E10
E11
Sync Hold
-
C = 50pF
L
DECODER TIMING
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
NOTE:
F
T
T
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Decoder Clock Frequency
Decoder Clock Rise Time
Decoder Clock Fall Time
Data Rate
0
-
-
-
-
-
-
-
-
-
-
12
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C = 50pF
L
DC
DCR
DCF
DD
DR
DRS
DRH
MR
D1
8
C = 50pF
L
-
8
C = 50pF
L
0
1.0
C = 50pF
L
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse Width
Bipolar Data Pulse Width
Sync Transition Span
One Zero Overlap
150
75
10
150
-
-
-
-
-
-
C = 50pF
L
C = 50pF
L
C = 50pF
L
C = 50pF
L
T
+10
Note 1, C = 50pF
L
DC
-
-
18T
DC
Note 1, C = 50pF
L
D2
-
T
-10
Note 1, C = 50pF
L
D3
DC
Short Data Transition Span
Long Data Transition Span
Sync Delay (ON)
-
6T
-
Note 1, C = 50pF
L
D4
DC
-
12T
-
Note 1, C = 50pF
L
D5
DC
-20
0
-
-
-
-
-
-
-
110
C
C
= 50pF
= 50pF
D6
L
L
Take Data Delay (ON)
Serial Data Out Delay
Sync Delay (OFF)
110
80
D7
C = 50pF
D8
L
0
0
0
110
110
110
C
C
C
= 50pF
= 50pF
= 50pF
D9
L
L
L
Take Data Delay (OFF)
Valid Word Delay
D10
D11
1
1. T
= Decoder Clock Period = /F . (These parameters are guaranteed but not 100% tested).
DC
DC
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
C
Input Capacitance
Output Capacitance
-
15
-
pF
pF
FREQ = 1MHz, all mea-
surements are referenced
to device GND
IN
C
-
15
-
O
5-7
HD-6408
AC Testing Input, Output Waveform
INPUT
V
V
OH
IH
50%
50%
V
V
OL
IL
NOTE: AC Testing: All input signals must switch between V and V . Input rise and fall times are driven at 1ns per volt.
IL
IH
Encoder Timing
(7)
SCI
ESC
SDI
TE1
(9)
TE3
VALID
VALID
TE2
(8)
SC
ESC
EE
(7)
TE1
TE10 (16)
(10)
TE4
(17)
TE11
(11)
TE5
(12)
TE6
SS
VALID
TE7
(13)
ESC
SD
(14)
TE8
SC
(15)
TE9
BOO OR BZO
5-8
HD-6408
Decoder Timing
NOTE: UI = 0, FOR NEXT DIAGRAMS
BIT PERIOD
BIT PERIOD
BIT PERIOD
BOI
BZI
T
D1
(26)
T
T
(27)
T
(28)
(28)
D3
D2
D3
T
D1
(26)
T
D2
(27)
COMMAND SYNC
T
(26)
D1
(28)
BOI
BZI
T
T
T
D3
(27)
D2
D3
(28)
T
D1
(26)
DATA SYNC
T
D2
(27)
T
T
D1
D1
BOI
BZI
(26)
(26)
(28)
T
T
(28)
T
T
T
D3
(28)
(28)
D3
D3
D3
D3
(28)
T
D1
(26)
T
T
(30)
T
(30)
D5
T
D4
D5
D4
(29)
(29)
ONE
ZERO
ONE
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS
(27)
(27)
T
T
D2
D2
UI
UI
COMMAND SYNC
(27)
(27)
T
T
D2
D2
DATA SYNC
(29)
(29)
(30)
T
T
T
T
T
UI
D4
D5
D5
D4
D4
(29)
(30)
ONE
ZERO
ONE
ONE
5-9
HD-6408
Decoder Timing (Continued)
DSC
(31)
T
D6
CDS
TD
T
D7
(32)
(33)
DSC
SDO
T
D8
DATA BIT
DSC
(34)
T
D9
CDS
TD
(35)
T
D10
(36) T
D11
VW
DSC
(23) T
DRS
(22) T
DR
DR
(24) T
DRH
5-10
HD-6408
Decoder Timing (Continued)
(31)
DSC
CDS
TD
T
D6
T
D6
(32)
(33)
D8
DSC
SDO
T
DATA BIT
DSC
CDS
(34)
T
D8
(35)
T
D10
TD
(34) T
D11
VW
DSC
DR
(34) T
D11
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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5-11
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