HD64F36902GP_技术文档

Rev. 3.00 Sep. 14, 2006 Page ii of xxviii

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or

a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,

diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products. Renesas

Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the

information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or

system that is used under circumstances in which human life is potentially at stake. Please contact

Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when

considering the use of a product contained herein for any specific purposes, such as apparatus or

systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in

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7. If these products or technologies are subject to the Japanese export control restrictions, they must

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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the

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8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

Rev. 3.00 Sep. 14, 2006 Page iii of xxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where the states are

undefined, the register settings and the output state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system's

operation is not guaranteed if they are accessed.

Rev. 3.00 Sep. 14, 2006 Page iv of xxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

•

CPU and System-Control Modules

On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section

includes notes in relation to the descriptions given, and usage notes are given, as required, as the

final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see the actual locations in this

manual.

11. Index

Rev. 3.00 Sep. 14, 2006 Page v of xxviii

Preface

The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the high-

speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the

peripheral functions required to configure a system. The H8/300H CPU has an instruction set that

is compatible with the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/36912 Group and

H8/36902 Group in the design of application systems. Target users are expected to

understand the fundamentals of electrical circuits, logical circuits, and

microcomputers.

Objective:

This manual was written to explain the hardware functions and electrical

characteristics of the H8/36912 Group and H8/36902 Group to the target users.

Refer to the H8/300H Series Software Manual for a detailed description of the

instruction set.

Notes on reading this manual:

•

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

•

In order to understand the details of the CPU's functions

Read the H8/300H Series Software Manual.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

register. The addresses, bits, and initial values of the registers are summarized in section 19,

List of Registers.

Example:

Register name:

The following notation is used for cases when the same or a

similar function, e.g. serial communication interface, is

implemented on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order:

The MSB is on the left and the LSB is on the right.

Rev. 3.00 Sep. 14, 2006 Page vi of xxviii

Notes:

When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and

debugging, the following restrictions must be noted.

1. The NMI pin is reserved for the E7 or E8, and cannot be used.

2. Area H'2000 to H'2FFF is used by the E7 or E8, and is not available to the user.

3. Area H'F980 to H'FD7F must on no account be accessed.

4. When the E7 or E8 is used, address breaks can be set as either available to the user or for use

by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break

control registers must not be accessed.

5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode).

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.renesas.com/

H8/36912 Group and H8/36902 Group manuals:

Document Title

Document No.

This manual

H8/36912 Group, H8/36902 Group Hardware Manual

H8/300H Series Software Manual

REJ09B0213

User's manuals for development tools:

Document Title

Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor

User's Manual

REJ10B0058

H8S, H8/300 Series Simulator/Debugger User's Manual

REJ10B0211

REJ10B0024

H8S, H8/300 Series High-Performance Embedded Workshop 3 Tutorial

H8S, H8/300 Series High-Performance Embedded Workshop 3 User's Manual REJ10B0026

Application notes:

Document Title

Document No.

REJ05B0464

REJ05B0520

H8S, H8/300 Series C/C++ Compiler Package Application Note

Single Power Supply F-ZTAT^TMOn-Board Programming

Rev. 3.00 Sep. 14, 2006 Page vii of xxviii

Rev. 3.00 Sep. 14, 2006 Page viii of xxviii

Contents

Section 1 Overview................................................................................................1

1.1

1.2

1.3

1.4

Features................................................................................................................................. 1

Internal Block Diagram......................................................................................................... 3

Pin Arrangement................................................................................................................... 5

Pin Functions ........................................................................................................................ 9

Section 2 CPU......................................................................................................11

2.1

Address Space and Memory Map....................................................................................... 12

2.2

Register Configuration........................................................................................................ 14

2.2.1

2.2.2

2.2.3

General Registers................................................................................................ 15

Program Counter (PC) ........................................................................................ 16

Condition-Code Register (CCR)......................................................................... 16

2.3

2.4

2.5

2.6

Data Formats....................................................................................................................... 18

2.3.1

2.3.2

General Register Data Formats........................................................................... 18

Memory Data Formats........................................................................................ 20

Instruction Set..................................................................................................................... 21

2.4.1

2.4.2

Table of Instructions Classified by Function ...................................................... 21

Basic Instruction Formats ................................................................................... 30

Addressing Modes and Effective Address Calculation....................................................... 32

2.5.1

2.5.2

Addressing Modes .............................................................................................. 32

Effective Address Calculation ............................................................................ 35

Basic Bus Cycle.................................................................................................................. 37

2.6.1

2.6.2

Access to On-Chip Memory (RAM, ROM)........................................................ 37

On-Chip Peripheral Modules .............................................................................. 38

2.7

2.8

CPU States.......................................................................................................................... 39

Usage Notes........................................................................................................................ 40

2.8.1

2.8.2

2.8.3

Notes on Data Access to Empty Areas ............................................................... 40

EEPMOV Instruction.......................................................................................... 40

Bit Manipulation Instruction............................................................................... 40

Section 3 Exception Handling .............................................................................47

3.1

Exception Sources and Vector Address.............................................................................. 47

3.2

Register Descriptions.......................................................................................................... 49

3.2.1

3.2.2

3.2.3

Interrupt Edge Select Register 1 (IEGR1) .......................................................... 49

Interrupt Edge Select Register 2 (IEGR2) .......................................................... 50

Interrupt Enable Register 1 (IENR1) .................................................................. 50

Rev. 3.00 Sep. 14, 2006 Page ix of xxviii

3.2.4

3.2.5

3.2.6

3.2.7

Interrupt Enable Register 2 (IENR2) .................................................................. 51

Interrupt Flag Register 1 (IRR1)......................................................................... 52

Interrupt Flag Register 2 (IRR2)......................................................................... 53

Wakeup Interrupt Flag Register (IWPR) ............................................................ 53

3.3

3.4

Reset Exception Handling .................................................................................................. 54

Interrupt Exception Handling ............................................................................................. 55

3.4.1

3.4.2

3.4.3

3.4.4

External Interrupts .............................................................................................. 55

Internal Interrupts ............................................................................................... 56

Interrupt Handling Sequence .............................................................................. 57

Interrupt Response Time..................................................................................... 59

3.5

Usage Notes........................................................................................................................ 61

3.5.1

3.5.2

3.5.3

Interrupts after Reset........................................................................................... 61

Notes on Stack Area Use .................................................................................... 61

Notes on Rewriting Port Mode Registers ........................................................... 61

Section 4 Address Break .....................................................................................63

4.1

Register Descriptions.......................................................................................................... 64

4.1.1

4.1.2

4.1.3

4.1.4

Address Break Control Register (ABRKCR) ..................................................... 64

Address Break Status Register (ABRKSR) ........................................................ 66

Break Address Registers (BARH, BARL).......................................................... 66

Break Data Registers (BDRH, BDRL) ............................................................... 66

4.2

Operation ............................................................................................................................ 67

Section 5 Clock Pulse Generators .......................................................................69

5.1

Features............................................................................................................................... 70

5.2

Register Descriptions.......................................................................................................... 71

5.2.1

5.2.2

5.2.3

5.2.4

RC Control Register (RCCR) ............................................................................. 71

RC Trimming Data Protect Register (RCTRMDPR).......................................... 72

RC Trimming Data Register (RCTRMDR)........................................................ 73

Clock Control/Status Register (CKCSR)............................................................ 74

5.3

System Clock Select Operation .......................................................................................... 75

5.3.1

5.3.2

Clock Control Operation..................................................................................... 76

Clock Change Timing......................................................................................... 78

5.4

5.5

Trimming of On-chip Oscillator Frequency ....................................................................... 80

External Oscillators ............................................................................................................ 82

5.5.1

5.5.2

5.5.3

Connecting Crystal Resonator ............................................................................ 82

Connecting Ceramic Resonator .......................................................................... 83

External Clock Input Method.............................................................................. 83

5.6

Prescaler.............................................................................................................................. 83

5.6.1 Prescaler S .......................................................................................................... 83

Rev. 3.00 Sep. 14, 2006 Page x of xxviii

5.7

Usage Notes........................................................................................................................ 84

5.7.1

5.7.2

Note on Resonators............................................................................................. 84

Notes on Board Design....................................................................................... 84

Section 6 Power-Down Modes ............................................................................85

6.1

6.2

Register Descriptions.......................................................................................................... 85

6.1.1

6.1.2

6.1.3

6.1.4

System Control Register 1 (SYSCR1)................................................................ 86

System Control Register 2 (SYSCR2)................................................................ 88

Module Standby Control Register 1 (MSTCR1) ................................................ 89

Module Standby Control Register 2 (MSTCR2) ................................................ 90

Mode Transitions and States of LSI.................................................................................... 91

6.2.1

6.2.2

6.2.3

Sleep Mode ......................................................................................................... 93

Standby Mode..................................................................................................... 93

Subsleep Mode.................................................................................................... 94

6.3

6.4

6.5

Operating Frequency in Active Mode................................................................................. 94

Direct Transition................................................................................................................. 94

Module Standby Function................................................................................................... 95

Section 7 ROM ....................................................................................................97

7.1

Block Configuration ........................................................................................................... 97

7.2

Register Descriptions.......................................................................................................... 99

7.2.1

7.2.2

7.2.3

7.2.4

Flash Memory Control Register 1 (FLMCR1).................................................... 99

Flash Memory Control Register 2 (FLMCR2).................................................. 100

Erase Block Register 1 (EBR1) ........................................................................ 101

Flash Memory Enable Register (FENR)........................................................... 101

7.3

7.4

On-Board Programming Modes........................................................................................ 102

7.3.1

7.3.2

Boot Mode ........................................................................................................ 102

Programming/Erasing in User Program Mode.................................................. 106

Flash Memory Programming/Erasing............................................................................... 107

7.4.1

7.4.2

7.4.3

Program/Program-Verify.................................................................................. 107

Erase/Erase-Verify............................................................................................ 109

Interrupt Handling when Programming/Erasing Flash Memory....................... 110

7.5

Program/Erase Protection ................................................................................................. 112

7.5.1

7.5.2

7.5.3

Hardware Protection ......................................................................................... 112

Software Protection........................................................................................... 112

Error Protection................................................................................................. 112

Section 8 RAM ..................................................................................................115

Rev. 3.00 Sep. 14, 2006 Page xi of xxviii

Section 9 I/O Ports.............................................................................................117

9.1

Port 1................................................................................................................................. 117

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

Port Mode Register 1 (PMR1).......................................................................... 118

Port Control Register 1 (PCR1)........................................................................ 119

Port Data Register 1 (PDR1) ............................................................................ 119

Port Pull-Up Control Register 1 (PUCR1)........................................................ 120

Pin Functions .................................................................................................... 120

9.2

9.3

Port 2................................................................................................................................. 121

9.2.1

9.2.2

9.2.3

Port Control Register 2 (PCR2)........................................................................ 122

Port Data Register 2 (PDR2) ............................................................................ 122

Pin Functions .................................................................................................... 123

Port 5................................................................................................................................. 124

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

Port Mode Register 5 (PMR5).......................................................................... 125

Port Control Register 5 (PCR5)........................................................................ 125

Port Data Register 5 (PDR5) ............................................................................ 126

Port Pull-Up Control Register 5 (PUCR5)........................................................ 126

Pin Functions .................................................................................................... 127

9.4

9.5

Port 7................................................................................................................................. 128

9.4.1

9.4.2

9.4.3

Port Control Register 7 (PCR7)........................................................................ 128

Port Data Register 7 (PDR7) ............................................................................ 129

Pin Functions .................................................................................................... 129

Port 8................................................................................................................................. 130

9.5.1

9.5.2

9.5.3

Port Control Register 8 (PCR8)........................................................................ 131

Port Data Register 8 (PDR8) ............................................................................ 131

Pin Functions .................................................................................................... 132

9.6

9.7

Port B................................................................................................................................ 134

9.6.1

9.6.2

Port Data Register B (PDRB) ........................................................................... 134

Pin Functions .................................................................................................... 135

Port C................................................................................................................................ 136

9.7.1

9.7.2

9.7.3

Port Control Register C (PCRC)....................................................................... 137

Port Data Register C (PDRC) ........................................................................... 137

Pin Functions .................................................................................................... 138

Section 10 Timer B1..........................................................................................139

10.1 Features............................................................................................................................. 139

10.2 Register Descriptions........................................................................................................ 140

10.2.1

10.2.2

10.2.3

Timer Mode Register B1 (TMB1) .................................................................... 140

Timer Counter B1 (TCB1)................................................................................ 141

Timer Load Register B1 (TLB1) ...................................................................... 141

Rev. 3.00 Sep. 14, 2006 Page xii of xxviii

10.3 Operation .......................................................................................................................... 142

10.3.1

10.3.2

Interval Timer Operation .................................................................................. 142

Auto-Reload Timer Operation .......................................................................... 142

10.4 Timer B1 Operating Modes .............................................................................................. 143

Section 11 Timer V............................................................................................145

11.1 Features............................................................................................................................. 145

11.2 Input/Output Pins.............................................................................................................. 147

11.3 Register Descriptions........................................................................................................ 147

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

Timer Counter V (TCNTV).............................................................................. 147

Time Constant Registers A and B (TCORA, TCORB) .................................... 148

Timer Control Register V0 (TCRV0) ............................................................... 148

Timer Control/Status Register V (TCSRV)...................................................... 150

Timer Control Register V1 (TCRV1) ............................................................... 151

11.4 Operation .......................................................................................................................... 152

11.4.1 Timer V Operation............................................................................................ 152

11.5 Timer V Application Examples ........................................................................................ 155

11.5.1

11.5.2

Pulse Output with Arbitrary Duty Cycle........................................................... 155

Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 156

11.6 Usage Notes...................................................................................................................... 157

Section 12 Timer W...........................................................................................159

12.1 Features............................................................................................................................. 159

12.2 Input/Output Pins.............................................................................................................. 162

12.3 Register Descriptions........................................................................................................ 162

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

12.3.8

Timer Mode Register W (TMRW) ................................................................... 163

Timer Control Register W (TCRW) ................................................................. 164

Timer Interrupt Enable Register W (TIERW) .................................................. 165

Timer Status Register W (TSRW) .................................................................... 166

Timer I/O Control Register 0 (TIOR0)............................................................. 168

Timer I/O Control Register 1 (TIOR1)............................................................. 169

Timer Counter (TCNT)..................................................................................... 171

General Registers A to D (GRA to GRD)......................................................... 171

12.4 Operation .......................................................................................................................... 172

12.4.1

12.4.2

Normal Operation ............................................................................................. 172

PWM Operation................................................................................................ 176

12.5 Operation Timing.............................................................................................................. 181

12.5.1

12.5.2

12.5.3

TCNT Count Timing ........................................................................................ 181

Output Compare Output Timing....................................................................... 182

Input Capture Timing........................................................................................ 183

Rev. 3.00 Sep. 14, 2006 Page xiii of xxviii

12.5.4

12.5.5

12.5.6

12.5.7

12.5.8

Timing of Counter Clearing by Compare Match.............................................. 183

Buffer Operation Timing .................................................................................. 184

Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 185

Timing of IMFA to IMFD Setting at Input Capture ......................................... 186

Timing of Status Flag Clearing......................................................................... 186

12.6 Usage Notes...................................................................................................................... 187

Section 13 Watchdog Timer..............................................................................191

13.1 Features............................................................................................................................. 191

13.2 Register Descriptions........................................................................................................ 192

13.2.1

13.2.2

13.2.3

Timer Control/Status Register WD (TCSRWD) .............................................. 192

Timer Counter WD (TCWD)............................................................................ 194

Timer Mode Register WD (TMWD) ................................................................ 194

13.3 Operation .......................................................................................................................... 195

Section 14 Serial Communication Interface 3 (SCI3).......................................197

14.1 Features............................................................................................................................. 197

14.2 Input/Output Pins.............................................................................................................. 199

14.3 Register Descriptions........................................................................................................ 199

14.3.1

14.3.2

14.3.3

14.3.4

14.3.5

14.3.6

14.3.7

14.3.8

14.3.9

Receive Shift Register (RSR) ........................................................................... 200

Receive Data Register (RDR)........................................................................... 200

Transmit Shift Register (TSR).......................................................................... 200

Transmit Data Register (TDR).......................................................................... 200

Serial Mode Register (SMR) ............................................................................ 201

Serial Control Register 3 (SCR3) ..................................................................... 202

Serial Status Register (SSR) ............................................................................. 204

Bit Rate Register (BRR) ................................................................................... 206

Sampling Mode Register (SPMR) .................................................................... 211

14.4 Operation in Asynchronous Mode.................................................................................... 212

14.4.1

14.4.2

14.4.3

14.4.4

Clock................................................................................................................. 212

SCI3 Initialization............................................................................................. 213

Data Transmission ............................................................................................ 214

Serial Data Reception ....................................................................................... 216

14.5 Operation in Clocked Synchronous Mode........................................................................ 219

14.5.1

14.5.2

14.5.3

14.5.4

14.5.5

Clock................................................................................................................. 219

SCI3 Initialization............................................................................................. 220

Serial Data Transmission.................................................................................. 220

Serial Data Reception (Clocked Synchronous Mode) ...................................... 223

Simultaneous Serial Data Transmission and Reception.................................... 225

14.6 Multiprocessor Communication Function ........................................................................ 227

Rev. 3.00 Sep. 14, 2006 Page xiv of xxviii

14.6.1

14.6.2

Multiprocessor Serial Data Transmission......................................................... 229

Multiprocessor Serial Data Reception .............................................................. 231

14.7 Interrupts........................................................................................................................... 235

14.8 Usage Notes...................................................................................................................... 236

14.8.1

14.8.2

Break Detection and Processing ....................................................................... 236

Mark State and Break Sending.......................................................................... 236

14.8.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only).................................................................. 236

14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode ................................................................................................................. 237

Section 15 I²C Bus Interface 2 (IIC2)................................................................239

15.1 Features............................................................................................................................. 239

15.2 Input/Output Pins.............................................................................................................. 241

15.3 Register Descriptions........................................................................................................ 242

15.3.1

15.3.2

15.3.3

15.3.4

15.3.5

15.3.6

15.3.7

15.3.8

15.3.9

I²C Bus Control Register 1 (ICCR1)................................................................. 242

I²C Bus Control Register 2 (ICCR2)................................................................. 245

I²C Bus Mode Register (ICMR)........................................................................ 246

I²C Bus Interrupt Enable Register (ICIER)....................................................... 248

I²C Bus Status Register (ICSR)......................................................................... 250

Slave Address Register (SAR).......................................................................... 252

I²C Bus Transmit Data Register (ICDRT)......................................................... 253

I²C Bus Receive Data Register (ICDRR).......................................................... 253

I²C Bus Shift Register (ICDRS)........................................................................ 253

15.4 Operation .......................................................................................................................... 254

15.4.1

15.4.2

15.4.3

15.4.4

15.4.5

15.4.6

15.4.7

15.4.8

I²C Bus Format.................................................................................................. 254

Master Transmit Operation............................................................................... 255

Master Receive Operation................................................................................. 257

Slave Transmit Operation ................................................................................. 259

Slave Receive Operation................................................................................... 261

Clocked Synchronous Serial Format................................................................. 263

Noise Canceler.................................................................................................. 265

Example of Use................................................................................................. 266

15.5 Interrupts........................................................................................................................... 270

15.6 Bit Synchronous Circuit.................................................................................................... 271

15.7 Usage Notes...................................................................................................................... 272

15.7.1

15.7.2

Issue (Retransmission) of Start/Stop Conditions .............................................. 272

WAIT Setting in I²C Bus Mode Register (ICMR) ............................................ 272

Rev. 3.00 Sep. 14, 2006 Page xv of xxviii

Section 16 A/D Converter .................................................................................273

16.1 Features............................................................................................................................. 273

16.2 Input/Output Pins.............................................................................................................. 275

16.3 Register Description ......................................................................................................... 275

16.3.1

16.3.2

16.3.3

A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 275

A/D Control/Status Register (ADCSR) ............................................................ 276

A/D Control Register (ADCR) ......................................................................... 278

16.4 Operation .......................................................................................................................... 279

16.4.1

16.4.2

16.4.3

16.4.4

Single Mode...................................................................................................... 279

Scan Mode ........................................................................................................ 279

Input Sampling and A/D Conversion Time ...................................................... 280

External Trigger Input Timing.......................................................................... 281

16.5 A/D Conversion Accuracy Definitions............................................................................. 282

16.6 Usage Notes...................................................................................................................... 284

16.6.1

16.6.2

Permissible Signal Source Impedance.............................................................. 284

Influences on Absolute Accuracy ..................................................................... 284

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage

Detection Circuits............................................................................285

17.1 Features............................................................................................................................. 286

17.2 Register Descriptions........................................................................................................ 288

17.2.1

17.2.2

Low-Voltage-Detection Control Register (LVDCR)........................................ 288

Low-Voltage-Detection Status Register (LVDSR)........................................... 290

17.3 Operations......................................................................................................................... 291

17.3.1

17.3.2

Power-On Reset Circuit.................................................................................... 291

Low-Voltage Detection Circuit......................................................................... 292

Section 18 Power Supply Circuit ......................................................................299

18.1 When Using Internal Power Supply Step-Down Circuit .................................................. 299

18.2 When Not Using Internal Power Supply Step-Down Circuit ........................................... 300

Section 19 List of Registers...............................................................................301

19.1 Register Addresses (Address Order)................................................................................. 302

19.2 Register Bits ..................................................................................................................... 306

19.3 Register States in Each Operating Mode .......................................................................... 309

Section 20 Electrical Characteristics.................................................................313

20.1 Absolute Maximum Ratings ............................................................................................. 313

20.2 Electrical Characteristics (F-ZTAT^TMVersion)................................................................. 314

Rev. 3.00 Sep. 14, 2006 Page xvi of xxviii

20.2.1

20.2.2

20.2.3

20.2.4

20.2.5

20.2.6

20.2.7

20.2.8

20.2.9

Power Supply Voltage and Operating Ranges.................................................. 314

DC Characteristics ............................................................................................ 316

AC Characteristics ............................................................................................ 321

A/D Converter Characteristics.......................................................................... 325

Watchdog Timer Characteristics....................................................................... 326

Power-Supply-Voltage Detection Circuit Characteristics................................. 327

LVDI External Voltage Detection Circuit Characteristics................................ 327

Power-On Reset Characteristics........................................................................ 328

Flash Memory Characteristics .......................................................................... 329

20.3 Electrical Characteristics (Masked ROM Version)........................................................... 331

20.3.1

20.3.2

20.3.3

20.3.4

20.3.5

20.3.6

20.3.7

20.3.8

Power Supply Voltage and Operating Ranges.................................................. 331

DC Characteristics ............................................................................................ 333

AC Characteristics ............................................................................................ 338

A/D Converter Characteristics.......................................................................... 342

Watchdog Timer Characteristics....................................................................... 343

Power-Supply-Voltage Detection Circuit Characteristics................................. 344

LVDI External Voltage Detection Circuit Characteristics................................ 344

Power-On Reset Characteristics........................................................................ 345

20.4 Operation Timing.............................................................................................................. 346

20.5 Output Load Condition ..................................................................................................... 348

Appendix A Instruction Set ...............................................................................349

A.1 Instruction List.................................................................................................................. 349

A.2 Operation Code Map......................................................................................................... 364

A.3 Number of Execution States ............................................................................................. 367

A.4 Combinations of Instructions and Addressing Modes ...................................................... 378

Appendix B I/O Port Block Diagrams...............................................................379

B.1

I/O Port Block Diagrams .................................................................................................. 379

B.2

Port States in Each Operating State .................................................................................. 394

Appendix C Product Code Lineup.....................................................................395

Appendix D Package Dimensions .....................................................................396

Main Revisions and Additions in this Edition.....................................................399

Index ....................................................................................................................405

Rev. 3.00 Sep. 14, 2006 Page xvii of xxviii

Rev. 3.00 Sep. 14, 2006 Page xviii of xxviii

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram of H8/36912 Group.................................................................3

Figure 1.2 Internal Block Diagram of H8/36902 Group.................................................................4

Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)...........................................................5

Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)...........................................................6

Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) ..............................................7

Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) ..............................................8

Section 2 CPU

Figure 2.1 Memory Map (1) .........................................................................................................12

Figure 2.1 Memory Map (2) .........................................................................................................13

Figure 2.2 CPU Registers .............................................................................................................14

Figure 2.3 Usage of General Registers .........................................................................................15

Figure 2.4 Relationship between Stack Pointer and Stack Area...................................................16

Figure 2.5 General Register Data Formats (1)..............................................................................18

Figure 2.5 General Register Data Formats (2)..............................................................................19

Figure 2.6 Memory Data Formats.................................................................................................20

Figure 2.7 Instruction Formats......................................................................................................31

Figure 2.8 Branch Address Specification in Memory Indirect Mode...........................................35

Figure 2.9 On-Chip Memory Access Cycle..................................................................................37

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).....................................38

Figure 2.11 CPU Operation States................................................................................................39

Figure 2.12 State Transitions........................................................................................................40

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same

Address......................................................................................................................41

Section 3 Exception Handling

Figure 3.1 Reset Sequence............................................................................................................56

Figure 3.2 Stack Status after Exception Handling........................................................................58

Figure 3.3 Interrupt Sequence.......................................................................................................60

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure ..............61

Section 4 Address Break

Figure 4.1 Block Diagram of Address Break................................................................................63

Figure 4.2 Address Break Interrupt Operation Example (1).........................................................67

Figure 4.2 Address Break Interrupt Operation Example (2).........................................................68

Rev. 3.00 Sep. 14, 2006 Page xix of xxviii

Section 5 Clock Pulse Generators

Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69

Figure 5.2 State Transition of System Clock................................................................................ 75

Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1)........ 76

Figure 5.4 Flowchart of Clock Switching External Clock to On-chip Oscillator Clock (2)......... 77

Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock.................... 78

Figure 5.6 Timing Chart to Switch External Clock to On-chip Oscillator Clock......................... 79

Figure 5.7 Example of Trimming Flow for On-chip Oscillator Frequency.................................. 80

Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency..................................... 81

Figure 5.9 Example of Connection to Crystal Resonator ............................................................. 82

Figure 5.10 Equivalent Circuit of Crystal Resonator.................................................................... 82

Figure 5.11 Example of Connection to Ceramic Resonator ......................................................... 83

Figure 5.12 Example of External Clock Input.............................................................................. 83

Figure 5.13 Example of Incorrect Board Design.......................................................................... 84

Section 6 Power-Down Modes

Figure 6.1 Mode Transition Diagram ...........................................................................................91

Section 7 ROM

Figure 7.1 Flash Memory Block Configuration............................................................................ 98

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 106

Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 108

Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 111

Section 9 I/O Ports

Figure 9.1 Port 1 Pin Configuration............................................................................................ 117

Figure 9.2 Port 2 Pin Configuration............................................................................................ 121

Figure 9.3 Port 5 Pin Configuration............................................................................................ 124

Figure 9.4 Port 7 Pin Configuration............................................................................................ 128

Figure 9.5 Port 8 Pin Configuration............................................................................................ 130

Figure 9.6 Port B Pin Configuration........................................................................................... 134

Figure 9.7 Port C Pin Configuration........................................................................................... 136

Section 10 Timer B1

Figure 10.1 Block Diagram of Timer B1.................................................................................... 139

Section 11 Timer V

Figure 11.1 Block Diagram of Timer V ..................................................................................... 146

Figure 11.2 Increment Timing with Internal Clock.................................................................... 153

Figure 11.3 Increment Timing with External Clock................................................................... 153

Figure 11.4 OVF Set Timing...................................................................................................... 153

Figure 11.5 CMFA and CMFB Set Timing................................................................................ 154

Rev. 3.00 Sep. 14, 2006 Page xx of xxviii

Figure 11.6 TMOV Output Timing ............................................................................................154

Figure 11.7 Clear Timing by Compare Match............................................................................154

Figure 11.8 Clear Timing by TMRIV Input ...............................................................................155

Figure 11.9 Pulse Output Example.............................................................................................155

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input.......................................156

Figure 11.11 Contention between TCNTV Write and Clear ......................................................157

Figure 11.12 Contention between TCORA Write and Compare Match.....................................158

Figure 11.13 Internal Clock Switching and TCNTV Operation.................................................158

Section 12 Timer W

Figure 12.1 Timer W Block Diagram.........................................................................................161

Figure 12.2 Free-Running Counter Operation............................................................................172

Figure 12.3 Periodic Counter Operation.....................................................................................173

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................173

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................174

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................174

Figure 12.7 Input Capture Operating Example...........................................................................175

Figure 12.8 Buffer Operation Example (Input Capture).............................................................176

Figure 12.9 PWM Mode Example (1) ........................................................................................177

Figure 12.10 PWM Mode Example (2) ......................................................................................177

Figure 12.11 Buffer Operation Example (Output Compare) ......................................................178

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: Initial Output Values are Set to 0).............................179

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: Initial Output Values are Set to 1).............................180

Figure 12.14 Count Timing for Internal Clock Source...............................................................181

Figure 12.15 Count Timing for External Clock Source..............................................................181

Figure 12.16 Output Compare Output Timing ...........................................................................182

Figure 12.17 Input Capture Input Signal Timing........................................................................183

Figure 12.18 Timing of Counter Clearing by Compare Match...................................................183

Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................184

Figure 12.20 Buffer Operation Timing (Input Capture) .............................................................184

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match..................................185

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture......................................186

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................186

Figure 12.24 Contention between TCNT Write and Clear .........................................................188

Figure 12.25 Internal Clock Switching and TCNT Operation....................................................188

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the

Same Timing .........................................................................................................189

Rev. 3.00 Sep. 14, 2006 Page xxi of xxviii

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 191

Figure 13.2 Watchdog Timer Operation Example...................................................................... 195

Section 14 Serial Communication Interface 3 (SCI3)

Figure 14.1 Block Diagram of SCI3........................................................................................... 198

Figure 14.2 Block Diagram of Noise Filter Circuit .................................................................... 211

Figure 14.3 Data Format in Asynchronous Communication ...................................................... 212

Figure 14.4 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 212

Figure 14.5 Sample SCI3 Initialization Flowchart ..................................................................... 213

Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ........................................................................... 214

Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 215

Figure 14.8 Example of SCI3 Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ........................................................................... 216

Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)........................... 218

Figure 14.10 Data Format in Clocked Synchronous Communication ........................................ 219

Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 221

Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 222

Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode................................ 223

Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 224

Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode)............................................................................... 226

Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A) .......................................... 228

Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart........................................ 230

Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 232

Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 233

Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 234

Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode ...................................... 237

Section 15 I²C Bus Interface 2 (IIC2)

Figure 15.1 Block Diagram of I²C Bus Interface 2..................................................................... 240

Figure 15.2 External Circuit Connections of I/O Pins................................................................ 241

Figure 15.3 I²C Bus Formats ...................................................................................................... 254

Figure 15.4 I²C Bus Timing........................................................................................................ 254

Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 256

Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 256

Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 258

Rev. 3.00 Sep. 14, 2006 Page xxii of xxviii

Figure 15.8 Master Receive Mode Operation Timing (2)...........................................................259

Figure 15.9 Slave Transmit Mode Operation Timing (1) ...........................................................260

Figure 15.10 Slave Transmit Mode Operation Timing (2) .........................................................261

Figure 15.11 Slave Receive Mode Operation Timing (1)...........................................................262

Figure 15.12 Slave Receive Mode Operation Timing (2)...........................................................262

Figure 15.13 Clocked Synchronous Serial Transfer Format.......................................................263

Figure 15.14 Transmit Mode Operation Timing.........................................................................264

Figure 15.15 Receive Mode Operation Timing ..........................................................................265

Figure 15.16 Block Diagram of Noise Canceler.........................................................................265

Figure 15.17 Sample Flowchart for Master Transmit Mode.......................................................266

Figure 15.18 Sample Flowchart for Master Receive Mode........................................................267

Figure 15.19 Sample Flowchart for Slave Transmit Mode.........................................................268

Figure 15.20 Sample Flowchart for Slave Receive Mode ..........................................................269

Figure 15.21 Timing of Bit Synchronous Circuit .......................................................................271

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter ...........................................................................274

Figure 16.2 A/D Conversion Timing..........................................................................................280

Figure 16.3 External Trigger Input Timing ................................................................................281

Figure 16.4 A/D Conversion Accuracy Definitions (1)..............................................................283

Figure 16.5 A/D Conversion Accuracy Definitions (2)..............................................................283

Figure 16.6 Analog Input Circuit Example.................................................................................284

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Figure 17.1 Block Diagram around BGR ...................................................................................286

Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....287

Figure 17.3 Operational Timing of Power-On Reset Circuit......................................................292

Figure 17.4 Operating Timing of LVDR Circuit........................................................................293

Figure 17.5 Operational Timing of LVDI Circuit.......................................................................294

Figure 17.6 Operational Timing of LVDI Circuit

(When Compared Voltage is Input through ExtU and ExtD Pins)..........................296

Figure 17.7 Timing for Enabling/Disabling of Low-Voltage Detection Circuit.........................297

Section 18 Power Supply Circuit

Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................299

Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............300

Section 20 Electrical Characteristics

Figure 20.1 System Clock Input Timing.....................................................................................346

Figure 20.2 RES Low Width Timing..........................................................................................346

Figure 20.3 Input Timing............................................................................................................346

Figure 20.4 I²C Bus Interface Input/Output Timing...................................................................347

Rev. 3.00 Sep. 14, 2006 Page xxiii of xxviii

Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 347

Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode.................................... 348

Figure 20.7 Output Load Circuit ................................................................................................ 348

Appendix

Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 379

Figure B.2 Port 1 Block Diagram (P14) ..................................................................................... 380

Figure B.3 Port 2 Block Diagram (P22) ..................................................................................... 381

Figure B.4 Port 2 Block Diagram (P21) ..................................................................................... 382

Figure B.5 Port 2 Block Diagram (P20) ..................................................................................... 383

Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) ................................... 384

Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) ................................... 385

Figure B.7 Port 5 Block Diagram (P55) ..................................................................................... 386

Figure B.8 Port 5 Block Diagram (P76) ..................................................................................... 387

Figure B.9 Port 7 Block Diagram (P75) ..................................................................................... 388

Figure B.10 Port 7 Block Diagram (P74) ................................................................................... 389

Figure B.11 Port 8 Block Diagram (P84 to P81)........................................................................ 390

Figure B.12 Port 8 Block Diagram (P80) ................................................................................... 391

Figure B.13 Port B Block Diagram (PB3, PB2)......................................................................... 392

Figure B.14 Port B Block Diagram (PB1, PB0)......................................................................... 392

Figure B.15 Port C Block Diagram (PC1).................................................................................. 393

Figure B.16 Port C Block Diagram (PC0).................................................................................. 394

Figure D.1 FP-32D Package Dimensions................................................................................... 396

Figure D.2 FP-32A Package Dimension..................................................................................... 397

Figure D.3 32P4B Package Dimension ...................................................................................... 398

Rev. 3.00 Sep. 14, 2006 Page xxiv of xxviii

Tables

Section 1 Overview

Table 1.1 Pin Functions ............................................................................................................9

Section 2 CPU

Table 2.1

Table 2.2

Table 2.3

Table 2.4

Table 2.5

Table 2.6

Table 2.7

Table 2.8

Table 2.9

Table 2.10

Table 2.11

Table 2.12

Operation Notation .................................................................................................21

Data Transfer Instructions.......................................................................................22

Arithmetic Operations Instructions (1) ...................................................................23

Arithmetic Operations Instructions (2) ...................................................................24

Logic Operations Instructions.................................................................................25

Shift Instructions.....................................................................................................25

Bit Manipulation Instructions (1)............................................................................26

Bit Manipulation Instructions (2)............................................................................27

Branch Instructions.................................................................................................28

System Control Instructions....................................................................................29

Block Data Transfer Instructions............................................................................30

Addressing Modes ..................................................................................................32

Absolute Address Access Ranges...........................................................................34

Effective Address Calculation (1)...........................................................................35

Effective Address Calculation (2)...........................................................................36

Section 3 Exception Handling

Table 3.1

Table 3.2

Exception Sources and Vector Address..................................................................47

Interrupt Wait States ...............................................................................................59

Section 4 Address Break

Table 4.1

Access and Data Bus Used .....................................................................................65

Section 5 Clock Pulse Generators

Table 5.1

Crystal Resonator Parameters.................................................................................82

Section 6 Power-Down Modes

Table 6.1

Table 6.2

Table 6.3

Operating Frequency and Wait Time......................................................................87

Transition Mode after SLEEP Instruction Execution and Interrupt Handling........92

Internal State in Each Operating Mode...................................................................92

Section 7 ROM

Table 7.1

Table 7.2

Table 7.3

Setting Programming Modes ................................................................................102

Boot Mode Operation ...........................................................................................104

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible.................................................................................................................105

Rev. 3.00 Sep. 14, 2006 Page xxv of xxviii

Table 7.4

Table 7.5

Table 7.6

Reprogram Data Computation Table.................................................................... 109

Additional-Program Data Computation Table...................................................... 109

Programming Time............................................................................................... 109

Section 10 Timer B1

Table 10.1

Timer B1 Operating Modes.................................................................................. 143

Section 11 Timer V

Table 11.1

Table 11.2

Pin Configuration.................................................................................................. 147

Clock Signals to Input to TCNTV and Counting Conditions ............................... 149

Section 12 Timer W

Table 12.1

Table 12.2

Timer W Functions............................................................................................... 160

Pin Configuration.................................................................................................. 162

Section 14 Serial Communication Interface 3 (SCI3)

Table 14.1

Table 14.2

Table 14.3

Table 14.4

Pin Configuration.................................................................................................. 199

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)............ 207

Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 209

Examples of BRR Settings for Various Bit Rates

(Clocked Synchronous Mode) .............................................................................. 210

SSR Status Flags and Receive Data Handling...................................................... 217

SCI3 Interrupt Requests........................................................................................ 235

Table 14.5

Table 14.6

Section 15 I²C Bus Interface 2 (IIC2)

Table 15.1

Table 15.2

Table 15.3

Table 15.4

Pin Configuration.................................................................................................. 241

Transfer Rate ........................................................................................................ 244

Interrupt Requests................................................................................................. 270

Time for Monitoring SCL..................................................................................... 271

Section 16 A/D Converter

Table 16.1

Table 16.2

Table 16.3

Pin Configuration.................................................................................................. 275

Analog Input Channels and Corresponding ADDR Registers.............................. 276

A/D Conversion Time (Single Mode)................................................................... 281

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Table 17.1 LVDCR Settings and Select Functions................................................................. 289

Section 20 Electrical Characteristics

Table 20.1

Table 20.2

Table 20.3

Table 20.4

Absolute Maximum Ratings ................................................................................. 313

DC Characteristics (1) .......................................................................................... 316

DC Characteristics (2) .......................................................................................... 320

AC Characteristics................................................................................................ 321

I²C Bus Interface Timing...................................................................................... 323

Rev. 3.00 Sep. 14, 2006 Page xxvi of xxviii

Table 20.5

Table 20.6

Table 20.7

Table 20.8

Table 20.9

Table 20.10

Table 20.11

Table 20.12

Table 20.13

Table 20.14

Table 20.15

Table 20.16

Table 20.17

Table 20.18

Table 20.19

Table 20.20

Serial Interface (SCI3) Timing .............................................................................324

A/D Converter Characteristics..............................................................................325

Watchdog Timer Characteristics...........................................................................326

Power-Supply-Voltage Detection Circuit Characteristics.....................................327

LVDI External Voltage Detection Circuit Characteristics....................................327

Power-On Reset Circuit Characteristics............................................................328

Flash Memory Characteristics ..........................................................................329

DC Characteristics (1).......................................................................................333

DC Characteristics (2).......................................................................................337

AC Characteristics ............................................................................................338

I²C Bus Interface Timing..................................................................................340

Serial Interface (SCI3) Timing .........................................................................341

A/D Converter Characteristics..........................................................................342

Watchdog Timer Characteristics.......................................................................343

Power-Supply-Voltage Detection Circuit Characteristics.................................344

LVDI External Voltage Detection Circuit Characteristics................................344

Power-On Reset Circuit Characteristics............................................................345

Appendix

Table A.1

Table A.2

Table A.3

Table A.4

Table A.5

Instruction Set.......................................................................................................351

Operation Code Map (1).......................................................................................364

Operation Code Map (2).......................................................................................365

Operation Code Map (3).......................................................................................366

Number of Cycles in Each Instruction..................................................................368

Number of Cycles in Each Instruction..................................................................369

Combinations of Instructions and Addressing Modes ..........................................378

Rev. 3.00 Sep. 14, 2006 Page xxvii of xxviii

Rev. 3.00 Sep. 14, 2006 Page xxviii of xxviii

Section 1 Overview

1.1

Features

•

High-speed H8/300H central processing unit with an internal 16-bit architecture

 Upward-compatible with H8/300 CPU on an object level

 Sixteen 16-bit general registers

 62 basic instructions

•

Various peripheral functions

 Timer B1* (8-bit timer)

 Timer V (8-bit timer)

 Timer W (16-bit timer)

 Watchdog timer

 SCI3 (Asynchronous or clocked synchronous serial communication interface)

 10-bit A/D converter

 I²C bus interface* (conforms to the Philips I²C bus interface functions)

 POR/LVD (Power-on reset and low-voltage detection circuits)

 Address break

Note: * Available for the H8/36912 Group only.

•

On-chip memory

Product Classification

Type

ROM

RAM

Remarks

Flash memory

version

(F-ZTAT^TM

H8/36912F HD64F36912G

H8/36902F HD64F36902G

8 kbytes

1,536 bytes

version)

Masked ROM

version

H8/36912

H8/36911

H8/36902

H8/36901

H8/36900

HD64336912G

HD64336911G

HD64336902G

HD64336901G

HD64336900G

8 kbytes

4 kbytes

8 kbytes

4 kbytes

2 kbytes

512 bytes

256 bytes

512 bytes

256 bytes

Note: F-ZTAT^TMis a trademark of Renesas Technology Corp.

Rev. 3.00 Sep. 14, 2006 Page 1 of 408

REJ09B0105-0300

Section 1 Overview

•

General I/O ports

 Eighteen I/O pins, including five large-current ports (I_OL= 20 mA, @V_OL= 1.5 V,

−I_OH= 4 mA, @V_OH= Vcc − 1.0 V)

 Four input only pins (also used for analog input)

•

On-chip oscillator

 Frequency accuracy:

8MHz 1% (Typ.)

Vcc = 5.0 V, Ta = 25°C

(Flash memory version): 8MHz 3%

Vcc = 4.0 to 5.0 V, Ta = −20 to 75°C

10MHz 4% (Typ.) Vcc = 4.0 to 5.0 V, Ta = −20 to 75°C

Supports various power-down modes

Compact package

•

Package

Code

Body Size

Pin Pitch

0.8 mm

Remarks

LQFP-32

SOP-32

FP-32A

FP-32D

32P4B

^7.0× 7.0 mm

11.3 × 20.45 mm

400 mil

1.27 mm

1.78 mm

SDIP-32*

Note:

*

Flash memory version only

Rev. 3.00 Sep. 14, 2006 Page 2 of 408

REJ09B0105-0300

Section 1 Overview

1.2

Internal Block Diagram

E10T_0*

E10T_1*

E10T_2*

System

On-chip

clock

CPU

H8/300H

oscillator

generator

Data bus (lower)

P17/IRQ3/TRGV

P14/IRQ0

P76/TMOV

P75/TMCIV

P74/TMRIV

ROM

RAM

SCI3

IIC2

Timer W

Timer V

P84/FTIOD

P83/FTIOC

P82/FTIOB

P81/FTIOA

P80/FTCI

P22/TXD

P21/RXD

P20/SCK3

Watchdog

timer

Timer B1

P57/SCL

P56/SDA

A/D

converter

POR & LVD

P55/WKP5/ADTRG

Port C

Port B

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.1 Internal Block Diagram of H8/36912 Group

Rev. 3.00 Sep. 14, 2006 Page 3 of 408

REJ09B0105-0300

Section 1 Overview

E10T_0*

E10T_1*

E10T_2*

System

clock

generator

On-chip

oscillator

CPU

H8/300H

Data bus (lower)

P17/IRQ3/TRGV

P14/IRQ0

P76/TMOV

P75/TMCIV

P74/TMRIV

ROM

RAM

SCI3

P22/TXD

P21/RXD

P20/SCK3

Timer W

Timer V

P84/FTIOD

P83/FTIOC

P82/FTIOB

P81/FTIOA

P80/FTCI

Watchdog

timer

P57

P56

A/D

converter

POR & LVD

P55/WKP5/ADTRG

Port C

Port B

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.2 Internal Block Diagram of H8/36902 Group

Rev. 3.00 Sep. 14, 2006 Page 4 of 408

REJ09B0105-0300

Section 1 Overview

1.3

Pin Arrangement

P84/FTIOD

P74/TMRIV

P75/TMCIV

P76/TMOV

PB3/AN3/ExtU

PB2/AN2/ExtD

PB1/AN1

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

P14/IRQ0

P56/SDA

P57/SCL

E10T_2*

E10T_1*

E10T_0*

H8/36912 Group

(Top view)

P17/IRQ3/TRGV

PB0/AN0

NMI

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)

Rev. 3.00 Sep. 14, 2006 Page 5 of 408

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Section 1 Overview

P84/FTIOD

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

P14/IRQ0

P56

P74/TMRIV

P75/TMCIV

P76/TMOV

PB3/AN3/ExtU

PB2/AN2/ExtD

PB1/AN1

P57

E10T_2*

E10T_1*

E10T_0*

P17/IRQ3/TRGV

NMI

H8/36902 Group

(Top view)

PB0/AN0

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)

Rev. 3.00 Sep. 14, 2006 Page 6 of 408

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Section 1 Overview

PB3/AN3/ExtU

PB2/AN2/ExtD

PB1/AN1

P76/TMOV

P75/TMCIV

P74/TMRIV

P84/FTIOD

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

3

PB0/AN0

4

AVcc

P83/FTIOC

P82/FTIOB

P81/FTIOA

P80/FTCI

5

Vcc

RES

6

7

TEST

H8/36912 Group

(Top view)

8

Vss

P22/TXD

P21/RXD

P20/SCK3

9

PC1/OSC2/CLKOUT

PC0/OSC1

10

11

12

13

14

15

16

VCL

P55/WKP5/ADTRG

P14/IRQ0

NMI

P17/IRQ3/TRGV

P56/SDA

P57/SCL

E10T_0*

E10T_1*

E10T_2*

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B)

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Section 1 Overview

PB3/AN3/ExtU

PB2/AN2/ExtD

PB1/AN1

P76/TMOV

P75/TMCIV

P74/TMRIV

P84/FTIOD

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

3

PB0/AN0

4

AVcc

P83/FTIOC

P82/FTIOB

P81/FTIOA

P80/FTCI

5

Vcc

RES

6

7

TEST

H8/36902 Group

(Top view)

8

Vss

P22/TXD

P21/RXD

P20/SCK3

9

PC1/OSC2/CLKOUT

PC0/OSC1

10

11

12

13

14

15

16

VCL

P55/WKP5/ADTRG

P14/IRQ0

NMI

P17/IRQ3/TRGV

P56

P57

E10T_0*

E10T_1*

E10T_2*

Note: * Can also be used for the E7 or E8 emulator.

Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B)

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Section 1 Overview

1.4

Pin Functions

Table 1.1 Pin Functions

Pin No.

FP-32D,

Type

Symbol

32P4B

FP-32A

I/O

Functions

Power

source

V_CC

6

2

Input

Power supply pin. Connect this pin

to the system power supply.

V_SS

9

5

1

Input

Ground pin. Connect this pin to the

system power supply (0 V).

AV_CC

Analog power supply pin for the

A/D converter. When the A/D

converter is not used, connect this

pin to the system power supply.

V_CL

12

8

Input

Internal step-down power supply

pin. Connect a capacitor of around

0.1 µF between this pin and the Vss

pin for stabilization.

Clock

OSC1

11

10

7

6

Input

These pins are connected to a

crystal or ceramic resonator for

system clocks, or can be used to

input an external clock. When an

on-chip oscillator is used, system

clocks can be output to OSC2. See

section 5, Clock Pulse Generators,

for a typical connection.

OSC2/

CLKOUT

Output

System

control

RES

7

3

Input

Reset pin. The pull-up resistor (typ.

150 kΩ) is incorporated. When

driven low, the chip is reset.

TEST

8

4

9

Input

Test pin. Connect this pin to Vss.

External

interrupt

NMI

13

Non-maskable interrupt request

input pin. Be sure to pull-up by a

pull-up resistor.

IRQ0,

20, 14

21

16, 10

17

Input

External interrupt request input

pins. Can select the rising or falling

edge.

IRQ3

WKP5

External interrupt request input pin.

Can select the rising or falling edge.

Rev. 3.00 Sep. 14, 2006 Page 9 of 408

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Section 1 Overview

Pin No.

FP-32D,

32P4B

Type

Symbol

FP-32A

I/O

Output TMOV is an output pin for

waveforms generated by the output

Functions

Timer V

TMOV

32

28

compare function.

TMCIV

TMRIV

TRGV

FTCI

31

27

Input

I/O

External event input pin

Counter reset input pin

Counter start trigger input pin

External event input pin

30

26

14

10

Timer W

25

21

FTIOA to

FTIOD

26 to 29

22 to 25

Output compare output/ input

capture input/ PWM output common

pins

I²C bus

interface 2*

SDA

SCL

19

18

15

14

I/O

I²C data I/O pin. NMOS open drain

output can directly drive the bus.

I²C clock I/O pin. NMOS open drain

output can directly drive the bus.

Serial

communi-

cation

TXD

24

23

22

20

19

18

Output Transmit data output pin

RXD

SCK3

Input

I/O

Receive data input pin

Clock I/O pin

interface

A/D

converter

AN3 to AN0 1 to 4

29 to 32

17

Input

I/O

Analog input pin

A/D converter trigger input pin

2-bit I/O port

ADTRG

21

I/O ports

P17, P14

14, 20

10, 16

20 to 18

P22 to P20 24 to 22

I/O

3-bit I/O port

P57 to P55 18, 19, 21 14, 15, 17 I/O

3-bit I/O port

P76 to P74 32 to 30

P84 to P80 29 to 25

PB3 to PB0 1 to 4

28 to 26

25 to 21

29 to 32

6, 7

I/O

3-bit I/O port

I/O

5-bit I/O port

Input

I/O

4-bit input port

2-bit I/O port

PC1, PC0

10, 11

Low voltage ExtU, ExtD 1, 2

detection

circuit

29, 30

Input

External input pins for the detection

voltage used in the low-voltage

detection circuit

E7, E8

E10T_0,

E10T_1,

E10T_2

15, 16, 17 11, 12, 13 

Interface pins for the E7 or E8

emulator

Note:

*

Available for the H8/36912 Group only.

Rev. 3.00 Sep. 14, 2006 Page 10 of 408

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Section 2 CPU

This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with

the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space.

•

Upward-compatible with H8/300 CPUs

 Can execute H8/300 CPUs object programs

 Additional eight 16-bit extended registers

 32-bit transfer and arithmetic and logic instructions are added

 Signed multiply and divide instructions are added.

General-register architecture

•

 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

Sixty-two basic instructions

 8/16/32-bit data transfer and arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

Eight addressing modes

•

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

•

64-kbyte address space

High-speed operation

 All frequently-used instructions execute in two or four states

 8/16/32-bit register-register add/subtract

 8 × 8-bit register-register multiply : 14 states

 16 ÷ 8-bit register-register divide : 14 states

: 2 state

 16 × 16-bit register-register multiply : 22 states

 32 ÷ 16-bit register-register divide : 22 states

Power-down state

•

 Transition to power-down state by SLEEP instruction

CPU30H2E_000120030300

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Section 2 CPU

2.1

Address Space and Memory Map

The address space of this LSI is 64 kbytes, which includes the program area and the data area. The

following two figures show the memory map, respectively.

H8/36912F

H8/36902F

(Flash memory version)

H8/36912

H8/36902

(Masked ROM version)

H'0000

H'0045

H'0046

H'0000

H'0045

H'0046

Interrupt vector

On-chip ROM

(8 kbytes)

On-chip ROM

(8 kbytes)

H'1FFF

H'2000

H'1FFF

E7 or E8 control

program area

(4 kbytes)

H'2FFF

Not used

H'F600

H'F77F

H'F600

H'F77F

Internal I/O register

Not used

Internal I/O register

Not used

H'F980

(E7 or E8 work area,

for flash memory

programming:

1 kbyte)

On-chip RAM

(1.5 kbytes)

H'FD7F

H'FD80

On-chip RAM

user area

On-chip RAM

user area

(512 bytes)

H'FF7F

H'FF80

H'FF7F

H'FF80

Internal I/O register

H'FFFF

Figure 2.1 Memory Map (1)

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Section 2 CPU

H8/36911

H8/36901

H8/36900

(Masked ROM version)

H'0000

H'0045

H'0046

H'0000

H'0045

H'0046

Interrupt vector

On-chip ROM

(2 kbytes)

On-chip ROM

(4 kbytes)

H'07FF

H'0FFF

Not used

H'F600

H'F77F

H'F600

H'F77F

Internal I/O register

Not used

Internal I/O register

Not used

H'FE80

On-chip RAM

user area

On-chip RAM

user area

(256 bytes)

H'FF7F

H'FF80

H'FF7F

H'FF80

Internal I/O register

H'FFFF

Figure 2.1 Memory Map (2)

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Section 2 CPU

2.2

Register Configuration

The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;

general registers and control registers. The control registers are a 24-bit program counter (PC), and

an 8-bit condition code register (CCR).

General registers (ERn)

15

0 7

0

ER0

E0

E1

E2

E3

E4

E5

E6

E7

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

Control registers (CR)

23

0

PC

7

6 5 4 3 2 1

CCR

I UI H U N Z V C

[Legend]

SP:

PC:

Stack pointer

Program counter

H: Half-carry flag

U: User bit

CCR: Condition-code register

N: Negative flag

Z: Zero flag

V: Overflow flag

C: Carry flag

I:

Interrupt mask bit

User bit

UI:

Figure 2.2 CPU Registers

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Section 2 CPU

2.2.1

General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally

identical and can be used as both address registers and data registers. When a general register is

used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates

the usage of the general registers. When the general registers are used as 32-bit registers or address

registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L

to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit

registers.

The usage of each register can be selected independently.

• Address registers

• 32-bit registers

• 16-bit registers

• 8-bit registers

E registers (extended registers)

(E0 to E7)

ER registers

(ER0 to ER7)

RH registers

(R0H to R7H)

R registers

(R0 to R7)

RL registers

(R0L to R7L)

Figure 2.3 Usage of General Registers

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Section 2 CPU

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the

stack.

Free area

SP (ER7)

Stack area

Figure 2.4 Relationship between Stack Pointer and Stack Area

2.2.2

Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an

instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the

start address is loaded by the vector address generated during reset exception-handling sequence.

2.2.3

Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1

by reset exception-handling sequence, but other bits are not initialized.

Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the

LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching

conditions for conditional branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List.

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Section 2 CPU

Initial

Bit

Bit Name Value

R/W

Description

7

I

1

R/W

Interrupt Mask Bit

Masks interrupts other than NMI when set to 1. NMI is

accepted regardless of the I bit setting. The I bit is set to

1 at the start of an exception-handling sequence.

6

5

UI

H

Undefined R/W

User Bit

Can be written and read by software using the LDC, STC,

ANDC, ORC, and XORC instructions.

Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or

NEG.B instruction is executed, this flag is set to 1 if there

is a carry or borrow at bit 3, and cleared to 0 otherwise.

When the ADD.W, SUB.W, CMP.W, or NEG.W

instruction is executed, the H flag is set to 1 if there is a

carry or borrow at bit 11, and cleared to 0 otherwise.

When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is

executed, the H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

4

3

2

1

0

U

N

Z

Undefined R/W

User Bit

Can be written and read by software using the LDC, STC,

ANDC, ORC, and XORC instructions.

Negative Flag

Stores the value of the most significant bit of data as a

sign bit.

Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to indicate

non-zero data.

V

C

Overflow Flag

Set to 1 when an arithmetic overflow occurs, and cleared

to 0 at other times.

Carry Flag

Set to 1 when a carry occurs, and cleared to 0 otherwise.

Used by:

•

Add instructions, to indicate a carry

Subtract instructions, to indicate a borrow

Shift and rotate instructions, to indicate a carry

The carry flag is also used as a bit accumulator by bit

manipulation instructions.

Rev. 3.00 Sep. 14, 2006 Page 17 of 408

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Section 2 CPU

2.3

Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit

(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,

…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two

digits of 4-bit BCD data.

2.3.1

General Register Data Formats

Figure 2.5 shows the data formats in general registers.

Data Type

1-bit data

General Register

RnH

Data Format

7

0

Don't care

7

6

5

4

3

2

1 0

7

0

Don't care

4 3

RnL

RnH

RnL

RnH

RnL

7

6

5

4

3

2

1 0

1-bit data

7

0

4-bit BCD data

Upper

Lower

Don't care

4 3

7

0

4-bit BCD data

Byte data

Don't care

Upper

Lower

7

0

Don't care

MSB

LSB

7

0

Byte data

Don't care

MSB

LSB

Figure 2.5 General Register Data Formats (1)

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Section 2 CPU

Data Type

Word data

General

Register

Data Format

Rn

15

0

MSB

LSB

Word data

En

15

0

MSB

31

LSB

Longword

data

ERn

16 15

0

MSB

LSB

[Legend]

ERn: General register ER

En:

Rn:

General register E

General register R

RnH: General register RH

RnL: General register RL

MSB: Most significant bit

LSB: Least significant bit

Figure 2.5 General Register Data Formats (2)

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Section 2 CPU

2.3.2

Memory Data Formats

Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and

longword data in memory, however word or longword data must begin at an even address. If an

attempt is made to access word or longword data at an odd address, an address error does not

occur, however the least significant bit of the address is regarded as 0, so access begins the

preceding address. This also applies to instruction fetches.

When ER7 (SP) is used as an address register to access the stack, the operand size should be word

or longword.

Data Type

Address

Data Format

7

0

1-bit data

Byte data

Word data

Address L

6

5

4

3

2

1

MSB

LSB

Address 2M

Address 2M+1

Longword data

Address 2N

MSB

Address 2N+1

Address 2N+2

Address 2N+3

LSB

Figure 2.6 Memory Data Formats

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Section 2 CPU

2.4

Instruction Set

2.4.1

Table of Instructions Classified by Function

The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each

functional category. The notation used in tables 2.2 to 2.9 is defined below.

Table 2.1 Operation Notation

Symbol

Rd

Rs

Rn

ERn

(EAd)

(EAs)

CCR

N

Description

General register (destination)*

General register (source)*

General register*

General register (32-bit register or address register)

Destination operand

Source operand

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

Z

V

C

PC

SP

#IMM

disp

+

Immediate data

Displacement

Addition

–

Subtraction

×

Multiplication

÷

Division

∧

Logical AND

∨

Logical OR

⊕

Logical XOR

→

Move

¬

NOT (logical complement)

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Section 2 CPU

Symbol

Description

:3/:8/:16/:24

3-, 8-, 16-, or 24-bit length

Note:

*

General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7).

Table 2.2 Data Transfer Instructions

Instruction

Size*

Function

MOV

B/W/L

(EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register.

MOVFPE

MOVTPE

POP

B

(EAs) → Rd, Cannot be used in this LSI.

Rs → (EAs) Cannot be used in this LSI.

B

W/L

@SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH

W/L

Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note:

*

Refers to the operand size.

B:

W:

L:

Byte

Word

Longword

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Section 2 CPU

Table 2.3 Arithmetic Operations Instructions (1)

Instruction

Size*

Function

ADD

SUB

B/W/L

Rd Rs → Rd, Rd #IMM → Rd

Performs addition or subtraction on data in two general registers, or on

immediate data and data in a general register (immediate byte data

cannot be subtracted from byte data in a general register. Use the SUBX

or ADD instruction.)

ADDX

SUBX

B

Rd Rs C → Rd, Rd #IMM C → Rd

Performs addition or subtraction with carry on byte data in two general

registers, or on immediate data and data in a general register.

INC

DEC

B/W/L

Rd 1 → Rd, Rd 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands

can be incremented or decremented by 1 only.)

ADDS

SUBS

L

Rd 1 → Rd, Rd 2 → Rd, Rd 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

DAA

DAS

B

Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to the CCR to produce 4-bit BCD data.

MULXU

MULXS

DIVXU

B/W

Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either

8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Rd × Rs → Rd

Performs signed multiplication on data in two general registers: either 8

bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16

bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →

16-bit quotient and 16-bit remainder.

Note:

*

Refers to the operand size.

B:

W:

L:

Byte

Word

Longword

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Section 2 CPU

Table 2.3 Arithmetic Operations Instructions (2)

Instruction

Size*

Function

DIVXS

B/W

Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷

8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bit remainder.

CMP

NEG

EXTU

B/W/L

W/L

Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register

or with immediate data, and sets CCR bits according to the result.

0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a

general register.

Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left.

EXTS

W/L

Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by extending the sign bit.

Note:

*

Refers to the operand size.

B:

W:

L:

Byte

Word

Longword

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Table 2.4 Logic Operations Instructions

Instruction

Size*

Function

AND

B/W/L

Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data.

OR

B/W/L

Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data.

XOR

NOT

Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data.

¬ (Rd) → (Rd)

Takes the one's complement of general register contents.

Note:

*

Refers to the operand size.

B:

W:

L:

Byte

Word

Longword

Table 2.5 Shift Instructions

Instruction

Size*

Function

SHAL

SHAR

B/W/L

Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

SHLL

SHLR

B/W/L

Rd (shift) → Rd

Performs a logical shift on general register contents.

ROTL

ROTR

Rd (rotate) → Rd

Rotates general register contents.

ROTXL

ROTXR

Rd (rotate) → Rd

Rotates general register contents through the carry flag.

Note:

*

Refers to the operand size.

B:

W:

L:

Byte

Word

Longword

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Table 2.6 Bit Manipulation Instructions (1)

Instruction

Size*

Function

BSET

B

1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register.

BCLR

BNOT

BTST

B

0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The

bit number is specified by 3-bit immediate data or the lower three bits of

a general register.

¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register.

¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or

clears the Z flag accordingly. The bit number is specified by 3-bit

immediate data or the lower three bits of a general register.

BAND

B

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

BIAND

C ∧ ¬ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in a general

register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR

B

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

BIOR

C ∨ ¬ (<bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in a general register

or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Note:

*

Refers to the operand size.

B: Byte

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Table 2.6 Bit Manipulation Instructions (2)

Instruction

Size*

Function

BXOR

B

C ⊕ (<bit-No.> of <EAd>) → C

XORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

BIXOR

B

C ⊕ ¬ (<bit-No.> of <EAd>) → C

XORs the carry flag with the inverse of a specified bit in a general

register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD

B

(<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the

carry flag.

BILD

¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory

operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST

B

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or

memory operand.

BIST

¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general

register or memory operand.

The bit number is specified by 3-bit immediate data.

Note:

*

Refers to the operand size.

B: Byte

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Table 2.7 Branch Instructions

Instruction

Size

Function

Bcc*

—

Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic

BRA(BT)

BRN(BF)

BHI

Description

Always (true)

Never (false)

High

Condition

Always

Never

C ∨ Z = 0

C ∨ Z = 1

C = 0

BLS

Low or same

BCC(BHS)

Carry clear

(high or same)

BCS(BLO)

BNE

BEQ

BVC

BVS

Carry set (low)

Not equal

C = 1

Z = 0

Equal

Z = 1

Overflow clear

Overflow set

Plus

V = 0

V = 1

BPL

N = 0

BMI

Minus

N = 1

BGE

BLT

Greater or equal

Less than

N ⊕ V = 0

N ⊕ V = 1

Z∨(N ⊕ V) = 0

Z∨(N ⊕ V) = 1

BGT

BLE

Greater than

Less or equal

JMP

BSR

JSR

RTS

—

Branches unconditionally to a specified address.

Branches to a subroutine at a specified address.

Returns from a subroutine

Note:

*

Bcc is the general name for conditional branch instructions.

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Table 2.8 System Control Instructions

Instruction

TRAPA

RTE

Size*

—

Function

Starts trap-instruction exception handling.

Returns from an exception-handling routine.

Causes a transition to a power-down state.

(EAs) → CCR

—

SLEEP

LDC

—

B/W

Moves the source operand contents to the CCR. The CCR size is one

byte, but in transfer from memory, data is read by word access.

STC

B/W

CCR → (EAd), EXR → (EAd)

Transfers the CCR contents to a destination location. The condition code

register size is one byte, but in transfer to memory, data is written by

word access.

ANDC

ORC

B

CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR with immediate data.

B

CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR with immediate data.

XORC

NOP

B

CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically XORs the CCR with immediate data.

—

PC + 2 → PC

Only increments the program counter.

Note:

*

Refers to the operand size.

B:

Byte

W:

Word

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Table 2.9 Block Data Transfer Instructions

Instruction

Size

Function

EEPMOV.B

—

if R4L ≠ 0 then

Repeat @ER5+ → @ER6+,

R4L–1 → R4L

Until R4L = 0

else next;

EEPMOV.W

—

if R4 ≠ 0 then

Repeat @ER5+ → @ER6+,

R4–1 → R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set

in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

2.4.2

Basic Instruction Formats

H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op field), a register field (r field), an effective address extension (EA field), and a

condition field (cc).

Figure 2.7 shows examples of instruction formats.

(1) Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried out

on the operand. The operation field always includes the first four bits of the instruction. Some

instructions have two operation fields.

(2) Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or

4 bits. Some instructions have two register fields. Some have no register field.

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(3) Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit

address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).

(4) Condition Field

Specifies the branching condition of Bcc instructions.

(1) Operation field only

op

NOP, RTS, etc.

(2) Operation field and register fields

op

rm

rn

ADD.B Rn, Rm, etc.

(3) Operation field, register fields, and effective address extension

op

rn

rm

MOV.B @(d:16, Rn), Rm

EA(disp)

(4) Operation field, effective address extension, and condition field

op cc EA(disp) BRA d:8

Figure 2.7 Instruction Formats

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2.5

Addressing Modes and Effective Address Calculation

The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the

generated 24-bit address, so the effective address is 16 bits.

2.5.1

Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses

a subset of these addressing modes. Addressing modes that can be used differ depending on the

instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing

Modes.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer

instructions can use all addressing modes except program-counter relative and memory indirect.

Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode

to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or

immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.10 Addressing Modes

No.

1

Addressing Mode

Symbol

Register direct

Rn

2

Register indirect

@ERn

3

Register indirect with displacement

@(d:16,ERn)/@(d:24,ERn)

4

Register indirect with post-increment

Register indirect with pre-decrement

@ERn+

@–ERn

5

6

7

8

Absolute address

Immediate

@aa:8/@aa:16/@aa:24

#xx:8/#xx:16/#xx:32

@(d:8,PC)/@(d:16,PC)

@@aa:8

Program-counter relative

Memory indirect

(1) Register Direct—Rn

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the

operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7

can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

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(2) Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of

which contain the address of the operand on memory.

(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)

A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the lower 24 bits of the sum the address of a

memory operand. A 16-bit displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

•

Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word

or longword access, the register value should be even.

•

Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the lower 24 bits of the result is the address of a memory operand.

The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for

word access, or 4 for longword access. For the word or longword access, the register value

should be even.

(5) Absolute Address—@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit

absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the

entire address space.

The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11,

because the upper 8 bits are ignored.

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Table 2.11 Absolute Address Access Ranges

Absolute Address

8 bits (@aa:8)

Access Range

H'FF00 to H'FFFF

H'0000 to H'FFFF

16 bits (@aa:16)

24 bits (@aa:24)

(6) Immediate—#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the

instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768

bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an

even number.

(8) Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit

absolute address specifying a memory operand. This memory operand contains a branch address.

The memory operand is accessed by longword access. The first byte of the memory operand is

ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in

memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the

address range is 0 to 255 (H'0000 to H'00FF).

Note that the first part of the address range is also the exception vector area.

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Specified

by @aa:8

Dummy

Branch address

Figure 2.8 Branch Address Specification in Memory Indirect Mode

Effective Address Calculation

2.5.2

Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI,

the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.

Table 2.12 Effective Address Calculation (1)

No

1

Addressing Mode and Instruction Format

Register direct(Rn)

Effective Address Calculation

Effective Address (EA)

Operand is general register contents.

op

rm rn

2

3

Register indirect(@ERn)

31

0

23

0

General register contents

op

r

Register indirect with displacement

@(d:16,ERn) or @(d:24,ERn)

31

0

23

0

op

r

disp

Sign extension

Register indirect with post-increment or

pre-decrement

•Register indirect with post-increment @ERn+

4

31

0

23

0

General register contents

op

r

1, 2, or 4

•Register indirect with pre-decrement @-ERn

General register contents

23

0

op

r

1, 2, or 4

The value to be added or subtracted is 1 when the

operand is byte size, 2 for word size, and 4 for

longword size.

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Table 2.12 Effective Address Calculation (2)

No

5

Addressing Mode and Instruction Format

Effective Address Calculation

Effective Address (EA)

Absolute address

@aa:8

23

8 7

0

op

abs

H'FFFF

@aa:16

23

16 15

op

abs

Sign extension

@aa:24

23

0

abs

6

7

Immediate

#xx:8/#xx:16/#xx:32

op

Operand is immediate data.

IMM

disp

23

0

Program-counter relative

@(d:8,PC) @(d:16,PC)

PC contents

op

23

Sign

disp

extension

23

0

8

Memory indirect @@aa:8

23

8

7

0

op

abs

H'0000

15

23

16 15

H'00

0

Memory contents

[Legend]

r, rm,rn : Register field

op :

Operation field

Displacement

Immediate data

Absolute address

disp :

IMM :

abs :

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2.6

Basic Bus Cycle

CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the

next rising edge is called one state. A bus cycle consists of two states or three states. The cycle

differs depending on whether access is to on-chip memory or to on-chip peripheral modules.

2.6.1

Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access

in byte or word size. Figure 2.9 shows the on-chip memory access cycle.

Bus cycle

T₁state

T₂state

φ

Internal address bus

Address

Internal read signal

Internal data bus

(read access)

Read data

Internal write signal

Internal data bus

(write access)

Write data

Figure 2.9 On-Chip Memory Access Cycle

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2.6.2

On-Chip Peripheral Modules

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits

or 16 bits depending on the register. For description on the data bus width and number of

accessing states of each register, refer to section 19.1, Register Addresses (Address Order).

Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data

bus width can be accessed by byte or word size. When a register with 8-bit data bus width is

accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the

same as that for on-chip memory.

Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral

module.

Bus cycle

T₁state

T₂state

T₃state

φ

Internal

address bus

Address

Internal

read signal

Internal

data bus

Read data

(read access)

Internal

write signal

Internal

data bus

Write data

(write access)

Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)

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2.7

CPU States

There are four CPU states: the reset state, program execution state, program halt state, and

exception-handling state. The program execution state includes active mode. In the program halt

state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12

shows the state transitions. For details on program execution state and program halt state, refer to

section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception

Handling.

CPU state

Reset state

The CPU is initialized

Program

execution state

Active

(high speed) mode

The CPU executes successive program

instructions at high speed,

synchronized by the system clock

Sleep mode

Program halt state

Power-down

modes

A state in which some

or all of the chip

functions are stopped

to conserve power

Standby mode

Exception-

handling state

A transient state in which the CPU changes

the processing flow due to a reset or an interrupt

Figure 2.11 CPU Operation States

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Reset cleared

Reset occurs

Reset state

Exception-handling state

Reset

occurs

Interrupt

source

Reset

occurs

Interrupt

source

Exception-

handling

complete

Program halt state

Program execution state

SLEEP instruction executed

Figure 2.12 State Transitions

2.8

Usage Notes

2.8.1

Notes on Data Access to Empty Areas

The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip

I/O registers areas available to the user. When data is transferred from CPU to empty areas, the

transferred data will be lost. This action may also cause the CPU to malfunction. When data is

transferred from an empty area to CPU, the contents of the data cannot be guaranteed.

2.8.2

EEPMOV Instruction

EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,

which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so

that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the

value of R6 must not change from H'FFFF to H'0000 during execution).

2.8.3

Bit Manipulation Instruction

The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in

byte units, manipulate the data of the target bit, and write data to the same address again in byte

units. Special care is required when using these instructions in cases where two registers are

assigned to the same address or when a bit is directly manipulated for a port, because this may

rewrite data of a bit other than the bit to be manipulated.

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(1) Bit Manipulation for Two Registers Assigned to the Same Address

Example 1: Bit manipulation for the timer load register and timer counter

(Applicable to timer B1, not available for the H8/36902 Group.)

Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same

address. When a bit manipulation instruction accesses the timer load register and timer counter of

a reloadable timer, since these two registers share the same address, the following operations takes

place.

1. Data is read in byte units.

2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.

3. The written data is written again in byte units to the timer load register.

The timer is counting, so the value read is not necessarily the same as the value in the timer load

register. As a result, bits other than the intended bit in the timer counter may be modified and the

modified value may be written to the timer load register.

Read

Count clock

Timer counter

Reload

Write

Timer load register

Internal bus

Figure 2.13 Example of Timer Configuration with Two Registers Allocated to

Same Address

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Example 2: The BSET instruction is executed for port 5.

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at

P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level

signal at P50 with a BSET instruction is shown below.

[Prior to executing BSET]

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

Low

level

PCR5

PDR5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

[BSET instruction executed]

BSET #0, @PDR5

The BSET instruction is executed for port 5.

[After executing BSET]

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

High

level

PCR5

PDR5

0

1

0

1

0

1

0

1

0

1

0

1

[Description on operation]

1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are

input pins, the CPU reads the pin states (low-level and high-level input).

P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a

value of H'80, but the value read by the CPU is H'40.

2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.

3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET.

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As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.

However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy

of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work

area, then write this data to PDR5.

[Prior to executing BSET]

MOV.B

#80, R0L

R0L, @RAM0

R0L, @PDR5

The PDR5 value (H'80) is written to a work area in

memory (RAM0) as well as to PDR5.

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

Low

level

PCR5

PDR5

RAM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

[BSET instruction executed]

BSET

#0,

@RAM0

The BSET instruction is executed designating the PDR5

work area (RAM0).

[After executing BSET]

MOV.B

@RAM0, R0L

R0L, @PDR5

The work area (RAM0) value is written to PDR5.

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

High

level

PCR5

PDR5

RAM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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Section 2 CPU

(2) Bit Manipulation in a Register Containing a Write-Only Bit

Example 3: BCLR instruction executed designating port 5 control register PCR5

P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at

P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as

an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be

input to this input pin.

[Prior to executing BCLR]

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

Low

level

PCR5

PDR5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

[BCLR instruction executed]

BCLR #0, @PCR5

The BCLR instruction is executed for PCR5.

[After executing BCLR]

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Output

Input

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

High

level

PCR5

PDR5

1

0

1

0

1

0

1

0

1

0

1

0

[Description on operation]

1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only

register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.

2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.

3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.

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Section 2 CPU

As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7

and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent

this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the

bit in the work area, then write this data to PCR5.

[Prior to executing BCLR]

MOV.B

#3F, R0L

R0L, @RAM0

R0L, @PCR5

The PCR5 value (H'3F) is written to a work area in

memory (RAM0) as well as to PCR5.

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

Low

level

PCR5

PDR5

RAM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

[BCLR instruction executed]

BCLR #0, @RAM0

The BCLR instructions executed for the PCR5 work area

(RAM0).

[After executing BCLR]

MOV.B

@RAM0, R0L

R0L, @PCR5

The work area (RAM0) value is written to PCR5.

P57

P56

P55

P54

P53

P52

P51

P50

Input/output

Pin state

Input

Output

Low

level

High

level

Low

level

Low

level

Low

level

Low

level

Low

level

High

level

PCR5

PDR5

RAM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

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Section 2 CPU

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Section 3 Exception Handling

Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.

•

Reset

A reset has the highest exception priority. Exception handling starts as soon as the reset is

cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and

exception handling starts. Exception handling is the same as exception handling by the RES

pin.

Trap Instruction

Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA

instruction generates a vector address corresponding to a vector number from 0 to 3, as

specified in the instruction code. Exception handling can be executed at all times in the

program execution state.

Interrupts

External interrupts other than NMI and internal interrupts other than address break are masked

by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when

the current instruction or exception handling ends, if an interrupt request has been issued.

3.1

Exception Sources and Vector Address

Table 3.1 shows the vector addresses and priority of each exception handling. When more than

one interrupt is requested, handling is performed from the interrupt with the highest priority.

Table 3.1 Exception Sources and Vector Address

Vector

Relative Module

RES pin

Exception Sources

Number

Vector Address

Priority

Reset

0

H'0000 to H'0001

High

Watchdog timer



Reserved for system use

NMI

1 to 6

7

H'0002 to H'000D

H'000E to H'000F

External interrupt

CPU

Trap instruction #0

Trap instruction #1

Trap instruction #2

Trap instruction #3

8

H'0010 to H'0011

H'0012 to H'0013

H'0014 to H'0015

H'0016 to H'0017

9

10

11

Low

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Section 3 Exception Handling

Vector

Relative Module

Address break

CPU

Exception Sources

Number

Vector Address

H'0018 to H'0019

H'001A to H'001B

Priority

Break conditions satisfied

12

13

High

Direct transition by executing

the SLEEP instruction

External interrupt

IRQ0, low-voltage detection

interrupt

14

H'001C to H'001D



Reserved for system use

15, 16

17

H'001E to H'0021

H'0022 to H'0023

H'0024 to H'0025

H'0026 to H'0029

H'002A to H'002B

External interrupt

IRQ3

WKP

18



Reserved for system use

19, 20

21

Timer W

Timer W input capture A/

compare match A

Timer W input capture B/

compare match B

Timer W input capture C/

compare match C

Timer W input capture D/

compare match D

Timer W overflow

Timer V

SCI3

Timer V compare match A

Timer V compare match B

Timer V overflow

22

23

H'002C to H'002D

H'002E to H'002F

SCI3 receive data full

SCI3 transmit data empty

SCI3 transmit end

SCI3 receive error

IIC2*

IIC_2 transmit data empty

IIC_2 transmit end

24

H'0030 to H'0031

IIC_2 receive error

A/D converter



A/D conversion end

25

H'0032 to H'0033

H'0034 to H'0039

H'003A to H'003B

H'003C to H'0043

H'0044 to H'0045

Reserved for system use

Timer B1 overflow

26 to 28

29

Timer B1*



Reserved for system use

30 to 33

Clock switch

Clock switch (external clock to 34

on-chip oscillator clock)

Low

Note:

*

Available for the H8/36912 Group only.

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Section 3 Exception Handling

3.2

Register Descriptions

Interrupts are controlled by the following registers.

•

Interrupt edge select register 1 (IEGR1)

Interrupt edge select register 2 (IEGR2)

Interrupt enable register 1 (IENR1)

Interrupt enable register 2 (IENR2)

Interrupt flag register 1 (IRR1)

Interrupt flag register 2 (IRR2)

Wakeup interrupt flag register (IWPR)

3.2.1

Interrupt Edge Select Register 1 (IEGR1)

IEGR1 selects the direction of an edge that generates interrupt requests of the IRQ3 and IRQ0

pins.

Initial

Bit

Bit Name Value

R/W

Description

7



0

−

Reserved

This bit is always read as 0.

Reserved

6 to 4

3



All 1

0



These bits are always read as 1.

IRQ3 Edge Select

IEG3

R/W

0: Falling edge of IRQ3 pin input is detected

1: Rising edge of IRQ3 pin input is detected

Reserved

2, 1

0



All 0

0



These bits are always read as 0.

IRQ0 Edge Select

IEG0

R/W

0: Falling edge of IRQ0 pin input is detected

1: Rising edge of IRQ0 pin input is detected

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Section 3 Exception Handling

3.2.2

Interrupt Edge Select Register 2 (IEGR2)

IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5

pins.

Initial

Bit

Bit Name Value

R/W

Description

7, 6



All 1

0



Reserved

These bits are always read as 1.

WKP5 Edge Select

5

WPEG5

R/W

0: Falling edge of WKP5 (ADTRG) pin input is detected

1: Rising edge of WKP5 (ADTRG) pin input is detected

Reserved

4 to 0



All 0



These bits are always read as 0.

3.2.3

Interrupt Enable Register 1 (IENR1)

IENR1 enables direct transition interrupts and external pin interrupts.

Initial

Bit

Bit Name Value

R/W

Description

7

IENDT

0

R/W

Direct Transfer Interrupt Enable

When this bit is set to 1, direct transition interrupt

requests are enabled.

6

5



0



Reserved

This bit is always read as 0.

Wakeup Interrupt Enable

IENWP

R/W

This bit is an enable bit of the WKP5 pin. When this bit is

set to 1, interrupt requests are enabled.

4

3



1

0



Reserved

This bit is always read as 1.

IRQ3 Interrupt Enable

IEN3

R/W

When this bit is set to 1, interrupt requests of the IRQ3

pin are enabled.

2, 1



All 0



Reserved

These bits are always read as 0.

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Section 3 Exception Handling

Initial

Bit

Bit Name Value

R/W

Description

0

IEN0

0

R/W

IRQ0 Interrupt Enable

When this bit is set to 1, interrupt requests of the IRQ0

pin are enabled.

3.2.4

Interrupt Enable Register 2 (IENR2)

IENR2 enables timer B1 interrupts.

Initial

Bit

Bit Name Value

R/W

Description

7



0



Reserved

This bit is always read as 0.

Reserved

6



R/W



Although this bit is readable/writable, it should not be set

to 1.

5

IENTB1

0

Timer B1 Interrupt Enable

When this bit is set to 1, overflow interrupt requests of

timer B1 are enabled.

4 to 0



All 1

Reserved

These bits are always read as 1.

When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in

an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear

operations are performed while I = 0, and as a result a conflict arises between the clear instruction

and an interrupt request, exception handling for the interrupt will be executed after the clear

instruction has been executed.

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Section 3 Exception Handling

3.2.5

Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests.

Initial

Bit

Bit Name Value

R/W

Description

7

IRRDT

0

R/W

Direct Transfer Interrupt Request Flag

[Setting condition]

•

When a direct transfer is made by executing a SLEEP

instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0

•

6



0



Reserved

This bit is always read as 0.

Reserved

5, 4

3



All 1

0



These bits are always read as 1.

IRQ3 Interrupt Request Flag

[Setting condition]

IRRI3

R/W

•

When IRQ3 pin is designated for interrupt input and

the designated signal edge is detected

[Clearing condition]

When IRRI3 is cleared by writing 0

•

2, 1

0



All 0

0



Reserved

These bits are always read as 0.

IRQ0 Interrupt Request Flag

[Setting condition]

IRRl0

R/W

•

When IRQ0 pin is designated for interrupt input and

the designated signal edge is detected

[Clearing condition]

When IRRI0 is cleared by writing 0

•

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Section 3 Exception Handling

3.2.6

Interrupt Flag Register 2 (IRR2)

IRR2 is a status flag register for timer B1 interrupt requests.

Initial

Bit

Bit Name Value

R/W

Description

7



0



Reserved

This bit is always read as 0.

Reserved

6

5



IRRTB1

0

R/W

Timer B1 Interrupt Request Flag

[Setting condition]

•

When timer B1 overflows

[Clearing condition]

When IRRTB1 is cleared by writing 0

•

4 to 0



All 1



Reserved

These bits are always read as 1.

3.2.7

Wakeup Interrupt Flag Register (IWPR)

IWPR is a status flag register for WKP5 interrupt requests.

Initial

Bit

Bit Name Value

R/W

Description

7, 6



All 1

0



Reserved

These bits are always read as 1.

WKP5 Interrupt Request Flag

[Setting condition]

5

IWPF5

R/W

•

When WKP5 pin is designated for interrupt input and

the designated signal edge is detected.

[Clearing condition]

When IWPF5 is cleared by writing 0

•

4 to 0



All 0



Reserved

These bits are always read as 0.

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Section 3 Exception Handling

3.3

Reset Exception Handling

When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of

the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure

that this LSI is reset at power-up, hold the RES pin low for the specified period. To reset the chip

during operation, hold the RES pin low for the specified period. For details, refer to section 17,

Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits. When the RES pin goes

high after being held low for a certain period, this LSI starts reset exception handling. The reset

exception handling sequence is shown in figure 3.1.

The reset exception handling sequence is as follows.

1. Set the I bit in the condition code register (CCR) to 1.

2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the

data in that address is sent to the program counter (PC) as the start address, and program

execution starts from that address.

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Section 3 Exception Handling

3.4

Interrupt Exception Handling

3.4.1

External Interrupts

As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts.

(1) NMI Interrupt

NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and

can always be accepted without depending on the I bit value in CCR.

(2) IRQ3 and IRQ0 Interrupts

IRQ3 and IRQ0 interrupts are requested by input signals to the IRQ3 and IRQ0 pins. These

interrupts are given different vector addresses, and are detected individually by either rising edge

sensing or falling edge sensing, depending on the settings of the IEG3 and IEG0 bits in IEGR1.

When the IRQ3 and IRQ0 pins are designated for interrupt input in PMR1 and the designated

signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.

These interrupts can be masked by setting the IEN3 and IEN0 bits in IENR1.

(3) WKP Interrupt

WKP interrupt is requested by an input signal to the WKP5 pin. This interrupt is detected by either

rising edge sensing or falling edge sensing, depending on the setting of the WPEG5 bit in IEGR2.

When the WKP5 pin is designated for interrupt input in PMR5 and the designated signal edge is

input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. This interrupt

can be masked by setting the IENWP bit in IENR1.

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Section 3 Exception Handling

Reset cleared

Initial program

instruction prefetch

Vector fetch Internal

processing

RES

φ

Internal

address bus

(1)

(2)

Internal read

signal

Internal write

signal

Internal data

bus (16 bits)

(2)

(3)

(1) Reset exception handling vector address (H'0000)

(2) Program start address

(3) Initial program instruction

Figure 3.1 Reset Sequence

3.4.2

Internal Interrupts

Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to

enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a

SLEEP instruction, this function is included in IRR1 and IENR1.

When an on-chip peripheral module requests an interrupt, the corresponding interrupt request

status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit

is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable

bit.

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Section 3 Exception Handling

3.4.3

Interrupt Handling Sequence

Interrupts are controlled by an interrupt controller.

Interrupt operation is described as follows.

1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request

signal is sent to the interrupt controller.

2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for

the interrupt handling with the highest priority at that time according to table 3.1. Other

interrupt requests are held pending.

3. The CPU accepts the NMI or address break without depending on the I bit value. Other

interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the

interrupt request is held pending.

4. If the CPU accepts the interrupt after processing of the current instruction is completed,

interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The

state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the

address of the first instruction to be executed upon return from interrupt handling.

5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address

break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be

restored and returned to the values prior to the start of interrupt exception handling.

6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and

transfers the address to PC as a start address of the interrupt handling-routine. Then a program

starts executing from the address indicated in PC.

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Section 3 Exception Handling

Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and

the stack area is in the on-chip RAM.

Reset cleared

Initial program

instruction prefetch

Vector fetch Internal

processing

RES

φ

Internal

address bus

(1)

(2)

Internal read

signal

Internal write

signal

Internal data

bus (16 bits)

(2)

(3)

(1) Reset exception handling vector address (H'0000)

(2) Program start address

(3) Initial program instruction

Figure 3.2 Stack Status after Exception Handling

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Section 3 Exception Handling

3.4.4

Interrupt Response Time

Table 3.2 shows the number of wait states after an interrupt request flag is set until the first

instruction of the interrupt handling-routine is executed.

Table 3.2 Interrupt Wait States

Item

States

Total

Waiting time for completion of executing instruction*

Saving of PC and CCR to stack

Vector fetch

1 to 23

15 to 37

4

2

4

Instruction fetch

Internal processing

Note:

*

EEPMOV instruction is not included.

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Section 3 Exception Handling

Figure 3.3 Interrupt Sequence

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Section 3 Exception Handling

3.5

Usage Notes

3.5.1

Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.W #xx: 16, SP).

3.5.2

Notes on Stack Area Use

When word data is accessed, the least significant bit of the address is regarded as 0. Access to the

stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd

address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore

register values.

3.5.3

Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3,

IRQ0, and WKP5, the interrupt request flag may be set to 1.

When switching a pin function, mask the interrupt before setting the bit in the port mode register.

After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the

interrupt request flag from 1 to 0.

Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.

Interrupts masked. (Another possibility

is to disable the relevant interrupt in

interrupt enable register 1.)

←

CCR I bit

1

Set port mode register bit

After setting the port mode register bit,

first execute at least one instruction

(e.g., NOP), then clear the interrupt

request flag to 0

Execute NOP instruction

Clear interrupt request flag to 0

←

Interrupt mask cleared

CCR I bit

0

Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure

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Section 3 Exception Handling

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Section 4 Address Break

The address break simplifies on-board program debugging. It requests an address break interrupt

when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.

Break conditions that can be set include instruction execution at a specific address and a

combination of access and data at a specific address. With the address break function, the

execution start point of a program containing a bug is detected and execution is branched to the

correcting program. Figure 4.1 shows a block diagram of the address break.

Internal address bus

Comparator

BARH

BARL

ABRKCR

ABRKSR

Interrupt

generation

control circuit

BDRH

BDRL

Comparator

Interrupt

[Legend]

BARH, BARL: Break address register

BDRH, BDRL: Break data register

ABRKCR:

ABRKSR:

Address break control register

Address break status register

Figure 4.1 Block Diagram of Address Break

ABK0001A_000020020200

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Section 4 Address Break

4.1

Register Descriptions

Address break has the following registers.

•

Address break control register (ABRKCR)

Address break status register (ABRKSR)

Break address register (BARH, BARL)

Break data register (BDRH, BDRL)

4.1.1

Address Break Control Register (ABRKCR)

ABRKCR sets address break conditions.

Initial

Bit

Bit Name Value

R/W

Description

7

RTINTE

1

R/W

RTE Interrupt Enable

When this bit is 0, the interrupt immediately after

executing RTE is masked and then one instruction must

be executed. When this bit is 1, the interrupt is not

masked.

6

5

CSEL1

CSEL0

0

R/W

Condition Select 1 and 0

These bits set address break conditions.

00: Instruction execution cycle

01: CPU data read cycle

10: CPU data write cycle

11: CPU data read/write cycle

Address Compare Condition Select 2 to 0

4

3

2

ACMP2

ACMP1

ACMP0

0

R/W

These bits comparison condition between the address set

in BAR and the internal address bus.

000: Compares 16-bit addresses

001: Compares upper 12-bit addresses

010: Compares upper 8-bit addresses

011: Compares upper 4-bit addresses

1XX: Reserved (setting prohibited)

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Section 4 Address Break

Initial

Bit

1

Bit Name Value

R/W

Description

DCMP1

DCMP0

0

Data Compare Condition Select 1 and 0

0

These bits set the comparison condition between the data

set in BDR and the internal data bus.

00: No data comparison

01: Compares lower 8-bit data between BDRL and data

bus

10: Compares upper 8-bit data between BDRH and data

bus

11: Compares 16-bit data between BDR and data bus

[Legend]

X:

Don't care

When an address break is set in the data read cycle or data write cycle, the data bus used will

depend on the combination of the byte/word access and address. Table 4.1 shows the access and

data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a

byte access is generated twice. For details on data widths of each register, see section 19.1,

Register Addresses (Address Order).

Table 4.1 Access and Data Bus Used

Word Access

Byte Access

Even Address Odd Address Even Address Odd Address

ROM space

RAM space

Upper 8 bits

Lower 8 bits

Upper 8 bits

I/O register with 8-bit data bus Upper 8 bits

width

I/O register with 16-bit data

bus width

Upper 8 bits

Lower 8 bits

—

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Section 4 Address Break

4.1.2

Address Break Status Register (ABRKSR)

ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.

Initial

Bit

Bit Name Value

R/W

Description

7

ABIF

0

R/W

Address Break Interrupt Flag

[Setting condition]

•

When the condition set in ABRKCR is satisfied

[Clearing condition]

When 0 is written after ABIF=1 is read

•

6

ABIE

—

0

R/W

—

Address Break Interrupt Enable

When this bit is 1, an address break interrupt request is

enabled.

5 to 0

All 1

Reserved

These bits are always read as 1.

4.1.3

Break Address Registers (BARH, BARL)

BARH and BARL are 16-bit read/write registers that set the address for generating an address

break interrupt. When setting the address break condition to the instruction execution cycle, set the

first byte address of the instruction. The initial value of this register is H'FFFF.

4.1.4

Break Data Registers (BDRH, BDRL)

BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break

interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-

bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for

even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH

for byte access. For word access, the data bus used depends on the address. See section 4.1.1,

Address Break Control Register (ABRKCR), for details. The initial value of this register is

undefined.

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Section 4 Address Break

4.2

Operation

When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an

interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the

address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt

request is accepted, interrupt exception handling starts after the instruction being executed ends.

The address break interrupt is not masked because of the I bit in CCR of the CPU.

The following figures show the operation examples of the address break interrupt setting.

When the address break is specified in instruction execution cycle

Register setting

• ABRKCR = H'80

• BAR = H'025A

Program

0258 NOP

* 025A NOP

025C MOV.W @H'025A,R0

0260 NOP

Underline indicates the address

to be stacked.

0262 NOP

:

NOP

MOV

instruc- instruc- instruc- instruc-

tion

tion 1

tion 2

Internal

prefetch prefetch prefetch prefetch processing

Stack save

φ

Address

bus

0258

025A

025C

025E

SP-2

SP-4

Interrupt

request

Interrupt acceptance

Figure 4.2 Address Break Interrupt Operation Example (1)

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Section 4 Address Break

When the address break is specified in the data read cycle

Register setting

• ABRKCR = H'A0

• BAR = H'025A

Program

0258 NOP

025A NOP

* 025C MOV.W @H'025A,R0

0260 NOP

0262 NOP

Underline indicates the address

to be stacked.

:

MOV

NOP

MOV

NOP

tion 1

tion 2

tion

Internal Stack

prefetch prefetch prefetch execution prefetch prefetch processing save

φ

Address

bus

025C

025E

0260

025A

0262

0264

SP-2

Interrupt

request

Interrupt acceptance

Figure 4.2 Address Break Interrupt Operation Example (2)

Rev. 3.00 Sep. 14, 2006 Page 68 of 408

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Section 5 Clock Pulse Generators

Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an on-

chip oscillator, a duty correction circuit, a clock select circuit, and system clock dividers.

Figure 5.1 shows a block diagram of the clock pulse generator.

Duty

correction

circuit

System

clock

oscillator

φ_OSC

OSC1

OSC2

φ

φ_OSC

φ/8

Clock

select

circuit

System

clock

divider

φ

φ/16

φ/32

φ/64

φ

R

OSC

ROSC

R

OSC

φ_RC

/2

/4

φ/2

On-chip

oscillator

Clock

divider

Prescaler S

(13 bits)

to

R

φ/8192

Figure 5.1 Block Diagram of Clock Pulse Generators

The system clock (φ) is a basic clock on which the CPU and on-chip peripheral modules operate.

The system clock is divided into φ/2 to φ/8192 by prescaler S and the divided clocks are supplied

to respective peripheral modules.

CPG0200A_000020020200

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Section 5 Clock Pulse Generators

5.1

Features

•

Choice of two clock sources

On-chip oscillator clock

External oscillator clock

•

Choice of two types of on-chip oscillation frequency by the user software

8MHz

10MHz

•

Frequency trimming

Users can adjust the on-chip oscillation frequency by rewriting the trimming registers.

Interrupt can be requested to the CPU when the system clock is changed from the external

clock to the on-chip oscillator clock.

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Section 5 Clock Pulse Generators

5.2

Register Descriptions

Clock oscillators are controlled by the following registers.

•

RC control register (RCCR)

RC trimming data protect register (RCTRMDPR)

RC trimming data register (RCTRMDR)

Clock control/status register (CKCSR)

5.2.1

RC Control Register (RCCR)

RCCR controls the on-chip oscillator.

Initial

Bit

Bit Name Value R/W

Description

7

RCSTP

0

R/W

On-chip Oscillator Standby

The internal on-chip oscillator standby state is entered by

setting this bit to 1.

6

5

FSEL

0

R/W

Frequency Select for On-chip Oscillator

0: 8MHz

1: 10MHz

VCLSEL

0

R/W

Power Supply Select for On-chip Oscillator

0: Selects VBGR

1: Selects VCL

When VCL is selected, the accuracy of the on-chip

oscillator frequency cannot be guaranteed.

4 to 2



All 0



Reserved

These bits are always read as 0.

Division Ratio Select for On-chip Oscillator

1

0

RCPSC1

RCPSC0

0

R/W

The division ratio of R_OSCchanges right after rewriting this

bit.

These bits can be written to only when the CKSTA bit in

CKCSR is 0.

0X: R_OSC(not divided)

10: R_OSC/2

11: R_OSC/4

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Section 5 Clock Pulse Generators

5.2.2

RC Trimming Data Protect Register (RCTRMDPR)

RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to

rewrite this register. Bit manipulation instruction cannot change the settings.

Initial

Bit

Bit Name Value R/W

Description

7

WRI

1

W

Write Inhibit

Only when writing 0 to this bit, this register can be written

to. This bit is always read as 1.

6

PRWE

0

R/W

Protect Information Write Enable

Bits 5 and 4 can be written to when this bit is set to 1.

[Setting condition]

•

When writing 0 to the WRI bit and writing 1 to the

PRWE bit

[Clearing conditions]

•

Reset

When writing 0 to the WRI bit and writing 0 to the

PRWE bit

5

LOCKDW

0

R/W

Trimming Data Register Lock Down

The RC trimming data register (RCTRMDR) cannot be

written to when this bit is set to 1. Once this bit is set to 1,

this register cannot be written to until a reset is input even

if 0 is written to this bit.

[Setting condition]

•

When writing 0 to the WRI bit and writing 1 to the

LOCKDW bit while the PRWE bit is 1

[Clearing condition]

Reset

•

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Section 5 Clock Pulse Generators

Initial

Bit

Bit Name Value R/W

Description

4

TRMDRWE

0

R/W

Trimming Date Register Write Enable

This register can be written to when the LOCKDW bit is 0

and this bit is 1.

[Setting condition]

•

When writing 0 to the WRI bit while writing 1 to the

TRMDRWE bit while the PRWE bit is 1

[Clearing conditions]

•

Reset

When writing 0 to the WRI bit and writing 0 to the

TRMDRWE bit while the PRWE bit is 1

3 to 0



All 1



Reserved

These bits are always read as 1

5.2.3

RC Trimming Data Register (RCTRMDR)

RCTRMDR stores the trimming data of the on-chip oscillator frequency.

Initial

Bit

7

Bit Name Value R/W

Description

TRMD7

TRMD6

TRMD5

TRMD4

TRMD3

TRMD2

TRMD1

TRMD0

(0)*

0

R/W

R

Trimming Data

6

In the flash memory version, the trimming data is loaded

from the flash memory to this register right after a reset.

These bits are always read as undefined value.

5

4

As for the masked ROM version, the on-chip oscillator

frequency can be trimmed by rewriting these bits. The

frequency generated in the on-chip oscillator changes

right after rewriting these bits. These bits are initialized to

H'00.

3

2

1

0

R

Frequency variation is expressed as follows (the TRMD7

bit is a sign bit):

(Min.) H'80 ← H'FC ← H'00 →H'04 → H'7C (Max.)

Note:

*

The initial value differs from product to product in the flash memory version.

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Section 5 Clock Pulse Generators

5.2.4

Clock Control/Status Register (CKCSR)

CKCSR selects the port C function, controls switching the system clocks, and indicates the system

clock state.

Initial

Bit

7

Bit Name Value R/W

Description

PMRC1

PMRC0

0

R/W

Port C Function Select 1 and 0

6

PMRC1 PMRC0 PC1

PC0

I/O

CLKOUT I/O

0

1

0

1

0

1

I/O

OSC1 (external clock input)

OSC1

OSC2

5

4



0

R/W

Reserved

Although this bit is readable/writable, it should not be set

to 1.

OSCSEL

LSI Operation Clock Select

This bit forcibly selects the system clock of this LSI.

0: Selects the on-chip oscillator clock as the system clock.

1: Selects the external clock as the system clock.

Clock Switch Interrupt Enable

3

2

CKSWIE

CKSWIF

0

R/W

Setting this bit to 1 enables the clock switch interrupt

request.

Clock Switch Interrupt Request Flag

[Setting condition]

•

When the external clock is switched to the on-chip

oscillator clock

[Clearing condition]

When writing 0 after reading 1

•

1

0



1

0

R

Reserved

This bit is always read as 1.

LSI Operating Clock Status

CKSTA

0: This LSI operates on on-chip oscillator clock.

1: This LSI operates on external clock.

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Section 5 Clock Pulse Generators

5.3

System Clock Select Operation

Figure 5.2 shows the state transition of the system clock.

LSI operates on on-chip oscillator clock

Reset release

Reset state

On-chip oscillator: Operated

External oscillator: Halted

Switching to

on-chip oscillator

external clock

On-chip oscillator halted

On-chip oscillator: Halted

External oscillator: Operated

On-chip oscillator: Operated

External oscillator: Operated

On-chip oscillator operated

LSI operates on external oscillator

Figure 5.2 State Transition of System Clock

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Section 5 Clock Pulse Generators

5.3.1

Clock Control Operation

The LSI system clock is generated by the on-chip oscillator clock after a reset. The on-chip

oscillator clock is switched to the external clock by the user software.

LSI operates on on-chip oscillator RC clock

[1] External oscillation starts when pins PC1 and PC0

are selected as external oscillation pins. Write 0 to

bit PMRC1 to input the external clock.

Start (reset)

[2] After writing 1 to the OSCSEL bit, this LSI waits

until the oscillation of the external oscillator

settles. The correspondence between Nwait,

which is the number of wait cycles for oscillation

settling, and Nstby, which is the number of wait

cycles for oscillation settling when returning from

standby mode, is as follows:

Write 1 to PMRC0 in CKCSR

Write 1 to PMRC1 in CKCSR

[1]

Nstby ≤ Nwait ≤ 2 × Nstby

Nstby is set by bits STS 2 to 0 in SYSCR1.

For details, see section 6.1.1, System Control

Register 1 (SYSCR1).

Write 0 to CKSWIE in CKCSR

[3] While the system is waiting for the external

oscillation settling, this LSI is not halted but

continues to operate on the on-chip oscillator clock.

Read the value of the CKSTA bit in CKCSR to

ensure that the system clocks are switched.

Write 1 to OSCSEL in CKCSR [2]

[3]

No

Switched to

external clock? (CKSTA in

CKCSR is 1)

Yes

LSI operates on external oscillator

Figure 5.3 Flowchart of Clock Switching On-chip Oscillator

Clock to External Clock (1)

Rev. 3.00 Sep. 14, 2006 Page 76 of 408

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Section 5 Clock Pulse Generators

LSI operates on

external clock

[1] When 0 is written to the OSCSEL bit, this LSI

switches the external clock to the on-chip oscillator

clock after the φ stop duration. Seven rising edges

of the φ_RCclock after the OSCSEL bit becomes 0

are included in the φ stop duration.

Start

(LSI operates on external clock)

[2] Writing 0 to PMRC0 stops the external oscillation.

Write 0 to RCSTP in RCCR

Write 1 to CKSWIE in CKCSR

if necessary

Write 0 to OSCSEL in CKCSR

LSI operates on

[1]

on-chip oscillator clock

When CKSWIE = 1

Exception handling

for clock switching

Write 0 to PMRC0 in CKCSR

[2]

if necessary

LSI operates on on-chip

oscillator

Figure 5.4 Flowchart of Clock Switching External

Clock to On-chip Oscillator Clock (2)

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Section 5 Clock Pulse Generators

5.3.2

Clock Change Timing

The timing for changing clocks are shown in figures 5.5 and 5.6.

φOSC

φRC

φ

OSCSEL

PHISTOP

(Internal signal)

CKSTA

φ halt*

On-chip oscillator clock operation

External clock operation

Wait for external

oscillation settling

Nwait

[Legend]

φOSC:

φRC:

φ:

External clock

On-chip oscillator clock

System clock

OSCSEL: Bit 4 in CKCSR

PHISTOP: System clock stop control signal

CKSTA:

Bit 0 in CKCSR

Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first

rising edge of the φ_OSCclock after six clock cycles of the φ_RCclock have elapsed.

Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock

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Section 5 Clock Pulse Generators

φOSC

φRC

φ

OSCSEL

PHISTOP

(Internal signal)

CKSTA

CKSWIF

On-chip oscillator

clock operation

External clock operation

φ halt*

Wait for external

oscillation settling

Nwait

[Legend]

φOSC:

φRC:

φ:

External clock

On-chip oscillator clock

System clock

OSCSEL: Bit 4 in CKCSR

PHISTOP: System clock stop control signal

CKSTA:

Bit 0 in CKCSR

CKSWIF: Bit 2 in CKCSR

Note: * The φ halt duration is the duration from the timing when the φ clock stops to the

seventh rising edge of the φ_RCclock.

Figure 5.6 Timing Chart to Switch External Clock to On-chip Oscillator Clock

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Section 5 Clock Pulse Generators

5.4

Trimming of On-chip Oscillator Frequency

Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the

input capture function in internal timer W. An example of trimming flow and a timing chart are

shown in figures 5.7 and 5.8, respectively. Because RCTRMDR is initialized by a reset, when

users have trimmed the oscillators, some operations after a reset are necessary, such as trimming it

again or saving the trimming value in an external device for later reloading.

Start

Setting timer W

GRA: Input capture

GRC: Buffer of GRA

Set RCTRMD to H'00

Input reference pulses to

pin P81/FTIOA

Capture 1

Modify RCTRMDR*

Capture 2

Frequency calculation

Within

desired frequency

range?

No

Yes

End

Note: * Comparing the difference between the measured frequency and the desired frequency,

individual bits of RCTRMDR are decided from the MSB bit by bit.

Figure 5.7 Example of Trimming Flow for On-chip Oscillator Frequency

Rev. 3.00 Sep. 14, 2006 Page 80 of 408

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Section 5 Clock Pulse Generators

φRC

FTIOA input

capture input

t_A(µs)

Timer W

TCNT

M + α

M

N

M + 1

M

M - 1

M + α

GRA

GRC

N

M

Capture 1

Capture 2

Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency

The on-chip oscillator frequency is gained by the expression below. Since the input-capture input

is sampled by the φ_RCclock, the calculated result may include a sampling error of 1 cycle of the

φ_RCclock.

(M + α) - M

(MHz)

φRC =

t_A

φRC: Frequency of on-chip oscillator (MHz)

t :

M:

Period of reference clock (µs)

Timer W counter value

A

Rev. 3.00 Sep. 14, 2006 Page 81 of 408

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Section 5 Clock Pulse Generators

5.5

External Oscillators

This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic

resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports

PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input

ports, refer to section 5.3, System Clock Select Operation.

5.5.1

Connecting Crystal Resonator

Figure 5.9 shows an example of connecting a crystal resonator. An AT-cut parallel-resonance

crystal resonator should be used. Figure 5.12 shows the equivalent circuit of a crystal resonator. A

resonator having the characteristics given in table 5.1 should be used.

C₁

PC0/OSC1

C₂

C₁= C₂= 10 to 22 pF

PC1/OSC2/CLKOUT

Figure 5.9 Example of Connection to Crystal Resonator

L_S

R_S

C_S

PC0/OSC1

PC1/OSC2/CLKOUT

C₀

Figure 5.10 Equivalent Circuit of Crystal Resonator

Table 5.1 Crystal Resonator Parameters

Frequency (MHz)

R_S(Max.)

2

4

8

10

12

500 Ω

120 Ω

80 Ω

60 Ω

50 Ω

C₀(Max.)

70 pF

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Section 5 Clock Pulse Generators

5.5.2

Connecting Ceramic Resonator

Figure 5.11 shows an example of connecting a ceramic resonator.

C₁

PC0/OSC1

C₂

C₁= C₂= 5 to 30 pF

PC1/OSC2/CLKOUT

Figure 5.11 Example of Connection to Ceramic Resonator

External Clock Input Method

5.5.3

To use the external clock, input the external clock on pin OSC1. Figure 5.12 shows an example of

connection. The duty cycle of the external clock signal must be 45 to 55%.

PC0/OSC1

External clock input

PC1/OSC2/CLKOUT

General port

Figure 5.12 Example of External Clock Input

5.6

Prescaler

5.6.1

Prescaler S

Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are

divided clocks, are used as internal clocks by the on-chip peripheral modules. Prescaler S is

initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode

and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized

to H'0000. It cannot be read from or written to by the CPU.

The outputs from prescaler S is shared by the on-chip peripheral modules. The division ratio can

be set separately for each on-chip peripheral module. In active mode and sleep mode, the clock

input to prescaler S is a system clock with the division ratio specified by bits MA2 to MA0 in

SYSCR2.

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Section 5 Clock Pulse Generators

5.7

Usage Notes

5.7.1

Note on Resonators

Resonator characteristics are closely related to board design and should be carefully evaluated by

the user, referring to the examples shown in this section. Resonator circuit parameters will differ

depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable

values should be determined in consultation with the resonator element manufacturer. Design the

circuit so that the resonator element never receives voltages exceeding its maximum rating.

5.7.2

Notes on Board Design

When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as

close as possible to pins OSC1 and OSC2. Other signal lines should be routed away from the

oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.13).

Prohibited

Signal A Signal B

C₁

C₂

PC0/OSC1

PC1/OSC2/CLKOUT

Figure 5.13 Example of Incorrect Board Design

Rev. 3.00 Sep. 14, 2006 Page 84 of 408

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Section 6 Power-Down Modes

For operating modes after a reset, this LSI has not only a normal active mode but also three

power-down modes in which power consumption is significantly reduced. In addition, there is also

a module standby function which reduces power consumption by individually stopping on-chip

peripheral modules.

•

Active mode

The CPU and all on-chip peripheral modules are operable on the system clock. The system

clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.

•

Sleep mode

The CPU halts. On-chip peripheral modules are operable on the system clock.

Standby mode

The CPU and all on-chip peripheral modules halt.

Subsleep mode

The CPU and all on-chip peripheral modules halt. I/O ports keep the same states as before the

transition.

•

Module standby function

Independent of the above modes, power consumption can be reduced by halting on-chip

peripheral modules that are not used in module units.

6.1

Register Descriptions

The registers related to power-down modes are listed below.

•

System control register 1 (SYSCR1)

System control register 2 (SYSCR2)

Module standby control register 1 (MSTCR1)

Module standby control register 2 (MSTCR2)

LPW3003A_000020020200

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Section 6 Power-Down Modes

6.1.1

System Control Register 1 (SYSCR1)

SYSCR1 controls the power-down modes, as well as SYSCR2.

Initial

Bit

Bit Name Value

R/W

Description

7

SSBY

0

R/W

Software Standby

Specifies the operating mode to be entered after

executing the SLEEP instruction.

0: Shifts to sleep mode.

1: Shifts to standby mode.

For details, see table 6.2.

Standby Timer Select 2 to 0

6

5

4

STS2

STS1

STS0

0

R/W

These bits set the wait time from when the system clock

oscillator starts functioning until the clock is supplied, in

shifting from standby mode, to active mode or sleep

mode. During the wait time, this LSI automatically selects

the on-chip oscillator clock as its system clock and counts

the number of wait states. Select a wait time of 6.5 ms

(oscillation stabilization time) or longer, depending on the

operating frequency. Table 6.1 shows the relationship

between the STS2 to STS0 values and the wait time.

When using an external clock, set the wait time to be

100 µs or longer in the F-ZTAT version. In the masked

ROM version, the minimum value (STS2 = STS1 = STS0

= 1) is recommended.

These bits also set the wait states for external oscillation

stabilization when system clock is switched from the on-

chip oscillator clock to the external clock by user

software.

The relationship between Nwait (number of wait states for

oscillation stabilization) and Nstby (number of wait states

for recovering to the standby mode) is as follows.

Nstby ≤ Nwait ≤ 2 × Nstby

Reserved

3 to 0



All 0



These bits are always read as 0.

Rev. 3.00 Sep. 14, 2006 Page 86 of 408

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Section 6 Power-Down Modes

Table 6.1 Operating Frequency and Wait Time

Bit Name

Operating Frequency

STS2 STS1 STS0 Wait Time

10 MHz

0.8

8 MHz

1.0

5 MHz

1.6

4 MHz

2.0

2.5 MHz

3.3

2 MHz

4.1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8,192 states

16,384 states

32,768 states

65,536 states

1.6

2.0

3.3

4.1

6.6

8.2

3.3

4.1

6.6

8.2

13.1

26.2

52.4

0.42

0.05

0.00

16.4

32.8

65.5

0.51

0.06

0.01

6.6

8.2

13.1

26.2

0.21

0.03

0.00

16.4

32.8

0.26

0.03

0.00

131,072 states 13.1

16.4

0.13

0.02

0.00

1,024 states

128 states

16 states

0.10

0.01

0.00

Notes: 1. Time unit is ms.

2. The on-chip oscillator clock counts the wait states, even when the external clock is used

as system clock.

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Section 6 Power-Down Modes

6.1.2

System Control Register 2 (SYSCR2)

SYSCR2 controls the power-down modes, as well as SYSCR1.

Initial

Bit

Bit Name Value

R/W

Description

7

SMSEL

0

R/W

Sleep Mode Selection

This bit specifies the mode to be entered after executing

the SLEEP instruction, as well as the SSBY bit in

SYSCR1. For details, see table 6.2.

6

5



0



Reserved

This bit is always read as 0.

Direct Transfer on Flag

DTON

R/W

This bit specifies the mode to be entered after executing

the SLEEP instruction, as well as the SSBY bit in

SYSCR1. For details, see table 6.2.

4

3

2

MA2

MA1

MA0

0

R/W

Active Mode Clock Select 2 to 0

These bits select the operating clock frequency in active

and sleep modes. The operating clock frequency

changes to the set frequency after the SLEEP instruction

is executed.

0XX: φ

100: φ /8

101: φ/16

110: φ/32

111: φ/64

1, 0



All 0



Reserved

These bits are always read as 0.

[Legend]

X:

Don't care

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Section 6 Power-Down Modes

6.1.3

Module Standby Control Register 1 (MSTCR1)

MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.

Initial

Bit

Bit Name Value

R/W

Description

7



0



Reserved

This bit is always read as 0.

IIC2 Module Standby

6

5

4

MSTIIC

MSTS3

MSTAD

R/W

IIC2 enters standby mode when this bit is set to 1.

SCI3 Module Standby

SCI3 enters standby mode when this bit is set to 1.

A/D Converter Module Standby

A/D converter enters standby mode when this bit is set

to 1.

3

MSTWD

0

R/W

Watchdog Timer Module Standby

Watchdog timer enters standby mode when this bit is set

to 1. (When the internal oscillator is selected for the

watchdog timer clock, the watchdog timer operates

regardless of the setting of this bit.)

2

1

0

MSTTW

MSTTV



0

R/W



Timer W Module Standby

Timer W enters standby mode when this bit is set to 1.

Timer V Module Standby

Timer V enters standby mode when this bit is set to 1.

Reserved

This bit is always read as 0.

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Section 6 Power-Down Modes

6.1.4

Module Standby Control Register 2 (MSTCR2)

MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.

Initial

Bit

Bit Name Value

R/W

Description

7 to 5



All 0

0



Reserved

These bits are always read as 0.

Timer B1 Module Standby

Timer B1 enters standby mode when this bit is set to 1.

Reserved

4

MSTTB1

R/W

3 to 0



All 0



These bits are always read as 0.

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Section 6 Power-Down Modes

6.2

Mode Transitions and States of LSI

Figure 6.1 shows the possible transitions among these operating modes. A transition is made from

the program execution state to the program halt state of the program by executing a SLEEP

instruction. Interrupts allow for returning from the program halt state to the program execution

state of the program. A direct transition from active mode to active mode changes the operating

frequency. RES input enables transitions from a mode to the reset state. Table 6.2 shows the

transition conditions of each mode after the SLEEP instruction is executed and a mode to return

by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.

Reset state

Program halt state

Standby mode

Program execution state

Active mode

Program halt state

Sleep mode

Direct transition

interrupt

SLEEP

instruction

SLEEP

instruction

Interrupt

SLEEP

instruction

Interrupt

Subsleep mode

Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt

is accepted.

2. Details on the mode transition conditions are given in table 6.2.

Figure 6.1 Mode Transition Diagram

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Section 6 Power-Down Modes

Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling

Transition Mode after SLEEP Transition Mode due to

DTON

SSBY

SMSEL

Instruction Execution

Interrupt

Active mode

—

0

1

X

0

Sleep mode

1

Subsleep mode

X

0*

Standby mode

1

Active mode (direct transition)

[Legend]

X:

Don’t care

Note:

*

When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D

converter are reset, and all registers are set to their initial values. To use these

functions after entering active mode, reset the registers.

Table 6.3 Internal State in Each Operating Mode

Function

Active Mode

Functioning

Sleep Mode

Functioning

Halted

Subsleep Mode

Halted

Standby Mode

Halted

System clock oscillator

CPU

operations

Instructions

Registers

Halted

Retained

RAM

IO ports

Register contents are

retained, but output is the

high-impedance state.

External

interrupts

IRQ3, IRQ0

WKP5

Functioning

Retained

Reset

Functioning

Retained

Reset

Peripheral Timer B1

modules

Timer V

Timer W

Retained

Watchdog

timer

Retained

(Functioning if the internal oscillator is selected

as a count clock.)

SCI3

IIC2

Functioning

Reset

Retained

Reset

Retained

Reset

A/D converter Functioning

LVD Functioning

Functioning

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Section 6 Power-Down Modes

6.2.1

Sleep Mode

In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock

frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an

interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling. Sleep

mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested

interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in sleep mode, the

CPU goes into the reset state and sleep mode is cleared.

6.2.2

Standby Mode

In standby mode, the system clock oscillator is halted, and operation of the CPU and on-chip

peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of

CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip

RAM contents will be retained as long as the voltage set by the RAM data retention voltage is

provided. The I/O ports go to the high-impedance state.

Standby mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator

starts functioning. The external oscillator also starts functioning when used. After the time set by

the STS2 to STS0 bits in SYSCR1 has elapsed, standby mode is cleared and the CPU starts

interrupt exception handling. Standby mode is not cleared if the I bit in the condition code register

(CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.

When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. The

system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The

RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation

stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared

and the CPU starts reset exception handling.

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Section 6 Power-Down Modes

6.2.3

Subsleep Mode

In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip

peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of

CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The

I/O ports keep the same states as before the transition.

Subsleep mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator

starts functioning. The external oscillator also starts functioning when used. After the time set by

the STS2 to STS0 bits in SYSCR1 has elapsed, subsleep mode is cleared and the CPU starts

interrupt exception handling. Subsleep mode is not cleared if the I bit in the condition code

register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.

When the RES pin is driven low in subsleep mode, the on-chip oscillator starts functioning. The

system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The

RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation

stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared

and the CPU starts reset exception handling.

6.3

Operating Frequency in Active Mode

Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in

SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction

execution.

6.4

Direct Transition

The CPU can execute programs in active mode. The operating frequency can be changed by

making a transition directly from active mode to active mode. A direct transition can be made by

executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. If the direct transition

interrupt is disabled by the interrupt enable register 1, a transition is made instead to sleep mode or

subsleep mode. Note that if a direct transition is attempted while the I bit in condition code

register (CCR) is set to 1, sleep mode or subsleep mode will be entered though that mode cannot

be cleared by means of an interrupt.

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Section 6 Power-Down Modes

6.5

Module Standby Function

The module standby function can be set to any peripheral module. In module standby mode, the

clock supply to the specified module stops and the module enters the power-down mode. Module

standby mode enables each on-chip peripheral module to enter the standby state by setting a bit

that corresponds to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing

the bit to 0.

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Section 6 Power-Down Modes

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Section 7 ROM

The features of the 12-kbyte (including 4 kbytes as the E7 or E8 control program area) flash

memory built into the HD64F36912G and HD64F36902G are summarized below.

•

Programming/erase methods

 The flash memory is programmed in 64-byte units at a time. Erase is performed in single-

block units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 4 kbytes ×

2 blocks. To erase the entire flash memory, each block must be erased in turn.

•

Reprogramming capability

 The flash memory can be reprogrammed up to 1,000 times.

On-board programming

 On-board programming/erasing can be done in boot mode, in which the boot program built

into the chip is started to erase or program of the entire flash memory. In normal user

program mode, individual blocks can be erased or programmed.

•

Automatic bit rate adjustment

 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match

the transfer bit rate of the host.

Programming/erasing protection

 Sets software protection against flash memory programming/erasing.

7.1

Block Configuration

Figure 7.1 shows the block configuration of 12-kbyte flash memory. The thick lines indicate

erasing units, the narrow lines indicate programming units, and the values are addresses. The flash

memory is divided into 1 kbyte × 4 blocks and 4 kbytes × 2 blocks. Erasing is performed in these

units. Programming is performed in 64-byte units starting from an address with lower eight bits

H'00, H'40, H'80, or H'C0.

ROM3321A_000120030300

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Section 7 ROM

H'0000

H'0040

H'0001

H'0041

H'0002

H'0042

H'003F

H'007F

Programming unit: 64 bytes

Erase unit

1 kbyte

H'03C0

H'0400

H'03C1

H'0401

H'0441

H'03C2

H'0402

H'0442

H'03FF

H'043F

H'047F

Erase unit H'0440

1 kbyte

H'07C0

H'0800

H'07C1

H'0801

H'0841

H'07C2

H'0802

H'0842

H'07FF

H'083F

H'087F

Erase unit

1 kbyte

H'0840

H'0BC0

H'0C00

H'0C40

H'0BC1

H'0C01

H'0C41

H'0BC2

H'0C02

H'0C42

H'0BFF

H'0C3F

H'0C7F

Programming unit: 64 bytes

Erase unit

1 kbyte

H'0FC0

H'1000

H'1040

H'0FC1

H'1001

H'1041

H'0FC2

H'1002

H'1042

H'0FFF

H'103F

H'107F

Programming unit: 64 bytes

Erase unit

4 kbytes

H'1FC0

H'2000

H'1FC1

H'2001

H'1FC2

H'2002

H'1FFF

H'203F

Programming unit: 64 bytes

Erase unit

4 kbytes

H'2040

H'2041

H'2042

H'207F

H'2FC0

H'2FC1

H'2FC2

H'2FFF

Figure 7.1 Flash Memory Block Configuration

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Section 7 ROM

7.2

Register Descriptions

The flash memory has the following registers.

•

Flash memory control register 1 (FLMCR1)

Flash memory control register 2 (FLMCR2)

Erase block register 1 (EBR1)

Flash memory enable register (FENR)

7.2.1

Flash Memory Control Register 1 (FLMCR1)

FLMCR1 is a register that makes the flash memory change to program mode, program-verify

mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash

Memory Programming/Erasing.

Initial

Bit

Bit Name Value

R/W

Description

7

—

0

—

Reserved

This bit is always read as 0.

Software Write Enable

6

5

4

3

SWE

R/W

When this bit is set to 1, flash memory

programming/erasing is enabled. When this bit is cleared

to 0, other FLMCR1 register bits and all EBR1 bits cannot

be set.

ESU

PSU

EV

0

Erase Setup

When this bit is set to 1, the flash memory changes to the

erase setup state. When it is cleared to 0, the erase setup

state is cancelled. Set this bit to 1 before setting the E bit

to 1 in FLMCR1.

Program Setup

When this bit is set to 1, the flash memory changes to the

program setup state. When it is cleared to 0, the program

setup state is cancelled. Set this bit to 1 before setting the

P bit in FLMCR1.

Erase-Verify

When this bit is set to 1, the flash memory changes to

erase-verify mode. When it is cleared to 0, erase-verify

mode is cancelled.

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Section 7 ROM

Initial

Bit Name Value

Bit

R/W

Description

2

PV

0

R/W

Program-Verify

When this bit is set to 1, the flash memory changes to

program-verify mode. When it is cleared to 0, program-

verify mode is cancelled.

1

0

E

R/W

Erase

When this bit is set to 1 while SWE = 1 and ESU = 1, the

flash memory changes to erase mode. When it is cleared

to 0, erase mode is cancelled.

P

Program

When this bit is set to 1 while SWE = 1 and PSU = 1, the

flash memory changes to program mode. When it is

cleared to 0, program mode is cancelled.

7.2.2

Flash Memory Control Register 2 (FLMCR2)

FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a

read-only register, and should not be written to.

Initial

Bit

Bit Name Value

R/W

Description

7

FLER

0

R

Flash Memory Error

Indicates that an error has occurred during an operation

on flash memory (programming or erasing). When FLER

is set to 1, flash memory goes to the error-protection

state.

See section 7.5.3, Error Protection, for details.

Reserved

6 to 0

—

All 0

—

These bits are always read as 0.

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Section 7 ROM

7.2.3

Erase Block Register 1 (EBR1)

EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit

in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to

be automatically cleared to 0.

Initial

Bit

Bit Name Value

R/W

Description

7, 6

—

All 0

—

Reserved

These bits are always read as 0.

5

4

3

2

1

0

EB5

EB4

EB3

EB2

EB1

EB0

0

R/W

When this bit is set to 1, 4 kbytes of H'2000 to H'2FFF will

be erased.

When this bit is set to 1, 4 kbytes of H'1000 to H'1FFF will

be erased.

When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will

be erased.

When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will

be erased.

When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will

be erased.

When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will

be erased.

7.2.4

Flash Memory Enable Register (FENR)

Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,

FLMCR1, FLMCR2, and EBR1.

Initial

Bit

Bit Name Value

R/W

Description

7

FLSHE

—

0

R/W

Flash Memory Control Register Enable

Flash memory control registers can be accessed when

this bit is set to 1. Flash memory control registers cannot

be accessed when this bit is set to 0.

6 to 0

All 0

—

Reserved

These bits are always read as 0.

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7.3

On-Board Programming Modes

There is a mode for programming/erasing of the flash memory; boot mode, which enables on-

board programming/erasing. On-board programming/erasing can also be performed in user

program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST

pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level

of each pin must be defined four states before the reset ends.

When changing to boot mode, the boot program built into this LSI is initiated. The boot program

transfers the programming control program from the externally-connected host to on-chip RAM

via SCI3. After erasing the entire flash memory, the programming control program is executed.

This can be used for programming initial values in the on-board state or for a forcible return when

programming/erasing can no longer be done in user program mode. In user program mode,

individual blocks can be erased and programmed by branching to the user program/erase control

program prepared by the user.

Table 7.1 Setting Programming Modes

TEST

NMI

1

E10T_0

LSI State after Reset End

User mode

0

X

1

0

Boot mode

[Legend]

X:

Don’t care

7.3.1

Boot Mode

Table 7.2 shows the boot mode operations between reset end and branching to the programming

control program.

1. When boot mode is used, the flash memory programming control program must be prepared in

the host beforehand. Prepare a programming control program in accordance with the

description in section 7.4, Flash Memory Programming/Erasing.

2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop

bit, and no parity.

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Section 7 ROM

3. When the boot program is initiated, the chip measures the low-level period of asynchronous

SCI communication data (H'00) transmitted continuously from the host. The chip then

calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that

of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be

pulled up on the board if necessary. After the reset is complete, it takes approximately 100

states before the chip is ready to measure the low-level period.

4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the

completion of bit rate adjustment. The host should confirm that this adjustment end indication

(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could

not be performed normally, initiate boot mode again by a reset. Depending on the host's

transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between

the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate

and system clock frequency of this LSI within the ranges listed in table 7.3.

5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F980 to

H'FEEF is the area to which the programming control program is transferred from the host.

The boot program area cannot be used until the execution state in boot mode switches to the

programming control program.

6. Before branching to the programming control program, the chip terminates transfer operations

by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value

remains set in BRR. Therefore, the programming control program can still use it for transfer of

write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The

contents of the CPU general registers are undefined immediately after branching to the

programming control program. These registers must be initialized at the beginning of the

programming control program, as the stack pointer (SP), in particular, is used implicitly in

subroutine calls, etc.

7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at

least 20 states, and then setting the TEST pin and NMI pin. Boot mode is also cleared when a

WDT overflow occurs.

8. Do not change the TEST pin and NMI pin input levels in boot mode.

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Section 7 ROM

Table 7.2 Boot Mode Operation

Host Operation

Communication Contents

LSI Operation

Processing Contents

Branches to boot program at reset-start.

Boot program initiation

. . .

H'00, H'00

H'00

Continuously transmits data H'00

at specified bit rate.

• Measures low-level period of receive data

H'00.

• Calculates bit rate and sets BRR in SCI3.

• Transmits data H'00 to host as adjustment

end indication.

H'00

Transmits data H'55 when data H'00

is received error-free.

H'55

H'55 reception.

H'FF

H'AA

Boot program

erase error

Checks flash memory data, erases all flash

memory blocks in case of written data

existing, and transmits data H'AA to host.

(If erase could not be done, transmits data

H'FF to host and aborts operation.)

H'AA reception

Upper bytes, lower bytes

Echoback

Transmits number of bytes (N) of

programming control program to be

transferred as 2-byte data

(low-order byte following high-order

byte)

Echobacks the 2-byte data

received to host.

Echobacks received data to host and also

transfers it to RAM.

(repeated for N times)

H'XX

Transmits 1-byte of programming

control program (repeated for N times)

Echoback

H'AA

Transmits data H'AA to host.

H'AA reception

Branches to programming control program

transferred to on-chip RAM and starts

execution.

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Section 7 ROM

Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible

Host Bit Rate

9,600 bps

System Clock Frequency Range of LSI

8 MHz (on-chip oscillator clock)

4,800 bps

2,400 bps

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Section 7 ROM

7.3.2

Programming/Erasing in User Program Mode

On-board programming/erasing of an individual flash memory block can also be performed in user

program mode by branching to a user program/erase control program. The user must set branching

conditions and provide on-board means of supplying programming data. The flash memory must

contain the user program/erase control program or a program that provides the user program/erase

control program from external memory. As the flash memory itself cannot be read during

programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot

mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode.

Prepare a user program/erase control program in accordance with the description in section 7.4,

Flash Memory Programming/Erasing.

Reset-start

No

Program/erase?

Yes

Transfer user program/erase control

program to RAM

Branch to flash memory application

program

Branch to user program/erase control

program in RAM

Execute user program/erase control

program (flash memory rewrite)

Branch to flash memory application

program

Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode

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7.4

Flash Memory Programming/Erasing

A software method using the CPU is employed to program and erase flash memory in the on-

board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one

of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify

mode. The programming control program in boot mode and the user program/erase control

program in user program mode use these operating modes in combination to perform

programming/erasing. Flash memory programming and erasing should be performed in

accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2,

Erase/Erase-Verify, respectively.

7.4.1

Program/Program-Verify

When writing data or programs to the flash memory, the program/program-verify flowchart shown

in figure 7.3 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to the flash memory without subjecting the chip to

voltage stress or sacrificing program data reliability.

1. Programming must be done to an empty address. Do not reprogram an address to which

programming has already been performed.

2. Programming should be carried out 64 bytes at a time. A 64-byte data transfer must be

performed even if writing fewer than 64 bytes. In this case, H'FF data must be written to the

extra addresses.

3. Prepare the following data storage areas in RAM: A 64-byte programming data area, a 64-byte

reprogramming data area, and a 64-byte additional-programming data area. Perform

reprogramming data computation according to table 7.4, and additional programming data

computation according to table 7.5.

4. Consecutively transfer 64 bytes of data in byte units from the reprogramming data area or

additional-programming data area to the flash memory. The program address and 64-byte data

are latched in the flash memory. The lower 8 bits of the start address in the flash memory

destination area must be H'00, H'40, H'80, or H'C0.

5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the

allowable programming times.

6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

An overflow cycle of approximately 6.6 ms is allowed.

7. For a dummy write to a verify address, write 1-byte data H'FF to an even address. Verify data

can be read in words from the address to which a dummy write was performed.

8. The maximum number of repetitions of the program/program-verify sequence of the same bit

is 1,000.

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Section 7 ROM

START

Write pulse application subroutine

Disable WDT

*2

Apply Write Pulse

Set SWE bit in FLMCR1

WDT enable

Wait 1 µs

Set PSU bit in FLMCR1

Store 64-byte program data in program

data area and reprogram data area

*1

Wait 50 µs

n = 1

m= 0

Set P bit in FLMCR1

Wait (Wait time = Programming time)

Write 64-byte data in RAM reprogram

data area consecutively to flash memory

Clear P bit in FLMCR1

Wait 5 µs

Apply Write pulse

Set PV bit in FLMCR1

Clear PSU bit in FLMCR1

Wait 5 µs

Wait 4 µs

Set block start address as

verify address

Disable WDT

n ← n + 1

H'FF dummy write to verify address

End Sub

Wait 2 µs

*

1

Read verify data

Increment address

Verify data =

Write data?

No

m = 1

Yes

No

n ≤ 6 ?

Yes

Additional-programming data computation

Reprogram data computation

64-byte

data verification completed?

No

Yes

Clear PV bit in FLMCR1

Wait 2 µs

No

n ≤ 6?

Yes

Successively write 64-byte data from additional-

programming data area in RAM to flash memory

Sub-Routine-Call

Apply Write Pulse

No

Yes

m = 0 ?

n ≤ 1000 ?

Yes

No

Clear SWE bit in FLMCR1

Wait 100 µs

End of programming

Programming failure

Notes: 1. The RTS instruction must not be used during the following (1) and (2) periods.

(1) A period between 64-byte data programming to flash memory and the P bit clearing

(2) A period between dummy writing of H'FF to a verify address and verify data reading

2. When WDT is in use, disable it once.

Figure 7.3 Program/Program-Verify Flowchart

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Section 7 ROM

Table 7.4 Reprogram Data Computation Table

Program Data

Verify Data

Reprogram Data

Comments

0

1

0

1

0

1

0

1

Programming completed

Reprogram bit

—

Remains in erased state

Table 7.5 Additional-Program Data Computation Table

Additional-Program

Reprogram Data

Verify Data

Data

Comments

0

1

0

1

0

1

0

1

Additional-program bit

No additional programming

Table 7.6 Programming Time

n

Programming

In Additional

Programming

(Number of Writes) Time

Comments

1 to 6

30

10

—

7 to 1,000

200

Note: Time shown in µs.

7.4.2

Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be

followed.

1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Erasing is performed in block units. Make only a single-bit specification in the erase block

register (EBR1). To erase multiple blocks, each block must be erased in turn.

3. The time during which the E bit is set to 1 is the flash memory erase time.

4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An

overflow cycle of approximately 19.8 ms is allowed.

5. For a dummy write to a verify address, write 1-byte data H'FF to an even address. Verify data

can be read in words from the address to which a dummy write was performed.

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Section 7 ROM

6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-

verify sequence as before. The maximum number of repetitions of the erase/erase-verify

sequence is 100.

7.4.3

Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed

or erased, or while the boot program is executing, for the following three reasons:

1. Interrupt during programming/erasing may cause a violation of the programming or erasing

algorithm, with the result that normal operation cannot be assured.

2. If interrupt exception handling starts before the vector address is written or during

programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.

3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be

carried out.

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Section 7 ROM

Erase start

*2

Disable WDT

SWE bit ← 1

Wait 1 µs

n ← 1

Set EBR1

Enable WDT

ESU bit ← 1

Wait 100 µs

E bit ← 1

Wait 10 ms

E bit ← 0

Wait 10 µs

ESU bit ← 10

Wait 10 µs

Disable WDT

EV bit ← 1

Wait 20 µs

Set block start address as verify address

H'FF dummy write to verify address

Wait 2 µs

*1

n ← n + 1

Read verify data

No

Verify data = all 1s ?

Yes

Increment address

No

Last address of block ?

Yes

EV bit ← 0

Wait 4 µs

EV bit ← 0

Wait 4µs

No

Yes

n ≤100 ?

All erase block erased ?

Yes

No

Yes

SWE bit ← 0

Wait 100 µs

End of erasing

Erase failure

Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.

2. When WDT is in use, disable it once.

Figure 7.4 Erase/Erase-Verify Flowchart

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Section 7 ROM

7.5

Program/Erase Protection

There are three kinds of flash memory program/erase protection; hardware protection, software

protection, and error protection.

7.5.1

Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash

memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase

block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered

unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset

during operation, hold the RES pin low for the RES pulse width specified in the AC

Characteristics section.

7.5.2

Software Protection

Software protection can be implemented against programming/erasing of all flash memory blocks

by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit

in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block

register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00,

erase protection is set for all blocks.

7.5.3

Error Protection

In error protection, an error is detected when CPU runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

When the following errors are detected during programming/erasing of flash memory, the FLER

bit in FLMCR2 is set to 1, and the error protection state is entered.

•

When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

•

Immediately after exception handling excluding a reset during programming/erasing

When a SLEEP instruction is executed during programming/erasing

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Section 7 ROM

The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode

is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-

entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition

can be made to verify mode. Error protection can be cleared only by a reset.

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Section 7 ROM

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Section 8 RAM

The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes,

and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM,

respectively. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by

the CPU to both byte data and word data.

Product Classification

RAM Size

RAM Address

Flash memory version

H8/36912F

1536 bytes H'F980 to H'FF7F*

H8/36902F

Masked ROM version

H8/36912, H8/36902

H8/36911, H8/36901

H8/36900

512 bytes

256 bytes

H'FD80 to H'FF7F

H'FE80 to H'FF7F

Note:

*

When the E7 or E8 is used, area H'F980 to H'FD7F must not be accessed.

RAM0400A_000020020200

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Section 8 RAM

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Section 9 I/O Ports

The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to

P80) is a large current port, which can drive 20 mA (@V_OL= 1.5 V) when a low level signal is

output. Any of these ports can become an input port immediately after a reset. They can also be

used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these

functions can be switched depending on the register settings. The registers for selecting these

functions can be divided into two types: those included in I/O ports and those included in each on-

chip peripheral module. General I/O ports are comprised of the port control register for controlling

inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit

units. For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of

bit manipulation instructions to the port control register and port data register, see section 2.8.3,

Bit Manipulation Instruction.

9.1

Port 1

Port 1 is a general I/O port also functioning as an IRQ interrupt input pin and timer V input pin.

Figure 9.1 shows its pin configuration.

P17/IRQ3/TRGV

Port 1

P14/IRQ0

Figure 9.1 Port 1 Pin Configuration

Port 1 has the following registers.

•

Port mode register 1 (PMR1)

Port control register 1 (PCR1)

Port data register 1 (PDR1)

Port pull-up control register 1 (PUCR1)

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Section 9 I/O Ports

9.1.1

Port Mode Register 1 (PMR1)

PMR1 switches the functions of pins in port 1 and port 2.

Initial

Bit

Bit Name Value

R/W

Description

7

IRQ3

0

R/W

P17/IRQ3/TRGV Pin Function Switch

Selects whether pin P17/IRQ3/TRGV is used as P17 or

as IRQ3/TRGV.

0: General I/O port

1: IRQ3/TRGV input pin

Reserved

6, 5

4



All 0

0



These bits are always read as 0.

IRQ0

R/W

P14/IRQ0 Pin Function Switch

Selects whether pin P14/IRQ0 is used as P14 or as

IRQ0.

0: General I/O port

1: IRQ0 input pin

3, 2

1



All 0

0



Reserved

These bits are always read as 0.

P22/TXD Pin Function Switch

Selects whether pin P22/TXD is used as P22 or as TXD.

0: General I/O port

TXD

R/W

1: TXD output pin

0



0



Reserved

This bit is always read as 0.

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Section 9 I/O Ports

9.1.2

Port Control Register 1 (PCR1)

PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.

Initial

Bit

7

Bit Name Value

R/W

W

Description

PCR17



0

When the corresponding pin is designated in PMR1 as a

general I/O pin, setting a PCR1 bit to 1 makes the

corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

6



0



W

5



4

PCR14



Bits 6, 5, and 3 to 0 are reserved.

3



2



1



0



9.1.3

Port Data Register 1 (PDR1)

PDR1 is a general I/O port data register of port 1.

Initial

Bit

7

Bit Name Value

R/W



Description

P17



0

1

0

1

These bits store output data for port 1 pins.

6

If PDR1 is read while PCR1 bits are set to 1, the value

stored in PDR1 are read. If PDR1 is read while PCR1 bits

are cleared to 0, the pin states are read regardless of the

value stored in PDR1.

5



4

P14



R/W



3

Bits 6, 5, and 3 to 0 are reserved. These bits are always

read as 1.

2



1



0



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Section 9 I/O Ports

9.1.4

Port Pull-Up Control Register 1 (PUCR1)

PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.

Initial

Bit

7

Bit Name Value

R/W



Description

PUCR17

0

1

0

1

Only bits for which PCR1 is cleared are valid.

6



The pull-up MOS of the P17 and P14 pins enter the on-

state when these bits are set to 1, while they enter the

off-state when these bits are cleared to 0.

5



4

PUCR14

R/W



Bits 6, 5, and 3 to 0 are reserved. These bits are always

read as 1.

3



2



1



0



9.1.5

Pin Functions

The correspondence between the register specification and the port functions is shown below.

P17/IRQ3/TRGV pin

•

Register

Bit Name

PMR1

IRQ3

PCR1

PCR17

Pin Function

Setting value 0

0

1

X

P17 input pin

P17 output pin

1

IRQ3 input/TRGV input pin

[Legend]

X:

Don't care

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Section 9 I/O Ports

•

P14/IRQ0 pin

Register

Bit Name

PMR1

IRQ0

PCR1

PCR14

Pin Function

P14 input pin

P14 output pin

IRQ0 input pin

Setting value 0

0

1

X

1

[Legend]

X:

Don't care

9.2

Port 2

Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in

figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both

uses.

P22/TXD

P21/RXD

Port 2

P20/SCK3

Figure 9.2 Port 2 Pin Configuration

Port 2 has the following registers.

•

Port control register 2 (PCR2)

Port data register 2 (PDR2)

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Section 9 I/O Ports

9.2.1

Port Control Register 2 (PCR2)

PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.

Initial

Bit

Bit Name Value

R/W



Description

7 to 3



0

Reserved

2

1

0

PCR22

PCR21

PCR20

W

When each of the port 2 pins, P22 to P20, functions as an

general I/O port, setting a PCR2 bit to 1 makes the

corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

0

W

0

W

9.2.2

Port Data Register 2 (PDR2)

PDR2 is a general I/O port data register of port 2.

Initial

Bit

Bit Name Value

R/W

Description

7 to 3



All 1



Reserved

These bits are always read as 1.

These bits store output data for port 2 pins.

2

1

0

P22

P21

P20

0

R/W

If PDR2 is read while PCR2 bits are set to 1, the value

stored in PDR2 is read. If PDR2 is read while PCR2 bits

are cleared to 0, the pin states are read regardless of the

value stored in PDR2.

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9.2.3

The correspondence between the register specification and the port functions is shown below.

P22/TXD pin

Pin Functions

•

Register

PMR1

TXD

0

PCR2

PCR22

0

Bit Name

Pin Function

Setting

value

P22 input pin

1

P22 output pin

TXD output pin

1

X

[Legend]

X:

Don't care

•

P21/RXD pin

Register

Bit Name

SCR3

RE

PCR2

PCR21

0

Pin Function

Setting

value

0

P21 input pin

1

P21 output pin

RXD input pin

1

X

[Legend]

X:

Don't care

•

P20/SCK3 pin

Register

Bit Name

SCR3

CKE1

SMR

COM

0

PCR2

CKE0

PCR20

Pin Function

P20 input pin

Setting value 0

0

1

P20 output pin

SCK3 output pin

SCK3 input pin

0

1

X

1

X

0

X

1

[Legend]

X:

Don't care

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Section 9 I/O Ports

9.3

Port 5

Port 5 is a general I/O port also functioning as an I²C bus interface I/O pin*, A/D trigger input pin,

and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting

of the I²C bus interface has priority for functions of the P57/SCL and P56/SDA pins.

Note: * Supported only by the H8/36912 Group.

P57/SCL

Port 5

P56/SDA

P55/WKP5/ADTRG

Figure 9.3 Port 5 Pin Configuration

Port 5 has the following registers.

•

Port mode register 5 (PMR5)

Port control register 5 (PCR5)

Port data register 5 (PDR5)

Port pull-up control register 5 (PUCR5)

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Section 9 I/O Ports

9.3.1

Port Mode Register 5 (PMR5)

PMR5 switches the functions of pins in port 5.

Initial

Bit

Bit Name Value

R/W

Description

7, 6



All 0

0



Reserved

These bits are always read as 0.

5

WKP5

R/W

P55/WKP5/ADTRG Pin Function Switch

Selects whether pin P55/WKP5/ADTRG is used as P55

or as WKP5/ADTRG.

0: General I/O port

1: WKP5/ADTRG input pin

Reserved

4 to 0



All 0



These bits are always read as 0.

9.3.2

Port Control Register 5 (PCR5)

PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.

Initial

Bit

7

Bit Name Value

R/W

W

Description

PCR57

PCR56

PCR55

0

When each of the port 5 pins, P57 to P55, functions as an

general I/O port, setting a PCR5 bit to 1 makes the

corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

6

W

5

W

4 to 0



Reserved

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Section 9 I/O Ports

9.3.3

Port Data Register 5 (PDR5)

PDR5 is a general I/O port data register of port 5.

Initial

Bit

7

Bit Name Value

R/W

Description

P57

P56

P55

0

These bits store output data for port 5 pins.

6

If PDR5 is read while PCR5 bits are set to 1, the value

stored in PDR5 are read. If PDR5 is read while PCR5 bits

are cleared to 0, the pin states are read regardless of the

value stored in PDR5.

5

4 to 0



All 1



Reserved

These bits are always read as 1.

9.3.4

Port Pull-Up Control Register 5 (PUCR5)

PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.

Initial

Bit

Bit Name Value

R/W

Description

7, 6



All 0

0



Reserved

These bits are always read as 0.

Only bits for which PCR5 is cleared are valid.

5

PUCR55

R/W

The pull-up MOS of the corresponding pins enter the on-

state when this bit is set to 1, while they enter the off-

state when this bit is cleared to 0.

4 to 0



All 0



Reserved

These bits are always read as 0.

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Section 9 I/O Ports

9.3.5

The correspondence between the register specification and the port functions is shown below.

P57/SCL pin

Pin Functions

•

Register

Bit Name

ICCR

ICE

PCR5

PCR57

Pin Function

P57 input pin

P57 output pin

SCL I/O pin*

Setting value 0

0

1

X

1

[Legend]

X:

Note: As the SCL output form is NMOS open-drain, direct bus drive is enabled.

Supported only by the H8/36912 Group.

Don't care

*

•

P56/SDA pin

Register

Bit Name

ICCR

ICE

PCR5

PCR56

Pin Function

P56 input pin

P56 output pin

SDA I/O pin*

Setting value 0

0

1

X

1

[Legend]

X:

Note: As the SDA output form is NMOS open-drain, direct bus drive is enabled.

Supported only by the H8/36912 Group.

Don't care

*

•

P55/WKP5/ADTRG pin

Register

Bit Name

PMR5

WKP5

PCR5

PCR55

Pin Function

Setting value 0

0

1

X

P55 input pin

P55 output pin

1

WKP5/ADTRG input pin

[Legend]

X:

Don't care

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Section 9 I/O Ports

9.4

Port 7

Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown

in figure 9.4. The register setting of TCSRV in timer V has priority for functions of the

P76/TMOV pin. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input

ports that are connected to the timer V regardless of the register setting of port 7.

P76/TMOV

P75/TMCIV

P74/TMRIV

Port 7

Figure 9.4 Port 7 Pin Configuration

Port 7 has the following registers.

•

Port control register 7 (PCR7)

Port data register 7 (PDR7)

9.4.1

Port Control Register 7 (PCR7)

PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.

Initial

Bit

7

Bit Name Value

R/W



Description



0

Reserved

6

PCR76

PCR75

PCR74

W

Setting a PCR7 bit to 1 makes the corresponding pin an

output port, while clearing the bit to 0 makes the pin an

input port. Note that the TCSRV setting of the timer V has

priority for deciding input/output direction of the

P76/TMOV pin.

5

0

W

4

0

W

3 to 0



Reserved

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Section 9 I/O Ports

9.4.2

Port Data Register 7 (PDR7)

PDR7 is a general I/O port data register of port 7.

Initial

Bit

Bit Name Value

R/W

Description

7



1



Reserved

This bit is always read as 1.

6

5

4

P76

P75

P74

0

R/W

These bits store output data for port 7 pins.

If PDR7 is read while PCR7 bits are set to 1, the value

stored in PDR7 is read. If PDR7 is read while PCR7 bits

are cleared to 0, the pin states are read regardless of the

value stored in PDR7.

3 to 0



All 1



Reserved

These bits are always read as 1.

9.4.3

Pin Functions

The correspondence between the register specification and the port functions is shown below.

P76/TMOV pin

•

Register

Bit Name

Setting value 0000

TCSRV

PCR7

OS3 to OS0 PCR76

Pin Function

P76 input pin

0

1

X

P76 output pin

TMOV output pin

Other than

the above

values

[Legend]

X: Don't care

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Section 9 I/O Ports

•

P75/TMCIV pin

Register

Bit Name

PCR7

PCR75

Pin Function

Setting value 0

1

P75 input/TMCIV input pin

P75 output/TMCIV input pin

•

P74/TMRIV pin

Register

Bit Name

PCR7

PCR74

Pin Function

Setting value 0

1

P74 input/TMRIV input pin

P74 output/TMRIV input pin

9.5

Port 8

Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown

in figure 9.5. The register setting of the timer W has priority for functions of the P84/FTIOD,

P83/FTIOC, P82/FTIOB, and P81/FTIOA pins. The P80/FTCI pin also functions as a timer W

input port that is connected to the timer W regardless of the register setting of port 8.

P84/FTIOD

P83/FTIOC

Port 8

P82/FTIOB

P81/FTIOA

P80/FTCI

Figure 9.5 Port 8 Pin Configuration

Port 8 has the following registers.

•

Port control register 8 (PCR8)

Port data register 8 (PDR8)

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Section 9 I/O Ports

9.5.1

Port Control Register 8 (PCR8)

PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.

Initial

Bit

Bit Name Value

R/W



W

Description

7 to 5



0

Reserved

4

3

2

1

0

PCR84

PCR83

PCR82

PCR81

PCR80

When each of the port 8 pins, P84 to P80, functions as an

general I/O port, setting a PCR8 bit to 1 makes the

corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

0

W

0

W

0

W

0

W

9.5.2

Port Data Register 8 (PDR8)

PDR8 is a general I/O port data register of port 8.

Initial

Bit

Bit Name Value

R/W



Description

7 to 5



All 0

Reserved

4

3

2

1

0

P84

P83

P82

P81

P80

0

R/W

These bits store output data for port 8 pins.

If PDR8 is read while PCR8 bits are set to 1, the value

stored in PDR8 is read. If PDR8 is read while PCR8 bits

are cleared to 0, the pin states are read regardless of the

value stored in PDR8.

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Section 9 I/O Ports

9.5.3

Pin Functions

The correspondence between the register specification and the port functions is shown below.

•

P84/FTIOD pin

Register TMRW

Bit Name PWMD

TIOR1

IOD1

PCR8

IOD2

IOD0

PCR84 Pin Function

Setting

value

0

P84 input/FTIOD input pin

1

X

0

1

X

P84 output/FTIOD input pin

FTIOD output pin

0

1

0

1

X

1

X

FTIOD output pin

P84 input/FTIOD input pin

P84 output/FTIOD input pin

PWM output pin

1

X

[Legend]

X:

Don't care

•

P83/FTIOC pin

Register TMRW

Bit Name PWMC

TIOR1

PCR8

PCR83

0

IOC2

IOC1

IOC0

Pin Function

Setting

value

0

P83 input/FTIOC input pin

1

X

0

1

X

P83 output/FTIOC input pin

FTIOC output pin

0

1

0

1

X

1

X

FTIOC output pin

P83 input/FTIOC input pin

P83 output/FTIOC input pin

PWM output pin

1

X

[Legend]

X:

Don't care

Rev. 3.00 Sep. 14, 2006 Page 132 of 408

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Section 9 I/O Ports

•

P82/FTIOB pin

Register TMRW

Bit Name PWMB

TIOR0

IOB1

PCR8

IOB2

IOB0

PCR82 Pin Function

Setting

value

0

P82 input/FTIOB input pin

1

X

0

1

X

P82 output/FTIOB input pin

FTIOB output pin

0

1

0

1

X

1

X

FTIOB output pin

P82 input/FTIOB input pin

P82 output/FTIOB input pin

PWM output pin

1

X

[Legend]

X:

Don't care

•

P81/FTIOA pin

Register

Bit Name

TIOR0

IOA1

PCR8

IOA2

IOA0

PCR81

Pin Function

Setting value 0

0

1

X

0

1

P81 input/FTIOA input pin

P81 output/FTIOA input pin

FTIOA output pin

0

1

0

1

X

1

X

FTIOA output pin

P81 input/FTIOA input pin

P81 output/FTIOA input pin

[Legend]

X:

Don't care

•

P80/FTCI pin

Register

Bit Name

PCR8

PCR80

Pin Function

Setting value 0

1

P80 input/FTCI input pin

P80 output/FTCI input pin

Rev. 3.00 Sep. 14, 2006 Page 133 of 408

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Section 9 I/O Ports

9.6

Port B

Port B is an input port also functioning as an A/D converter analog input pin and LVD external

comparison voltage input pin. Each pin of the port B is shown in figure 9.6.

PB3/AN3/ExtU

PB2/AN2/ExtD

Port B

PB1/AN1

PB0/AN0

Figure 9.6 Port B Pin Configuration

Port B has the following register.

•

Port data register B (PDRB)

9.6.1 Port Data Register B (PDRB)

PDRB is a general input-only port data register of port B.

Initial

Bit

Bit Name Value

R/W



R

Description

7 to 4



Reserved

3

2

1

0

PB3

PB2

PB1

PB0

The input value of each pin is read by reading this

register.

R

However, if a port B pin is designated as an analog input

channel by ADCSR in A/D converter or external

comparison voltage input pin by LVDCR in low-voltage

detection circuit, 0 is read.

R

Rev. 3.00 Sep. 14, 2006 Page 134 of 408

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Section 9 I/O Ports

9.6.2

The correspondence between the register specification and the port functions is shown below.

PB3/AN3/ExtU pin

Pin Functions

•

Register

Bit Name

Setting value 0

ADCSR

CH1

LVDCR

CH2

CH0

VDDII

Pin Function

1

0

1

0

AN3 input pin

AN3 input/ExtU input pin

PB3 input pin

Other than the above values

PB3 input/ExtU input pin

•

PB2/AN2/ExtD pin

Register

Bit Name

ADCSR

LVDCR

CH2

SCAN

CH1

CH0

0

VDDII

Pin Function

Setting value 0

0

1

0

1

0

AN2 input pin

X

AN2 input/ExtD input pin

PB2 input pin

Other than the above values

PB2 input/ExtD input pin

[Legend]

X:

Don't care

•

PB1/AN1 pin

Register

Bit Name

ADCSR

CH2

SCAN

CH1

CH0

1

Pin Function

Setting value 0

0

X

1

0

1

AN1 input pin

X

Other than the above values

PB1 input pin

[Legend]

X: Don't care

Rev. 3.00 Sep. 14, 2006 Page 135 of 408

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Section 9 I/O Ports

•

PB0/AN0 pin

Register

ADCSR

Bit Name

CH2

SCAN

CH1

0

CH0

0

Pin Function

Setting

value

0

1

AN0 input pin

X

Other than the above values

PB0 input pin

[Legend]

X:

Don't care

9.7

Port C

Port C is a general I/O port also functioning as an external oscillation pin and clock output pin.

Each pin of the port C is shown in figure 9.7. The register setting of CKCSR has priority for

functions of the pins for both uses.

PC1/OSC2/CLKOUT

Port C

PC0/OSC1

Figure 9.7 Port C Pin Configuration

Port C has the following registers.

•

Port control register C (PCRC)

Port data register C (PDRC)

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Section 9 I/O Ports

9.7.1

Port Control Register C (PCRC)

PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C.

Initial

Bit

7 to 2

1

Bit Name Value

R/W



Description



0

Reserved

PCRC1

PCRC0

W

When each of the port C pins, PC1 and PC0, functions as

an general I/O port, setting a PCRC bit to 1 makes the

corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

0

W

9.7.2

Port Data Register C (PDRC)

PDRC is a general I/O port data register of port C.

Initial

Bit

7 to 2

1

Bit Name Value

R/W



Description



0

Reserved

PC1

PC0

R/W

These bits store output data for port C pins.

0

If PDRC is read while PCRC bits are set to 1, the value

stored in PDRC is read. If PDRC is read while PCRC bits

are cleared to 0, the pin states are read regardless of the

value stored in PDRC.

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Section 9 I/O Ports

9.7.3

Pin Functions

The correspondence between the register specification and the port functions is shown below.

•

PC1/OSC2/CLKOUT pin

Register

Bit Name

CKCSR

PMRC0

PCRC

PMRC1

PCRC1

Pin Function

Setting value

0

X

0

1

X

PC1 input pin

PC1 output pin

1

0

1

CLKOUT output pin

OSC2 oscillation pin

[Legend]

X:

Don't care

•

PC0/OSC1 pin

Register

Bit Name

CKCSR

PMRC0

PCRC

PCRC0

Pin Function

PC0 input pin

PC0 output pin

Setting value 0

0

1

X

1

OSC1 oscillation pin

[Legend]

X:

Don't care

Rev. 3.00 Sep. 14, 2006 Page 138 of 408

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Section 10 Timer B1

Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two

operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1.

10.1

Features

•

Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4)

An interrupt is generated when the counter overflows.

TMB1

φ

PSS

TCB1

TLB1

[Legend]

TMB1:

TCB1:

TLB1:

Timer mode register B1

Timer counter B1

Timer load register B1

IRRTB1

IRRTB1: Timer B1 interrupt request flag

PSS: Prescaler S

Figure 10.1 Block Diagram of Timer B1

TIM08B0A_000020020200

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Section 10 Timer B1

10.2

Register Descriptions

The timer B1 has the following registers.

•

Timer mode register B1 (TMB1)

Timer counter B1 (TCB1)

Timer load register B1 (TLB1)

10.2.1 Timer Mode Register B1 (TMB1)

TMB1 selects the auto-reload function and input clock.

Initial

Bit

Bit Name Value

R/W

Description

7

TMB17

0

R/W

Auto-Reload Function Select

0: Interval timer function selected

1: Auto-reload function selected

Reserved

6



1

R/W

Although this bit is readable/writable, it should not be set

to 0.

5 to 3

All 1



Reserved

These bits are always read as 1.

2

1

0

TMB12

TMB11

TMB10

0

R/W

Clock Select

000: Internal clock: φ/8192

001: Internal clock: φ/2048

010: Internal clock: φ/512

011: Internal clock: φ/256

100: Internal clock: φ/64

101: Internal clock: φ/16

110: Internal clock: φ/4

111: Reserved (setting prohibited)

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Section 10 Timer B1

10.2.2 Timer Counter B1 (TCB1)

TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock

source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can

be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in

TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1.

10.2.3 Timer Load Register B1 (TLB1)

TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is

set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that

value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded

into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks.

TLB1 is allocated to the same address as TCB1.

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Section 10 Timer B1

10.3

Operation

10.3.1 Interval Timer Operation

When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon

reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing

resume immediately. The operating clock of timer B1 is selected from seven internal clock signals

output by prescaler S. The selection is made by the TMB12 to TMB10 bits in TMB1.

After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to

overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to

the CPU.

At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation

(TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1.

10.3.2 Auto-Reload Timer Operation

Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When

a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which

TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input

causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues

from that value. The overflow period can be set within a range from 1 to 256 input clocks,

depending on the TLB1 value.

The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-

reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into

TCB1.

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Section 10 Timer B1

10.4

Timer B1 Operating Modes

Table 10.1 shows the timer B1 operating modes.

Table 10.1 Timer B1 Operating Modes

Operating Mode

Reset

Active

Sleep

Subsleep

Halted

Standby

Halted

TCB1

Interval

Reset

Functions

Retained

Auto-reload Reset

Reset

Halted

TMB1

Retained

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Section 10 Timer B1

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REJ09B0105-0300

Section 11 Timer V

Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare-

match signals with two registers can also be used to reset the counter, request an interrupt, or

output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at

the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary

delay from the trigger input. Figure 11.1 shows a block diagram of timer V.

11.1

Features

•

Choice of seven clock signals is available.

Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.

•

Counter can be cleared by compare match A or B, or by an external reset signal. If the count

stop function is selected, the counter can be halted when cleared.

Timer output is controlled by two independent compare match signals, enabling pulse output

with an arbitrary duty cycle, PWM output, and other applications.

•

Three interrupt sources: compare match A, compare match B, timer overflow

Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or

both edges of the TRGV input can be selected.

TIM08V0A_000120030300

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Section 11 Timer V

TCRV1

TCORB

Trigger

control

TRGV

TMCIV

φ

Comparator

Clock select

TCNTV

Comparator

TCORA

PSS

Clear

control

TCRV0

TMRIV

Interrupt

request

control

Output

control

TCSRV

TMOV

CMIA

CMIB

OVI

[Legend]

TCORA:

TCORB:

TCNTV:

TCSRV:

TCRV0:

TCRV1:

PSS:

Time constant register A

Time constant register B

Timer counter V

Timer control/status register V

Timer control register V0

Timer control register V1

Prescaler S

CMIA:

CMIB:

OVI:

Compare-match interrupt A

Compare-match interrupt B

Overflow interrupt

Figure 11.1 Block Diagram of Timer V

Rev. 3.00 Sep. 14, 2006 Page 146 of 408

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Section 11 Timer V

11.2

Input/Output Pins

Table 11.1 shows the timer V pin configuration.

Table 11.1 Pin Configuration

Name

Abbreviation I/O

Function

Timer V output

Timer V clock input

Timer V reset input

Trigger input

TMOV

TMCIV

TMRIV

TRGV

Output

Input

Timer V waveform output

Clock input to TCNTV

External input to reset TCNTV

Trigger input to initiate counting

11.3

Register Descriptions

Time V has the following registers.

•

Timer counter V (TCNTV)

Timer constant register A (TCORA)

Timer constant register B (TCORB)

Timer control register V0 (TCRV0)

Timer control/status register V (TCSRV)

Timer control register V1 (TCRV1)

11.3.1 Timer Counter V (TCNTV)

TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer

control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time.

TCNTV can be cleared by an external reset input signal, or by compare match A or B. The

clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.

When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV).

TCNTV is initialized to H'00.

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Section 11 Timer V

11.3.2 Time Constant Registers A and B (TCORA, TCORB)

TCORA and TCORB have the same function.

TCORA and TCORB are 8-bit read/write registers.

TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,

CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.

Note that they must not be compared during the T3 state of a TCORA write cycle.

Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)

and the settings of bits OS3 to OS0 in TCSRV.

TCORA and TCORB are initialized to H'FF.

11.3.3 Timer Control Register V0 (TCRV0)

TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,

and controls each interrupt request.

Initial

Bit

Bit Name Value

R/W

Description

7

CMIEB

CMIEA

OVIE

0

R/W

Compare Match Interrupt Enable B

When this bit is set to 1, interrupt request from the CMFB

bit in TCSRV is enabled.

6

5

R/W

Compare Match Interrupt Enable A

When this bit is set to 1, interrupt request from the CMFA

bit in TCSRV is enabled.

Timer Overflow Interrupt Enable

When this bit is set to 1, interrupt request from the OVF

bit in TCSRV is enabled.

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Section 11 Timer V

Initial

Bit

4

Bit Name Value

R/W

Description

CCLR1

CCLR0

0

Counter Clear 1 and 0

3

These bits specify the clearing conditions of TCNTV.

00: Clearing is disabled

01: Cleared by compare match A

10: Cleared by compare match B

11: Cleared on the rising edge of the TMRIV pin.

The operation of TCNTV after clearing depends on TRGE

in TCRV1.

2

1

0

CKS2

CKS1

CKS0

0

R/W

Clock Select 2 to 0

These bits select clock signals to input to TCNTV and the

counting condition in combination with ICKS0 in TCRV1.

Refer to table 11.2.

Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions

TCRV0

Bit 1

TCRV1

Bit 2

CKS2

0

Bit 0

CKS0

0

Bit 0

CKS1

ICKS0

Description

0



0

Clock input prohibited

1

Internal clock: counts on φ/4, falling edge

Internal clock: counts on φ/8, falling edge

Internal clock: counts on φ/16, falling edge

Internal clock: counts on φ/32, falling edge

Internal clock: counts on φ/64, falling edge

Internal clock: counts on φ/128, falling edge

Clock input prohibited

1

0

1

0

1

0

1

0

1

0

1

0

1



External clock: counts on rising edge

External clock: counts on falling edge

External clock: counts on rising and falling

edge

Rev. 3.00 Sep. 14, 2006 Page 149 of 408

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Section 11 Timer V

11.3.4 Timer Control/Status Register V (TCSRV)

TCSRV indicates the status flag and controls outputs by using a compare match.

Initial

Bit

Bit Name Value

R/W

Description

7

CMFB

CMFA

OVF



0

1

R/W

Compare Match Flag B

[Setting condition]

•

When the TCNTV value matches the TCORB value

[Clearing condition]

After reading CMFB = 1, cleared by writing 0 to CMFB

•

6

5

4

R/W



Compare Match Flag A

[Setting condition]

•

When the TCNTV value matches the TCORA value

[Clearing condition]

After reading CMFA = 1, cleared by writing 0 to CMFA

•

Timer Overflow Flag

[Setting condition]

•

When TCNTV overflows from H'FF to H'00

[Clearing condition]

After reading OVF = 1, cleared by writing 0 to OVF

•

Reserved

This bit is always read as 1.

Output Select 3 and 2

3

2

OS3

OS2

0

R/W

These bits select an output method for the TMOV pin by

the compare match of TCORB and TCNTV.

00: No change

01: 0 output

10: 1 output

11: Output toggles

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Section 11 Timer V

Initial

Bit

1

Bit Name Value

R/W

Description

OS1

OS0

0

Output Select 1 and 0

0

These bits select an output method for the TMOV pin by

the compare match of TCORA and TCNTV.

00: No change

01: 0 output

10: 1 output

11: Output toggles

OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level

for compare match A. The two output levels can be controlled independently. After a reset, the

timer output is 0 until the first compare match.

11.3.5 Timer Control Register V1 (TCRV1)

TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to

TCNTV.

Initial

Bit

Bit Name Value

R/W

Description

7 to 5



All 1



Reserved

These bits are always read as 1.

TRGV Input Edge Select

4

3

TVEG1

TVEG0

0

R/W

These bits select the TRGV input edge.

00: TRGV trigger input is prohibited

01: Rising edge is selected

10: Falling edge is selected

11: Rising and falling edges are both selected

2

TRGE

0

R/W

TCNT starts counting up by the input of the edge which is

selected by TVEG1 and TVEG0.

0: Disables starting counting-up TCNTV by the input of

the TRGV pin and halting counting-up TCNTV when

TCNTV is cleared by a compare match.

1: Enables starting counting-up TCNTV by the input of

the TRGV pin and halting counting-up TCNTV when

TCNTV is cleared by a compare match.

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Section 11 Timer V

Initial

Bit Name Value

Bit

R/W

Description

1



1



Reserved

This bit is always read as 1.

Internal Clock Select 0

0

ICKS0

0

R/W

This bit selects clock signals to input to TCNTV in

combination with CKS2 to CKS0 in TCRV0.

Refer to table 11.2.

11.4

Operation

11.4.1 Timer V Operation

1. According to table 11.2, six internal/external clock signals output by prescaler S can be

selected as the timer V operating clock signals. When the operating clock signal is selected,

TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal

selected, and figure 11.3 shows the count timing with both edges of an external clock signal

selected.

2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0

will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the

CPU when OVIE in TCRV0 is 1.

3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B

(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The

compare-match signal is generated in the last state in which the values match. Figure 11.5

shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in

TCRV0 is 1.

4. When a compare match A or B is generated, the TMOV responds with the output value

selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is

toggled by compare match A.

5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding

compare match. Figure 11.7 shows the timing.

6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the

input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.

Figure 11.8 shows the timing.

7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is

halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by

TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.

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Section 11 Timer V

φ

Internal clock

TCNTV input

clock

N – 1

N

N + 1

TCNTV

Figure 11.2 Increment Timing with Internal Clock

φ

TMCIV

(External clock

input pin)

TCNTV input

clock

N – 1

N

N + 1

TCNTV

Figure 11.3 Increment Timing with External Clock

φ

TCNTV

H'FF

H'00

Overflow signal

OVF

Figure 11.4 OVF Set Timing

Rev. 3.00 Sep. 14, 2006 Page 153 of 408

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Section 11 Timer V

φ

TCNTV

N

N+1

TCORA or

TCORB

Compare match

signal

CMFA or

CMFB

Figure 11.5 CMFA and CMFB Set Timing

φ

Compare match

A signal

Timer V output

Figure 11.6 TMOV Output Timing

φ

Compare match

A signal

N

H'00

TCNTV

Figure 11.7 Clear Timing by Compare Match

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Section 11 Timer V

φ

TMRIV

(External counter

reset input pin)

TCNTV reset signal

TCNTV

N – 1

N

H'00

Figure 11.8 Clear Timing by TMRIV Input

11.5

Timer V Application Examples

11.5.1 Pulse Output with Arbitrary Duty Cycle

Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.

1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with

TCORA.

2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA

and to 0 at compare match with TCORB.

3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.

4. With these settings, a waveform is output without further software intervention, with a period

determined by TCORA and a pulse width determined by TCORB.

TCNTV value

H'FF

Counter cleared

TCORA

TCORB

H'00

Time

TMOV

Figure 11.9 Pulse Output Example

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Section 11 Timer V

11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input

The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary

delay from the TRGV input, as shown in figure 11.10. To set up this output:

1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with

TCORB.

2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA

and to 0 at compare match with TCORB.

3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV

input.

4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.

5. After these settings, a pulse waveform will be output without further software intervention,

with a delay determined by TCORA from the TRGV input, and a pulse width determined by

(TCORB to TCORA).

TCNTV value

H'FF

Counter cleared

TCORB

TCORA

H'00

Time

TRGV

TMOV

Compare match A

Compare match B

Compare match A

Compare match B

clears TCNTV and

halts count-up

clears TCNTV and

halts count-up

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input

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Section 11 Timer V

11.6

Usage Notes

The following types of contention or operation can occur in timer V operation.

1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear

signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing

takes precedence and the write to the counter is not carried out. If counting-up is generated in

the T3 state of a TCNTV write cycle, writing takes precedence.

2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write

to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure

11.12 shows the timing.

3. If compare matches A and B occur simultaneously, any conflict between the output selections

for compare match A and compare match B is resolved by the following priority: toggle

output > output 1 > output 0.

4. Depending on the timing, TCNTV may be incremented by a switch between different internal

clock sources. When TCNTV is internally clocked, an increment pulse is generated from the

falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown

in figure 11.13 the switch is from a high clock signal to a low clock signal, the switchover is

seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a

switch between internal and external clocks.

TCNTV write cycle by CPU

T₁

T₂

T₃

φ

Address

TCNTV address

Internal write signal

Counter clear signal

TCNTV

N

H'00

Figure 11.11 Contention between TCNTV Write and Clear

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Section 11 Timer V

TCORA write cycle by CPU

T₁T₂T₃

φ

Address

TCORA address

Internal write signal

TCNTV

TCORA

N

N+1

M

TCORA write data

Compare match signal

Inhibited

Figure 11.12 Contention between TCORA Write and Compare Match

Clock before

switching

Clock after

switching

Count clock

TCNTV

N

N+1

N+2

Write to CKS1 and CKS0

Figure 11.13 Internal Clock Switching and TCNTV Operation

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Section 12 Timer W

The timer W has a 16-bit timer having output compare and input capture functions. The timer W

can count external events and output pulses with an arbitrary duty cycle by compare match

between the timer counter and four general registers. Thus, it can be applied to various systems.

12.1

Features

•

Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an

external clock (external events can be counted)

•

Capability to process up to four pulse outputs or four pulse inputs

Four general registers:

 Independently assignable output compare or input capture functions

 Usable as two pairs of registers; one register of each pair operates as a buffer for the output

compare or input capture register

•

Four selectable operating modes:

 Waveform output by compare match

Selections of 0 output, 1 output, or toggle output

 Input capture function

Rising edge, falling edge, or both edges

 Counter clearing function

Counters can be cleared by compare match

 PWM mode

Up to three-phase PWM output can be provided with desired duty ratio.

Any initial timer output value can be set

Five interrupt sources

•

Four compare match/input capture interrupts and an overflow interrupt.

TIM08W0A_000020020200

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Section 12 Timer W

Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer

W.

Table 12.1 Timer W Functions

Input/Output Pins

Item

Counter

FTIOA

FTIOB

FTIOC

FTIOD

Count clock

Internal clocks: φ, φ/2, φ/4, φ/8

External clock: FTCI

General registers

(output compare/input

capture registers)

Period

specified in

GRA

GRB

GRC (buffer GRD (buffer

register for

GRA in

register for

GRB in buffer

buffer mode) mode)

Counter clearing function GRA

compare

GRA

compare

match

—

match

Initial output value

setting function

—

Yes

—

Buffer function

Yes

Compare

match output

0

—

Yes

1

—

Yes

Toggle

—

Yes

Input capture function

PWM mode

—

Yes

—

Yes

Interrupt sources

Overflow

Compare

match/input match/input match/input match/input

capture capture capture capture

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Section 12 Timer W

FTIOA

Internal clock:

φ

/2

/4

/8

Clock

selector

FTIOB

FTIOC

FTIOD

IRRTW

Control logic

External clock: FTCI

Comparator

Internal

data bus

[Legend]

TMRW: Timer mode register W (8 bits)

TCRW: Timer control register W (8 bits)

TIERW: Timer interrupt enable register W (8 bits)

TSRW: Timer status register W (8 bits)

TIOR:

Timer I/O control register (8 bits)

TCNT: Timer counter (16 bits)

GRA:

GRB:

GRC:

GRD:

General register A (input capture/output compare register: 16 bits)

General register B (input capture/output compare register: 16 bits)

General register C (input capture/output compare register: 16 bits)

General register D (input capture/output compare register: 16 bits)

IRRTW: Timer W interrupt request

Figure 12.1 Timer W Block Diagram

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Section 12 Timer W

12.2

Input/Output Pins

Table 12.2 summarizes the timer W pins.

Table 12.2 Pin Configuration

Name

Abbreviation Input/Output

Function

External clock input

FTCI

Input

External clock input pin

Input capture/output

compare A

FTIOA

Input/output

Output pin for GRA output compare or

input pin for GRA input capture

Input capture/output

compare B

FTIOB

FTIOC

FTIOD

Input/output

Output pin for GRB output compare,

input pin for GRB input capture, or

PWM output pin in PWM mode

Input capture/output

compare C

Output pin for GRC output compare,

input pin for GRC input capture, or

PWM output pin in PWM mode

Input capture/output

compare D

Output pin for GRD output compare,

input pin for GRD input capture, or

PWM output pin in PWM mode

12.3

Register Descriptions

The timer W has the following registers.

•

Timer mode register W (TMRW)

Timer control register W (TCRW)

Timer interrupt enable register W (TIERW)

Timer status register W (TSRW)

Timer I/O control register 0 (TIOR0)

Timer I/O control register 1 (TIOR1)

Timer counter (TCNT)

General register A (GRA)

General register B (GRB)

General register C (GRC)

General register D (GRD)

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Section 12 Timer W

12.3.1 Timer Mode Register W (TMRW)

TMRW selects the general register functions and the timer output mode.

Initial

Bit

Bit Name Value

R/W

Description

7

CTS

0

R/W

Counter Start

The counter operation is halted when this bit is 0, while it

can be performed when this bit is 1.

6

5



1

0



Reserved

This bit is always read as 1.

Buffer Operation B

Selects the GRD function.

BUFEB

R/W

0: GRD operates as an input capture/output compare

register

1: GRD operates as the buffer register for GRB

Buffer Operation A

4

BUFEA

0

R/W

Selects the GRC function.

0: GRC operates as an input capture/output compare

register

1: GRC operates as the buffer register for GRA

Reserved

3

2



1

0



This bit is always read as 1.

PWM Mode D

PWMD

R/W

Selects the output mode of the FTIOD pin.

0: FTIOD operates normally (output compare output)

1: PWM output

1

0

PWMC

PWMB

0

R/W

PWM Mode C

Selects the output mode of the FTIOC pin.

0: FTIOC operates normally (output compare output)

1: PWM output

PWM Mode B

Selects the output mode of the FTIOB pin.

0: FTIOB operates normally (output compare output)

1: PWM output

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Section 12 Timer W

12.3.2 Timer Control Register W (TCRW)

TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer

output levels.

Initial

Bit

Bit Name Value

R/W

Description

7

CCLR

0

R/W

Counter Clear

The TCNT value is cleared by compare match A when

this bit is 1. When it is 0, TCNT operates as a free-

running counter.

6

5

4

CKS2

CKS1

CKS0

0

R/W

Clock Select 2 to 0

Select the TCNT clock source.

000: Internal clock: counts on φ

001: Internal clock: counts on φ/2

010: Internal clock: counts on φ/4

011: Internal clock: counts on φ/8

1XX: Counts on rising edges of the external event (FTCI)

When the internal clock source (φ) is selected, subclock

sources are counted in subactive and subsleep modes.

3

2

1

TOD

TOC

TOB

0

R/W

Timer Output Level Setting D

Sets the output value of the FTIOD pin until the first

compare match D is generated.

0: Output value is 0*

1: Output value is 1*

Timer Output Level Setting C

Sets the output value of the FTIOC pin until the first

compare match C is generated.

0: Output value is 0*

1: Output value is 1*

Timer Output Level Setting B

Sets the output value of the FTIOB pin until the first

compare match B is generated.

0: Output value is 0*

1: Output value is 1*

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Section 12 Timer W

Initial

Bit

Bit Name Value

R/W

Description

0

TOA

0

R/W

Timer Output Level Setting A

Sets the output value of the FTIOA pin until the first

compare match A is generated.

0: Output value is 0*

1: Output value is 1*

[Legend]

X:

Don't care

The change of the setting is immediately reflected in the output value.

Note:

*

12.3.3 Timer Interrupt Enable Register W (TIERW)

TIERW controls the timer W interrupt request.

Initial

Bit

Bit Name Value

R/W

Description

7

OVIE

0

R/W

Timer Overflow Interrupt Enable

When this bit is set to 1, FOVI interrupt requested by OVF

flag in TSRW is enabled.

6 to 4

3



All 1

0



Reserved

These bits are always read as 1.

Input Capture/Compare Match Interrupt Enable D

IMIED

R/W

When this bit is set to 1, IMID interrupt requested by

IMFD flag in TSRW is enabled.

2

1

0

IMIEC

IMIEB

IMIEA

0

R/W

Input Capture/Compare Match Interrupt Enable C

When this bit is set to 1, IMIC interrupt requested by

IMFC flag in TSRW is enabled.

Input Capture/Compare Match Interrupt Enable B

When this bit is set to 1, IMIB interrupt requested by

IMFB flag in TSRW is enabled.

Input Capture/Compare Match Interrupt Enable A

When this bit is set to 1, IMIA interrupt requested by

IMFA flag in TSRW is enabled.

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Section 12 Timer W

12.3.4 Timer Status Register W (TSRW)

TSRW shows the status of interrupt requests.

Initial

Bit

Bit Name Value

R/W

Description

7

OVF

0

R/W

Timer Overflow Flag

[Setting condition]

•

When TCNT overflows from H'FFFF to H'0000

[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF

•

6 to 4

3



All 1

0



Reserved

These bits are always read as 1.

Input Capture/Compare Match Flag D

[Setting conditions]

IMFD

R/W

•

TCNT = GRD when GRD functions as an output

compare register

•

The TCNT value is transferred to GRD by an input

capture signal when GRD functions as an input

capture register

[Clearing condition]

Read IMFD when IMFD = 1, then write 0 in IMFD

•

2

IMFC

0

R/W

Input Capture/Compare Match Flag C

[Setting conditions]

•

TCNT = GRC when GRC functions as an output

compare register

•

The TCNT value is transferred to GRC by an input

capture signal when GRC functions as an input

capture register

[Clearing condition]

Read IMFC when IMFC = 1, then write 0 in IMFC

•

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Section 12 Timer W

Initial

Bit

Bit Name Value

R/W

Description

1

IMFB

0

R/W

Input Capture/Compare Match Flag B

[Setting conditions]

•

TCNT = GRB when GRB functions as an output

compare register

•

The TCNT value is transferred to GRB by an input

capture signal when GRB functions as an input

capture register

[Clearing condition]

Read IMFB when IMFB = 1, then write 0 in IMFB

•

0

IMFA

0

R/W

Input Capture/Compare Match Flag A

[Setting conditions]

•

TCNT = GRA when GRA functions as an output

compare register

•

The TCNT value is transferred to GRA by an input

capture signal when GRA functions as an input

capture register

[Clearing condition]

•

Read IMFA when IMFA = 1, then write 0 in IMFA

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Section 12 Timer W

12.3.5 Timer I/O Control Register 0 (TIOR0)

TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and

FTIOB pins.

Initial

Bit

Bit Name Value

R/W

Description

7



1

0



Reserved

This bit is always read as 1.

I/O Control B2

6

IOB2

R/W

Selects the GRB function.

0: GRB functions as an output compare register

1: GRB functions as an input capture register

I/O Control B1 and B0

5

4

IOB1

IOB0

0

R/W

When IOB2 = 0,

00: No output at compare match

01: 0 output to the FTIOB pin at GRB compare match

10: 1 output to the FTIOB pin at GRB compare match

11: Output toggles to the FTIOB pin at GRB compare

match

When IOB2 = 1,

00: Input capture at rising edge at the FTIOB pin

01: Input capture at falling edge at the FTIOB pin

1X: Input capture at rising and falling edges of the FTIOB

3

2



1

0



Reserved

This bit is always read as 1.

I/O Control A2

IOA2

R/W

Selects the GRA function.

0: GRA functions as an output compare register

1: GRA functions as an input capture register

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Section 12 Timer W

Initial

Bit

1

Bit Name Value

R/W

Description

IOA1

IOA0

0

I/O Control A1 and A0

When IOA2 = 0,

0

00: No output at compare match

01: 0 output to the FTIOA pin at GRA compare match

10: 1 output to the FTIOA pin at GRA compare match

11: Output toggles to the FTIOA pin at GRA compare

match

When IOA2 = 1,

00: Input capture at rising edge of the FTIOA pin

01: Input capture at falling edge of the FTIOA pin

1X: Input capture at rising and falling edges of the FTIOA

[Legend]

X:

Don't care

12.3.6 Timer I/O Control Register 1 (TIOR1)

TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and

FTIOD pins.

Initial

Bit

Bit Name Value

R/W

Description

7



1

0



Reserved

This bit is always read as 1.

I/O Control D2

6

IOD2

R/W

Selects the GRD function.

0: GRD functions as an output compare register

1: GRD functions as an input capture register

When GRB buffer operation has been selected by

BUFEB in TMRW, select the same function as GRB.

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Section 12 Timer W

Initial

Bit Name Value

Bit

5

R/W

Description

IOD1

IOD0

0

I/O Control D1 and D0

4

When IOD2 = 0,

00: No output at compare match

01: 0 output to the FTIOD pin at GRD compare match

10: 1 output to the FTIOD pin at GRD compare match

11: Output toggles to the FTIOD pin at GRD compare

match

When IOD2 = 1,

00: Input capture at rising edge at the FTIOD pin

01: Input capture at falling edge at the FTIOD pin

1X: Input capture at rising and falling edges at the FTIOD

3

2



1

0



Reserved

This bit is always read as 1.

I/O Control C2

IOC2

R/W

Selects the GRC function.

0: GRC functions as an output compare register

1: GRC functions as an input capture register

When GRA buffer operation has been selected by

BUFEA in TMRW, select the same function as GRA.

1

0

IOC1

IOC0

0

R/W

I/O Control C1 and C0

When IOC2 = 0,

00: No output at compare match

01: 0 output to the FTIOC pin at GRC compare match

10: 1 output to the FTIOC pin at GRC compare match

11: Output toggles to the FTIOC pin at GRC compare

match

When IOC2 = 1,

00: Input capture to GRC at rising edge of the FTIOC pin

01: Input capture to GRC at falling edge of the FTIOC pin

1X: Input capture to GRC at rising and falling edges of

the FTIOC pin

[Legend]

X:

Don't care

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Section 12 Timer W

12.3.7 Timer Counter (TCNT)

TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to

CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting

the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF

flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is

generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.

TCNT is initialized to H'0000 by a reset.

12.3.8 General Registers A to D (GRA to GRD)

Each general register is a 16-bit readable/writable register that can function as either an output-

compare register or an input-capture register. The function is selected by settings in TIOR0 and

TIOR1.

When a general register is used as an input-compare register, its value is constantly compared with

the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA,

IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when

IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR.

When a general register is used as an input-capture register, an external input-capture signal is

detected and the current TCNT value is stored in the general register. The corresponding flag

(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit

(IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is

generated. The edge of the input-capture signal is selected in TIOR.

GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA

and BUFEB in TMRW.

For example, when GRA is set as an output-compare register and GRC is set as the buffer register

for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is

generated.

When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the

value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to

GRA whenever an input capture is generated.

GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are

initialized to H'FFFF by a reset.

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Section 12 Timer W

12.4

Operation

The timer W has the following operating modes.

•

Normal Operation

PWM Operation

12.4.1 Normal Operation

TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free-

running counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count.

When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE

in TIERW is set to 1, an interrupt request is generated. Figure 12.2 shows free-running counting.

TCNT value

H'FFFF

H'0000

CTS bit

Time

Flag cleared

by software

OVF

Figure 12.2 Free-Running Counter Operation

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Section 12 Timer W

Periodic counting operation can be performed when GRA is set as an output compare register and

bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the

IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt

request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic

counting.

TCNT value

GRA

H'0000

CTS bit

Time

Flag cleared

by software

IMFA

Figure 12.3 Periodic Counter Operation

By setting a general register as an output compare register, compare match A, B, C, or D can

cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle.

Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1

output is selected for compare match A, and 0 output is selected for compare match B. When

signal is already at the selected output level, the signal level does not change at compare match.

TCNT value

H'FFFF

GRA

GRB

Time

No change

H'0000

FTIOA

FTIOB

No change

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)

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Section 12 Timer W

Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter,

and toggle output is selected for both compare match A and B.

TCNT value

H'FFFF

GRA

GRB

Time

H'0000

FTIOA

FTIOB

Toggle output

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)

Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter,

cleared by compare match A. Toggle output is selected for both compare match A and B.

TCNT value

Counter cleared by compare match with GRA

H'FFFF

GRA

GRB

Time

H'0000

FTIOA

Toggle

output

Toggle

output

FTIOB

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)

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Section 12 Timer W

The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a

signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can

take place on the rising edge, falling edge, or both edges. By using the input-capture function, the

pulse width and periods can be measured. Figure 12.7 shows an example of input capture when

both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates

as a free-running counter.

TCNT value

H'FFFF

H'F000

H'AA55

H'55AA

H'1000

H'0000

Time

FTIOA

GRA

H'1000

H'F000

H'55AA

FTIOB

GRB

H'AA55

Figure 12.7 Input Capture Operating Example

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Section 12 Timer W

Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture

register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter,

and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation,

the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.

TCNT value

H'FFFF

H'DA91

H'5480

H'0245

H'0000

Time

FTIOA

H'0245

H'5480

H'0245

H'DA91

H'5480

GRA

GRC

Figure 12.8 Buffer Operation Example (Input Capture)

12.4.2 PWM Operation

In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,

GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and

FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register

functions as an output compare register automatically. The output level of each pin depends on the

corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the

FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the

FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare

match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode.

If the same value is set in the cycle register and the duty register, the output does not change when

a compare match occurs.

Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT

is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D

(TOB, TOC, and TOD = 1: initial output values are set to 1).

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Section 12 Timer W

TCNT value

Counter cleared by compare match A

GRA

GRB

GRC

GRD

H'0000

Time

FTIOB

FTIOC

FTIOD

Figure 12.9 PWM Mode Example (1)

Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and

TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and

D (TOB, TOC, and TOD = 0: initial output values are set to 1).

TCNT value

Counter cleared by compare match A

GRA

GRB

GRC

GRD

H'0000

Time

FTIOB

FTIOC

FTIOD

Figure 12.10 PWM Mode Example (2)

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Section 12 Timer W

Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and

GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB

outputs 1 at compare match B and 0 at compare match A.

Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD

is transferred to GRB whenever compare match B occurs. This procedure is repeated every time

compare match B occurs.

TCNT value

GRA

H'0520

H'0450

H'0200

GRB

Time

H'0000

GRD

H'0200

H'0450

H'0520

H'0200

H'0450

H'0520

GRB

FTIOB

Figure 12.11 Buffer Operation Example (Output Compare)

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Section 12 Timer W

Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0%

and 100%.

TCNT value

Write to GRB

GRA

GRB

Write to GRB

H'0000

Time

Duty 0%

FTIOB

Output does not change when cycle register

and duty register compare matches occur

simultaneously.

TCNT value

Write to GRB

GRA

Write to GRB

Duty 100%

GRB

H'0000

Time

FTIOB

Output does not change when cycle register

and duty register compare matches occur

simultaneously.

TCNT value

Write to GRB

GRA

Write to GRB

Time

GRB

H'0000

Duty 100%

Duty 0%

FTIOB

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: Initial Output Values are Set to 0)

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Section 12 Timer W

TCNT value

GRA

Write to GRB

GRB

Write to GRB

H'0000

Time

Duty 100%

FTIOB

Output does not change when cycle register

and duty register compare matches occur

simultaneously.

TCNT value

Write to GRB

GRA

Write to GRB

Duty 0%

GRB

H'0000

Time

FTIOB

Output does not change when cycle register

and duty register compare matches occur

simultaneously.

TCNT value

Write to GRB

GRA

Write to GRB

Time

GRB

H'0000

Duty 0%

Duty 100%

FTIOB

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: Initial Output Values are Set to 1)

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Section 12 Timer W

12.5

Operation Timing

12.5.1 TCNT Count Timing

Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure

12.15 shows the timing when the external clock source is selected. The pulse width of the external

clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted

correctly.

φ

Internal

clock

Rising edge

TCNT input

clock

TCNT

N

N+1

N+2

Figure 12.14 Count Timing for Internal Clock Source

φ

External

clock

Rising edge

TCNT input

clock

TCNT

N

N+1

N+2

Figure 12.15 Count Timing for External Clock Source

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Section 12 Timer W

12.5.2 Output Compare Output Timing

The compare match signal is generated in the last state in which TCNT and GR match (when

TCNT changes from the matching value to the next value). When the compare match signal is

generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,

FTIOB, FTIOC, or FTIOD).

When TCNT matches GR, the compare match signal is generated only after the next counter clock

pulse is input.

Figure 12.16 shows the output compare timing.

φ

TCNT input

clock

N

N+1

TCNT

GRA to GRD

Compare

match signal

FTIOA to FTIOD

Figure 12.16 Output Compare Output Timing

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Section 12 Timer W

12.5.3 Input Capture Timing

Input capture on the rising edge, falling edge, or both edges can be selected through settings in

TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse

width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will

not be detected correctly.

φ

Input capture

input

Input capture

signal

N–1

N

N+1

N

N+2

TCNT

GRA to GRD

Figure 12.17 Input Capture Input Signal Timing

12.5.4 Timing of Counter Clearing by Compare Match

Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA

value is N, the counter counts from 0 to N, and its cycle is N + 1.

φ

Compare

match signal

N

H'0000

TCNT

GRA

Figure 12.18 Timing of Counter Clearing by Compare Match

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Section 12 Timer W

12.5.5 Buffer Operation Timing

Figures 12.19 and 12.20 show the buffer operation timing.

φ

Compare

match signal

N

N+1

TCNT

M

GRC, GRD

GRA, GRB

M

Figure 12.19 Buffer Operation Timing (Compare Match)

φ

Input capture

signal

N

N+1

TCNT

GRA, GRB

M

N

N+1

N

GRC, GRD

M

Figure 12.20 Buffer Operation Timing (Input Capture)

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Section 12 Timer W

12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match

If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the

corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general

register.

The compare match signal is generated in the last state in which the values match (when TCNT is

updated from the matching count to the next count). Therefore, when TCNT matches a general

register, the compare match signal is generated only after the next TCNT clock pulse is input.

Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match.

φ

TCNT input

clock

TCNT

N

N+1

GRA to GRD

Compare

match signal

IMFA to IMFD

IRRTW

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match

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Section 12 Timer W

12.5.7 Timing of IMFA to IMFD Setting at Input Capture

If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the

corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure

12.22 shows the timing of the IMFA to IMFD flag setting at input capture.

φ

Input capture

signal

TCNT

N

GRA to GRD

IMFA to IMFD

IRRTW

N

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture

12.5.8 Timing of Status Flag Clearing

When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag

is cleared. Figure 12.23 shows the status flag clearing timing.

TSRW write cycle

T1

T2

φ

TSRW address

Address

Write signal

IMFA to IMFD

IRRTW

Figure 12.23 Timing of Status Flag Clearing by CPU

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Section 12 Timer W

12.6

Usage Notes

The following types of contention or operation can occur in timer W operation.

1. The pulse width of the input clock signal and the input capture signal must be at least two

system clock (φ) cycles; shorter pulses will not be detected correctly.

2. Writing to registers is performed in the T2 state of a TCNT write cycle.

If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter

takes priority and the write is not performed, as shown in figure 12.24. If counting-up is

generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes

precedence.

3. Depending on the timing, TCNT may be incremented by a switch between different internal

clock sources. When TCNT is internally clocked, an increment pulse is generated from the

rising edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown in

figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen

as a rising edge, causing TCNT to increment.

4. If timer W enters module standby mode while an interrupt request is generated, the interrupt

request cannot be cleared. Before entering module standby mode, disable interrupt requests.

5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the

first compare match occurs. Once a compare match occurs and this compare match changes the

values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the

values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and

the generation of the compare match A to D occur at the same timing, the writing to TCRW

has the priority. Thus, output change due to the compare match is not reflected to the FTIOA

to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the

values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is

to be written to while compare match is operating, stop the counter once before accessing to

TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD,

and then restart the counter. Figure 12.26 shows an example when the compare match and the

bit manipulation instruction to TCRW occur at the same timing.

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Section 12 Timer W

TCNT write cycle

T1 T2

φ

TCNT address

Address

Write signal

Counter clear

signal

N

H'0000

TCNT

Figure 12.24 Contention between TCNT Write and Clear

Clock before switching

Clock after switching

Count clock

N

N+1

N+2

N+3

TCNT

The change in signal level at clock switching is

assumed to be a rising edge, and TCNT

increments the count.

Figure 12.25 Internal Clock Switching and TCNT Operation

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Section 12 Timer W

TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state,

and is set to the toggle output or the 0 output by compare match B.

When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs

at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low;

the FTIOB signal remains high.

7

6

5

4

3

2

1

0

Bit

TCRW

Set value

CCLR

0

CKS2

0

CKS1

0

CKS0

0

TOD

0

TOC

1

TOB

1

TOA

0

BCLR#2, @TCRW

(1) TCRW read operation: Read H'06

(2) Modify operation: Modify H'06 to H'02

(3) Write operation to TCRW: Write H'02

φ

TCRW

write signal

Compare match

signal B

FTIOB pin

Expected output

Remains high because the 1 writing to TOB has priority

Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW

Occur at the Same Timing

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Section 12 Timer W

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Section 13 Watchdog Timer

The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a

system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.

The block diagram of the watchdog timer is shown in figure 13.1.

CLK

PSS

WDT dedicated

internal oscillator

TCSRWD

TCWD

φ

TMWD

[Legend]

Internal reset

signal

TCSRWD: Timer control/status register WD

TCWD:

PSS:

Timer counter WD

Prescaler S

TMWD:

Timer mode register WD

Figure 13.1 Block Diagram of Watchdog Timer

13.1

Features

•

Selectable from nine counter input clocks.

Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the

WDT dedicated internal oscillator can be selected as the timer-counter clock. When the WDT

dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating

mode.

•

Reset signal generated on counter overflow

An overflow period of 1 to 256 times the selected clock can be set.

The watchdog timer is enabled in the initial state.

It starts operating after the reset state is canceled.

WDT0110A_000020030300

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Section 13 Watchdog Timer

13.2

Register Descriptions

The watchdog timer has the following registers.

•

Timer control/status register WD (TCSRWD)

Timer counter WD (TCWD)

Timer mode register WD (TMWD)

13.2.1 Timer Control/Status Register WD (TCSRWD)

TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the

watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using

the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.

Initial

Bit

Bit Name Value

R/W

Description

7

B6WI

1

R/W

Bit 6 Write Inhibit

The TCWE bit can be written only when the write value of

the B6WI bit is 0.

This bit is always read as 1.

6

TCWE

0

R/W

Timer Counter WD Write Enable

TCWD can be written when the TCWE bit is set to 1.

When writing data to this bit, the value for bit 7 must be 0.

Bit 4 Write Inhibit

5

4

B4WI

1

0

R/W

The TCSRWE bit can be written only when the write

value of the B4WI bit is 0. This bit is always read as 1.

TCSRWE

Timer Control/Status Register WD Write Enable

The WDON and WRST bits can be written when the

TCSRWE bit is set to 1.

When writing data to this bit, the value for bit 5 must be 0.

Bit 2 Write Inhibit

3

B2WI

1

R/W

This bit can be written to the WDON bit only when the

write value of the B2WI bit is 0.

This bit is always read as 1.

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Section 13 Watchdog Timer

Initial

Bit

Bit Name Value

R/W

Description

2

WDON

1

R/W

Watchdog Timer On

TCWD starts counting up when the WDON bit is set to 1

and halts when the WDON bit is cleared to 0. The

watchdog timer is enabled in the initial state. When the

watchdog timer is not used, clear the WDON bit to 0.

[Setting conditions]

•

Reset

When 1 is written to the WDON bit and 0 is written to

the B2WI bit while the TCSRWE bit = 1

[Clearing conditions]

•

When 0 is written to the WDON bit and 0 is written to

the B2WI bit while the TCSRWE bit = 1

1

0

B0WI

1

0

R/W

Bit 0 Write Inhibit

This bit can be written to the WRST bit only when the

write value of the B0WI bit is 0. This bit is always read as

1.

WRST*

Watchdog Timer Reset

[Setting condition]

•

When TCWD overflows and an internal reset signal is

generated

[Clearing conditions]

•

Reset by the RES pin

When 0 is written to the WRST bit and 0 is written to

the B0WI bit while the TCSRWE bit = 1

Note:

*

The WRST bit cannot be modified to 1.

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Section 13 Watchdog Timer

13.2.2 Timer Counter WD (TCWD)

TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the

internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to

H'00.

13.2.3 Timer Mode Register WD (TMWD)

TMWD selects the input clock.

Initial

Bit

Bit Name Value

R/W

Description

7 to 4



All 1



Reserved

These bits are always read as 1.

Clock Select 3 to 0

3

2

1

0

CKS3

CKS2

CKS1

CKS0

1

R/W

Select the clock to be input to TCWD.

1000: Internal clock: counts on φ/64

1001: Internal clock: counts on φ/128

1010: Internal clock: counts on φ/256

1011: Internal clock: counts on φ/512

1100: Internal clock: counts on φ/1024

1101: Internal clock: counts on φ/2048

1110: Internal clock: counts on φ/4096

1111: Internal clock: counts on φ8192

0XXX: WDT dedicated internal oscillator

For the overflow periods of the WDT dedicated internal

oscillator, see section 20, Electrical Characteristics.

[Legend]

X:

Don't care

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Section 13 Watchdog Timer

13.3

Operation

The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD

starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is

generated. The internal reset signal is output for a period of 256 φ_RCclock cycles. As TCWD is a

writable counter, it starts counting from the value set in TCWD. An overflow period in the range

of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the

watchdog timer is not used, stop TCWD counting by writing 0 to B2WI and WDON

simultaneously while the TCSRWE bit in TCSRWD is set to 1. (To stop the watchdog timer, two

write accesses to TCSRWD are required.)

Figure 13.2 shows an example of watchdog timer operation.

Example: With 30ms overflow period when φ = 4 MHz

4 × 10⁶

8192

× 30 × 10^–3= 14.6

Therefore, 256 – 15 = 241 (H'F1) is set in TCW.

TCWD overflow

H'FF

H'F1

TCWD

count value

H'00

H'F1 written H'F1 written to TCWD

to TCWD

Reset generated

Internal reset

signal

256 φ_RCclock cycles

Figure 13.2 Watchdog Timer Operation Example

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Section 13 Watchdog Timer

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Section 14 Serial Communication Interface 3 (SCI3)

This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous

and clocked synchronous serial communication. In asynchronous mode, serial data

communication can be carried out using standard asynchronous communication chips such as a

Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication

Interface Adapter (ACIA). A function is also provided for serial communication between

processors (multiprocessor communication function).

Figure 14.1 is a block diagram of SCI3.

14.1

Features

•

Choice of asynchronous or clocked synchronous serial communication mode

Full-duplex communication capability

The transmitter and receiver are mutually independent, enabling transmission and reception to

be executed simultaneously.

Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data.

•

On-chip baud rate generator allows any bit rate to be selected

External clock or on-chip baud rate generator can be selected as a transfer clock source.

Six interrupt sources

Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity

error.

•

Internal noise filter circuit (available for asynchronous serial communication only)

Asynchronous mode

•

Data length: 7 or 8 bits

Stop bit length: 1 or 2 bits

Parity: Even, odd, or none

Receive error detection: Parity, overrun, and framing errors

Break detection: Break can be detected by reading the RXD pin level directly in the case of a

framing error

SCI0010A_000120030300

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Section 14 Serial Communication Interface 3 (SCI3)

Clocked synchronous mode

•

Data length: 8 bits

Receive error detection: Overrun errors

External

SCK3

Internal clock (φ/64,φ/16, φ/4, φ)

clock

Baud rate

generator

BRC

BRR

Clock

SMR

SCR3

SSR

Transmit/receive

control circuit

SPMR

TXD

RXD

TSR

RSR

TDR

RDR

Noise

filter circuit

Interrupt request

(TEI, TXI, RXI, ERI)

[Legend]

RSR:

RDR:

TSR:

TDR:

SMR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

SCR3: Serial control register 3

SSR:

BRR:

BRC:

Serial status register

Bit rate register

Bit rate counter

SPMR: Sampling mode register

Figure 14.1 Block Diagram of SCI3

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Section 14 Serial Communication Interface 3 (SCI3)

14.2

Input/Output Pins

Table 14.1 shows the SCI3 pin configuration.

Table 14.1 Pin Configuration

Pin Name

Abbreviation

SCK3

I/O

Function

SCI3 clock

Input/output

Input

SCI3 clock input/output

SCI3 receive data input

SCI3 transmit data output

SCI3 receive data input

RXD

SCI3 transmit data output TXD

Output

14.3

Register Descriptions

SCI3 has the following registers for each channel.

•

Receive shift register (RSR)

Receive data register (RDR)

Transmit shift register (TSR)

Transmit data register (TDR)

Serial mode register (SMR)

Serial control register 3 (SCR3)

Serial status register (SSR)

Bit rate register (BRR)

Sampling mode register (SPMR)

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Section 14 Serial Communication Interface 3 (SCI3)

14.3.1 Receive Shift Register (RSR)

RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into

parallel data. When one frame of data has been received, it is transferred to RDR automatically.

RSR cannot be directly accessed by the CPU.

14.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores received data. When SCI3 has received one frame of serial

data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is

receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive

operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only

once. RDR cannot be written to by the CPU. RDR is initialized to H'00.

14.3.3 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, SCI3 first

transfers transmit data from TDR to TSR automatically, then sends the data that starts from the

LSB to the TXD pin. TSR cannot be directly accessed by the CPU.

14.3.4 Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for transmission. When SCI3 detects that TSR is empty, it

transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered

structure of TDR and TSR enables continuous serial transmission. If the next transmit data has

already been written to TDR during transmission of one-frame data, SCI3 transfers the written

data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data

to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to

H'FF.

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Section 14 Serial Communication Interface 3 (SCI3)

14.3.5 Serial Mode Register (SMR)

SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock

source.

Initial

Bit

Bit Name Value

R/W

Description

7

COM

CHR

PE

0

R/W

Communication Mode

0: Asynchronous mode

1: Clocked synchronous mode

Character Length (enabled only in asynchronous mode)

0: Selects 8 bits as the data length.

1: Selects 7 bits as the data length.

Parity Enable (enabled only in asynchronous mode)

6

5

R/W

When this bit is set to 1, the parity bit is added to transmit

data before transmission, and the parity bit is checked in

reception.

4

3

PM

0

R/W

Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity.

1: Selects odd parity.

STOP

Stop Bit Length (enabled only in asynchronous mode)

Selects the stop bit length in transmission.

0: 1 stop bit

1: 2 stop bits

For reception, only the first stop bit is checked, regardless

of the value in the bit. If the second stop bit is 0, it is

treated as the start bit of the next transmit character.

2

MP

0

R/W

Multiprocessor Mode

When this bit is set to 1, the multiprocessor

communication function is enabled. The PE bit and PM

bit settings are invalid in multiprocessor mode. In clocked

synchronous mode, clear this bit to 0.

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Section 14 Serial Communication Interface 3 (SCI3)

Initial

Bit

1

Bit Name Value

R/W

Description

CKS1

CKS0

0

Clock Select 0 and 1

0

These bits select the clock source for the baud rate

generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relationship between the bit rate register setting

and the baud rate, see section 14.3.8, Bit Rate Register

(BRR). n is the decimal representation of the value of n in

BRR (see section 14.3.8, Bit Rate Register (BRR)).

14.3.6 Serial Control Register 3 (SCR3)

SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is

also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,

Interrupts.

Initial

Bit

Bit Name Value

R/W

Description

7

TIE

0

R/W

Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request is

enabled.

6

RIE

0

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

5

4

TE

RE

0

R/W

Transmit Enable

When this bit s set to 1, transmission is enabled.

Receive Enable

When this bit is set to 1, reception is enabled.

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Section 14 Serial Communication Interface 3 (SCI3)

Initial

Bit

Bit Name Value

R/W

Description

3

MPIE

0

R/W

Multiprocessor Interrupt Enable (enabled only when the

MP bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and OER status flags in SSR is disabled.

On receiving data in which the multiprocessor bit is 1, this

bit is automatically cleared and normal reception is

resumed. For details, refer to section 14.6, Multiprocessor

Communication Function.

2

TEIE

0

R/W

Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is enabled.

Clock Enable 0 and 1

1

0

CKE1

CKE0

0

R/W

Selects the clock source.

•

Asynchronous mode

00: On-chip baud rate generator

01: On-chip baud rate generator

Outputs a clock of the same frequency as the bit rate

from the SCK3 pin.

10: External clock

Inputs a clock with a frequency 16 times the bit rate

from the SCK3 pin.

11:Reserved

•

Clocked synchronous mode

00: On-chip clock (SCK3 pin functions as clock output)

01:Reserved

10: External clock (SCK3 pin functions as clock input)

11:Reserved

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Section 14 Serial Communication Interface 3 (SCI3)

14.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be

written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.

Initial

Bit

Bit Name Value

R/W

Description

7

TDRE 1

R/W

Transmit Data Register Empty

Indicates whether TDR contains transmit data.

[Setting conditions]

•

When the TE bit in SCR3 is 0

When data is transferred from TDR to TSR

[Clearing conditions]

•

When 0 is written to TDRE after reading TDRE = 1

When the transmit data is written to TDR

6

RDRF

0

R/W

Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

•

When serial reception ends normally and receive data

is transferred from RSR to RDR

[Clearing conditions]

•

When 0 is written to RDRF after reading RDRF = 1

When data is read from RDR

5

4

OER

FER

0

R/W

Overrun Error

[Setting condition]

•

When an overrun error occurs in reception

[Clearing condition]

When 0 is written to OER after reading OER = 1

•

Framing Error

[Setting condition]

•

When a framing error occurs in reception

[Clearing condition]

When 0 is written to FER after reading FER = 1

•

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Section 14 Serial Communication Interface 3 (SCI3)

Initial

Bit

Bit Name Value

R/W

Description

3

PER

0

R/W

Parity Error

[Setting condition]

•

When a parity error is detected during reception

[Clearing condition]

When 0 is written to PER after reading PER = 1

•

2

TEND

1

R

Transmit End

[Setting conditions]

•

When the TE bit in SCR3 is 0

When TDRE = 1 at transmission of the last bit of a 1-

frame serial transmit character

[Clearing conditions]

•

When 0 is written to TDRE after reading TDRE = 1

When the transmit data is written to TDR

1

0

MPBR

MPBT

0

R

Multiprocessor Bit Receive

MPBR stores the multiprocessor bit in the receive

character data. When the RE bit in SCR3 is cleared to 0,

its state is retained.

R/W

Multiprocessor Bit Transfer

MPBT stores the multiprocessor bit to be added to the

transmit character data.

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Section 14 Serial Communication Interface 3 (SCI3)

14.3.8 Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2

shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of

SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in

asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (high-

speed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in

bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 14.5 are

values in active (high-speed) mode. The N setting in BRR and error for other operating

frequencies and bit rates can be obtained by the following formulas:

[Asynchronous Mode]

φ

× 10⁶– 1

N =

64 × 2^2n–1× B

φ × 10⁶

(N + 1) × B × 64 × 2^2n–1











Error (%) =

– 1 × 100



[Clocked Synchronous Mode]

φ

× 10⁶– 1

N =

8 × 2^2n–1× B

Legend B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

φ: Operating frequency (MHz)

n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)

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Section 14 Serial Communication Interface 3 (SCI3)

Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)

Operating Frequency φ (MHz)

2

2.097152

Error

(%)

2.4576

Error

(%)

3

Bit Rate

(bits/s)

Error

(%)

Error

(%)

n

1

0

N

n

1

0

N

n

1

0

N

n

1

0

—

N

110

141 0.03

103 0.16

207 0.16

103 0.16

148 –0.04

108 0.21

217 0.21

108 0.21

174 –0.26

127 0.00

255 0.00

127 0.00

212 0.03

155 0.16

150

300

77

0.16

600

155 0.16

1200

2400

4800

9600

19200

31250

38400

51

25

12

6

0.16

54

26

13

6

–0.70

1.14

63

31

15

7

0.00

22.88

0.00

77

38

19

9

0.16

–2.34

0.00

—

0.16

–2.48

13.78

4.86

–6.99

8.51

2

3

4

1

0.00

1

2

1

–18.62

1

–14.67

1

—

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Section 14 Serial Communication Interface 3 (SCI3)

Operating Frequency φ (MHz)

4.9152

Error

3.6864

Error

4

5

Bit Rate

(bits/s)

Error

(%)

Error

(%)

n

2

1

0

—

0

N

(%)

n

2

1

0

N

n

2

1

0

N

(%)

n

2

1

0

N

110

64

0.70

70

0.03

86

0.31

88

64

–0.25

0.16

150

191 0.00

95 0.00

191 0.00

207 0.16

103 0.16

207 0.16

103 0.16

255 0.00

127 0.00

255 0.00

127 0.00

300

129 0.16

64 0.16

129 0.16

600

1200

2400

4800

9600

19200

31250

38400

[Legend]

95

47

23

11

5

0.00

—

51

25

12

6

0.16

–6.99

0.00

8.51

63

31

15

7

0.00

–1.70

0.00

64

32

15

7

0.16

–1.36

1.73

0.00

1.73

—

2

3

4

0.00

2

3

:

A setting is available but error occurs

Operating Frequency φ (MHz)

6

6.144

7.3728

Bit Rate

(bit/s)

Error

(%)

Error

(%)

Error

(%)

n

2

1

0

N

n

2

1

0

N

n

2

1

0

N

110

106

77

155

77

155

77

38

19

9

–0.44

0.16

108

79

159

79

159

79

39

19

9

0.08

0.00

2.40

0.00

130

95

191

95

191

95

47

23

11

6

–0.07

0.00

5.33

0.00

150

300

0.16

600

0.16

1200

2400

4800

9600

19200

31250

38400

0.16

–2.34

0.00

5

4

–2.34

4

5

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Section 14 Serial Communication Interface 3 (SCI3)

Operating Frequency φ (MHz)

9.8304

Error (%)

8

10

Bit Rate

(bit/s)

n

2

1

0

N

Error (%)

0.03

n

2

1

0

N

n

2

1

0

N

Error (%)

110

141

103

207

103

207

103

51

174 –0.26

127 0.00

255 0.00

127 0.00

255 0.00

127 0.00

177 –0.25

129 0.16

150

0.16

300

0.16

64

129 0.16

64 0.16

129 0.16

0.16

600

0.16

1200

2400

4800

9600

19200

31250

38400

0.16

63

31

15

9

0.00

–1.70

0.00

64

32

15

9

0.16

–1.36

1.73

0.00

1.73

25

0.16

12

0.16

7

0.00

6

-6.99

7

Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

Maximum Bit

φ (MHz) Rate (bit/s)

Maximum Bit

Rate (bit/s)

n

0

N

0

φ (MHz)

5

n

N

0

2

62500

156250

187500

192000

230400

250000

307200

312500

0

2.097152 65536

6

2.4576

3

76800

6.144

7.3728

8

93750

3.6864

4

115200

125000

153600

9.8304

10

4.9152

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Section 14 Serial Communication Interface 3 (SCI3)

Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Operating Frequency φ (MHz)

2

4

8

10

Bit Rate

(bit/s)

n

3

2

1

0

N

n

—

2

1

0

N

n

—

3

2

1

0

N

n

N

110

250

500

1k

70

124

249

124

199

99

49

19

9

—

1

—

249

124

249

99

49

24

9

249

124

249

99

199

99

39

19

9

124

249

124

199

99

199

79

39

19

7

2.5k

5k

1

10k

0

25k

0

50k

0

100k

250k

500k

1M

4

0

1

3

0

0*

1

3

0

4

0*

1

—

0

—

0*

2M

0*

2.5M

4M

[Legend]

Blank: No setting is available.

—:

A setting is available but error occurs.

Continuous transfer is not possible.

*:

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Section 14 Serial Communication Interface 3 (SCI3)

14.3.9 Sampling Mode Register (SPMR)

SPMR controls the serial communication function.

Initial

Bit

Bit Name

Value

R/W

Description

7 to 3



All 1



Reserved

These bits are always read as 1.

Noise Filter Function Select

2

STDSPM

1

R/W

Selects the noise filter function for the RXD pin in

asynchronous mode.

0: Noise filter circuit is enabled

1: Noise filter circuit is disabled

Reserved

1, 0



All 1



These bits are always read as 1.

•

Noise Filter Circuit

The RXD input signal is latched through the noise filter circuit. The noise filter circuit

comprises a series of three latch circuits and a match detection circuit. The RXD input signal is

sampled by the basic clock with the 16 times the transfer clock frequency. If three latch

outputs match, its level is transferred to the next stage. If not, the circuit holds the previous

value.

That is, when the incoming signal holds the same level for three clock cycles, it is regarded as

the proper signal. If the levels of the signal is less than three clock cycles, the signal is

regarded as a noise.

Sampling clock

C

Internal RXD

signal shown

in figure 14.1

Match

detection

circuit

SPMR

(STDSPM)

D

Q

D

Q

D

Q

RXD input signal

Latch

Internal basic clock cycle

Sampling clock

Figure 14.2 Block Diagram of Noise Filter Circuit

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Section 14 Serial Communication Interface 3 (SCI3)

14.4

Operation in Asynchronous Mode

Figure 14.3 shows the general format for asynchronous serial communication. One character (or

frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or

low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are

independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-

buffered structure, so data can be read or written during transmission or reception, enabling

continuous data transfer.

LSB

MSB

1

Serial

data

Parity

bit

Start

bit

Mark state

Transmit/receive data

7 or 8 bits

Stop bit

1 bit

1 bit,

1 or

or none

2 bits

One unit of transfer data (character or frame)

Figure 14.3 Data Format in Asynchronous Communication

14.4.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK3 pin can be selected as the SCI3’s serial clock, according to the setting of the COM bit in

SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the

clock frequency should be 16 times the bit rate used.

When SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4.

Clock

1

0

D0 D1 D2 D3 D4 D5 D6 D7 0/1

1 character (frame)

Serial data

Figure 14.4 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)

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Section 14 Serial Communication Interface 3 (SCI3)

14.4.2 SCI3 Initialization

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0,

then initialize SCI3 as described below. When the operating mode, or transfer format, is changed

for example, the TE and RE bits must be cleared to 0 before making the change using the

following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing

the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the

contents of RDR. When the external clock is used in asynchronous mode, the clock must be

supplied even during initialization.

[1] Set the clock selection in SCR3.

Be sure to clear bits RIE, TIE, TEIE, and

MPIE, and bits TE and RE, to 0.

Start initialization

When the clock output is selected in

asynchronous mode, clock is output

immediately after CKE1 and CKE0

settings are made. When the clock

output is selected at reception in clocked

synchronous mode, clock is output

immediately after CKE1, CKE0, and RE

are set to 1.

Clear TE and RE bits in SCR3 to 0

Set CKE1 and CKE0 bits in SCR3

Set data transfer format in SMR

[1]

[2]

[3]

[2] Set the data transfer format in SMR.

Set value in BRR

Wait

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

No

1-bit interval elapsed?

Yes

[4] Wait at least one bit interval, then set the

TE bit or RE bit in SCR3 to 1. RE

settings enable the RXD pin to be used.

For transmission, set the TXD bit in

PMR1 to 1 to enable the TXD output pin

to be used. Also set the RIE, TIE, TEIE,

and MPIE bits, depending on whether

interrupts are required. In asynchronous

mode, the bits are marked at

Set TE and RE bits in

SCR3 to 1, and set RIE, TIE, TEIE,

and MPIE bits. For transmit (TE=1),

also set the TxD bit in PMR1.

[4]

transmission and idled at reception to

wait for the start bit.

For transmission, set the TE bit to 1 and

then output 1 for one frame to enable.

Figure 14.5 Sample SCI3 Initialization Flowchart

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Section 14 Serial Communication Interface 3 (SCI3)

14.4.3 Data Transmission

Figure 14.6 shows an example of operation for transmission in asynchronous mode. In

transmission, SCI3 operates as described below.

1. SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, SCI3 recognizes that data has

been written to TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, SCI3 sets the TDRE flag to 1 and starts

transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.

Continuous transmission is possible because the TXI interrupt routine writes next transmit data

to TDR before transmission of the current transmit data has been completed.

3. SCI3 checks the TDRE flag at the timing for sending the stop bit.

4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then

serial transmission of the next frame is started.

5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark

state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI

interrupt request is generated.

6. Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.

Start

bit

Transmit

data

Parity Stop Start

Transmit

data

Parity Stop

Mark

state

bit

bit bit

bit

Serial

data

1

0

D0 D1

D7 0/1

1

0

D0 D1

1 frame

D7 0/1

1

1 frame

TDRE

TEND

LSI

TXI interrupt

TDRE flag

cleared to 0

TXI interrupt request generated

TEI interrupt request

generated

operation request

generated

User

processing

Data written

to TDR

Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)

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Section 14 Serial Communication Interface 3 (SCI3)

Start transmission

[1] Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. When data is

written to TDR, the TDRE flag is

automaticaly cleared to 0.

[1]

Read TDRE flag in SSR

[2] To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR. When data

is written to TDR, the TDRE flag is

automaticaly cleared to 0.

No

TDRE = 1

Yes

Write transmit data to TDR

[3] To output a break in serial

transmission, after setting PCR to 1

and PDR to 0, clear TxD in PMR1

to 0, then clear the TE bit in SCR3

to 0.

Yes

[2]

All data transmitted?

No

Read TEND flag in SSR

No

TEND = 1

Yes

[3]

Break output?

Yes

Clear PDR to 0 and

set PCR to 1

Clear TE bit in SCR3 to 0

<End>

Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)

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Section 14 Serial Communication Interface 3 (SCI3)

14.4.4 Serial Data Reception

Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial

reception, SCI3 operates as described below.

1. SCI3 monitors the communication line. If a start bit is detected, SCI3 performs internal

synchronization, receives receive data in RSR, and checks the parity bit and stop bit.

2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an

ERI interrupt request is generated. Receive data is not transferred to RDR.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.

4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive

data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt

request is generated.

5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is

generated. Continuous reception is possible because the RXI interrupt routine reads the receive

data transferred to RDR before reception of the next receive data has been completed.

Start

bit

Receive

data

Parity Stop Start

Receive

data

Parity Stop Mark state

bit

bit bit

bit

(idle state)

Serial

data

1

0

D0 D1

D7 0/1

1

0

D0 D1

1 frame

D7 0/1

0

1

1 frame

RDRF

FER

LSI

operation

RXI request RDRF

cleared to 0

0 stop bit

detected

ERI request in

response to

framing error

User

processing

RDR data read

Framing error

processing

Figure 14.8 Example of SCI3 Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)

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Section 14 Serial Communication Interface 3 (SCI3)

Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error

is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flow chart

for serial data reception.

Table 14.5 SSR Status Flags and Receive Data Handling

SSR Status Flag

RDRF* OER

FER

0

PER

Receive Data

Lost

Receive Error Type

Overrun error

1

0

1

0

1

0

1

0

1

0

1

0

1

Transferred to RDR

Lost

Framing error

0

Parity error

1

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

0

Lost

1

Transferred to RDR

Lost

1

Overrun error + framing error +

parity error

Note:

*

The RDRF flag retains the state it had before data reception.

Rev. 3.00 Sep. 14, 2006 Page 217 of 408

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Section 14 Serial Communication Interface 3 (SCI3)

Start reception

[1] Read the OER, PER, and FER flags in

SSR to identify the error. If a receive

error occurs, performs the appropriate

error processing.

[2] Read SSR and check that RDRF = 1,

then read the receive data in RDR.

The RDRF flag is cleared automatically.

[3] To continue serial reception, before the

stop bit for the current frame is

Read OER, PER, and

[1]

FER flags in SSR

Yes

OER+PER+FER = 1

[4]

received, read the RDRF flag and read

RDR.

No

Error processing

The RDRF flag is cleared automatically.

[4] If a receive error occurs, read the OER,

PER, and FER flags in SSR to identify

the error. After performing the

(Continued on next page)

[2]

Read RDRF flag in SSR

appropriate error processing, ensure

that the OER, PER, and FER flags are

all cleared to 0. Reception cannot be

resumed if any of these flags are set to

1. In the case of a framing error, a

break can be detected by reading the

value of the input port corresponding to

the RxD pin.

No

RDRF = 1

Yes

Read receive data in RDR

Yes

All data received?

No

[3]

(A)

Clear RE bit in SCR3 to 0

<End>

Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)

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Section 14 Serial Communication Interface 3 (SCI3)

14.5

Operation in Clocked Synchronous Mode

Figure 14.10 shows the general format for clocked synchronous communication. In clocked

synchronous mode, data is transmitted or received synchronous with clock pulses. A single

character in the transmit data consists of the 8-bit data starting from the LSB. In clocked

synchronous serial communication, data on the transmission line is output from one falling edge of

the synchronization clock to the next. In clocked synchronous mode, SCI3 receives data in

synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the

transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor

bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-

duplex communication through the use of a common clock. Both the transmitter and the receiver

also have a double-buffered structure, so data can be read or written during transmission or

reception, enabling continuous data transfer.

8-bit

One unit of transfer data (character or frame)

*

Synchronization

clock

LSB

Bit 0

MSB

Bit 7

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Serial data

Don’t care

Note: * High except in continuous transfer

Don’t care

Figure 14.10 Data Format in Clocked Synchronous Communication

14.5.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external

synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM

bit in SMR and CKE0 and CKE1 bits in SCR3. When SCI3 is operated on an internal clock, the

synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are output

in the transfer of one character, and when no transfer is performed the clock is fixed high.

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Section 14 Serial Communication Interface 3 (SCI3)

14.5.2 SCI3 Initialization

Before transmitting and receiving data, SCI3 should be initialized as described in a sample

flowchart in figure 14.5.

14.5.3 Serial Data Transmission

Figure 14.11 shows an example of SCI3 operation for transmission in clocked synchronous mode.

In serial transmission, SCI3 operates as described below.

1. SCI3 monitors the TDRE flag in SSR, and if the flag is 0, SCI3 recognizes that data has been

written to TDR, and transfers the data from TDR to TSR.

2. SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this

time, a transmit data empty interrupt (TXI) is generated.

3. 8-bit data is sent from the TXD pin synchronized with the output clock when output clock

mode has been specified, and synchronized with the input clock when use of an external clock

has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD

pin.

4. SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the

output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt

request is generated.

7. The SCK3 pin is fixed high at the end of transmission.

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Section 14 Serial Communication Interface 3 (SCI3)

Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.

Make sure that the receive error flags are cleared to 0 before starting transmission.

Serial

clock

Serial

data

Bit 0

Bit 1

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

1 frame

TDRE

TEND

LSI

TXI interrupt

TDRE flag

cleared

to 0

TXI interrupt request generated

TEI interrupt request

generated

operation request

generated

User

processing

Data written

to TDR

Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode

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Section 14 Serial Communication Interface 3 (SCI3)

Start transmission

[1] Read SSR and check that the TDRE flag is

set to 1, then write transmit data to TDR.

When data is written to TDR, the TDRE flag

is automatically cleared to 0 and clocks are

output to start the data transmission.

[1]

Read TDRE flag in SSR

[2] To continue serial transmission, be sure to

read 1 from the TDRE flag to confirm that

writing is possible, then write data to TDR.

When data is written to TDR, the TDRE flag

is automatically cleared to 0.

No

TDRE = 1

Yes

Write transmit data to TDR

Yes

All data transmitted?

No

[2]

Read TEND flag in SSR

No

TEND = 1

Yes

Clear TE bit in SCR3 to 0

<End>

Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)

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Section 14 Serial Communication Interface 3 (SCI3)

14.5.4 Serial Data Reception (Clocked Synchronous Mode)

Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In

serial reception, SCI3 operates as described below.

1. SCI3 performs internal initialization synchronous with a synchronization clock input or

output, starts receiving data.

2. SCI3 stores the receive data in RSR.

3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this

time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the

RDRF flag remains to be set to 1.

4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is

generated.

Serial

clock

Serial

data

Bit 7

Bit 0

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

1 frame

RDRF

OER

LSI

RXI interrupt RDRF flag

RXI interrupt request generated

ERI interrupt request

operation

request

generated

cleared

to 0

generated by

overrun error

User

processing

RDR data read

RDR data has

not been read

(RDRF = 1)

Overrun error

processing

Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode

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Section 14 Serial Communication Interface 3 (SCI3)

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.14 shows a sample flow

chart for serial data reception.

Start reception

[1] Read the OER flag in SSR to determine if

there is an error. If an overrun error has

[1]

occurred, execute overrun error processing.

[2] Read SSR and check that the RDRF flag is

set to 1, then read the receive data in RDR.

When data is read from RDR, the RDRF

flag is automatically cleared to 0.

Read OER flag in SSR

Yes

OER = 1

No

[4]

[3] To continue serial reception, before the

MSB (bit 7) of the current frame is received,

reading the RDRF flag and reading RDR

should be finished. When data is read from

RDR, the RDRF flag is automatically

cleared to 0.

Error processing

(Continued below)

Read RDRF flag in SSR

[2]

[4] If an overrun error occurs, read the OER

flag in SSR, and after performing the

appropriate error processing, clear the OER

flag to 0. Reception cannot be resumed if

the OER flag is set to 1.

No

RDRF = 1

Yes

Read receive data in RDR

Yes

All data received?

No

[3]

Clear RE bit in SCR3 to 0

<End>

[4]

Error processing

Overrun error processing

Clear OER flag in SSR to 0

<End>

Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)

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Section 14 Serial Communication Interface 3 (SCI3)

14.5.5 Simultaneous Serial Data Transmission and Reception

Figure 14.15 shows a sample flowchart for simultaneous serial transmit and receive operations.

The following procedure should be used for simultaneous serial data transmit and receive

operations. To switch from transmit mode to simultaneous transmit and receive mode, after

checking that SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE

to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive

mode to simultaneous transmit and receive mode, after checking that SCI3 has finished reception,

clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER)

are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.

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Section 14 Serial Communication Interface 3 (SCI3)

Start transmission/reception

[1] Read SSR and check that the TDRE

flag is set to 1, then write transmit

data to TDR.

When data is written to TDR, the

TDRE flag is automatically cleared to

0.

Read TDRE flag in SSR

[1]

[2] Read SSR and check that the RDRF

flag is set to 1, then read the receive

data in RDR.

No

TDRE = 1

Yes

When data is read from RDR, the

RDRF flag is automatically cleared to

0.

[3] To continue serial transmission/

reception, before the MSB (bit 7) of

the current frame is received, finish

reading the RDRF flag, reading RDR.

Also, before the MSB (bit 7) of the

current frame is transmitted, read 1

from the TDRE flag to confirm that

writing is possible. Then write data to

TDR.

Write transmit data to TDR

Read OER flag in SSR

Yes

OER = 1

No

When data is written to TDR, the

TDRE flag is automatically cleared to

0. When data is read from RDR, the

RDRF flag is automatically cleared to

0.

Read RDRF flag in SSR

[2]

[4] If an overrun error occurs, read the

OER flag in SSR, and after

performing the appropriate error

processing, clear the OER flag to 0.

Transmission/reception cannot be

resumed if the OER flag is set to 1.

For overrun error processing, see

figure 14.14.

No

[4]

RDRF = 1

Yes

Overrun error

processing

Read receive data in RDR

Yes

All data received?

No

[3]

Clear TE and RE bits in SCR to 0

<End>

Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode)

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Section 14 Serial Communication Interface 3 (SCI3)

14.6

Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer between a number of

processors sharing communication lines by asynchronous serial communication using the

multiprocessor format, in which a multiprocessor bit is added to the transfer data. When

multiprocessor communication is performed, each receiving station is addressed by a unique ID

code. The serial communication cycle consists of two component cycles; an ID transmission cycle

that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to

differentiate between the ID transmission cycle and the data transmission cycle. If the

multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the

cycle is a data transmission cycle. Figure 14.16 shows an example of inter-processor

communication using the multiprocessor format. The transmitting station first sends the ID code

of the receiving station with which it wants to perform serial communication as data with a 1

multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.

When data with a 1 multiprocessor bit is received, the receiving station compares that data with its

own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not

match continue to skip data until data with a 1 multiprocessor bit is again received.

SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,

transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,

RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On

reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and

the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is

set to 1 at this time, an RXI interrupt is generated.

When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit

settings are the same as those in normal asynchronous mode. The clock used for multiprocessor

communication is the same as that in normal asynchronous mode.

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Section 14 Serial Communication Interface 3 (SCI3)

Transmitting

station

Serial transmission line

Receiving

station A

Receiving

station B

Receiving

station C

Receiving

station D

(ID = 01)

(ID = 02)

(ID = 03)

(ID = 04)

Serial

data

H'01

H'AA

(MPB = 1)

(MPB = 0)

ID transmission cycle = Data transmission cycle =

receiving station

specification

Data transmission to

receiving station specified by ID

[Legend]

MPB: Multiprocessor bit

Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)

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Section 14 Serial Communication Interface 3 (SCI3)

14.6.1 Multiprocessor Serial Data Transmission

Figure 14.17 shows a sample flowchart for multiprocessor serial data transmission. For an ID

transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission

cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same

as those in asynchronous mode.

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Section 14 Serial Communication Interface 3 (SCI3)

Start transmission

[1] Read SSR and check that the TDRE

flag is set to 1, set the MPBT bit in

SSR to 0 or 1, then write transmit

data to TDR. When data is written to

TDR, the TDRE flag is automatically

cleared to 0.

[1]

Read TDRE flag in SSR

No

TDRE = 1

Yes

[2] To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR. When data is

written to TDR, the TDRE flag is

automatically cleared to 0.

Set MPBT bit in SSR

[3] To output a break in serial

transmission, set the port PCR to 1,

clear PDR to 0, then clear the TE bit

in SCR3 to 0.

Write transmit data to TDR

Yes

[2]

All data transmitted?

No

Read TEND flag in SSR

No

TEND = 1

Yes

Break output?

Yes

[3]

Clear PDR to 0 and set PCR to 1

Clear TE bit in SCR3 to 0

<End>

Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart

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Section 14 Serial Communication Interface 3 (SCI3)

14.6.2 Multiprocessor Serial Data Reception

Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in

SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data

with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is

generated at this time. All other SCI3 operations are the same as those in asynchronous mode.

Figure 14.19 shows an example of SCI3 operation for multiprocessor format reception.

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Section 14 Serial Communication Interface 3 (SCI3)

Start reception

[1] Set the MPIE bit in SCR3 to 1.

[2] Read OER and FER in SSR to check for

errors. Receive error processing is performed

in cases where a receive error occurs.

[3] Read SSR and check that the RDRF flag is

set to 1, then read the receive data in RDR

and compare it with this station’s ID.

If the data is not this station’s ID, set the MPIE

bit to 1 again.

Set MPIE bit in SCR3 to 1

[1]

[2]

Read OER and FER flags in SSR

Yes

FER+OER = 1

When data is read from RDR, the RDRF flag

is automatically cleared to 0.

No

Read RDRF flag in SSR

[3]

[4] Read SSR and check that the RDRF flag is

set to 1, then read the data in RDR.

[5] If a receive error occurs, read the OER and

FER flags in SSR to identify the error. After

performing the appropriate error processing,

ensure that the OER and FER flags are all

cleared to 0.

No

RDRF = 1

Yes

Read receive data in RDR

Reception cannot be resumed if either of

these flags is set to 1.

This station’s ID?

Yes

In the case of a framing error, a break can be

detected by reading the RxD pin value.

Read OER and FER flags in SSR

Yes

FER+OER = 1

No

Read RDRF flag in SSR

[4]

No

[5]

RDRF = 1

Error processing

Yes

(Continued on

next page)

Read receive data in RDR

Yes

All data received?

No

[A]

Clear RE bit in SCR3 to 0

<End>

Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)

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Section 14 Serial Communication Interface 3 (SCI3)

[5]

Error processing

No

OER = 1

Yes

Overrun error processing

No

FER = 1

Yes

Break?

No

[A]

Framing error processing

Clear OER, and

FER flags in SSR to 0

<End>

Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)

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Section 14 Serial Communication Interface 3 (SCI3)

Start

bit

Receive

data (ID1)

Stop Start

bit bit

Receive data

(Data1)

Stop Mark state

bit

(idle state)

MPB

1

MPB

0

Serial

data

1

0

D0 D1

D7

1

0

D0 D1

1 frame

D7

1

1 frame

MPIE

RDRF

RDR

value

ID1

LSI

operation

RXI interrupt

request

MPIE cleared

to 0

RDRF flag

cleared

to 0

RXI interrupt request

is not generated, and

RDR retains its state

User

processing

RDR data read

When data is not

this station's ID,

MPIE is set to 1

again

(a) When data does not match this receiver's ID

Start

bit

Receive

data (ID2)

Stop Start

bit bit

Receive data

(Data2)

Stop Mark state

bit

(idle state)

MPB

1

MPB

0

Serial

data

1

0

D0 D1

D7

1

0

D0 D1

1 frame

D7

1

1 frame

MPIE

RDRF

RDR

value

ID1

ID2

Data2

LSI

operation

RXI interrupt

request

MPIE cleared

to 0

RDRF flag

cleared

to 0

RXI interrupt RDRF flag

request

cleared

to 0

User

processing

RDR data read

When data is

this station's

ID, reception

is continued

RDR data read

MPIE set to 1

again

(b) When data matches this receiver's ID

Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

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Section 14 Serial Communication Interface 3 (SCI3)

14.7

Interrupts

SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive

data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the

interrupt sources.

Table 14.6 SCI3 Interrupt Requests

Interrupt Requests

Receive Data Full

Transmit Data Empty

Transmission End

Receive Error

Abbreviation

Interrupt Sources

RXI

TXI

TEI

ERI

Setting RDRF in SSR

Setting TDRE in SSR

Setting TEND in SSR

Setting OER, FER, and PER in SSR

The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before

transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data

is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is

set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if

the transmit data has not been sent. It is possible to make use of the most of these interrupt

requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent

the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that

correspond to these interrupt requests to 1, after transferring the transmit data to TDR.

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Section 14 Serial Communication Interface 3 (SCI3)

14.8

Usage Notes

14.8.1 Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RXD pin value

directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly

the PER flag. Note that as SCI3 continues the receive operation after receiving a break, even if the

FER flag is cleared to 0, it will be set to 1 again.

14.8.2 Mark State and Break Sending

When the TXD bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction (input or

output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark

state (high level) or send a break during serial data transmission. To maintain the communication

line at mark state until TE is set to 1, set PCR and PDR to 1 respectively, and also set the TXD bit

to 1. At this time, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a

break during serial data transmission, first set PCR to 1 and clear PDR to 0, and then set the TXD

bit to 1. Regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is

output from the TxD pin.

14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

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Section 14 Serial Communication Interface 3 (SCI3)

14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer

rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the

basic clock as shown in figure 14.20. Thus, the reception margin in asynchronous mode is given

by formula (1) below.



1

D – 0.5

N

M = (0.5 –

) –

– (L – 0.5) F × 100(%)



2N



... Formula (1)

Legend N : Ratio of bit rate to clock (N = 16)

D : Clock duty (D = 0.5 to 1.0)

L : Frame length (L = 9 to 12)

F : Absolute value of clock rate deviation

Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in

formula (1), the reception margin can be given by the formula.

M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 20% to 30% should be allowed for in

system design.

16 clocks

8 clocks

0

7

15

0

7

15 0

Internal basic

clock

Receive data

(RxD)

Start bit

D0

D1

Synchronization

sampling timing

Data sampling

timing

Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode

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Section 14 Serial Communication Interface 3 (SCI3)

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Section 15 I²C Bus Interface 2 (IIC2)

The I²C bus interface 2 conforms to and provides a subset of the Philips I²C bus (inter-IC bus)

interface functions. The register configuration that controls the I²C bus differs partly from the

Philips configuration, however.

Figure 15.1 shows a block diagram of the I²C bus interface 2.

Figure 15.2 shows an example of I/O pin connections to external circuits.

15.1

Features

•

Selection of I²C format or clocked synchronous serial format

Continuous transmission/reception

Since the shift register, transmit data register, and receive data register are independent from

each other, the continuous transmission/reception can be performed.

I²C bus format:

•

Start and stop conditions generated automatically in master mode

Selection of acknowledge output levels when receiving

Automatic loading of acknowledge bit when transmitting

Bit synchronization/wait function

In master mode, the state of SCL is monitored per bit, and the timing is synchronized

automatically.

If transmission/reception is not yet possible, set the SCL to low until preparations are

completed.

•

Six interrupt sources

Transmit data empty (including slave-address match), transmit end, receive data full (including

slave-address match), arbitration lost, NACK detection, and stop condition detection

Direct bus drive

Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive

function is selected.

Clocked synchronous format:

•

Four interrupt sources

Transmit-data-empty, transmit-end, receive-data-full, and overrun error

IFIIC10A_000020030300

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Section 15 I²C Bus Interface 2 (IIC2)

Transfer clock

generation

circuit

Transmit/

receive

control circuit

ICCR1

ICCR2

ICMR

Output

control

SCL

Noise canceler

ICDRT

SAR

Output

control

ICDRS

SDA

Address

comparator

Noise canceler

ICDRR

Bus state

decision circuit

Arbitration

decision circuit

ICSR

ICIER

[Legend]

ICCR1: I²C bus control register 1

ICCR2: I²C bus control register 2

ICMR: I²C bus mode register

Interrupt

generator

Interrupt request

ICSR:

I²C bus status register

ICIER: I²C bus interrupt enable register

ICDRT: I²C bus transmit data register

ICDRR: I²C bus receive data register

ICDRS: I²C bus shift register

SAR:

Slave address register

Figure 15.1 Block Diagram of I²C Bus Interface 2

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Section 15 I²C Bus Interface 2 (IIC2)

Vcc

SCL

SDA

SCL

SDA

SCL in

SCL out

SDA in

SDA out

SCL in

(Master)

SCL out

SDA in

SDA out

(Slave 1)

(Slave 2)

Figure 15.2 External Circuit Connections of I/O Pins

15.2

Input/Output Pins

Table 15.1 summarizes the input/output pins used by the I²C bus interface 2.

Table 15.1 Pin Configuration

Name

Abbreviation

SCL

I/O

Function

Serial clock

Serial data

I²C serial clock input/output

I²C serial data input/output

SDA

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Section 15 I²C Bus Interface 2 (IIC2)

15.3

Register Descriptions

The I²C bus interface 2 has the following registers.

•

I²C bus control register 1 (ICCR1)

I²C bus control register 2 (ICCR2)

I²C bus mode register (ICMR)

I²C bus interrupt enable register (ICIER)

I²C bus status register (ICSR)

I²C bus slave address register (SAR)

I²C bus transmit data register (ICDRT)

I²C bus receive data register (ICDRR)

I²C bus shift register (ICDRS)

15.3.1 I²C Bus Control Register 1 (ICCR1)

ICCR1 enables or disables the I²C bus interface 2, controls transmission or reception, and selects

master or slave mode, transmission or reception, and transfer clock frequency in master mode.

Bit

Bit Name Initial Value R/W Description

7

ICE

0

R/W I²C Bus Interface Enable

0: This module is halted. (SCL and SDA pins are set to

port function.)

1: This bit is enabled for transfer operations. (SCL and

SDA pins are bus drive state.)

6

RCVD

0

R/W Reception Disable

This bit enables or disables the next operation when TRS

is 0 and ICDRR is read.

0: Enables next reception

1: Disables next reception

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Section 15 I²C Bus Interface 2 (IIC2)

Bit

5

Bit Name Initial Value R/W Description

MST

TRS

0

R/W Master/Slave Select

4

R/W Transmit/Receive Select

In master mode with the I²C bus format, when arbitration is

lost, MST and TRS are both reset by hardware, causing a

transition to slave receive mode. Modification of the TRS

bit should be made between transfer frames.

After data receive has been started in slave receive mode,

when the first seven bits of the receive data agree with the

slave address that is set to SAR and the eighth bit is 1,

TRS is automatically set to 1. If an overrun error occurs in

master mode with the clock synchronous serial format,

MST is cleared to 0 and slave receive mode is entered.

Operating modes are described below according to MST

and TRS combination. When clocked synchronous serial

format is selected and MST is 1, clock is output.

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

R/W Transfer Clock Select 3 to 0

3 to 0 CKS3 to All 0

CKS0

These bits should be set according to the necessary

transfer rate (see table 15.2) in master mode. In slave

mode, these bits are used reservation of the set up time in

transmit mode. The time is 10t_cycwhen CKS3 = 0, and

20t_cycwhen CKS3 = 1.

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Section 15 I²C Bus Interface 2 (IIC2)

Table 15.2 Transfer Rate

Bit 3 Bit 2

Bit 1

Bit 0

Transfer Rate

φ = 8 MHz

286 kHz

Clock

CKS3 CKS2 CKS1

CKS0

φ = 5 MHz

179 kHz

125 kHz

104 kHz

78.1 kHz

62.5 kHz

50.0 kHz

44.6 kHz

39.1 kHz

89.3 kHz

62.5 kHz

52.1 kHz

39.1 kHz

31.3 kHz

25.0 kHz

22.3 kHz

19.5 kHz

φ = 10 MHz

357 kHz

250 kHz

208 kHz

156 kHz

125 kHz

100 kHz

89.3 kHz

78.1 kHz

179 kHz

125 kHz

104 kHz

78.1 kHz

62.5 kHz

50.0 kHz

44.6 kHz

39.1 kHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

φ/28

φ/40

200 kHz

φ/48

167 kHz

φ/64

125 kHz

φ/80

100 kHz

φ/100

φ/112

φ/128

φ/56

80.0 kHz

71.4 kHz

62.5 kHz

143 kHz

1

φ/80

100 kHz

φ/96

83.3 kHz

62.5 kHz

50.0 kHz

40.0 kHz

35.7 kHz

31.3 kHz

φ/128

φ/160

φ/200

φ/224

φ/256

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Section 15 I²C Bus Interface 2 (IIC2)

15.3.2 I²C Bus Control Register 2 (ICCR2)

ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls

reset in the control part of the I²C bus interface 2.

Bit Bit Name Initial Value R/W Description

7

BBSY

0

R/W Bus Busy

This bit enables to confirm whether the I²C bus is occupied or

released and to issue start/stop conditions in master mode.

With the clocked synchronous serial format, this bit has no

meaning. With the I²C bus format, this bit is set to 1 when the

SDA level changes from high to low under the condition of

SCL = high, assuming that the start condition has been

issued. This bit is cleared to 0 when the SDA level changes

from low to high under the condition of SCL = high, assuming

that the stop condition has been issued. Write 1 to BBSY and

0 to SCP to issue a start condition. Follow this procedure

when also re-transmitting a start condition. Write 0 in BBSY

and 0 in SCP to issue a stop condition. To issue start/stop

conditions, use the MOV instruction.

6

5

SCP

1

R/W Start/Stop Issue Condition Disable

The SCP bit controls the issue of start/stop conditions in

master mode.

To issue a start condition, write 1 in BBSY and 0 in SCP. A

retransmit start condition is issued in the same way. To issue

a stop condition, write 0 in BBSY and 0 in SCP. This bit is

always read as 1. If 1 is written, the data is not stored.

SDAO

R/W SDA Output Value Control

This bit is used with SDAOP when modifying output level of

SDA. This bit should not be manipulated during transfer.

0: When reading, SDA pin outputs low.

When writing, SDA pin is changed to output low.

1: When reading, SDA pin outputs high.

When writing, SDA pin is changed to output Hi-Z (outputs

high by external pull-up resistance).

4

SDAOP

1

R/W SDAO Write Protect

This bit controls change of output level of the SDA pin by

modifying the SDAO bit. To change the output level, clear

SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP

to 0 by the MOV instruction. This bit is always read as 1.

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Section 15 I²C Bus Interface 2 (IIC2)

Bit Bit Name Initial Value R/W Description

3

SCLO

1

R

This bit monitors SCL output level. When SCLO is 1, SCL pin

outputs high. When SCLO is 0, SCL pin outputs low.

2



1



Reserved

This bit is always read as 1.

1

0

IICRST

0

1

R/W IIC Control Part Reset

This bit resets the control part except for I²C registers. If this

bit is set to 1 when hang-up occurs because of

communication failure during I²C operation, I²C control part

can be reset without setting ports and initializing registers.



Reserved

This bit is always read as 1.

15.3.3 I²C Bus Mode Register (ICMR)

ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,

and selects the transfer bit count.

Bit Bit Name Initial Value R/W Description

7

MLS

0

R/W MSB-First/LSB-First Select

0: MSB-first

1: LSB-first

Set this bit to 0 when the I²C bus format is used.

6

WAIT

0

R/W Wait Insertion Bit

In master mode with the I²C bus format, this bit selects

whether to insert a wait after data transfer except the

acknowledge bit. When WAIT is set to 1, after the fall of the

clock for the final data bit, low period is extended for two

transfer clocks. If WAIT is cleared to 0, data and

acknowledge bits are transferred consecutively with no wait

inserted.

The setting of this bit is invalid in slave mode with the I²C bus

format or with the clocked synchronous serial format.

5, 4 

All 1



Reserved

These bits are always read as 1.

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Section 15 I²C Bus Interface 2 (IIC2)

Bit Bit Name Initial Value R/W Description

3

BCWP

1

R/W BC Write Protect

This bit controls the BC2 to BC0 modifications. When

modifying BC2 to BC0, this bit should be cleared to 0 and

use the MOV instruction. In clock synchronous serial mode,

BC should not be modified.

0: When writing, values of BC2 to BC0 are set.

1: When reading, 1 is always read.

When writing, settings of BC2 to BC0 are invalid.

R/W Bit Counter 2 to 0

2

1

0

BC2

BC1

BC0

0

R/W These bits specify the number of bits to be transferred next.

When read, the remaining number of transfer bits is

R/W

indicated. With the I²C bus format, the data is transferred with

one addition acknowledge bit. Bit BC2 to BC0 settings should

be made during an interval between transfer frames. If bits

BC2 to BC0 are set to a value other than 000, the setting

should be made while the SCL pin is low. The value returns

to 000 at the end of a data transfer, including the

acknowledge bit. With the clock synchronous serial format,

these bits should not be modified.

I²C Bus Format

000: 9 bits

001: 2 bits

010: 3 bits

011: 4 bits

100: 5 bits

101: 6 bits

110: 7 bits

111: 8 bits

Clock Synchronous Serial Format

000: 8 bits

001: 1 bits

010: 2 bits

011: 3 bits

100: 4 bits

101: 5 bits

110: 6 bits

111: 7 bits

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Section 15 I²C Bus Interface 2 (IIC2)

15.3.4 I²C Bus Interrupt Enable Register (ICIER)

ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be

transferred, and confirms acknowledge bits to be received.

Bit Bit Name Initial Value R/W Description

7

6

TIE

0

R/W Transmit Interrupt Enable

When the TDRE bit in ICSR is set to 1, this bit enables or

disables the transmit data empty interrupt (TXI).

0: Transmit data empty interrupt request (TXI) is disabled.

1: Transmit data empty interrupt request (TXI) is enabled.

R/W Transmit End Interrupt Enable

TEIE

This bit enables or disables the transmit end interrupt (TEI) at

the rising of the ninth clock while the TDRE bit in ICSR is 1.

TEI can be canceled by clearing the TEND bit or the TEIE bit

to 0.

0: Transmit end interrupt request (TEI) is disabled.

1: Transmit end interrupt request (TEI) is enabled.

R/W Receive Interrupt Enable

5

RIE

0

This bit enables or disables the receive data full interrupt

request (RXI) and the overrun error interrupt request (ERI)

with the clocked synchronous format, when a receive data is

transferred from ICDRS to ICDRR and the RDRF bit in ICSR

is set to 1. RXI can be canceled by clearing the RDRF or RIE

bit to 0.

0: Receive data full interrupt request (RXI) and overrun error

interrupt request (ERI) with the clocked synchronous

format are disabled.

1: Receive data full interrupt request (RXI) and overrun error

interrupt request (ERI) with the clocked synchronous

format are enabled.

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Section 15 I²C Bus Interface 2 (IIC2)

Bit Bit Name Initial Value R/W Description

4

NAKIE

0

R/W NACK Receive Interrupt Enable

This bit enables or disables the NACK receive interrupt

request (NAKI) and the overrun error (setting of the OVE bit

in ICSR) interrupt request (ERI) with the clocked

synchronous format, when the NACKF and AL bits in ICSR

are set to 1. NAKI can be canceled by clearing the NACKF,

OVE, or NAKIE bit to 0.

0: NACK receive interrupt request (NAKI) is disabled.

1: NACK receive interrupt request (NAKI) is enabled.

R/W Stop Condition Detection Interrupt Enable

3

2

1

STIE

0

0: Stop condition detection interrupt request (STPI) is

disabled.

1: Stop condition detection interrupt request (STPI) is

enabled.

ACKE

ACKBR

R/W Acknowledge Bit Judgement Select

0: The value of the receive acknowledge bit is ignored, and

continuous transfer is performed.

1: If the receive acknowledge bit is 1, continuous transfer is

halted.

R

Receive Acknowledge

In transmit mode, this bit stores the acknowledge data that

are returned by the receive device. This bit cannot be

modified.

0: Receive acknowledge = 0

1: Receive acknowledge = 1

0

ACKBT

0

R/W Transmit Acknowledge

In receive mode, this bit specifies the bit to be sent at the

acknowledge timing.

0: 0 is sent at the acknowledge timing.

1: 1 is sent at the acknowledge timing.

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Section 15 I²C Bus Interface 2 (IIC2)

15.3.5 I²C Bus Status Register (ICSR)

ICSR performs confirmation of interrupt request flags and status.

Bit Bit Name Initial Value R/W Description

7

TDRE

0

R/W Transmit Data Register Empty

[Setting conditions]

•

When data is transferred from ICDRT to ICDRS and

ICDRT becomes empty

When TRS is set

•

When a start condition (including re-transfer) has been

issued

•

When transmit mode is entered from receive mode in

slave mode

[Clearing conditions]

•

When 0 is written in TDRE after reading TDRE = 1

When data is written to ICDRT with an instruction

6

TEND

0

R/W Transmit End

[Setting conditions]

•

When the ninth clock of SCL rises with the I²C bus format

while the TDRE flag is 1

When the final bit of transmit frame is sent with the clock

synchronous serial format

[Clearing conditions]

•

When 0 is written in TEND after reading TEND = 1

When data is written to ICDRT with an instruction

5

RDRF

0

R/W Receive Data Register Full

[Setting condition]

•

When a receive data is transferred from ICDRS to ICDRR

[Clearing conditions]

•

When 0 is written in RDRF after reading RDRF = 1

When ICDRR is read with an instruction

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Section 15 I²C Bus Interface 2 (IIC2)

Bit Bit Name Initial Value R/W Description

4

NACKF

0

R/W No Acknowledge Detection Flag

[Setting condition]

•

When no acknowledge is detected from the receive

device in transmission while the ACKE bit in ICIER is 1

[Clearing condition]

When 0 is written in NACKF after reading NACKF = 1

•

3

STOP

0

R/W Stop Condition Detection Flag

[Setting conditions]

•

In master mode, when a stop condition is detected after

frame transfer

•

In slave mode, when a stop condition is detected

after the general call address or the first byte slave

address, next to detection of start condition, accords

with the address set in SAR

[Clearing condition]

When 0 is written in STOP after reading STOP = 1

•

2

AL/OVE

0

R/W Arbitration Lost Flag/Overrun Error Flag

This flag indicates that arbitration was lost in master mode

with the I²C bus format and that the final bit has been

received while RDRF = 1 with the clocked synchronous

format.

When two or more master devices attempt to seize the bus

at nearly the same time, if the I²C bus interface detects data

differing from the data it sent, it sets AL to 1 to indicate that

the bus has been taken by another master.

[Setting conditions]

•

If the internal SDA and SDA pin disagree at the rise of

SCL in master transmit mode

When the SDA pin outputs high in master mode while a

start condition is detected

When the final bit is received with the clocked

synchronous format while RDRF = 1

[Clearing condition]

•

When 0 is written in AL/OVE after reading AL/OVE=1

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Section 15 I²C Bus Interface 2 (IIC2)

Bit Bit Name Initial Value R/W Description

1

AAS

0

R/W Slave Address Recognition Flag

In slave receive mode, this flag is set to 1 if the first frame

following a start condition matches bits SVA6 to SVA0 in

SAR.

[Setting conditions]

•

When the slave address is detected in slave receive

mode

•

When the general call address is detected in slave

receive mode.

[Clearing condition]

When 0 is written in AAS after reading AAS=1

•

0

ADZ

0

R/W General Call Address Recognition Flag

This bit is valid in I²C bus format slave receive mode.

[Setting condition]

•

When the general call address is detected in slave

receive mode

[Clearing condition]

When 0 is written in ADZ after reading ADZ=1

•

15.3.6 Slave Address Register (SAR)

SAR selects the communication format and sets the slave address. When the chip is in slave mode

with the I²C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame

received after a start condition, the chip operates as the slave device.

Bit

Bit Name Initial Value R/W Description

7 to 1 SVA6 to All 0

SVA0

R/W Slave Address 6 to 0

These bits set a unique address in bits SVA6 to SVA0,

differing form the addresses of other slave devices

connected to the I²C bus.

0

FS

0

R/W Format Select

0: I²C bus format is selected.

1: Clocked synchronous serial format is selected.

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Section 15 I²C Bus Interface 2 (IIC2)

15.3.7 I²C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the

space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to

ICDRS and starts transferring data. If the next transfer data is written to ICDRT during

transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and

when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of

ICDRT is H'FF.

15.3.8 I²C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR

transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a

receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR

is H'FF.

15.3.9 I²C Bus Shift Register (ICDRS)

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from

ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from

ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the

CPU.

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Section 15 I²C Bus Interface 2 (IIC2)

15.4

Operation

The I²C bus interface can communicate either in I²C bus mode or clocked synchronous serial mode

by setting FS in SAR.

15.4.1 I²C Bus Format

Figure 15.3 shows the I²C bus formats. Figure 15.4 shows the I²C bus timing. The first frame

following a start condition always consists of 8 bits.

(a) I²C bus format (FS = 0)

S

1

SLA

7

R/W

A

1

DATA

n

A

1

A/A

P

1

n: Transfer bit count

(n = 1 to 8)

1

m

m: Transfer frame count

(m ≥ 1)

(b) I²C bus format (Start condition retransmission, FS = 0)

S

1

SLA

7

R/W

A

1

DATA

n1

A/A

S

1

SLA

7

R/W

A

1

DATA

n2

A/A

P

1

m1

1

m2

n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)

m1 and m2: Transfer frame count (m1 and m2 ≥ 1)

Figure 15.3 I²C Bus Formats

SDA

1-7

8

9

1-7

8

9

1-7

8

9

SCL

S

SLA

R/W

A

DATA

A

DATA

A

P

Figure 15.4 I²C Bus Timing

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Section 15 I²C Bus Interface 2 (IIC2)

[Legend]

S:

Start condition. The master device drives SDA from high to low while SCL is high.

SLA: Slave address

R/W: Indicates the direction of data transfer: from the slave device to the master device when

R/W is 1, or from the master device to the slave device when R/W is 0.

A:

Acknowledge. The receive device drives SDA to low.

DATA: Transfer data

P:

Stop condition. The master device drives SDA from low to high while SCL is high.

15.4.2 Master Transmit Operation

In master transmit mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. For master transmit mode operation timing, refer to

figures 15.5 and 15.6. The transmission procedure and operations in master transmit mode are

described below.

1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0

bits in ICCR1 to 1. (Initial setting)

2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in

ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV

instruction. (Start condition issued) This generates the start condition.

3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data

show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,

and data is transferred from ICDRT to ICDRS. TDRE is set again.

4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1

at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the

slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,

the slave device has not been acknowledged, so issue the stop condition. To issue the stop

condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the

transmit data is prepared or the stop condition is issued.

5. The transmit data after the second byte is written to ICDRT every time TDRE is set.

6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last

byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the

receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or

NACKF.

7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.

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Section 15 I²C Bus Interface 2 (IIC2)

SCL

(Master output)

1

2

3

4

5

6

7

8

9

1

2

SDA

(Master output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Slave address

R/W

SDA

(Slave output)

A

TDRE

TEND

ICDRT

ICDRS

Address + R/W

Data 1

Data 2

User

processing

[2] Instruction of start

condition issuance

[4] Write data to ICDRT (second byte)

[5] Write data to ICDRT (third byte)

[3] Write data to ICDRT (first byte)

Figure 15.5 Master Transmit Mode Operation Timing (1)

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

SDA

(Master output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SDA

(Slave output)

A

A/A

TDRE

TEND

ICDRT

ICDRS

Data n

User

processing

[6] Issue stop condition. Clear TEND.

[7] Set slave receive mode

[5] Write data to ICDRT

Figure 15.6 Master Transmit Mode Operation Timing (2)

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Section 15 I²C Bus Interface 2 (IIC2)

15.4.3 Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave

device, and returns an acknowledge signal. For master receive mode operation timing, refer to

figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown

below.

1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master

transmit mode to master receive mode. Then, clear the TDRE bit to 0.

2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,

and data received, in synchronization with the internal clock. The master device outputs the

level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.

3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise

of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF

is cleared to 0.

4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th

receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is

fixed low until ICDRR is read.

5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.

This enables the issuance of the stop condition after the next reception.

6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.

7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.

8. The operation returns to the slave receive mode.

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Section 15 I²C Bus Interface 2 (IIC2)

Master transmit mode

SCL

Master receive mode

9

1

2

3

4

5

6

7

8

9

1

(Master output)

SDA

(Master output)

A

SDA

(Slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

A

TDRE

TEND

TRS

RDRF

ICDRS

ICDRR

Data 1

[3] Read ICDRR

User

[2] Read ICDRR (dummy read)

processing

[1] Clear TDRE after clearing

TEND and TRS

Figure 15.7 Master Receive Mode Operation Timing (1)

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Section 15 I²C Bus Interface 2 (IIC2)

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

SDA

(Master output)

A

A/A

SDA

(Slave output)

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDRF

RCVD

ICDRS

ICDRR

Data n

Data n-1

Data n

Data n-1

User

processing

[7] Read ICDRR,

and clear RCVD

[5] Read ICDRR after setting RCVD

[6] Issue stop

condition

[8] Set slave

receive mode

Figure 15.8 Master Receive Mode Operation Timing (2)

15.4.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,

refer to figures 15.9 and 15.10.

The transmission procedure and operations in slave transmit mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0

bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive

mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are

set to 1, and the mode changes to slave transmit mode automatically. The continuous

transmission is performed by writing transmit data to ICDRT every time TDRE is set.

3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,

with TDRE = 1. When TEND is set, clear TEND.

4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.

5. Clear TDRE.

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Section 15 I²C Bus Interface 2 (IIC2)

Slave transmit mode

Slave receive mode

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

1

SDA

(Master output)

A

SCL

(Slave output)

SDA

(Slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

A

TDRE

TEND

TRS

ICDRT

ICDRS

ICDRR

Data 1

Data 2

Data 3

Data 1

Data 2

User

processing

[2] Write data to ICDRT (data 1)

[2] Write data to ICDRT (data 2)

[2] Write data to ICDRT (data 3)

Figure 15.9 Slave Transmit Mode Operation Timing (1)

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Section 15 I²C Bus Interface 2 (IIC2)

Slave receive

mode

Slave transmit mode

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

SDA

(Master output)

A

SCL

(Slave output)

SDA

(Slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TDRE

TEND

TRS

ICDRT

ICDRS

ICDRR

Data n

User

processing

[5] Clear TDRE

[4] Read ICDRR (dummy read)

after clearing TRS

[3] Clear TEND

Figure 15.10 Slave Transmit Mode Operation Timing (2)

15.4.5 Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. For slave receive mode operation timing, refer to

figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are

described below.

1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0

bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive

mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the

read data show the slave address and R/W, it is not used.)

3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is

fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be

returned to the master device, is reflected to the next transmit frame.

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Section 15 I²C Bus Interface 2 (IIC2)

4. The last byte data is read by reading ICDRR.

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

1

SDA

(Master output)

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

SCL

(Slave output)

SDA

(Slave output)

A

RDRF

ICDRS

ICDRR

Data 1

Data 2

Data 1

User

processing

[2] Read ICDRR

[2] Read ICDRR (dummy read)

Figure 15.11 Slave Receive Mode Operation Timing (1)

SCL

(Master output)

9

1

2

3

4

5

6

7

8

9

SDA

(Master output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCL

(Slave output)

SDA

(Slave output)

A

RDRF

ICDRS

ICDRR

Data 2

Data 1

User

processing

[3] Set ACKBT

[4] Read ICDRR

[3] Read ICDRR

Figure 15.12 Slave Receive Mode Operation Timing (2)

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Section 15 I²C Bus Interface 2 (IIC2)

15.4.6 Clocked Synchronous Serial Format

This module can be operated with the clocked synchronous serial format, by setting the FS bit in

SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When

MST is 0, the external clock input is selected.

(1) Data Transfer Format:

Figure 15.13 shows the clocked synchronous serial transfer format.

The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge

of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the

MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the

SDAO bit in ICCR2.

SCL

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

SDA

Figure 15.13 Clocked Synchronous Serial Transfer Format

(2) Transmit Operation:

In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer

clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For

transmit mode operation timing, refer to figure 15.14. The transmission procedure and operations

in transmit mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial

setting)

2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.

3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is

transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous

transmission is performed by writing data to ICDRT every time TDRE is set. When changing

from transmit mode to receive mode, clear TRS while TDRE is 1.

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Section 15 I²C Bus Interface 2 (IIC2)

1

2

7

8

1

7

8

1

SCL

SDA

(Output)

Bit 6

Bit 7

Bit 0

Bit 6

Bit 7

Bit 0

Bit 1

TRS

TDRE

ICDRT

ICDRS

Data 1

Data 2

Data 3

Data 1

Data 2

User

processing

[3] Write data

to ICDRT

[3] Write data

to ICDRT

[3] Write data [3] Write data

to ICDRT to ICDRT

[2] Set TRS

Figure 15.14 Transmit Mode Operation Timing

(3) Receive Operation:

In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when

MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to

figure 15.15. The reception procedure and operations in receive mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial

setting)

2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.

3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and

RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is

continually output. The continuous reception is performed by reading ICDRR every time

RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and

AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.

4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is

fixed high after receiving the next byte data.

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Section 15 I²C Bus Interface 2 (IIC2)

SCL

1

2

7

8

1

7

8

1

2

SDA

(Input)

Bit 6

Bit 7

Bit 0

Bit 6

Bit 7

Bit 0

Bit 1

Bit 0

Bit 1

MST

TRS

RDRF

Data 2

Data 3

Data 2

Data 1

ICDRS

ICDRR

Data 1

User

processing

[2] Set MST

(when outputting the clock)

[3] Read ICDRR

Figure 15.15 Receive Mode Operation Timing

15.4.7 Noise Canceler

The logic levels at the SCL and SDA pins are routed through the noise canceler before being

latched internally. Figure 15.16 shows a block diagram of the noise canceler.

The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

Sampling clock

C

SCL or SDA

input signal

Internal

SCL or SDA

signal

D

Q

D

Q

March detector

Latch

System clock

period

Sampling

clock

Figure 15.16 Block Diagram of Noise Canceler

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Section 15 I²C Bus Interface 2 (IIC2)

15.4.8 Example of Use

Flowcharts in respective modes that use the I²C bus interface are shown in figures 15.17 to 15.20.

Start

[1] Test the status of the SCL and SDA lines.

[2] Set master transmit mode.

Initialize

Read BBSY in ICCR2

BBSY=0 ?

[1]

No

[3] Issue the start candition.

Yes

Set MST and TRS

in ICCR1 to 1.

[4] Set the first byte (slave address + R/W) of transmit data.

[5] Wait for 1 byte to be transmitted.

[2]

[3]

[4]

Write 1 to BBSY

and 0 to SCP.

[6] Test the acknowledge transferred from the specified slave device.

[7] Set the second and subsequent bytes (except for the final byte) of transmit data.

[8] Wait for ICDRT empty.

Write transmit data

in ICDRT

Read TEND in ICSR

[5]

[6]

No

TEND=1 ?

Yes

[9] Set the last byte of transmit data.

Read ACKBR in ICIER

[10] Wait for last byte to be transmitted.

No

ACKBR=0 ?

Yes

[11] Clear the TEND flag.

Mater receive mode

Transmit

mode?

Yes

[12] Clear the STOP flag.

[7]

[8]

Write transmit data in ICDRT

[13] Issue the stop condition.

Read TDRE in ICSR

No

TDRE=1 ?

[14] Wait for the creation of stop condition.

[15] Set slave receive mode. Clear TDRE.

Yes

No

Last byte?

[9]

Yes

Write transmit data in ICDRT

Read TEND in ICSR

[10]

No

TEND=1 ?

Yes

[11]

[12]

Clear TEND in ICSR

Clear STOP in ICSR

Write 0 to BBSY

and SCP

[13]

Read STOP in ICSR

[14]

No

STOP=1 ?

Yes

Set MST to 1 and TRS

to 0 in ICCR1

[15]

Clear TDRE in ICSR

End

Figure 15.17 Sample Flowchart for Master Transmit Mode

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Section 15 I²C Bus Interface 2 (IIC2)

Mater receive mode

[1] Clear TEND, select master receive mode, and then clear TDRE.*

Clear TEND in ICSR

Clear TRS in ICCR1 to 0

Clear TDRE in ICSR

[2] Set acknowledge to the transmit device.*

[3] Dummy-read ICDDR.*

[1]

[4] Wait for 1 byte to be received

Clear ACKBT in ICIER to 0

Dummy-read ICDRR

[2]

[3]

[5] Check whether it is the (last receive - 1).

[6] Read the receive data last.

Read RDRF in ICSR

No

[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).

[8] Read the (final byte - 1) of receive data.

[9] Wait for the last byte to be receive.

[10] Clear the STOP flag.

[4]

RDRF=1 ?

Yes

Last receive

[5]

[6]

- 1?

No

Read ICDRR

[11] Issue the stop condition.

[12] Wait for the creation of stop condition.

[13] Read the last byte of receive data.

[14] Clear RCVD.

Set ACKBT in ICIER to 1

Set RCVD in ICCR1 to 1

[7]

[8]

[9]

Read ICDRR

[15] Set slave receive mode.

Read RDRF in ICSR

No

RDRF=1 ?

Yes

[10]

[11]

Clear STOP in ICSR.

Write 0 to BBSY

and SCP

Read STOP in ICSR

[12]

No

STOP=1 ?

Yes

[13]

[14]

Read ICDRR

Clear RCVD in ICCR1 to 0

[15]

Clear MST in ICCR1 to 0

End

Note: Do not activate an interrupt during the execution of steps [1] to [3].

When one byte is received, steps [2] to [6] are skipped after step [1],

before jumping to step [7]. The step [8] is dammy-read in ICDRR.

Supplementary explanation:

Figure 15.18 Sample Flowchart for Master Receive Mode

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Section 15 I²C Bus Interface 2 (IIC2)

[1] Clear the AAS flag.

Slave transmit mode

Clear AAS in ICSR

[1]

[2]

[2] Set transmit data for ICDRT (except for the last data).

[3] Wait for ICDRT empty.

Write transmit data

in ICDRT

[4] Set the last byte of transmit data.

[5] Wait for the last byte to be transmitted.

[6] Clear the TEND flag .

Read TDRE in ICSR

[3]

[4]

No

TDRE=1 ?

[7] Set slave receive mode.

Yes

[8] Dummy-read ICDRR to release the SCL line.

[9] Clear the TDRE flag.

Last

byte?

No

Yes

Write transmit data

in ICDRT

Read TEND in ICSR

[5]

No

TEND=1 ?

Yes

Clear TEND in ICSR

[6]

[7]

Clear TRS in ICCR1 to 0

Dummy read ICDRR

Clear TDRE in ICSR

[8]

[9]

End

Figure 15.19 Sample Flowchart for Slave Transmit Mode

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Section 15 I²C Bus Interface 2 (IIC2)

Slave receive mode

Clear AAS in ICSR

[1] Clear the AAS flag.

[1]

[2] Set acknowledge to the transmit device.

[3] Dummy-read ICDRR.

Clear ACKBT in ICIER to 0

Dummy-read ICDRR

[2]

[3]

[4] Wait for 1 byte to be received.

[5] Check whether it is the (last receive - 1).

[6] Read the receive data.

Read RDRF in ICSR

No

[4]

RDRF=1 ?

[7] Set acknowledge of the last byte.

[8] Read the (last byte - 1) of receive data.

[9] Wait the last byte to be received.

[10] Read for the last byte of receive data.

Yes

Last receive

- 1?

[5]

[6]

No

Read ICDRR

Set ACKBT in ICIER to 1

[7]

[8]

Read ICDRR

Read RDRF in ICSR

[9]

No

RDRF=1 ?

Yes

[10]

Read ICDRR

End

Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1],

before jumping to step [7]. The step [8] is dammy-read in ICDRR.

Figure 15.20 Sample Flowchart for Slave Receive Mode

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Section 15 I²C Bus Interface 2 (IIC2)

15.5

Interrupts

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the

contents of each interrupt request.

Table 15.3 Interrupt Requests

Clocked

Synchronous

Interrupt Request

Abbreviation Interrupt Condition

I²C Mode Mode

•

Transmit Data Empty TXI

(TDRE=1) (TIE=1)

{

×

{

•

Transmit End

TEI

(TEND=1) (TEIE=1)

•

Receive Data Full

STOP Recognition

NACK Receive

RXI

(RDRF=1) (RIE=1)

•

STPI

NAKI

(STOP=1) (STIE=1)

•

{(NACKF=1)+(AL=1)}

(NAKIE=1)

Arbitration

Lost/Overrun Error

When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU

executes an interrupt exception processing. Interrupt sources should be cleared in the exception

processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to

ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the

same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive

data of one byte may be transmitted.

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Section 15 I²C Bus Interface 2 (IIC2)

15.6

Bit Synchronous Circuit

In master mode, this module has a possibility that high level period may be short in the two states

described below.

•

When SCL is driven to low by the slave device

When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-

up resistance)

Therefore, it monitors SCL and communicates by bit with synchronization.

Figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when

SCL output changes from low to Hi-Z then SCL is monitored.

SCL monitor

timing reference

clock

V_IH

SCL

Internal SCL

Figure 15.21 Timing of Bit Synchronous Circuit

Table 15.4 Time for Monitoring SCL

CKS3

CKS2

Time for Monitoring SCL

7.5 tcyc

0

1

0

1

19.5 tcyc

1

17.5 tcyc

41.5 tcyc

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Section 15 I²C Bus Interface 2 (IIC2)

15.7

Usage Notes

15.7.1 Issue (Retransmission) of Start/Stop Conditions

In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing

under the following condition 1 or 2, such conditions may not be output successfully. To avoid

this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check

the SCLO bit in the I²C control register 2 (IICR2) to confirm the fall of the ninth clock.

1. When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous

Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)

2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth

clocks, that is driven by the slave device

15.7.2 WAIT Setting in I²C Bus Mode Register (ICMR)

If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the

slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To

avoid this, set the WAIT bit in ICMR to 0.

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Section 16 A/D Converter

This LSI includes a successive approximation type 10-bit A/D converter that allows up to four

analog input channels to be selected. The block diagram of the A/D converter is shown in figure

16.1.

16.1

Features

•

10-bit resolution

Four input channels

Conversion time: At least 7 µs per channel (at 10 MHz operation)

Two operating modes

 Single mode: Single-channel A/D conversion

 Scan mode: Continuous A/D conversion on 1 to 4 channels

Four data registers

•

 Conversion results are held in a 16-bit data register for each channel

Sample and hold function

•

Two conversion start methods

 Software

 External trigger signal

•

Interrupt request

 An A/D conversion end interrupt request (ADI) can be generated

ADCMS32A_000020020200

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Section 16 A/D Converter

Internal data bus

Module data bus

AV_CC

A

D

R

A

D

R

B

A

D

R

C

A

D

R

D

A

D

C

S

R

A

D

C

R

10-bit D/A

+

φ

/4

/8

AN0

AN1

AN2

AN3

Control circuit

Comparator

Sample-and-

hold circuit

ADI

interrupt request

ADTRG

[Legend]

ADCR: A/D control register

ADCSR: A/D control/status register

ADDRA: A/D data register A

ADDRB: A/D data register B

ADDRC: A/D data register C

ADDRD: A/D data register D

Figure 16.1 Block Diagram of A/D Converter

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Section 16 A/D Converter

16.2

Input/Output Pins

Table 16.1 summarizes the input pins used by the A/D converter.

Table 16.1 Pin Configuration

Pin Name

Symbol

AV_CC

I/O

Function

Analog power supply pin

Analog input pin 0

Analog input pin 1

Analog input pin 2

Analog input pin 3

A/D external trigger input pin

Input

Analog block power supply pin

Analog input pins

AN0

AN1

AN2

AN3

ADTRG

External trigger input pin for starting A/D

conversion

16.3

Register Description

The A/D converter has the following registers.

•

A/D data register A (ADDRA)

A/D data register B (ADDRB)

A/D data register C (ADDRC)

A/D data register D (ADDRD)

A/D control/status register (ADCSR)

A/D control register (ADCR)

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown

in table 16.2.

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

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Section 16 A/D Converter

Therefore, byte access to ADDR should be done by reading the upper byte first then the lower

one. ADDR is initialized to H'0000.

Table 16.2 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

A/D Data Register to Be Stored Results of A/D Conversion

AN0

AN1

AN2

AN3

ADDRA

ADDRB

ADDRC

ADDRD

16.3.2 A/D Control/Status Register (ADCSR)

ADCSR consists of the control bits and conversion end status bits of the A/D converter.

Initial

Bit

Bit Name Value

R/W

Description

7

ADF

0

R/W

A/D End Flag

[Setting conditions]

•

When A/D conversion ends in single mode

When A/D conversion ends on all the channels

selected in scan mode

[Clearing condition]

When 0 is written after reading ADF = 1

•

6

5

ADIE

0

R/W

A/D Interrupt Enable

A/D conversion end interrupt (ADI) request enabled by

ADF when 1 is set

ADST

A/D Start

Setting this bit to 1 starts A/D conversion. In single mode,

this bit is cleared to 0 automatically when conversion on

the specified channel is complete. In scan mode,

conversion continues sequentially on the specified

channels until this bit is cleared to 0 by software, a reset,

or a transition to standby mode.

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Section 16 A/D Converter

Initial

Bit

Bit Name Value

R/W

Description

4

SCAN

0

R/W

Scan Mode

Selects single mode or scan mode as the A/D conversion

operating mode.

0: Single mode

1: Scan mode

3

CKS

0

R/W

Clock Select

Selects the A/D conversions time

0: Conversion time = 134 states (max.)

1: Conversion time = 70 states (max.)

Clear the ADST bit to 0 before switching the conversion

time.

2

1

0

CH2

CH1

CH0

0

R/W

Channel Select 0 to 2

Select analog input channels.

When SCAN = 0

000: AN0

When SCAN = 1

000: AN0

001: AN1

001: AN0 to AN1

010: AN0 to AN2

011: AN0 to AN3

010: AN2

011: AN3

Note: When executing the A/D conversion through AN3

or AN2, do not set the VDDII bit in LVDCR to 0. If 0

is set, the A/D conversion accuracy is not

guaranteed.

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Section 16 A/D Converter

16.3.3 A/D Control Register (ADCR)

ADCR enables A/D conversion started by an external trigger signal.

Initial

Bit

Bit Name Value

R/W

Description

7

TRGE

0

R/W

Trigger Enable

A/D conversion is started at the falling edge and the rising

edge of the external trigger signal (ADTRG) when this bit

is set to 1.

The selection between the falling edge and rising edge of

the external trigger pin (ADTRG) conforms to the WPEG5

bit in the interrupt edge select register 2 (IEGR2)

6 to 4

3, 2

—

All 1

All 0

—

Reserved

These bits are always read as 1.

Reserved

R/W

Although these bits are readable/writable, they should not

be set to 1.

1

0

—

1

0

R/W

Reserved

This bit is always read as 1.

Reserved

Although this bit is readable/writable, it should not be set

to 1.

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Section 16 A/D Converter

16.4

Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes; single mode and scan mode. When changing the operating mode or analog input

channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The

ADST bit can be set at the same time as the operating mode or analog input channel is changed.

16.4.1 Single Mode

In single mode, A/D conversion is performed once for the analog input on the specified single

channel as follows:

1. A/D conversion is started from the first channel when the ADST bit in ADCSR is set to 1,

according to software or external trigger input.

2. When A/D conversion is completed, the result is transferred to the corresponding A/D data

register to the channel.

3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at

this time, an ADI interrupt request is generated.

4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the

ADST bit is automatically cleared to 0 and the A/D converter enters the wait state.

16.4.2 Scan Mode

In scan mode, A/D conversion is performed sequentially for the analog input on the specified

channels (four channels maximum) as follows:

1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on

the first channel in the group.

2. When A/D conversion for each channel is completed, the result is sequentially transferred to

the A/D data register corresponding to each channel.

3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first

channel in the group starts again.

4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the

ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.

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Section 16 A/D Converter

16.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (t_D) has passed after the ADST bit is set to 1, then

starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D

conversion time.

As indicated in figure 16.2, the A/D conversion time includes t_Dand the input sampling time. The

length of t_Dvaries depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 16.3.

In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and

subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states

(fixed) when CKS = 1.

(1)

φ

Address

(2)

Write signal

Input sampling

timing

ADF

t_D

t_SPL

t_CONV

[Legend]

(1):

(2):

t_D:

ADCSR write cycle

ADCSR address

A/D conversion start delay

Input sampling time

t_SPL

:

t_CONV

:

A/D conversion time

Figure 16.2 A/D Conversion Timing

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Section 16 A/D Converter

Table 16.3 A/D Conversion Time (Single Mode)

CKS = 0

CKS = 1

Item

Symbol

Min.

6

Typ.

—

Max.

9

Min.

4

Typ.

—

Max.

5

A/D conversion start delay t_D

Input sampling time

A/D conversion time

t_SPL

t_CONV

—

31

—

15

—

131

—

134

69

—

70

Note: All values represent the number of states.

16.4.4 External Trigger Input Timing

A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in

ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input

pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single

and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3

shows the timing.

φ

ADTRG

Internal trigger signal

ADST

A/D conversion

Figure 16.3 External Trigger Input Timing

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Section 16 A/D Converter

16.5

A/D Conversion Accuracy Definitions

This LSI's A/D conversion accuracy definitions are given below.

•

Resolution

The number of A/D converter digital output codes

Quantization error

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).

Offset error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value 0000000000 to 0000000001

(see figure 16.5).

•

Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from 1111111110 to 1111111111 (see figure 16.5).

Nonlinearity error

The error with respect to the ideal A/D conversion characteristics between zero voltage and

full-scale voltage. Does not include offset error, full-scale error, or quantization error.

Absolute accuracy

The deviation between the digital value and the analog input value. Includes offset error, full-

scale error, quantization error, and nonlinearity error.

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Section 16 A/D Converter

Digital output

Ideal A/D conversion

characteristic

111

110

101

100

011

010

001

Quantization error

000

1

2

8

3

8

4

8

5

8

6

8

7

8

FS

8

Analog

input voltage

Figure 16.4 A/D Conversion Accuracy Definitions (1)

Full-scale error

Digital output

Ideal A/D conversion

characteristic

Nonlinearity

error

Actual A/D conversion

characteristic

FS

Analog

input voltage

Offset error

Figure 16.5 A/D Conversion Accuracy Definitions (2)

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Section 16 A/D Converter

16.6

Usage Notes

16.6.1 Permissible Signal Source Impedance

This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal

for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the

A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;

if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be

possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with

a large capacitance provided externally, the input load will essentially comprise only the internal

input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass

filter effect is obtained in this case, it may not be possible to follow an analog signal with a large

differential coefficient (e.g., 5 mV/µs or greater) (see figure 16.6). When converting a high-speed

analog signal or converting in scan mode, a low-impedance buffer should be inserted.

16.6.2 Influences on Absolute Accuracy

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely

affect absolute accuracy. Be sure to make the connection to an electrically stable GND.

Care is also required to ensure that filter circuits do not interfere with digital signals or act as

antennas on the mounting board.

This LSI

A/D converter

Sensor output

impedance

equivalent circuit

10 kΩ

to 5 kΩ

Sensor input

C_in

15 pF

=

Low-pass

filter

20 pF

C to 0.1 µF

Figure 16.6 Analog Input Circuit Example

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Section 17 Band-Gap Circuit, Power-On Reset, and

Low-Voltage Detection Circuits

This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and

low-voltage detection circuit.

BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit.

Figure 17.1 shows the block diagram of how BGR is allocated.

The low-voltage detection (LVD) circuit consists of two circuits: LVDI (interrupt by low voltage

detection) and LVDR (reset by low voltage detection) circuits.

This circuit is used to prevent abnormal operation (program runaway) from occurring due to the

power supply voltage fall and to recreate the state before the power supply voltage fall when the

power supply voltage rises again.

Even if the power supply voltage falls, the unstable state when the power supply voltage falls

below the guaranteed operating voltage can be removed by entering standby mode when

exceeding the guaranteed operating voltage and during normal operation. Thus, system stability

can be improved. If the power supply voltage falls more, the reset state is automatically entered. If

the power supply voltage rises again, the reset state is held for a specified period, then active mode

is automatically entered.

Figure 17.2 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.

PSCKT00A_000020020200

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

17.1

Features

•

BGR circuit

Supplies stable reference voltage covering the entire operating voltage range and the operating

temperature range.

Reduces power consumption when BGR is disabled by setting registers.

Power-on reset circuit

•

Uses an external capacitor to generate an internal reset signal when power is first supplied.

Low-voltage detection circuit

LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the

voltage falls below a given value.

LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls

below or rises above respective given values.

Two detection levels for reset generation voltage are available: when only the LVDR circuit is

used, or when the LVDI and LVDR circuits are both used.

VCLSEL

VCL

Vcc

Step-down circuit

BGR

On-chip

oscillator

RCSTP

LVDE

VBGR

BGRE

LVD (low-voltage

detection circuit)

[Legend]

Vcc:

Power supply

BGRE:

VCL:

VBGR:

BGR circuit enable signal

Internal power supply generated from Vcc by the step-down circuit

Reference voltage from BGR

VCLSEL: Select signal for the source of the on-chip oscillator power supply

RCSTP:

LVDE:

On-chip oscillator stop signal

LVD enable signal

Figure 17.1 Block Diagram around BGR

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

φ

OVF

CK

R

PSS

R

S

Internal

reset signal

RES

Noise filter

circuit

Q

C

RES

Power-on reset circuit

Noise filter

circuit

External

power

supply

LVDCR

Vreset

VintU

VintD

LVDRES

Ladder

network

Vcc

ExtD

ExtU

LVDINT

Interrupt

control

circuit

LVDSR

Interrupt request

VDDII

VBGR

[Legend]

PSS:

Prescaler S

LVDCR:

LVDSR:

VBGR:

ExtD:

Low-voltage-detection control register

Low-voltage-detection status register

Reference voltage from BGR

Compared voltage for falling external input voltage

Compared voltage for rising external input voltage

Bit 5 in LVDCR

ExtU:

VDDII:

Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

17.2

Register Descriptions

The low-voltage detection circuit has the following registers.

•

Low-voltage-detection control register (LVDCR)

Low-voltage-detection status register (LVDSR)

17.2.1 Low-Voltage-Detection Control Register (LVDCR)

LVDCR enables or disables the low-voltage detection circuit and BGR circuit, selects the

compared voltage of the LVDI circuit, sets the detection levels for the LVDR circuit, enables or

disables the LVDR circuit, and enables or disables generation of an interrupt when the power-

supply voltage rises above or falls below the respective levels.

Table 17.1 shows the relationship between the LVDCR settings and functions to be selected.

LVDCR should be set according to table 17.1.

Initial

Bit

Bit Name Value

R/W

Description

7

LVDE

1*

R/W

LVD Enable

0: Low-voltage detection circuit is not used (standby

mode)

1: Low-voltage detection circuit is used

BGR Enable

6

5

4

BGRE

VDDII



1*

1

R/W



0: BGR circuit is not used (standby mode)

1: BGR circuit is used

LVDR External Compared Voltage Input Inhibit

0: Use external voltage as LVDI compared voltage

1: Use internal voltage as LVDI compared voltage

Reserved

This bit is always read as 1 and cannot be modified.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Initial

Bit Name Value

Bit

R/W

Description

3

LVDSEL

0*

R/W

LVDR Detection Level Select

0: Reset detection voltage is 2.3 V (Typ.)

1: Reset detection voltage is 3.6 V (Typ.)

When the falling or rising voltage detection interrupt is

used, the reset detection voltage of 2.3 V (Typ.) should

be used. When only a reset detection interrupt is used,

reset detection voltage of 3.6 V (Typ.) should be used.

2

LVDRE

LVDDE

LVDUE

1*

0

R/W

LVDR Enable

0: Disables an LVDR

1: Enables an LVDR

1

Voltage-Fall-Interrupt Enable

0: Interrupt on the power-supply voltage falling disabled

1: Interrupt on the power-supply voltage falling enabled

Voltage-Rise-Interrupt Enable

0

0: Interrupt on the power-supply voltage rising disabled

1: Interrupt on the power-supply voltage rising enabled

Note:

*

Not initialized by an LVDR but initialized by a power-on reset or a watchdog timer reset.

Table 17.1 LVDCR Settings and Select Functions

LVDCR Settings

Select Functions

Low-

Voltage-

Detection

Fall

Voltage-

Detection

Rise

Power-On

LVDE BGRE VDDII LVDSEL LVDRE LVDDE LVDUE Reset

LVDR



√

Interrupt

1

*

2

1

2

*

2

*

2

0

1

*

√



√



√

1

0

1

0

1

0

1

0

1



√

Notes: 1. Set these bits if necessary.

2. Settings are ignored.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

17.2.2 Low-Voltage-Detection Status Register (LVDSR)

LVDSR indicates whether the power-supply voltage falls below or rises above the respective

given values.

Initial

Bit

Bit Name Value

R/W

Description

7 to 2



All 1



Reserved

These bits are always read as 1 and cannot be modified.

LVD Power-Supply Voltage Fall Flag

[Setting condition]

1

0

LVDDF

0*

R/W

•

When the power-supply voltage falls below Vint (D)

(Typ. = 3.7 V)

[Clearing condition]

When writing 0 to this bit after reading it as 1

•

LVDUF

0*

LVD Power-Supply Voltage Rise Flag

[Setting condition]

•

When the power supply voltage falls below Vint (D)

while the LVDUE bit in LVDCR is set to 1 and then

rises above Vint (U) (Typ. = 4.0 V) before falling

below Vreset1 (Typ. = 2.3 V)

[Clearing condition]

When writing 0 to this bit after reading it as 1

•

Note:

*

Initialized by an LVDR.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

17.3

Operations

17.3.1 Power-On Reset Circuit

Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply

voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via

the internal pull-up resistor (Typ. 150 kΩ). While the RES signal is driven low, the prescaler S and

the entire chip retains the reset state. When the level on the RES signal reaches the specified value,

the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to

release the internal reset signal after the prescaler S has counted 131,072 cycles of the φ clock. The

noise filter circuit which removes noise with less than 400 ns (Typ.) is included to prevent the

incorrect operation of this LSI caused by noise on the RES signal.

To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles

within the specified time. The maximum time required for the power supply to rise and settle

(t_PWON) is determined by the oscillation frequency (f_OSC) and capacitance which is connected to RES

pin (C_RES). Where t_PWONis assumed to be the time required to reach 90 % of the full level of the

power supply, the power supply circuit should be designed to satisfy the following formula.

t_PWON(ms) ≤ 90 × C_RES(µF) + 162/f_OSC(MHz)

(t_PWON≤ 3000 ms, C_RES≥ 0.22 µF, and f_OSC= 10 in 2-MHz to 10-MHz operation)

Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV to remove charge on the

RES pin. After that, it can be risen. To remove charge on the RES pin, it is recommended that the

diode should be placed to Vcc. If the power supply voltage (Vcc) rises from the point above Vpor,

a power-on reset may not occur.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

t_PWON

Vcc

Vpor

Vss

RES

PSS-reset

signal

OVF

Internal reset

signal

131,072 cycles

PSS counter starts Reset released

Figure 17.3 Operational Timing of Power-On Reset Circuit

17.3.2 Low-Voltage Detection Circuit

(1) LVDR (Reset by Low Voltage Detection) Circuit

Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled

after a power-on reset is released. To cancel the LVDR circuit, first the LVDRE bit in LVDCR

should be cleared to 0 and then the LVDE bit in LVDCR and, if necessary, the BGRE bit should

be cleared to 0. The LVDE and the BGRE bits must not be cleared to 0 simultaneously with the

LVDRE bit because incorrect operation may occur. To restart the LVDR circuit, set the LVDE bit

and the BGRE bit to 1, wait for 50 µs (t_LVDON) given by a software timer until the reference voltage

and the low-voltage-detection power supply have settled, then set the LVDRE bit to 1. After that,

the output settings of ports must be made.

When the power-supply voltage falls below the Vreset voltage (2.3 V or 3.6 V (Typ.)), the LVDR

circuit clears the LVDRES signal to 0, and resets prescaler S. The low-voltage detection reset state

remains in place until a power-on reset is generated. When the power-supply voltage rises above

the Vreset voltage again, prescaler S starts counting. It counts 131,072 clock (φ) cycles, and then

releases the internal reset signal. In this case, the LVDE, BGRE, VDDII, LVDSEL, and LVDRE

bits in LVDCR are not initialized.

Note that if the power supply voltage (Vcc) falls below V_LVDRmin= 1.0 V and then rises from that

point, the low-voltage detection reset may not occur.

If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

V^CC

Vreset

V^SS

VLVDRmin

LVDRES

PSS-reset

signal

OVF

Internal reset

signal

131,072 cycles

PSS counter starts

Reset released

Figure 17.4 Operating Timing of LVDR Circuit

(2) Low Voltage Detection Interrupt (LVDI) Circuit

(When Internally Generated Voltage is used for Detection)

Figure 17.5 shows the timing of the operation of the LVDI circuit.

The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To

enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the

LVDDE bit or LVDUE bit in LVDCR must be set to 1. After that, the output settings of ports

must be made.

To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for

Enabling/Disabling LVDR and LVDI Circuits.

To restart the LVDI circuit after standby mode, set the LVDE bit to 1, write 1 to VDDII (if

necessary), and wait for 50 µs (t_LVDON) given by a software timer until the reference voltage and the

low-voltage detection power supply have settled. Then, clear the LVDDF and LVDUF bits to 0

and set the LVDDE or the LVDUE bit to 1. After that, the output settings of ports must be made.

When the power-supply voltage falls below Vint (D) (Typ. = 3.7 V) voltage, the LVDI circuit

clears the LVDINT signal to 0 and sets the LVDDF bit to 1. If the LVDDE bit is 1 at this time, an

IRQ0 interrupt request is generated. In this case, the necessary data must be saved in the external

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing

is completed, the power supply voltage must be higher than the lower limit of the guaranteed

operating voltage.

When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and rises

above the Vint (U) (Typ. = 4.0 V) voltage, the LVDI circuit sets the LVDINT signal to 1. If the

LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is

simultaneously generated.

If the power supply voltage (Vcc) falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters

low voltage detection reset operation (when LVDRE = 1).

Vint (U)

Vint (D)

Vcc

Vreset1

VSS

LVDINT

LVDDE

LVDDF

LVDUE

LVDUF

IRQ0 interrupt generated IRQ0 interrupt generated

Figure 17.5 Operational Timing of LVDI Circuit

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

(3) Low Voltage Detection Interrupt (LVDI) Circuit

(When Voltages Input via ExtU and ExtD Pins are used for Detection)

Figure 17.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on

reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF

bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1.

When using external compared voltage, write 0 to the VDDII bit in LVDCR, and wait for 50 µs

(t_LVDON) given by a software timer until the detection circuit has settled. Then clear the LVDDF and

LVDUF bits to 0 and set the LVDDE or LVDUE bit to 1. After that, the output settings of ports

must be made. The initial value of the external compared voltages input on the ExtU and ExtD

pins must be higher than the Vexd voltage.

To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for

Enabling/Disabling LVDR and LVDI Circuits.

When the external comparison voltage of ExtD pin falls below the Vexd (D) (Typ. = 1.15 V)

voltage, the LVDI clears the LVDINT signal to 0 and sets the LVDDF bit in LVDSR to 1. If the

LVDDE bit is 1 at this time, an IRQ0 interrupt request is generated. In this case, the necessary

data must be saved in the external EEPROM, and a transition to standby mode or subsleep mode

must be made. Until this processing is completed, the power supply voltage must be higher than

the lower limit of the guaranteed operating voltage.

When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and the

input voltage of the ExtU pin rises above Vexd (Typ. = 1.15 V) voltage, the LVDI circuit sets the

LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and

an IRQ0 interrupt request is generated.

If the power supply voltage falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters low-

voltage detection reset operation. When the voltages input on the ExtU and ExtD pins are used as

the compared voltage, ensure to use the LVDR (reset detection voltage: Typ. = 2.3 V) circuit.

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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

External power

supply voltage

ExtD input voltage

(1)

ExtU input voltage

(2)

Vexd

(3)

(4)

V

reset1

SS

V

LVDINT

LVDDE

LVDDF

LVDUE

LVDUF

IRQ0 interrupt IRQ0 interrupt

generated

Figure 17.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input

through ExtU and ExtD Pins)

Rev. 3.00 Sep. 14, 2006 Page 296 of 408

REJ09B0105-0300

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

(4) Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits

The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage

detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for

the operation and release of the low-voltage detection circuit.

1. To disable the low-voltage detection circuit, clear all of the LVDRE, LVDDE, and LVDUE

bits to 0. Then, clear the LVDE and BGRE bits to 0. Set the VDDII bit in LVDCR if

necessary. The LVDE and BGRE bits must not be cleared to 0 at the same timing as the

LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.

2. To enable the low-voltage detection circuit, set the LVDE and BGRE bits in LVDCR to 1.

When the voltages input on the ExtU and ExtD pins are used as the compared voltage, clear

the LVDDII bit to 0.

3. Wait for 50 µs (t_LVDON) given by a software timer until the reference voltage and the low-

voltage-detection power supply have settled. Then, clear the LVDDF and LVDUF bits in

LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, if necessary.

LVDE

BGRE

VDDII

LVDRE

LVDDE

LVDUE

t_LVDON

Longer than one instruction operation time

Figure 17.7 Timing for Enabling/Disabling of Low-Voltage Detection Circuit

Rev. 3.00 Sep. 14, 2006 Page 297 of 408

REJ09B0105-0300

Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits

Rev. 3.00 Sep. 14, 2006 Page 298 of 408

REJ09B0105-0300

Section 18 Power Supply Circuit

This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the

internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the

voltage of the power supply connected to the external V_CCpin. As a result, the current consumed

when an external power supply is used at 3.0 V or above can be held down to virtually the same

low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the

internal voltage will be practically the same as the external voltage. It is, of course, also possible

to use the same level of external power supply voltage and internal power supply voltage without

using the internal power supply step-down circuit.

18.1

When Using Internal Power Supply Step-Down Circuit

Connect the external power supply to the V_CCpin, and connect a capacitance of approximately 0.1

µF between V_CLand V_SS, as shown in figure 18.1. The internal step-down circuit is made effective

simply by adding this external circuit. In the external circuit interface, the external power supply

voltage connected to V_CCand the GND potential connected to V_SSare the reference levels. For

example, for port input/output levels, the V_CClevel is the reference for the high level, and the V_SS

level is that for the low level. The A/D converter analog power supply is not affected by the

internal step-down circuit.

V_CC

V_CC= 3.0 to 5.5 V

Step-down circuit

V_CL

Stabilization

capacitance

(approx. 0.1 µF)

Internal

power

supply

Internal

logic

V_SS

Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used

PSCKT00A_000020020200

Rev. 3.00 Sep. 14, 2006 Page 299 of 408

REJ09B0105-0300

Section 18 Power Supply Circuit

18.2

When Not Using Internal Power Supply Step-Down Circuit

When the internal power supply step-down circuit is not used, connect the external power supply

to the V_CLpin and V_CCpin, as shown in figure 18.2. The external power supply is then input directly

to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V.

Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V)

is input.

V_CC

V_CC= 3.0 to 3.6 V

Step-down circuit

Internal

V_CL

Internal

logic

power

supply

V_SS

Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used

Rev. 3.00 Sep. 14, 2006 Page 300 of 408

REJ09B0105-0300

Section 19 List of Registers

The register list gives information on the on-chip I/O register addresses, how the register bits are

configured, and the register states in each operating mode. The information is given as shown

below.

1. Register addresses (address order)

•

Registers are listed from the lower allocation addresses.

Registers are classified by functional modules.

The data bus width is indicated.

The number of access states is indicated.

2. Register bits

•

Bit configurations of the registers are described in the same order as the register addresses.

Reserved bits are indicated by  in the bit name column.

When registers consist of 16 bits, bits are described from the MSB side.

3. Register states in each operating mode

•

Register states are described in the same order as the register addresses.

The register states described here are for the basic operating modes. If there is a specific reset

for an on-chip peripheral module, refer to the section on that on-chip peripheral module.

Rev. 3.00 Sep. 14, 2006 Page 301 of 408

REJ09B0105-0300

Section 19 List of Registers

19.1

Register Addresses (Address Order)

The data bus width indicates the numbers of bits by which the register is accessed.

The number of access states indicates the number of states based on the specified reference clock.

Abbre-

viation

Bit

No

Module

Address Name

Data Bus Access

Register Name

Width

State

Low-voltage-detection control

register

LVDCR

8

H'F730 Low-voltage 8

detection

2

circuit

Low-voltage-detection status

register

LVDSR

8

H'F731 Low-voltage 8

detection

2

circuit

Clock control status register

RC control register

CKCSR

RCCR

8

H'F734 Clock

oscillator

8

2

H'F735 On-chip

oscillator

RC trimming data protect register RCTRMDPR 8

H'F736 On-chip

oscillator

RC trimming data register

RCTRMDR

8

H'F737 On-chip

oscillator

I²C bus control register 1

I²C bus control register 2

I²C bus mode register

I²C bus interrupt enable register ICIER

I²C bus status register

ICCR1

ICCR2

ICMR

8

H'F748 IIC2

H'F749 IIC2

H'F74A IIC2

H'F74B IIC2

H'F74C IIC2

H'F74D IIC2

H'F74E IIC2

H'F74F IIC2

H'F760 Timer B1

H'F761 Timer B1

8

2

ICSR

Slave address register

SAR

I²C bus transmit data register

I²C bus receive data register

Timer mode register B1

ICDRT

ICDRR

TMB1

Timer counter B1/Timer load

register B1

TCB1(R)/

TLB1 (W)

Timer mode register W

Timer control register W

TMRW

TCRW

8

H'FF80 Timer W

H'FF81 Timer W

H'FF82 Timer W

H'FF83 Timer W

8

2

Timer interrupt enable register W TIERW

Timer status register W TSRW

Rev. 3.00 Sep. 14, 2006 Page 302 of 408

REJ09B0105-0300

Section 19 List of Registers

Abbre-

viation

Bit

No

Module

Address Name

Data Bus Access

Register Name

Width

State

Timer I/O control register 0

Timer I/O control register 1

Timer counter

TIOR0

TIOR1

TCNT

GRA

8

H'FF84 Timer W

H'FF85 Timer W

H'FF86 Timer W

H'FF88 Timer W

H'FF8A Timer W

H'FF8C Timer W

H'FF8E Timer W

H'FF90 ROM

8

2

8

2

16

8

16*¹

8

2

General register A

General register B

General register C

General register D

2

GRB

2

GRC

2

GRD

2

Flash memory control register 1 FLMCR1

Flash memory control register 2 FLMCR2

2

8

H'FF91 ROM

8

2

Erase block register 1

Flash memory enable register

Timer control register V0

Timer control/status register V

Timer constant register A

Timer constant register B

Timer counter V

EBR1

FENR

TCRV0

TCSRV

TCORA

TCORB

TCNTV

TCRV1

SMR

8

H'FF93 ROM

8

2

8

H'FF9B ROM

8

2

8

H'FFA0 Timer V

H'FFA1 Timer V

H'FFA2 Timer V

H'FFA3 Timer V

H'FFA4 Timer V

H'FFA5 Timer V

H'FFA8 SCI3

8

3

8

3

8

3

8

3

8

3

Timer control register V1

Serial mode register

Bit rate register

8

3

8

3

BRR

8

H'FFA9 SCI3

8

3

Serial control register 3

Transmit data register

Serial status register

Receive data register

Sampling mode register

A/D data register A

SCR3

TDR

8

H'FFAA SCI3

8

3

8

H'FFAB SCI3

8

3

SSR

8

H'FFAC SCI3

8

3

RDR

8

H'FFAD SCI3

8

3

SPMR

8

H'FFAE SCI3

8

3

ADDRA 16

ADDRB 16

ADDRC 16

ADDRD 16

H'FFB0 A/D converter

H'FFB2 A/D converter

H'FFB4 A/D converter

H'FFB6 A/D converter

H'FFB8 A/D converter

H'FFB9 A/D converter

H'FFC0 WDT*²

8

3

A/D data register B

8

3

A/D data register C

8

3

A/D data register D

8

3

A/D control/status register

A/D control register

ADCSR

ADCR

8

3

8

3

Timer control/status register WD TCSRWD 8

8

2

Rev. 3.00 Sep. 14, 2006 Page 303 of 408

REJ09B0105-0300

Section 19 List of Registers

Abbre-

viation

Bit

Module

Data Bus Access

Register Name

No Address Name

Width

State

Timer counter WD

TCWD

TMWD

ABRKCR

ABRKSR

BARH

BARL

8

H'FFC1 WDT*²

H'FFC2 WDT*²

8

2

Timer mode register WD

Address break control register

Address break status register

Break address register H

Break address register L

Break data register H

Break data register L

Port pull-up control register 1

Port pull-up control register 5

Port data register 1

8

2

H'FFC8 Address break

H'FFC9 Address break

H'FFCA Address break

H'FFCB Address break

H'FFCC Address break

H'FFCD Address break

H'FFD0 I/O port

8

2

8

2

8

2

8

2

BDRH

BDRL

8

2

8

2

PUCR1

PUCR5

PDR1

8

2

H'FFD1 I/O port

8

2

H'FFD4 I/O port

8

2

Port data register 2

PDR2

H'FFD5 I/O port

8

2

Port data register 5

PDR5

H'FFD8 I/O port

8

2

Port data register 7

PDR7

H'FFDA I/O port

8

2

Port data register 8

PDR8

H'FFDB I/O port

8

2

Port data register B

PDRB

PDRC

PMR1

PMR5

PCR1

H'FFDD I/O port

8

2

Port data register C

H'FFDE I/O port

8

2

Port mode register 1

H'FFE0 I/O port

8

2

Port mode register 5

H'FFE1 I/O port

8

2

Port control register 1

Port control register 2

Port control register 5

Port control register 7

Port control register 8

Port control register C

System control register 1

System control register 2

Interrupt edge select register 1

Interrupt edge select register 2

Interrupt enable register 1

Interrupt enable register 2

H'FFE4 I/O port

8

2

PCR2

H'FFE5 I/O port

8

2

PCR5

H'FFE8 I/O port

8

2

PCR7

H'FFEA I/O port

8

2

PCR8

H'FFEB I/O port

8

2

PCRC

SYSCR1

SYSCR2

IEGR1

IEGR2

IENR1

IENR2

H'FFEE I/O port

8

2

H'FFF0 Power-down

H'FFF1 Power-down

H'FFF2 Interrupts

H'FFF3 Interrupts

H'FFF4 Interrupts

H'FFF5 Interrupts

8

2

8

2

8

2

8

2

8

2

8

2

Rev. 3.00 Sep. 14, 2006 Page 304 of 408

REJ09B0105-0300

Section 19 List of Registers

Abbre-

viation

Bit

Module

Data Bus Access

Register Name

No Address Name

Width

State

Interrupt flag register 1

Interrupt flag register 2

Wake-up interrupt flag register

IRR1

IRR2

IWPR

8

H'FFF6 Interrupts

H'FFF7 Interrupts

H'FFF8 Interrupts

H'FFF9 Power-down

8

2

Module standby control register MSTCR1

1

Module standby control register MSTCR2

2

8

H'FFFA Power-down

8

2

Notes: 1. Only word access can be used.

2. WDT: Watchdog timer

Rev. 3.00 Sep. 14, 2006 Page 305 of 408

REJ09B0105-0300

Section 19 List of Registers

19.2

Register Bits

Register bit names of the on-chip peripheral modules are described below.

Each line covers eight bits, and 16-bit registers are shown as 2 lines.

Register

Name

Module

Name

Bit 7

LVDE

—

Bit 6

Bit 5

Bit 4

—

Bit 3

LVDSEL LVDRE LVDDE

LVDDF

CKSWIE CKSWIF —

Bit 2

Bit 1

Bit 0

LVDCR

LVDSR

CKCSR

BGRE VDDII

LVDUE LVDC

LVDUF

—

PMRC1 PMRC0

OSCSEL

CKSTA Clock

oscillator

RCCR

RCSTP FSEL

VCLSEL

—

RCPSC1 RCPSC0 On-chip

oscillator

RCTRMDPR WRI

PRWE LOCKDW

—

TRMDRWE

TRMD4

TRS

RCTRMDR TRMD7 TRMD6 TRMD5

TRMD3 TRMD2 TRMD1 TRMD0

ICCR1

ICCR2

ICMR

ICIER

ICSR

ICE

RCVD MST

CKS3

SCLO

CKS2

—

CKS1

IICRST

BC1

CKS0

—

IIC2

BBSY

MLS

TIE

SCP

SDAO

SDAOP

—

WAIT

TEIE

TEND

SVA5

—

BCWP BC2

BC0

RIE

NAKIE

NACKF

SVA3

STIE

ACKE

AL/OVE AAS

SVA1 SVA0

ACKBR ACKBT

TDRE

SVA6

RDRF

SVA4

STOP

SVA2

ADZ

FS

SAR

ICDRT

ICDRR

TMB1

ICDRT7 ICDRT6 ICDRT5 ICDRT4

ICDRR7 ICDRR6 ICDRR5 ICDRR4

ICDRT3 ICDRT2 ICDRT1 ICDRT0

ICDRR3 ICDRR2 ICDRR1 ICDRR0

TMB17

BIT7

—

TMB12 TMB11

BIT2 BIT1

TMB10 Timer B1

BIT0

TCB1 (R)/

TLB1 (W)

BIT6

BIT5

BIT4

BIT3

TMRW

TCRW

TIERW

TSRW

TIOR0

TIOR1

TCNT

CTS

CCLR

OVIE

OVF

—

BUFEB

CKS1

—

BUFEA

CKS0

—

PWMD PWMC

PWMB

TOA

Timer W

CKS2

—

TOD

IMIED

IMFD

—

TOC

TOB

IMIEC

IMFC

IOA2

IOC2

IMIEB

IMFB

IOA1

IOC1

IMIEA

IMFA

—

IOB2

IOD2

IOB1

IOD1

IOB0

IOD0

IOA0

—

IOC0

TCNT15 TCNT14 TCNT13 TCNT12

TCNT11 TCNT10 TCNT9

TCNT3 TCNT2 TCNT1

GRA11 GRA10 GRA9

TCNT8

TCNT0

GRA8

GRA0

GRB8

GRB0

TCNT7 TCNT6 TCNT5

GRA15 GRA14 GRA13

TCNT4

GRA12

GRA4

GRA

GRB

GRA7

GRB15 GRB14 GRB13

GRB7 GRB6 GRB5

GRA6

GRA5

GRA3

GRB11 GRB10 GRB9

GRB3 GRB2 GRB1

GRA2

GRA1

GRB12

GRB4

Rev. 3.00 Sep. 14, 2006 Page 306 of 408

REJ09B0105-0300

Section 19 List of Registers

Register

Name

Module

Name

Bit 7

GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9

GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1

GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GRC8

GRC0

GRD8

GRD0

P

GRC

Timer W

GRD

GRD7

—

GRD6

SWE

—

GRD5

ESU

—

GRD4

PSU

—

GRD3

EV

GRD2

PV

GRD1

E

FLMCR1

ROM

FLMCR2 FLER

—

EBR1

FENR

TCRV0

TCSRV

TCORA

TCORB

TCNTV

TCRV1

SMR

—

EB5

—

EB4

—

EB3

—

EB2

—

EB1

—

EB0

—

FLSHE

CMIEB

CMFB

—

CMIEA

CMFA

OVIE

OVF

CCLR1 CCLR0 CKS2

OS3 OS2

CKS1

OS1

CKS0

OS0

Timer V

—

TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0

TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0

TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0

—

TVEG1 TVEG0 TRGE

—

ICKS0

CKS0

BRR0

CKE0

TDR0

MPBT

RDR0

—

COM

BRR7

TIE

CHR

BRR6

RIE

PE

PM

STOP

BRR3

MPIE

TDR3

PER

RDR3

—

MP

CKS1

BRR1

CKE1

TDR1

MPBR

RDR1

SCI3

BRR

BRR5

TE

BRR4

RE

BRR2

TEIE

TDR2

TEND

RDR2

SCR3

TDR

TDR7

TDRE

RDR7

—

TDR6

RDRF

RDR6

—

TDR5

OER

RDR5

—

TDR4

FER

RDR4

—

SSR

RDR

SPMR

ADDRA

STDSPM —

AD9

AD1

AD9

AD1

AD8

AD0

AD8

AD0

AD8

AD0

AD8

AD0

ADIE

—

AD7

—

AD6

—

AD5

—

AD4

—

AD3

AD2

—

A/D converter

—

ADDRB

AD7

—

AD6

—

AD5

—

AD4

—

AD3

—

AD2

—

ADDRC AD9

AD1

AD7

—

AD6

—

AD5

—

AD4

—

AD3

—

AD2

—

ADDRD AD9

AD1

AD7

—

AD6

—

AD5

—

AD4

—

AD3

—

AD2

—

ADCSR

ADCR

ADF

ADST

—

SCAN

—

CKS

—

CH2

—

CH1

—

CH0

—

TRGE

TCSRWD B6WI

TCWE

B4WI

TCSRWE B2WI

WDON

B0WI

WRST

WDT*

TCWD

TMWD

TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0

CKS3 CKS2 CKS1 CKS0

—

Rev. 3.00 Sep. 14, 2006 Page 307 of 408

REJ09B0105-0300

Section 19 List of Registers

Register

Name

Module

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ABRKCR RTINTE CSEL1

CSEL0

ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address

break

ABRKSR ABIF

ABIE

—

BARH

BARL

BDRH

BDRL

PUCR1

PUCR5

PDR1

PDR2

PDR5

PDR7

PDR8

PDRB

PDRC

PMR1

PMR5

PCR1

PCR2

PCR5

PCR7

PCR8

PCRC

BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0

BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0

BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0

BDRL7

PUCR17

—

BDRL6

—

BDRL5

—

BDRL4

PUCR14

—

BDRL3

—

BDRL2

—

BDRL1

—

BDRL0

—

I/O port

—

PUCR55

—

P17

—

P14

—

P22

—

P21

—

P20

—

P57

—

P56

P76

—

P55

—

P75

P74

P84

—

P83

PB3

—

P82

PB2

—

P81

PB1

PC1

TXD

—

P80

PB0

PC0

—

IRQ3

—

IRQ0

—

WKP5

—

PCR17

—

PCR14

—

PCR22

—

PCR21

—

PCR20

—

PCR57

—

PCR56

PCR76

—

PCR55

PCR75

—

PCR74

PCR84

—

PCR83

—

PCR82

—

PCR81

PCR80

—

PCRC1 PCRC0

SYSCR1 SSBY

SYSCR2 SMSEL

STS2

—

STS1

DTON

—

STS0

MA2

—

Power-down

Interrupts

MA1

IEG3

—

MA0

—

IEGR1

IEGR2

IENR1

IENR2

IRR1

—

IEG0

—

WPEG5

IENWP

IENTB1

—

IENDT

—

IEN3

—

IEN0

—

IRRDT

—

IRRI3

—

IRRI0

—

IRR2

—

IRRTB1

IWPF5

—

IWPR

—

MSTCR1

MSTCR2

—

MSTIIC MSTS3 MSTAD MSTWD MSTTW MSTTV

MSTTB1

—

Power-down

—

Note:

*

WDT:Watchdog timer

Rev. 3.00 Sep. 14, 2006 Page 308 of 408

REJ09B0105-0300

Section 19 List of Registers

19.3

Register States in Each Operating Mode

Register

Name

Reset

Active

—

Sleep

—

Subsleep Standby

Module

LVDCR

LVDSR

CKCSR

RCCR

Initialized

—

LVDC

—

Clock oscillator

—

On-chip oscillation

RCTRMDPR Initialized

RCTRMDR Initialized

—

ICCR1

ICCR2

ICMR

ICIER

ICSR

Initialized

—

IIC2

—

SAR

—

ICDRT

ICDRR

TMB1

—

Timer B1

Timer W

TCB1/TLB1 Initialized

—

TMRW

TCRW

TIERW

TSRW

TIOR0

TIOR1

TCNT

GRA

Initialized

—

GRB

—

GRC

—

GRD

—

FLMCR1

FLMCR2

EBR1

Initialized

ROM

FENR

TCRV0

Timer V

Rev. 3.00 Sep. 14, 2006 Page 309 of 408

REJ09B0105-0300

Section 19 List of Registers

Register

Name

TCSRV

TCORA

TCORB

TCNTV

TCRV1

SMR

Reset

Active

—

Sleep

—

Subsleep Standby

Module

Initialized

—

Initialized

—

Timer V

SCI3

BRR

SCR3

TDR

SSR

RDR

SPMR

ADDRA

ADDRB

A/D converter

ADDRC Initialized

ADDRD Initialized

ADCSR

ADCR

Initialized

TCSRWD Initialized

WDT*

TCWD

TMWD

Initialized

—

ABRKCR Initialized

ABRKSR Initialized

—

Address Break

—

BARH

BARL

BDRH

BDRL

PUCR1

PUCR5

PDR1

PDR2

PDR5

PDR7

PDR8

PDRB

Initialized

—

I/O port

—

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Section 19 List of Registers

Register

Name

Reset

Active

—

Sleep

—

Subsleep Standby

Module

PDRC

PMR1

PMR5

PCR1

PCR2

PCR5

PCR7

PCR8

PCRC

Initialized

—

I/O port

SYSCR1 Initialized

SYSCR2 Initialized

Power-down

Interrupts

IEGR1

IEGR2

IENR1

IENR2

IRR1

Initialized

IRR2

IWPR

MSTCR1 Initialized

MSTCR2 Initialized

Power-down

Note:  is not initialized

WDT: Watchdog timer

*

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Section 19 List of Registers

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Section 20 Electrical Characteristics

20.1

Absolute Maximum Ratings

Table 20.1 Absolute Maximum Ratings

Item

Symbol

V_CC

Value

Unit

V

Note

Power supply voltage

Analog power supply voltage

–0.3 to +7.0

–0.3 to V_CC+0.3

–0.3 to AV_CC+0.3

–20 to +75

*

AV_CC

V_IN

V

Input voltage

Ports other than port B

Port B

V

Operating temperature

Storage temperature

T_opr

T_stg

°C

–55 to +125

Note:

*

Permanent damage may result if maximum ratings are exceeded. Normal operation

should be under the conditions specified in Electrical Characteristics. Exceeding these

values can result in incorrect operation and reduced reliability.

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Section 20 Electrical Characteristics

20.2

Electrical Characteristics (F-ZTAT^TMVersion)

20.2.1 Power Supply Voltage and Operating Ranges

1. Supply voltage and external oscillation frequency range

φosc(MHz)

12.0

2.0

3.0

5.5

Vcc(V)

AVcc = 3.0 to 5.5 V

• Active mode

• Sleep mode

2. Power supply voltage and operating frequency range

φosc(MHz)

φ(kHz)

12.0

1500

2.0

31.25

3.0

5.5

3.0

5.5

Vcc(V)

AVcc = 3.0 to 5.5 V

• Active mode

• Sleep mode

AVcc = 3.0 to 5.5 V

• Active mode

• Sleep mode

(When MA2 = 0 in SYSCR2)

(When MA2 = 1 in SYSCR2)

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Section 20 Electrical Characteristics

3. Analog power supply voltage and A/D converter accuracy guarantee range

φosc(MHz)

12.0

2.0

3.0

5.5

Vcc = 3.0 to 5.5 V

AVcc(V)

• Active mode

• Sleep mode

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Section 20 Electrical Characteristics

20.2.2 DC Characteristics

Table 20.2 DC Characteristics (1)

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C unless otherwise indicated.

Values

Applicable

Symbol Pins

Test

Condition

Item

Min.

Typ. Max.

Unit

V

Notes

Input high V_IH

voltage

RES, NMI, WKP5, V_CC= 4.0 V to 5.5 V

IRQ0, IRQ3,

V_CC× 0.8

V_CC× 0.9

—

V_CC+ 0.3

V

ADTRG, TMRIV,

TMCIV, FTCI,

FTIOA to FTIOD,

SCK3, TRGV

RXD, SCL, SDA, V_CC= 4.0 V to 5.5 V

P17, P14,

P22 to P20,

V_CC× 0.7

V_CC× 0.8

—

V_CC+ 0.3

V

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

PB3 to PB0

AV_CC= 4.0 V to 5.5 V AV_CC× 0.7

AV_CC= 3.0 V to 5.5 V AV_CC× 0.8

—

AV_CC+ 0.3 V

OSC1

V_CC= 4.0 V to 5.5 V

V_CC– 0.5

V_CC– 0.3

–0.3

V_CC+ 0.3

V_CC× 0.2

V

RES, NMI, WKP5,

IRQ0, IRQ3,

Input low V_IL

voltage

V_CC= 4.0 V to 5.5 V

—

ADTRG, TMRIV,

TMCIV, FTCI,

–0.3

V_CC× 0.1

V_CC× 0.3

V

FTIOA to FTIOD,

SCK3, TRGV

RXD, SCL, SDA, V_CC= 4.0 V to 5.5 V

P17, P14,

P22 to P20,

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

–0.3

—

V_CC× 0.2

V

PB3 to PB0

AV_CC= 4.0 V to 5.5 V –0.3

AV_CC= 3.0 V to 5.5 V –0.3

—

AV_CC× 0.3

AV_CC× 0.2

0.5

OSC1

V_CC= 4.0 V to 5.5 V

–0.3

V

0.3

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Section 20 Electrical Characteristics

Values

Applicable

Symbol Pins

Test

Condition

Item

Min.

Typ.

Max.

Unit Notes

Output

high

voltage

V_OH

P17, P14,

P22 to P20,

P55,

P76 to P74,

P84 to P80,

PC1, PC0

V_CC= 4.0 V to 5.5 V V_CC– 1.0 —

–I_OH= 4 mA

—

V

–I_OH= 0.1 mA

V_CC– 0.5 —

—

V

P56, P57

V_CC= 4.0 V to 5.5 V

–I_OH= 0.1 mA

V

_CC– 2.5 —

_CC– 2.2 —

—

V

_CC= 3.0 V to 4.0 V

—

–I_OH= 0.1 mA

Output low V_OL

voltage

P17, P14,

V_CC= 4.0 V to 5.5 V

I_OL= 1.6 mA

—

0.6

P22 to P20,

P57 to P55,

P76 to P74,

PC1, PC0

I

_OL= 0.4 mA

—

0.4

1.5

V

P84 to P80

V_CC= 4.0 V to 5.5 V

I_OL= 20.0 mA

V_CC= 4.0 V to 5.5 V

I_OL= 10.0 mA

—

1.0

0.4

V

V_CC= 4.0 V to 5.5 V

I_OL= 1.6 mA

I_OL= 0.4 mA

—

0.4

0.6

V

SCL, SDA

V_CC= 4.0 V to 5.5 V

I_OL= 6.0 mA

I

_OL= 3.0 mA

_IN= 0.5 V to

(V_CC– 0.5 V)

—

0.4

1.0

V

Input/

| I_IL

|

OSC1, NMI,

V

µA

output

leakage

current

WKP5,

IRQ0, IRQ3,

ADTRG, TRGV,

TMRIV, TMCIV,

FTCI, FTIOA to

FTIOD, RXD,

SCK3, SCL, SDA

P17, P14,

V

_IN= 0.5 V to

—

1.0

µA

P22 to P20,

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

(V_CC– 0.5 V)

PB3 to PB0

V_IN= 0.5 V to

(AV_CC– 0.5 V)

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Section 20 Electrical Characteristics

Values

Typ.

—

Applicable

Symbol Pins

Test

Condition

Item

Min.

Max.

Unit Notes

–I_p

P17, P14, P55

V_CC= 5.0 V,

50.0

300.0

µA

Pull-up

MOS

current

V

_IN= 0.0 V

V_CC= 3.0 V,

_IN= 0.0 V

f = 1 MHz,

_IN= 0.0 V,

—

60.0

—

µA

pF

Reference

value

V

Input

capaci-

tance

C_in

All input pins

except power

supply pins

15.0

V

T_a= 25°C

Active

mode

current

consump-

tion

I_OPE1

V_CC

Active mode 1

—

12.0

9.6

2.0

1.5

7.2

6.0

1.8

1.4

—

18.0

—

mA

µA

*

V

_CC= 5.0 V,

f_OSC= 12 MHz

Active mode 1

_CC= 3.0 V,

_OSC= 12 MHz

Reference

value*

V

f

I_OPE2

Active mode 2

_CC= 5.0 V,

_OSC= 12 MHz

2.5

—

*

V

f

Active mode 2

_CC= 3.0 V,

_OSC= 12 MHz

Reference

value*

V

f

Sleep

mode

current

consump-

tion

I_SLEEP1

Sleep mode 1

_CC= 5.0 V,

_OSC= 12 MHz

12.0

—

*

V

f

Sleep mode 1

_CC= 3.0 V,

_OSC= 12 MHz

Reference

value*

V

f

I_SLEEP2

Sleep mode 2

_CC= 5.0 V,

_OSC= 12 MHz

2.2

—

*

V

f

Sleep mode 2

_CC= 3.0 V,

_OSC= 12 MHz

Reference

value*

V

f

Subsleep I_SUBSP

mode

current

V_CC

V_CC= 5.0 V

LVDE = 0,

BGRE = 0

5.0

*

consump-

tion

Standby

mode

I_STBY

V_CC

LVDE = 0,

BGRE = 0

—

5.0

µA

*

current

consump-

tion

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Section 20 Electrical Characteristics

Values

Applicable

Symbol Pins

Test

Condition

Item

Min.

Typ.

Max.

Unit Notes

RAM data V_RAM

retaining

V_CC

2.0

—

V

voltage

Note:

*

Pin states during current consumption measurement are given below (excluding current

in the pull-up MOS transistors and output buffers).

Mode

RES Pin Internal State

Other Pins Oscillator Pins

Active mode 1

Active mode 2

Sleep mode 1

Sleep mode 2

V_CC

Operates

V_CC

System clock:

Crystal or ceramic

resonator, and on-chip

oscillator

Operates (φ/64)

Only timers operate

Only timers operate (φ/64)

CPU and timers both stop

Subsleep mode

Standby mode

—

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Section 20 Electrical Characteristics

Table 20.2 DC Characteristics (2)

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise indicated.

Values

Application

Symbol Pins

Test

Item

Condition

Min. Typ. Max. Unit

Allowable output low I_OL

current (per pin)

Output pins except

P84 to P80, SCL, and

SDA

V

_CC= 4.0 V to 5.5 V —

—

2.0

mA

P84 to P80

—

20.0 mA

0.5 mA

Output pins except

P84 to P80, SCL, and

SDA

P84 to P80

SCL, SDA

—

10.0 mA

6.0 mA

Allowable output low ∑I_OL

current (total)

Output pins except

P84 to P80, SCL, and

SDA

V

_CC= 4.0 V to 5.5 V —

40.0 mA

P84 to P80, SCL, and

SDA

—

80.0 mA

20.0 mA

Output pins except

P84 to P80, SCL, and

SDA

P84 to P80, SCL, and

SDA

—

40.0 mA

Allowable output high I –I_OH

current (per pin)

I

Output pins except

P56, P57

V_CC= 4.0 V to 5.5 V —

—

4.0

0.2

2.0

0.2

mA

—

P56, P57

V_CC= 4.0 V to 5.5 V —

—

V_CC= 4.0 V to 5.5 V —

—

Allowable output high I –∑I_OHI All output pins

current (total)

40.0 mA

8.0 mA

Rev. 3.00 Sep. 14, 2006 Page 320 of 408

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Section 20 Electrical Characteristics

20.2.3 AC Characteristics

Table 20.3 AC Characteristics

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable

Symbol Pins

Test

Condition

Reference

Item

Min. Typ. Max. Unit Figure

System clock

f_OSC

OSC1, OSC2

2.0

—

12.0 MHz

oscillation frequency

1

System clock (φ) cycle t_cyc

time

1

—

64

32.0 µs

t_cyc

10.0 ms

t_OSC

*

Figure 20.1

—

2

Instruction cycle time

—

Oscillation stabilization t_rc

time (crystal resonator)

OSC1, OSC2

—

Oscillation stabilization t_rc

time (ceramic

—

5.0

ms

resonator)

External clock high

width

t_CPH

t_CPL

t_CPr

OSC1

35.0

—

ns

Figure 20.1

External clock low

width

External clock rise

time

15.0 ns

External clock fall time t_CPf

OSC1

RES

NMI

—

RES pin low width*⁴

NMI pin high width

NMI pin low width

Input pin high width

t_REL

t_IHNMI

t_ILNMI

t_IH

2500 —

1500 —

—

ns

t_cyc

Figure 20.2

Figure 20.3

NMI

IRQ0 , IRQ3,

2

—

Figure 20.3

WKP5, TMCIV,

TMRIV, TRGV,

ADTRG, FTCI,

FTIOA to FTIOD

Input pin low width

t_IL

IRQ0, IRQ3,

2

—

t_cyc

WKP5, TMCIV,

TMRIV, TRGV,

ADTRG, FTCI,

FTIOA to FTIOD

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Section 20 Electrical Characteristics

Values

Applicable

Symbol Pins

Test

Condition

Reference

Item

Min. Typ. Max. Unit Figure

On-chip oscillator

f_RC

V_CC= 5.0 V

Ta = 25°C

FSEL = 0,

VCLSEL = 0

7.92*³8.0 8.08*³MHz

oscillation frequency *²

V_CC= 4.0 V to 5.5 V 7.76 8.0 8.24 MHz

FSEL = 0,

VCLSEL = 0

V

_CC= 4.0 V to 5.5 V 9.6*³10.0 10.4*³MHz

FSEL = 1,

VCLSEL = 0

Notes: 1. Determined by MA2 to MA0 in system control register 2 (SYSCR2).

2. For the oscillation frequency of the masked ROM version, refer to the electrical

characteristics specified separately.

3. The values are for reference.

4. Except when power-on reset circuit is used.

Rev. 3.00 Sep. 14, 2006 Page 322 of 408

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Section 20 Electrical Characteristics

Table 20.4 I²C Bus Interface Timing

V_CC= 3.0 to 5.5 V, V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Applicable Test

Reference

Item

Symbol Pins

Condition Min.

Typ. Max. Unit Figure

SCL input cycle time

t_SCL

12t_cyc+ 600 



ns

Figure

20.4

SCL input high pulse

width

t_SCLH

3t_cyc+ 300



SCL input low pulse

width

t_SCLL

5t_cyc+ 300



ns

SCL and SDA input fall t_Sf

time



300 ns

1t_cycns

SCL and SDA input

spike pulse removal

time

t_SP

SDA input bus-free

time

t_BUF

5t_cyc

3t_cyc



ns

Start condition input

hold time

t_STAH

t_STAS

Retransmission start

condition input setup

time

Setup time for stop

condition input

t_STOS

3t_cyc



ns

Data input setup time

Data input hold time

t_SDAS

t_SDAH

c_b

1t_cyc+ 20



ns

0

Capacitive load of

SCL and SDA

400 pF

SCL and SDA output

fall time

t_Sf

V_CC= 4.0

to 5.5 V



250 ns

300 ns

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Section 20 Electrical Characteristics

Table 20.5 Serial Interface (SCI3) Timing

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable Test

Reference

Unit Figure

Item

Symbol

Pins

Condition Min.

Typ.

Max.

Input

clock

cycle

Asynchro-

nous

t_scyc

SCK3

4

—

t_cyc

Figure

20.5

Clocked

6

—

t_cyc

synchronous

Input clock pulse width t_SCKW

SCK3

TXD

0.4

—

0.6

1

t_scyc

t_cyc

Transmit data delay

time (clocked

t_TXD

t_RXS

t_RXH

Figure

20.6

synchronous)

Receive data setup

time (clocked

RXD

83.3

—

ns

synchronous)

Receive data hold

time (clocked

synchronous)

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Section 20 Electrical Characteristics

20.2.4 A/D Converter Characteristics

Table 20.6 A/D Converter Characteristics

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable Test

Item

Symbol

Pins

Condition

Min.

Typ.

Max.

Unit Notes

1

*

Analog power supply

voltage

AV_CC

3.0

V_CC

5.5

V

Analog input voltage

AV_IN

AI_OPE

AN3 to AN0

AV_CC

V_SS

0.3

–

—

AV_CC

0.3

+

V

Analog power supply

current

AV_CC= 5.0 V

f_OSC= 12 MHz

—

2.0

mA

2

*

AI_STOP1

AV_CC

—

50

—

µA

Reference

value

3

*

AI_STOP2

AV_CC

—

5.0

µA

pF

kΩ

Analog input capacitance C_AIN

AN3 to AN0

30.0

5.0

Allowable signal source R_AIN

impedance

Resolution (data length)

10

—

10

—

bit

t_cyc

Conversion time (single

mode)

AV_CC= 3.0 V 134

to 5.5 V

Nonlinearity error

Offset error

—

7.5

0.5

8.0

—

LSB

t_cyc

Full-scale error

Quantization error

Absolute accuracy

Conversion time (single

mode)

AV_CC= 4.0 V 70

to 5.5 V

Nonlinearity error

Offset error

—

7.5

0.5

8.0

LSB

Full-scale error

Quantization error

Absolute accuracy

Rev. 3.00 Sep. 14, 2006 Page 325 of 408

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Section 20 Electrical Characteristics

Values

Typ.

—

Applicable Test

Pins Condition

Item

Symbol

Min.

Max.

Unit Notes

Conversion time (single

mode)

AV_CC= 4.0 V 134

to 5.5 V

—

t_cyc

Nonlinearity error

Offset error

—

3.5

0.5

4.0

LSB

Full-scale error

Quantization error

Absolute accuracy

Notes: 1. Set AV_CC= V_CCwhen the A/D converter is not used.

2. AI_STOP1is the current in active and sleep modes while the A/D converter is idle.

3. AI_STOP2is the current at reset and in standby and subsleep modes while the A/D

converter is idle.

20.2.5 Watchdog Timer Characteristics

Table 20.7 Watchdog Timer Characteristics

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable Test

Item

Symbol

Pins

Condition

Min.

Typ.

Max.

Unit Notes

Internal

oscillator

overflow

time

t_OVF

0.2

0.4

—

s

*

Note:

*

Shows the time to count from 0 to 255, at which point an internal reset is generated,

when the internal oscillator is selected.

Rev. 3.00 Sep. 14, 2006 Page 326 of 408

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Section 20 Electrical Characteristics

20.2.6 Power-Supply-Voltage Detection Circuit Characteristics

Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics

V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Test

Item

Symbol Condition

Min.

Typ.

Max. Unit

Power-supply falling detection

voltage

Vint(D)

LVDSEL = 0

3.3

3.7

4.3

V

Power-supply rising detection

voltage

Vint(U)

LVDSEL = 0

3.6

4.0

4.5

V

Reset detection voltage 1*¹

Reset detection voltage 2*²

Vreset1 LVDSEL = 0

Vreset2 LVDSEL = 1

V_LVDRmin

2.0

3.0

1.0

2.3

3.6

—

2.7

4.2

—

V

Lower-limit voltage of LVDR

operation*³

LVD stabilization time

t_LVDON

50

—

µs

Current consumption in standby I_STBY

mode

LVDE = 1,

BGRE = 1

Vcc = 5.0 V



350

µA

Notes: 1. This voltage should be used when the falling and rising voltage detection function is

used.

2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.

3. When the power-supply voltage (Vcc) falls below V_LVDRmin= 1.0 V and then rises, a reset

may not occur. Therefore sufficient evaluation is required.

20.2.7 LVDI External Voltage Detection Circuit Characteristics

Table 20.9 LVDI External Voltage Detection Circuit Characteristics

Vcc = 4.5 to 5.5 V, AVcc = 3.0 to 5.5 V, V_SS= 0.0 V, T_a= –20 to +75°C

Values

Test

Item

Symbol Condition

Min.

Typ.

Max.

Unit

ExtD/ExtU input

detection voltage

Vexd

0.85

1.15

1.45

V

ExtD/ExtU input voltage VextD/U VextD > VextU

range

−0.3

—

Lower voltage,

either AVcc + 0.3

or Vcc + 0.3

V

Rev. 3.00 Sep. 14, 2006 Page 327 of 408

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Section 20 Electrical Characteristics

20.2.8 Power-On Reset Characteristics

Table 20.10 Power-On Reset Circuit Characteristics

V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Test

Item

Symbol

R_RES

Condition

Min.

100

—

Typ.

150

—

Max. Unit

Pull-up resistance of RES pin

Power-on reset start voltage*

—

kΩ

V_por

100

mV

Note:

*

The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after

charge of the RES pin is removed completely. In order to remove charge of the RES

pin, it is recommended that the diode be placed in the Vcc side. If the power-supply

voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.

Rev. 3.00 Sep. 14, 2006 Page 328 of 408

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Section 20 Electrical Characteristics

20.2.9 Flash Memory Characteristics

Table 20.11 Flash Memory Characteristics

V_CC= 3.0 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Test

Item

Symbol Condition

Min. Typ. Max. Unit

Programming time (per 128 bytes)*¹*²*⁴t_P

—

7

200

ms

Erase time (per block) *¹*³*⁶

t_E

100

1200 ms

Reprogramming count

N_WEC

x

1000 10000 —

Times

µs

Programming Wait time after SWE

1

—

bit setting*¹

Wait time after PSU

y

50

—

µs

bit setting*¹

Wait time after P bit

z1

z2

z3

1 ≤ n ≤ 6

28

30

32

µs

setting*¹*⁴

7 ≤ n ≤ 1000 198

200

10

202

12

Additional-

8

programming

Wait time after P bit

α

β

γ

5

—

µs

clear*¹

Wait time after PSU

5

bit clear*¹

Wait time after PV

4

bit setting*¹

Wait time after

ε

2

dummy write*¹

Wait time after PV

η

θ

N

2

bit clear*¹

Wait time after SWE

100

—

bit clear*¹

Maximum

1000 Times

programming count*¹*⁴*⁵

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Section 20 Electrical Characteristics

Values

Test

Item

Symbol Condition

Min. Typ. Max. Unit

Erase

Wait time after SWE

x

y

z

α

β

γ

1

—

µs

bit setting*¹

Wait time after ESU

100

10

20

2

—

µs

bit setting*¹

Wait time after E bit

100

—

ms

µs

setting*¹*⁶

Wait time after E bit

clear*¹

Wait time after ESU

—

µs

bit clear*¹

Wait time after EV

—

µs

bit setting*¹

Wait time after

ε

—

µs

dummy write*¹

Wait time after EV

η

θ

N

4

—

µs

bit clear*¹

Wait time after SWE

100

—

µs

bit clear*¹

Maximum erase

120

Times

count*¹*⁶*⁷

Notes: 1. Make the time settings in accordance with the program/erase algorithms.

2. The programming time for 64 bytes. (Indicates the total time for which the P bit in flash

memory control register 1 (FLMCR1) is set. The program-verify time is not included.)

3. The time required to erase one block. (Indicates the time for which the E bit in flash

memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)

4. Programming time maximum value (t_P(max.)) = wait time after P bit setting (z) ×

maximum programming count (N)

5. Set the maximum programming count (N) according to the actual set values of z1, z2,

and z3, so that it does not exceed the programming time maximum value (t_P(max.)).

The wait time after P bit setting (z1, z2) should be changed as follows according to the

value of the programming count (n).

Programming count (n)

1 ≤ n ≤ 6

z1 = 30 µs

7 ≤ n ≤ 1000 z2 = 200 µs

6. Erase time maximum value (t_E(max.)) = wait time after E bit setting (z) × maximum

erase count (N)

7. Set the maximum erase count (N) according to the actual set value of (z), so that it

does not exceed the erase time maximum value (t_E(max.)).

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Section 20 Electrical Characteristics

20.3

Electrical Characteristics (Masked ROM Version)

20.3.1 Power Supply Voltage and Operating Ranges

1. Supply voltage and external oscillation frequency range

φosc(MHz)

12.0

2.0

2.7

5.5

Vcc(V)

AVcc = 2.7 to 5.5 V

• Active mode

• Sleep mode

2. Power supply voltage and operating frequency range

φosc(MHz)

φ(kHz)

12.0

1500

2.0

31.25

2.7

AVcc = 2.7 to 5.5 V

5.5

2.7

AVcc = 2.7 to 5.5 V

5.5

Vcc(V)

• Active mode

• Sleep mode

• Active mode

• Sleep mode

(When MA2 = 0 in SYSCR2)

(When MA2 = 1 in SYSCR2)

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Section 20 Electrical Characteristics

3. Analog power supply voltage and A/D converter accuracy guarantee range

φosc(MHz)

12.0

2.0

2.7

Vcc = 2.7 to 5.5 V

5.5

AVcc(V)

• Active mode

• Sleep mode

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Section 20 Electrical Characteristics

20.3.2 DC Characteristics

Table 20.12 DC Characteristics (1)

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C unless otherwise indicated.

Values

Applicable

Symbol Pins

Test

Condition

Item

Min.

Typ. Max.

Unit

V

Notes

Input high V_IH

voltage

RES, NMI, WKP5, V_CC= 4.0 V to 5.5 V

IRQ0, IRQ3,

V_CC× 0.8

V_CC× 0.9

—

V_CC+ 0.3

V

ADTRG, TMRIV,

TMCIV, FTCI,

FTIOA to FTIOD,

SCK3, TRGV

RXD, SCL, SDA, V_CC= 4.0 V to 5.5 V

P17, P14,

V_CC× 0.7

V_CC× 0.8

—

V_CC+ 0.3

V

P22 to P20,

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

PB3 to PB0

AV_CC= 4.0 V to 5.5 V AV_CC× 0.7

AV_CC= 2.7 V to 5.5 V AV_CC× 0.8

—

AV_CC+ 0.3 V

OSC1

V_CC= 4.0 V to 5.5 V

V_CC– 0.5

V_CC– 0.3

–0.3

V_CC+ 0.3

V_CC× 0.2

V

RES, NMI, WKP5,

IRQ0, IRQ3,

Input low V_IL

voltage

V_CC= 4.0 V to 5.5 V

—

ADTRG, TMRIV,

TMCIV, FTCI,

–0.3

V_CC× 0.1

V_CC× 0.3

V

FTIOA to FTIOD,

SCK3, TRGV

RXD, SCL, SDA, V_CC= 4.0 V to 5.5 V

P17, P14,

P22 to P20,

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

–0.3

—

V_CC× 0.2

V

PB3 to PB0

AV_CC= 4.0 V to 5.5 V –0.3

AV_CC= 2.7 V to 5.5 V –0.3

—

AV_CC× 0.3

AV_CC× 0.2

0.5

OSC1

V_CC= 4.0 V to 5.5 V

–0.3

V

0.3

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Section 20 Electrical Characteristics

Values

Typ.

—

Applicable

Symbol Pins

Test

Condition

Item

Min.

Max.

Unit Notes

Output

high

voltage

V_OHP17, P14,

V_CC= 4.0 V to 5.5 V V_CC

–

—

V

P22 to P20,

P55,

P76 to P74,

P84 to P80,

PC1, PC0

1.0

–I_OH= 4 mA

–I_OH= 0.1 mA

V_CC

0.5

–

—

V

P56, P57

V_CC= 4.0 V to 5.5 V V_CC

–

—

V

2.5

–I_OH= 0.1 mA

V

_CC= 2.7 V to 4.0 V V_CC

2.2

—

–I_OH= 0.1 mA

Output low V_OL

voltage

P17, P14,

V_CC= 4.0 V to 5.5 V

I_OL= 1.6 mA

—

0.6

P22 to P20,

P57 to P55,

P76 to P74,

PC1, PC0

I

_OL= 0.4 mA

—

0.4

1.5

V

P84 to P80

V_CC= 4.0 V to 5.5 V

I_OL= 20.0 mA

V_CC= 4.0 V to 5.5 V

I_OL= 10.0 mA

—

1.0

0.4

V

V_CC= 4.0 V to 5.5 V

I_OL= 1.6 mA

I_OL= 0.4 mA

—

0.4

0.6

V

SCL, SDA

V_CC= 4.0 V to 5.5 V

I_OL= 6.0 mA

I

_OL= 3.0 mA

_IN= 0.5 V to

(V_CC– 0.5 V)

—

0.4

1.0

V

Input/

| I_IL

|

OSC1, NMI,

V

µA

output

leakage

current

WKP5,

IRQ0, IRQ3,

ADTRG, TRGV,

TMRIV, TMCIV,

FTCI, FTIOA to

FTIOD, RXD,

SCK3, SCL, SDA

P17, P14,

V

_IN= 0.5 V to

—

1.0

µA

P22 to P20,

P57 to P55,

P76 to P74,

P84 to P80,

PC1, PC0

(V_CC– 0.5 V)

PB3 to PB0

V_IN= 0.5 V to

(AV_CC– 0.5 V)

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Section 20 Electrical Characteristics

Values

Applicable

Symbol Pins

Test

Condition

Item

Min.

Typ. Max.

Unit Notes

–I_p

P17, P14, P55

V_CC= 5.0 V,

50.0

—

300.0

µA

Pull-up

MOS

current

V

_IN= 0.0 V

V_CC= 2.7 V,

_IN= 0.0 V

f = 1 MHz,

_IN= 0.0 V,

—

60.0

—

µA Reference

value

V

Input

capaci-

tance

C_in

All input pins

except power

supply pins

15.0

pF

V

T_a= 25°C

Active

mode

current

consump-

tion

I_OPE1

V_CC

Active mode 1

—

12.0

9.6

2.0

1.5

7.2

6.0

1.8

1.4

—

18.0

—

mA

*

V

_CC= 5.0 V,

f_OSC= 12 MHz

Active mode 1

_CC= 2.7 V,

_OSC= 12 MHz

mA Reference

V

value*

f

I_OPE2

Active mode 2

_CC= 5.0 V,

_OSC= 12 MHz

2.5

—

mA

*

V

f

Active mode 2

_CC= 2.7 V,

_OSC= 12 MHz

mA Reference

V

value*

f

Sleep

mode

current

consump-

tion

I_SLEEP1

Sleep mode 1

_CC= 5.0 V,

_OSC= 12 MHz

12.0

—

mA

*

V

f

Sleep mode 1

_CC= 2.7 V,

_OSC= 12 MHz

mA Reference

V

value*

f

I_SLEEP2

Sleep mode 2

_CC= 5.0 V,

_OSC= 12 MHz

2.2

—

mA

*

V

f

Sleep mode 2

_CC= 2.7 V,

_OSC= 12 MHz

mA Reference

V

value*

f

Subsleep I_SUBSP

mode

current

consump-

tion

V_CC

V_CC= 5.0 V

LVDE = 0,

BGRE = 0

5.0

µA

*

Standby

mode

I_STBY

V_CC

LVDE = 0,

BGRE = 0

—

5.0

*

current

consump-

tion

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Section 20 Electrical Characteristics

Values

Applicable

Test

Item

Symbol Pins

Condition

Min.

Typ. Max.

Unit Notes

RAM data V_RAM

retaining

V_CC

2.0

—

V

voltage

Note:

*

Pin states during current consumption measurement are given below (excluding current

in the pull-up MOS transistors and output buffers).

Mode

RES Pin

Internal State

Other Pins

Oscillator Pins

Active mode 1

Active mode 2

Sleep mode 1

Sleep mode 2

V_CC

Operates

V_CC

System clock:

Crystal or ceramic

resonator, and on-chip

oscillator

Operates (φ/64)

V_CC

Only timers operate

Only timers operate (φ/64)

CPU and timers both stop

V_CC

Subsleep mode

Standby mode

—

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Section 20 Electrical Characteristics

Table 20.12 DC Characteristics (2)

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise indicated.

Values

Application

Symbol Pins

Test

Item

Condition

Min.

Typ. Max. Unit

Allowable output low I_OL

current (per pin)

Output pins except

P84 to P80, SCL,

and SDA

V

_CC= 4.0 V to 5.5 V —

—

2.0

mA

P84 to P80

—

20.0

0.5

mA

Output pins except

P84 to P80, SCL,

and SDA

P84 to P80

SCL, SDA

—

10.0

6.0

mA

Allowable output low ∑I_OL

current (total)

Output pins except

P84 to P80, SCL,

and SDA

V

_CC= 4.0 V to 5.5 V —

40.0

P84 to P80, SCL,

and SDA

—

80.0

20.0

mA

Output pins except

P84 to P80, SCL,

and SDA

P84 to P80, SCL,

and SDA

—

40.0

mA

Allowable output high I –I_OH

current (per pin)

I

Output pins except V_CC= 4.0 V to 5.5 V —

—

4.0

0.2

2.0

0.2

40.0

8.0

mA

P56, P57

—

P56, P57

V_CC= 4.0 V to 5.5 V —

—

V_CC= 4.0 V to 5.5 V —

—

Allowable output high I –∑I_OH

current (total)

I

All output pins

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Section 20 Electrical Characteristics

20.3.3 AC Characteristics

Table 20.13 AC Characteristics

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable

Symbol Pins

Test

Condition

Reference

Max. Unit Figure

Item

Min.

Typ.

System clock

oscillation

f_OSC

OSC1, OSC2

2.0

—

12.0

MHz

frequency

System clock (φ)

cycle time

t_cyc

1

—

64

t_OSC

µs

*

Figure 20.1

—

2

32.0

—

Instruction cycle

time

t_cyc

Oscillation

stabilization time

(crystal resonator)

t_rc

OSC1, OSC2

—

10.0

5.0

ms

Oscillation

t_rc

stabilization time

(ceramic resonator)

External clock high t_CPH

width

OSC1

35.0

—

ns

Figure 20.1

External clock low t_CPL

width

—

External clock rise t_CPr

time

15.0

External clock fall t_CPf

time

—

RES pin low width* t_REL

NMI pin high width t_IHNMI

NMI pin low width t_ILNMI

Input pin high width t_IH

RES

NMI

2500

1500

2

—

ns

t_cyc

Figure 20.2

Figure 20.3

IRQ0 , IRQ3,

Figure 20.3

WKP5,TMCIV,

TMRIV, TRGV,

ADTRG, FTCI,

FTIOA to FTIOD

Note:

*

Except when power-on reset circuit is used.

Rev. 3.00 Sep. 14, 2006 Page 338 of 408

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Section 20 Electrical Characteristics

Values

Applicable

Symbol Pins

Test

Condition

Reference

Max. Unit Figure

Item

Min.

Typ.

Input pin low width t_IL

IRQ0, IRQ3,

2

—

t_cyc

Figure 20.3

WKP5, TMCIV,

TMRIV, TRGV,

ADTRG, FTCI,

FTIOA to FTIOD

On-chip oscillator f_RC

oscillation

frequency

V_CC= 4.0 V to

5.5 V

FSEL = 0,

VCLSEL = 0

7.6

9.4

8.0

8.4

MHz

V

_CC= 4.0 V to

10.0

10.6

5.5 V

FSEL = 1,

VCLSEL = 0

Notes: * Determined by MA2 to MA0 in system control register 2 (SYSCR2).

Rev. 3.00 Sep. 14, 2006 Page 339 of 408

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Section 20 Electrical Characteristics

Table 20.14 I²C Bus Interface Timing

V_CC= 2.7 to 5.5 V, V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Applicable Test

Reference

Item

Symbol

Pins

Condition Min.

Typ. Max. Unit Figure

SCL input cycle time t_SCL

12t_cyc+ 600 



ns Figure

20.4

SCL input high pulse t_SCLH

width

3t_cyc+ 300



ns

SCL input low pulse

width

t_SCLL

5t_cyc+ 300



ns

SCL and SDA input

fall time

t_Sf



300 ns

1t_cycns

SCL and SDA input

spike pulse removal

time

t_SP

SDA input bus-free

time

t_BUF

5t_cyc

3t_cyc



ns

Start condition input

hold time

t_STAH

Retransmission start t_STAS

condition input setup

time

Setup time for stop

condition input

t_STOS

3t_cyc



ns

Data input setup time t_SDAS

1t_cyc+ 20



ns

Data input hold time

t_SDAH

c_b

0

Capacitive load of

SCL and SDA

400 pF

SCL and SDA output t_Sf

fall time

V_CC= 4.0 to 



250 ns

5.5 V



300 ns

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Section 20 Electrical Characteristics

Table 20.15 Serial Interface (SCI3) Timing

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable Test

Reference

Unit Figure

Item

Symbol

Pins

Condition Min.

Typ.

Max.

Input

clock

cycle

Asynchro-

nous

t_scyc

SCK3

4

—

t_cyc

Figure

20.5

Clocked

6

—

t_cyc

synchronous

Input clock pulse width t_SCKW

SCK3

TXD

0.4

—

0.6

1

t_scyc

t_cyc

Transmit data delay

time (clocked

t_TXD

t_RXS

t_RXH

Figure

20.6

synchronous)

Receive data setup

time (clocked

RXD

83.3

—

ns

synchronous)s

Receive data hold

time (clocked

synchronous)

Rev. 3.00 Sep. 14, 2006 Page 341 of 408

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Section 20 Electrical Characteristics

20.3.4 A/D Converter Characteristics

Table 20.16 A/D Converter Characteristics

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Applicable Test

Item

Symbol Pins

Condition

Min.

Typ. Max.

Unit Notes

1

*

Analog power supply

voltage

AV_CC

2.7

V_CC5.5

V

Analog input voltage

AV_IN

AI_OPE

AN3 to AN0

AV_CC

V_SS– 0.3 —

AV_CC+ 0.3 V

Analog power supply

current

AV_CC= 5.0 V

f_OSC= 12 MHz

—

2.0

mA

2

*

AI_STOP1

AV_CC

—

50

—

µA

Reference

value

3

*

AI_STOP2

C_AIN

AV_CC

—

5.0

µA

pF

Analog input

capacitance

AN3 to AN0

30.0

Allowable signal source R_AIN

impedance

AN3 to AN0

—

5.0

kΩ

Resolution (data length)

10

—

10

—

bit

t_cyc

Conversion time (single

mode)

AV_CC= 2.7 V 134

to 5.5 V

Nonlinearity error

Offset error

—

7.5

0.5

8.0

—

LSB

t_cyc

Full-scale error

Quantization error

Absolute accuracy

Conversion time (single

mode)

AV_CC= 4.0 V 70

to 5.5 V

Nonlinearity error

Offset error

—

7.5

0.5

8.0

LSB

Full-scale error

Quantization error

Absolute accuracy

Rev. 3.00 Sep. 14, 2006 Page 342 of 408

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Section 20 Electrical Characteristics

Values

Applicable Test

Pins Condition

Item

Symbol

Min.

Typ.

Max.

Unit Notes

Conversion time (single

mode)

AV_CC= 4.0 V 134

to 5.5 V

—

t_cyc

Nonlinearity error

Offset error

—

3.5

0.5

4.0

LSB

Full-scale error

Quantization error

Absolute accuracy

Notes: 1. Set AV_CC= V_CCwhen the A/D converter is not used.

2. AI_STOP1is the current in active and sleep modes while the A/D converter is idle.

3. AI_STOP2is the current at reset and in standby and subsleep modes while the A/D

converter is idle.

20.3.5 Watchdog Timer Characteristics

Table 20.17 Watchdog Timer Characteristics

V_CC= 2.7 V to 5.5 V, V_SS= 0.0 V, T_a= –20°C to +75°C, unless otherwise specified.

Values

Test

Applicable

Pins

Item

Symbol

Condition Min. Typ. Max. Unit Notes

Internal oscillator

overflow time

t_OVF

0.2

0.4

—

s

*

Note:

*

Shows the time to count from 0 to 255, at which point an internal reset is generated,

when the internal oscillator is selected.

Rev. 3.00 Sep. 14, 2006 Page 343 of 408

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Section 20 Electrical Characteristics

20.3.6 Power-Supply-Voltage Detection Circuit Characteristics

Table 20.18 Power-Supply-Voltage Detection Circuit Characteristics

V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Test

Item

Symbol

Condition

Min.

Typ.

Max. Unit

Power-supply falling detection

voltage

Vint(D)

LVDSEL = 0 3.3

3.7

4.3

V

Power-supply rising detection

voltage

Vint(U)

LVDSEL = 0 3.6

4.0

4.5

V

Reset detection voltage 1*¹

Reset detection voltage 2*²

Vreset1

Vreset2

V_LVDRmin

LVDSEL = 0 2.0

LVDSEL = 1 3.0

1.0

2.3

3.6

—

2.7

4.2

—

V

Lower-limit voltage of LVDR

operation*³

LVD stabilization time

t_LVDON

I_STBY

50

—

µs

Current consumption in standby

mode

LVDE = 1,

BGRE = 1

Vcc = 5.0 V



350

µA

Notes: 1. This voltage should be used when the falling and rising voltage detection function is

used.

2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.

3. When the power-supply voltage (Vcc) falls below V_LVDRmin= 1.0 V and then rises, a reset

may not occur. Therefore sufficient evaluation is required.

20.3.7 LVDI External Voltage Detection Circuit Characteristics

Table 20.19 LVDI External Voltage Detection Circuit Characteristics

Vcc = 4.5 to 5.5 V, AVcc = 2.7 to 5.5 V, V_SS= 0.0 V, T_a= –20 to +75°C

Values

Test

Item

Symbol Condition

Min.

Typ.

Max.

Unit

ExtD/ExtU input

detection voltage

Vexd

0.85

1.15

1.45

V

ExtD/ExtU input voltage VextD/U VextD > VextU

range

−0.3

—

Lower voltage,

either AVcc + 0.3

or Vcc + 0.3

V

Rev. 3.00 Sep. 14, 2006 Page 344 of 408

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Section 20 Electrical Characteristics

20.3.8 Power-On Reset Characteristics

Table 20.20 Power-On Reset Circuit Characteristics

V_SS= 0.0 V, T_a= –20 to +75°C, unless otherwise indicated.

Values

Test

Item

Symbol

Condition

Min.

100

—

Typ.

150

—

Max.

—

Unit

kΩ

Pull-up resistance of RES pin R_RES

Power-on reset start voltage* V_por

100

mV

Note:

*

The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after

charge of the RES pin is removed completely. In order to remove charge of the RES

pin, it is recommended that the diode be placed in the Vcc side. If the power-supply

voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.

Rev. 3.00 Sep. 14, 2006 Page 345 of 408

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Section 20 Electrical Characteristics

20.4

Operation Timing

tOSC

V

IH

IL

OSC1

V

tCPH

tCPL

tCPr

tCPf

Figure 20.1 System Clock Input Timing

Vcc × 0.7

Vcc

OSC1

t

REL

RES

VIL

V

IL

t

REL

Figure 20.2 RES Low Width Timing

IRQ0, IRQ3

WKP5, NMI

ADTRG

V

IH

IL

V

FTCI, FTIOA

FTIOB, FTIOC

FTIOD

tIL

tIH

TMCIV, TMRIV

TRGV

Figure 20.3 Input Timing

Rev. 3.00 Sep. 14, 2006 Page 346 of 408

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Section 20 Electrical Characteristics

V_IH

V_IL

SDA

SCL

t_BUF

t_STAH

t_SP

t_STOS

t_SCLH

t_STAS

P*

S*

Sr*

P*

t_SCLL

t_SDAS

t_Sf

t_Sr

t_SCL

t_SDAH

Note: * S, P, and Sr represent the following:

S: Start condition

P: Stop comdition

Sr: Retransmission start condition

Figure 20.4 I²C Bus Interface Input/Output Timing

t

SCKW

SCK3

t

scyc

Figure 20.5 SCK3 Input Clock Timing

Rev. 3.00 Sep. 14, 2006 Page 347 of 408

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Section 20 Electrical Characteristics

t_scyc

*

V_IHor V_OH

SCK3

*

V_ILor V_OL

t_TXD

*

V_OH

TXD

(transmit data)

*

V_OL

t_RXS

t_RXH

RXD

(receive data)

*

Note:

Output timing reference levels

Output high:

Output low:

V

= 2.0 V

OH

= 0.8 V

OL

Load conditions are shown in figure 20.7.

Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode

20.5

Output Load Condition

V_CC

2.4 kΩ

LSI output pin

30 pF

12 kΩ

Figure 20.7 Output Load Circuit

Rev. 3.00 Sep. 14, 2006 Page 348 of 408

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Appendix

Appendix A Instruction Set

A.1

Instruction List

•

Operand Notation

Symbol

Description

Rd

General (destination*) register

General (source*) register

General register*

Rs

Rn

ERd

ERs

ERn

(EAd)

(EAs)

PC

SP

General destination register (address register or 32-bit register)

General source register (address register or 32-bit register)

General register (32-bit register)

Destination operand

Source operand

Program counter

Stack pointer

CCR

N

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

Z

V

V (overflow) flag in CCR

C (carry) flag in CCR

C

disp

→

Displacement

Transfer from the operand on the left to the operand on the right, or transition from

the state on the left to the state on the right

+

–

×

÷

∧

∨

⊕

¬

Addition of the operands on both sides

Subtraction of the operand on the right from the operand on the left

Multiplication of the operands on both sides

Division of the operand on the left by the operand on the right

Logical AND of the operands on both sides

Logical OR of the operands on both sides

Logical exclusive OR of the operands on both sides

NOT (logical complement)

Rev. 3.00 Sep. 14, 2006 Page 349 of 408

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Appendix

Symbol

Description

( ), < >

Contents of operand

Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers

(R0 to R7 and E0 to E7).

•

Condition Code Notation

Symbol

Description

Changed according to execution result

Undetermined (no guaranteed value)

Cleared to 0

*

0

1

Set to 1

—

∆

Not affected by execution of the instruction

Varies depending on conditions, described in notes

Rev. 3.00 Sep. 14, 2006 Page 350 of 408

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Appendix

Table A.1 Instruction Set

•

Data transfer instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

MOV.B #xx:8, Rd

B

2

#xx:8 → Rd8

—

0

—

2

MOV

MOV.B Rs, Rd

2

4

8

2

Rs8 → Rd8

MOV.B @ERs, Rd

MOV.B @(d:16, ERs), Rd

MOV.B @(d:24, ERs), Rd

MOV.B @ERs+, Rd

@ERs → Rd8

4

@(d:16, ERs) → Rd8

@(d:24, ERs) → Rd8

6

10

6

@ERs → Rd8

ERs32+1 → ERs32

MOV.B @aa:8, Rd

B

2

@aa:8 → Rd8

—

0

—

4

6

MOV.B @aa:16, Rd

MOV.B @aa:24, Rd

MOV.B Rs, @ERd

4

@aa:16 → Rd8

@aa:24 → Rd8

Rs8 → @ERd

6

8

2

4

8

2

4

MOV.B Rs, @(d:16, ERd)

MOV.B Rs, @(d:24, ERd)

MOV.B Rs, @–ERd

Rs8 → @(d:16, ERd)

Rs8 → @(d:24, ERd)

6

10

6

ERd32–1 → ERd32

Rs8 → @ERd

MOV.B Rs, @aa:8

B

2

4

6

Rs8 → @aa:8

—

0

—

4

6

MOV.B Rs, @aa:16

MOV.B Rs, @aa:24

MOV.W #xx:16, Rd

MOV.W Rs, Rd

Rs8 → @aa:16

Rs8 → @aa:24

#xx:16 → Rd16

Rs16 → Rd16

B

8

W

4

2

4

8

2

MOV.W @ERs, Rd

MOV.W @(d:16, ERs), Rd

MOV.W @(d:24, ERs), Rd

MOV.W @ERs+, Rd

@ERs → Rd16

@(d:16, ERs) → Rd16

@(d:24, ERs) → Rd16

4

6

10

6

@ERs → Rd16

ERs32+2 → @ERd32

MOV.W @aa:16, Rd

MOV.W @aa:24, Rd

MOV.W Rs, @ERd

W

4

@aa:16 → Rd16

—

0

—

6

8

6

@aa:24 → Rd16

2

4

8

Rs16 → @ERd

4

MOV.W Rs, @(d:16, ERd)

MOV.W Rs, @(d:24, ERd)

Rs16 → @(d:16, ERd)

Rs16 → @(d:24, ERd)

6

10

Rev. 3.00 Sep. 14, 2006 Page 351 of 408

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Appendix

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

MOV.W Rs, @–ERd

W

2

ERd32–2 → ERd32

Rs16 → @ERd

—

0

—

6

MOV

MOV.W Rs, @aa:16

MOV.W Rs, @aa:24

MOV.L #xx:32, Rd

W

L

4

6

Rs16 → @aa:16

—

0

—

6

8

Rs16 → @aa:24

6

#xx:32 → Rd32

6

MOV.L ERs, ERd

L

2

ERs32 → ERd32

@ERs → ERd32

2

MOV.L @ERs, ERd

MOV.L @(d:16, ERs), ERd

MOV.L @(d:24, ERs), ERd

MOV.L @ERs+, ERd

L

4

8

L

6

@(d:16, ERs) → ERd32

@(d:24, ERs) → ERd32

10

14

10

L

10

4

L

@ERs → ERd32

ERs32+4 → ERs32

MOV.L @aa:16, ERd

MOV.L @aa:24, ERd

MOV.L ERs, @ERd

L

6

@aa:16 → ERd32

—

0

—

10

12

8

@aa:24 → ERd32

4

ERs32 → @ERd

MOV.L ERs, @(d:16, ERd)

MOV.L ERs, @(d:24, ERd)

MOV.L ERs, @–ERd

6

ERs32 → @(d:16, ERd)

ERs32 → @(d:24, ERd)

10

14

10

4

ERd32–4 → ERd32

ERs32 → @ERd

MOV.L ERs, @aa:16

MOV.L ERs, @aa:24

POP.W Rn

L

6

8

ERs32 → @aa:16

ERs32 → @aa:24

—

0

—

10

12

6

W

2

4

2

4

@SP → Rn16

SP+2 → SP

POP

POP.L ERn

PUSH.W Rn

PUSH.L ERn

L

W

L

@SP → ERn32

SP+4 → SP

—

0

—

10

6

SP–2 → SP

Rn16 → @SP

PUSH

SP–4 → SP

10

ERn32 → @SP

Cannot be used in

this LSI

_MOVFPEMOVFPE @aa:16, Rd

_MOVTPEMOVTPE Rs, @aa:16

B

Cannot be used in

this LSI

4

Cannot be used in

this LSI

Cannot be used in

this LSI

Rev. 3.00 Sep. 14, 2006 Page 352 of 408

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Appendix

•

Arithmetic instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

ADD.B #xx:8, Rd

ADD.B Rs, Rd

B

2

4

6

Rd8+#xx:8 → Rd8

Rd8+Rs8 → Rd8

—

2

4

2

6

ADD

2

ADD.W #xx:16, Rd

ADD.W Rs, Rd

W

L

Rd16+#xx:16 → Rd16

Rd16+Rs16 → Rd16

— (1)

— (2)

ADD.L #xx:32, ERd

ERd32+#xx:32 →

ERd32

ADD.L ERs, ERd

L

2

ERd32+ERs32 →

— (2)

2

ERd32

ADDX.B #xx:8, Rd

ADDX.B Rs, Rd

ADDS.L #1, ERd

ADDS.L #2, ERd

ADDS.L #4, ERd

INC.B Rd

B

L

2

Rd8+#xx:8 +C → Rd8

Rd8+Rs8 +C → Rd8

ERd32+1 → ERd32

ERd32+2 → ERd32

ERd32+4 → ERd32

Rd8+1 → Rd8

—

(3)

—

2

ADDX

ADDS

2

—

*

—

L

B

W

L

INC

INC.W #1, Rd

INC.W #2, Rd

INC.L #1, ERd

INC.L #2, ERd

DAA Rd

Rd16+1 → Rd16

Rd16+2 → Rd16

ERd32+1 → ERd32

ERd32+2 → ERd32

L

B

Rd8 decimal adjust

*

DAA

SUB

→ Rd8

SUB.B Rs, Rd

B

W

L

2

Rd8–Rs8 → Rd8

—

2

4

2

6

2

SUB.W #xx:16, Rd

SUB.W Rs, Rd

SUB.L #xx:32, ERd

SUB.L ERs, ERd

SUBX.B #xx:8, Rd

SUBX.B Rs, Rd

SUBS.L #1, ERd

SUBS.L #2, ERd

SUBS.L #4, ERd

DEC.B Rd

4

6

2

Rd16–#xx:16 → Rd16

Rd16–Rs16 → Rd16

— (1)

ERd32–#xx:32 → ERd32 — (2)

ERd32–ERs32 → ERd32 — (2)

L

SUBX

SUBS

B

L

Rd8–#xx:8–C → Rd8

Rd8–Rs8–C → Rd8

ERd32–1 → ERd32

ERd32–2 → ERd32

ERd32–4 → ERd32

Rd8–1 → Rd8

—

(3)

—

2

—

L

DEC

B

W

DEC.W #1, Rd

DEC.W #2, Rd

Rd16–1 → Rd16

Rd16–2 → Rd16

Rev. 3.00 Sep. 14, 2006 Page 353 of 408

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Appendix

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

DEC.L #1, ERd

DEC.L #2, ERd

L

B

2

ERd32–1 → ERd32

ERd32–2 → ERd32

—

*

—

2

DEC

DAS DAS.Rd

Rd8 decimal adjust

*

→ Rd8

MULXU MULXU. B Rs, Rd

MULXU. W Rs, ERd

MULXS MULXS. B Rs, Rd

MULXS. W Rs, ERd

B

W

B

2

4

2

Rd8 × Rs8 → Rd16

(unsigned multiplication)

—

14

22

16

24

14

Rd16 × Rs16 → ERd32

(unsigned multiplication)

Rd8 × Rs8 → Rd16

(signed multiplication)

W

B

Rd16 × Rs16 → ERd32

(signed multiplication)

DIVXU DIVXU. B Rs, Rd

Rd16 ÷ Rs8 → Rd16

(RdH: remainder,

RdL: quotient)

— (6) (7) —

— (8) (7) —

(unsigned division)

DIVXU. W Rs, ERd

DIVXS DIVXS. B Rs, Rd

DIVXS. W Rs, ERd

W

B

2

4

ERd32 ÷ Rs16 → ERd32

(Ed: remainder,

—

22

16

24

Rd: quotient)

(unsigned division)

Rd16 ÷ Rs8 → Rd16

(RdH: remainder,

RdL: quotient)

(signed division)

W

ERd32 ÷ Rs16 → ERd32

(Ed: remainder,

Rd: quotient)

(signed division)

CMP CMP.B #xx:8, Rd

CMP.B Rs, Rd

B

2

4

6

Rd8–#xx:8

—

2

4

2

4

2

Rd8–Rs8

CMP.W #xx:16, Rd

CMP.W Rs, Rd

W

L

Rd16–#xx:16

Rd16–Rs16

ERd32–#xx:32

ERd32–ERs32

— (1)

— (2)

CMP.L #xx:32, ERd

CMP.L ERs, ERd

L

Rev. 3.00 Sep. 14, 2006 Page 354 of 408

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Appendix

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

NEG.B Rd

B

0–Rd8 → Rd8

W 0–Rd16 → Rd16

0–ERd32 → ERd32

2

—

2

NEG

NEG.W Rd

NEG.L ERd

L

EXTU EXTU.W Rd

W 0 → (<bits 15 to 8>

—

0

—

of Rd16)

EXTU.L ERd

L

0 → (<bits 31 to 16>

of ERd32)

2

—

2

EXTS EXTS.W Rd

EXTS.L ERd

W (<bit 7> of Rd16) →

(<bits 15 to 8> of Rd16)

L

(<bit 15> of ERd32) →

(<bits 31 to 16> of

ERd32)

Rev. 3.00 Sep. 14, 2006 Page 355 of 408

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Appendix

•

Logic instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

AND.B #xx:8, Rd

AND.B Rs, Rd

B

W

L

2

4

6

2

4

6

2

4

6

Rd8∧#xx:8 → Rd8

—

0

—

2

4

2

6

4

2

4

2

6

4

2

4

2

6

4

2

AND

2

4

2

4

2

Rd8∧Rs8 → Rd8

AND.W #xx:16, Rd

AND.W Rs, Rd

AND.L #xx:32, ERd

AND.L ERs, ERd

OR.B #xx:8, Rd

OR.B Rs, Rd

Rd16∧#xx:16 → Rd16

Rd16∧Rs16 → Rd16

ERd32∧#xx:32 → ERd32

ERd32∧ERs32 → ERd32

Rd8⁄#xx:8 → Rd8

L

B

W

L

OR

Rd8⁄Rs8 → Rd8

OR.W #xx:16, Rd

OR.W Rs, Rd

Rd16⁄#xx:16 → Rd16

Rd16⁄Rs16 → Rd16

ERd32⁄#xx:32 → ERd32

ERd32⁄ERs32 → ERd32

Rd8⊕#xx:8 → Rd8

Rd8⊕Rs8 → Rd8

OR.L #xx:32, ERd

OR.L ERs, ERd

L

XOR XOR.B #xx:8, Rd

XOR.B Rs, Rd

B

W

L

XOR.W #xx:16, Rd

XOR.W Rs, Rd

Rd16⊕#xx:16 → Rd16

Rd16⊕Rs16 → Rd16

ERd32⊕#xx:32 → ERd32

ERd32⊕ERs32 → ERd32

¬ Rd8 → Rd8

XOR.L #xx:32, ERd

XOR.L ERs, ERd

NOT NOT.B Rd

NOT.W Rd

L

4

2

B

W

L

¬ Rd16 → Rd16

NOT.L ERd

¬ Rd32 → Rd32

Rev. 3.00 Sep. 14, 2006 Page 356 of 408

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Appendix

•

Shift instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

SHAL.B Rd

B

W

L

2

—

2

SHAL

C

0

SHAL.W Rd

SHAL.L ERd

SHAR.B Rd

SHAR.W Rd

SHAR.L ERd

SHLL.B Rd

MSB

LSB

B

W

L

0

SHAR

SHLL

C

MSB

LSB

B

W

L

C

0

SHLL.W Rd

SHLL.L ERd

SHLR.B Rd

SHLR.W Rd

SHLR.L ERd

ROTXL.B Rd

ROTXL.W Rd

ROTXL.L ERd

ROTXR.B Rd

ROTXR.W Rd

ROTXR.L ERd

MSB

LSB

B

W

L

SHLR

ROTXL

0

C

B

W

L

C

MSB

LSB

B

W

L

ROTXR

C

MSB

LSB

ROTL ROTL.B Rd

ROTL.W Rd

B

W

L

C

MSB

LSB

ROTL.L ERd

ROTR.B Rd

ROTR.W Rd

ROTR.L ERd

B

W

L

ROTR

C

MSB

LSB

Rev. 3.00 Sep. 14, 2006 Page 357 of 408

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Appendix

•

Bit manipulation instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

BSET #xx:3, Rd

BSET #xx:3, @ERd

BSET #xx:3, @aa:8

BSET Rn, Rd

B

2

4

2

4

2

4

2

4

2

(#xx:3 of Rd8) ← 1

(#xx:3 of @ERd) ← 1

(#xx:3 of @aa:8) ← 1

(Rn8 of Rd8) ← 1

—

2

8

2

8

2

8

2

8

2

BSET

BSET Rn, @ERd

BSET Rn, @aa:8

BCLR #xx:3, Rd

BCLR #xx:3, @ERd

BCLR #xx:3, @aa:8

BCLR Rn, Rd

(Rn8 of @ERd) ← 1

(Rn8 of @aa:8) ← 1

(#xx:3 of Rd8) ← 0

(#xx:3 of @ERd) ← 0

(#xx:3 of @aa:8) ← 0

(Rn8 of Rd8) ← 0

BCLR

BNOT

BCLR Rn, @ERd

BCLR Rn, @aa:8

BNOT #xx:3, Rd

(Rn8 of @ERd) ← 0

(Rn8 of @aa:8) ← 0

(#xx:3 of Rd8) ←

¬ (#xx:3 of Rd8)

BNOT #xx:3, @ERd

BNOT #xx:3, @aa:8

BNOT Rn, Rd

B

4

(#xx:3 of @ERd) ←

¬ (#xx:3 of @ERd)

—

8

2

8

4

(#xx:3 of @aa:8) ←

¬ (#xx:3 of @aa:8)

2

4

(Rn8 of Rd8) ←

¬ (Rn8 of Rd8)

BNOT Rn, @ERd

BNOT Rn, @aa:8

(Rn8 of @ERd) ←

¬ (Rn8 of @ERd)

(Rn8 of @aa:8) ←

¬ (Rn8 of @aa:8)

BTST #xx:3, Rd

BTST #xx:3, @ERd

BTST #xx:3, @aa:8

BTST Rn, Rd

B

2

4

2

4

2

¬ (#xx:3 of Rd8) → Z

¬ (#xx:3 of @ERd) → Z

¬ (#xx:3 of @aa:8) → Z

¬ (Rn8 of @Rd8) → Z

¬ (Rn8 of @ERd) → Z

¬ (Rn8 of @aa:8) → Z

(#xx:3 of Rd8) → C

—

2

6

2

6

2

BTST

BTST Rn, @ERd

BTST Rn, @aa:8

BLD #xx:3, Rd

—

BLD

Rev. 3.00 Sep. 14, 2006 Page 358 of 408

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Appendix

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

BLD #xx:3, @ERd

BLD #xx:3, @aa:8

BILD #xx:3, Rd

B

4

(#xx:3 of @ERd) → C

—

6

2

6

2

8

2

8

2

6

2

6

2

6

2

6

2

6

2

6

BLD

4

(#xx:3 of @aa:8) → C

2

¬ (#xx:3 of Rd8) → C

BILD

BILD #xx:3, @ERd

BILD #xx:3, @aa:8

BST #xx:3, Rd

4

¬ (#xx:3 of @ERd) → C

¬ (#xx:3 of @aa:8) → C

C → (#xx:3 of Rd8)

4

2

—

BST

BST #xx:3, @ERd

BST #xx:3, @aa:8

BIST #xx:3, Rd

4

C → (#xx:3 of @ERd24)

C → (#xx:3 of @aa:8)

4

BIST

2

¬ C → (#xx:3 of Rd8)

BIST #xx:3, @ERd

BIST #xx:3, @aa:8

BAND #xx:3, Rd

4

¬ C → (#xx:3 of @ERd24)

¬ C → (#xx:3 of @aa:8)

C∧(#xx:3 of Rd8) → C

4

2

BAND

BAND #xx:3, @ERd

BAND #xx:3, @aa:8

BIAND #xx:3, Rd

BIAND #xx:3, @ERd

BIAND #xx:3, @aa:8

BOR #xx:3, Rd

4

C∧(#xx:3 of @ERd24) → C

C∧(#xx:3 of @aa:8) → C

C∧ ¬ (#xx:3 of Rd8) → C

C∧ ¬ (#xx:3 of @ERd24) → C

C∧ ¬ (#xx:3 of @aa:8) → C

C⁄(#xx:3 of Rd8) → C

4

BIAND

2

4

2

BOR

BIOR

BOR #xx:3, @ERd

BOR #xx:3, @aa:8

BIOR #xx:3, Rd

4

C⁄(#xx:3 of @ERd24) → C

C⁄(#xx:3 of @aa:8) → C

C⁄ ¬ (#xx:3 of Rd8) → C

C⁄ ¬ (#xx:3 of @ERd24) → C

C⁄ ¬ (#xx:3 of @aa:8) → C

C⊕(#xx:3 of Rd8) → C

C⊕(#xx:3 of @ERd24) → C

C⊕(#xx:3 of @aa:8) → C

C⊕ ¬ (#xx:3 of Rd8) → C

C⊕ ¬ (#xx:3 of @ERd24) → C

C⊕ ¬ (#xx:3 of @aa:8) → C

4

2

BIOR #xx:3, @ERd

BIOR #xx:3, @aa:8

BXOR #xx:3, Rd

4

2

BXOR

BIXOR

BXOR #xx:3, @ERd

BXOR #xx:3, @aa:8

BIXOR #xx:3, Rd

BIXOR #xx:3, @ERd

BIXOR #xx:3, @aa:8

4

2

4

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Appendix

•

Branching instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

Branch

I

H

N

Z

V

C

Condition

BRA d:8 (BT d:8)

BRA d:16 (BT d:16)

BRN d:8 (BF d:8)

BRN d:16 (BF d:16)

BHI d:8

—

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

Always

—

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

4

6

If condition

is true then

PC ← PC+d

else next;

Bcc

Never

C ⁄ Z = 0

C ⁄ Z = 1

C = 0

BHI d:16

BLS d:8

BLS d:16

BCC d:8 (BHS d:8)

BCC d:16 (BHS d:16)

BCS d:8 (BLO d:8)

BCS d:16 (BLO d:16)

BNE d:8

C = 1

Z = 0

BNE d:16

BEQ d:8

Z = 1

BEQ d:16

BVC d:8

V = 0

BVC d:16

BVS d:8

V = 1

BVS d:16

BPL d:8

N = 0

BPL d:16

BMI d:8

N = 1

BMI d:16

BGE d:8

N⊕V = 0

N⊕V = 1

Z ⁄ (N⊕V) = 0

Z ⁄ (N⊕V) = 1

BGE d:16

BLT d:8

BLT d:16

BGT d:8

BGT d:16

BLE d:8

BLE d:16

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Appendix

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

JMP @ERn

JMP @aa:24

JMP @@aa:8

BSR d:8

—

2

4

2

PC ← ERn

—

4

6

JMP

BSR

PC ← aa:24

PC ← @aa:8

8

6

10

8

PC → @–SP

PC ← PC+d:8

BSR d:16

—

4

PC → @–SP

PC ← PC+d:16

—

8

6

8

10

8

JSR

JSR @ERn

JSR @aa:24

JSR @@aa:8

2

4

2

PC → @–SP

PC ← ERn

PC → @–SP

PC ← aa:24

10

12

10

PC → @–SP

PC ← @aa:8

RTS RTS

2

PC ← @SP+

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Appendix

•

System control instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

1

TRAPA #x:2

—

2

PC → @–SP

—

14 16

TRAPA

CCR → @–SP

<vector> → PC

RTE

—

CCR ← @SP+

PC ← @SP+

10

2

RTE

—

SLEEP SLEEP

Transition to power-

down state

—

LDC #xx:8, CCR

B

2

#xx:8 → CCR

2

LDC

LDC Rs, CCR

2

Rs8 → CCR

LDC @ERs, CCR

W

4

@ERs → CCR

6

LDC @(d:16, ERs), CCR

LDC @(d:24, ERs), CCR

LDC @ERs+, CCR

6

@(d:16, ERs) → CCR

@(d:24, ERs) → CCR

8

10

4

12

8

@ERs → CCR

ERs32+2 → ERs32

LDC @aa:16, CCR

LDC @aa:24, CCR

STC CCR, Rd

W

B

6

@aa:16 → CCR

@aa:24 → CCR

CCR → Rd8

8

10

2

8

—

2

—

STC

STC CCR, @ERd

W

4

CCR → @ERd

6

STC CCR, @(d:16, ERd)

STC CCR, @(d:24, ERd)

STC CCR, @–ERd

6

CCR → @(d:16, ERd)

CCR → @(d:24, ERd)

8

10

4

12

8

ERd32–2 → ERd32

CCR → @ERd

—

STC CCR, @aa:16

STC CCR, @aa:24

ANDC #xx:8, CCR

ORC #xx:8, CCR

XORC #xx:8, CCR

W

B

6

8

CCR → @aa:16

CCR → @aa:24

CCR∧#xx:8 → CCR

CCR⁄#xx:8 → CCR

CCR⊕#xx:8 → CCR

PC ← PC+2

—

8

10

2

ANDC

ORC

B

2

XORC

B

2

—

NOP NOP

—

2

—

2

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Appendix

•

Block transfer instructions

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

I

H

N

Z

V

C

EEPMOV

EEPMOV. B

—

4

if R4L ≠ 0 then

repeat @R5 → @R6

R5+1 → R5

—

8+

4n^*2

R6+1 → R6

R4L–1 → R4L

until

else next

R4L=0

EEPMOV. W

if R4 ≠ 0 then

repeat @R5 → @R6

R5+1 → R5

—

8+

4n^*2

R6+1 → R6

R4–1 → R4

until

R4=0

else next

Notes: 1. The number of states in cases where the instruction code and its operands are located

in on-chip memory is shown here. For other cases see appendix A.3, Number of

Execution States.

2. n is the value set in register R4L or R4.

(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.

(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.

(3) Retains its previous value when the result is zero; otherwise cleared to 0.

(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.

(5) The number of states required for execution of an instruction that transfers data in

synchronization with the E clock is variable.

(6) Set to 1 when the divisor is negative; otherwise cleared to 0.

(7) Set to 1 when the divisor is zero; otherwise cleared to 0.

(8) Set to 1 when the quotient is negative; otherwise cleared to 0.

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Appendix

A.2

Operation Code Map

Table A.2 Operation Code Map (1)

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Appendix

Table A.2 Operation Code Map (2)

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Appendix

Table A.2 Operation Code Map (3)

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Appendix

A.3

Number of Execution States

The status of execution for each instruction of the H8/300H CPU and the method of calculating

the number of states required for instruction execution are shown below. Table A.4 shows the

number of cycles of each type occurring in each instruction, such as instruction fetch and data

read/write. Table A.3 shows the number of states required for each cycle. The total number of

states required for execution of an instruction can be calculated by the following expression:

Execution states = I × S_I+ J × S_J+ K × S_K+ L × S_L+ M × S_M+ N × S_N

Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.

BSET #0, @FF00

From table A.4:

I = L = 2, J = K = M = N= 0

From table A.3:

S_I= 2, S_L= 2

Number of states required for execution = 2 × 2 + 2 × 2 = 8

When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and

on-chip RAM is used for stack area.

JSR @@ 30

From table A.4:

I = 2, J = K = 1, L = M = N = 0

From table A.3:

S_I= S_J= S_K= 2

Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8

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Appendix

Table A.3 Number of Cycles in Each Instruction

Access Location

On-Chip Peripheral Module

Execution Status

(Instruction Cycle)

On-Chip Memory

Instruction fetch

S_I

2

—

Branch address read

Stack operation

S_J

S_K

S_L

S_M

S_N

Byte data access

Word data access

Internal operation

2 or 3*

1

Note:

*

Depends on which on-chip peripheral module is accessed. See section 19.1, Register

Addresses (Address Order).

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Appendix

Table A.4 Number of Cycles in Each Instruction

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

ADD

ADD.B #xx:8, Rd

1

2

1

3

1

2

1

3

2

1

2

ADD.B Rs, Rd

ADD.W #xx:16, Rd

ADD.W Rs, Rd

ADD.L #xx:32, ERd

ADD.L ERs, ERd

ADDS #1/2/4, ERd

ADDX #xx:8, Rd

ADDX Rs, Rd

AND.B #xx:8, Rd

AND.B Rs, Rd

AND.W #xx:16, Rd

AND.W Rs, Rd

AND.L #xx:32, ERd

AND.L ERs, ERd

ANDC #xx:8, CCR

BAND #xx:3, Rd

BAND #xx:3, @ERd

BAND #xx:3, @aa:8

BRA d:8 (BT d:8)

BRN d:8 (BF d:8)

BHI d:8

ADDS

ADDX

AND

ANDC

BAND

1

Bcc

BLS d:8

BCC d:8 (BHS d:8)

BCS d:8 (BLO d:8)

BNE d:8

BEQ d:8

BVC d:8

BVS d:8

BPL d:8

BMI d:8

BGE d:8

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

Bcc

BLT d:8

2

1

2

1

2

1

2

1

2

BGT d:8

BLE d:8

BRA d:16(BT d:16)

BRN d:16(BF d:16)

BHI d:16

2

BLS d:16

BCC d:16(BHS d:16)

BCS d:16(BLO d:16)

BNE d:16

BEQ d:16

BVC d:16

BVS d:16

BPL d:16

BMI d:16

BGE d:16

BLT d:16

BGT d:16

BLE d:16

BCLR

BCLR #xx:3, Rd

BCLR #xx:3, @ERd

BCLR #xx:3, @aa:8

BCLR Rn, Rd

BCLR Rn, @ERd

BCLR Rn, @aa:8

BIAND #xx:3, Rd

BIAND #xx:3, @ERd

BIAND #xx:3, @aa:8

BILD #xx:3, Rd

BILD #xx:3, @ERd

BILD #xx:3, @aa:8

2

BIAND

BILD

1

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

BIOR

BIOR #xx:8, Rd

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

BIOR #xx:8, @ERd

BIOR #xx:8, @aa:8

BIST #xx:3, Rd

1

BIST

BIST #xx:3, @ERd

BIST #xx:3, @aa:8

BIXOR #xx:3, Rd

BIXOR #xx:3, @ERd

BIXOR #xx:3, @aa:8

BLD #xx:3, Rd

2

BIXOR

BLD

1

BLD #xx:3, @ERd

BLD #xx:3, @aa:8

BNOT #xx:3, Rd

BNOT #xx:3, @ERd

BNOT #xx:3, @aa:8

BNOT Rn, Rd

1

BNOT

2

BNOT Rn, @ERd

BNOT Rn, @aa:8

BOR #xx:3, Rd

2

BOR

BOR #xx:3, @ERd

BOR #xx:3, @aa:8

BSET #xx:3, Rd

BSET #xx:3, @ERd

BSET #xx:3, @aa:8

BSET Rn, Rd

1

BSET

2

BSET Rn, @ERd

BSET Rn, @aa:8

BSR d:8

2

BSR

BST

1

BSR d:16

2

BST #xx:3, Rd

BST #xx:3, @ERd

BST #xx:3, @aa:8

2

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

BTST

BTST #xx:3, Rd

1

2

1

2

1

2

1

2

1

3

1

2

1

2

1

BTST #xx:3, @ERd

BTST #xx:3, @aa:8

BTST Rn, Rd

1

BTST Rn, @ERd

BTST Rn, @aa:8

BXOR #xx:3, Rd

BXOR #xx:3, @ERd

BXOR #xx:3, @aa:8

CMP.B #xx:8, Rd

CMP.B Rs, Rd

1

BXOR

CMP

1

CMP.W #xx:16, Rd

CMP.W Rs, Rd

CMP.L #xx:32, ERd

CMP.L ERs, ERd

DAA Rd

DAA

DAS

DEC

DAS Rd

DEC.B Rd

DEC.W #1/2, Rd

DEC.L #1/2, ERd

DIVXS.B Rs, Rd

DIVXS.W Rs, ERd

DIVXU.B Rs, Rd

DIVXU.W Rs, ERd

DUVXS

DIVXU

12

20

12

20

EEPMOV EEPMOV.B

EEPMOV.W

2n+2*¹

EXTS

EXTS.W Rd

EXTS.L ERd

EXTU.W Rd

EXTU.L ERd

EXTU

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

INC

INC.B Rd

1

2

1

2

3

5

2

3

4

1

2

4

1

2

3

1

2

4

1

INC.W #1/2, Rd

INC.L #1/2, ERd

JMP @ERn

JMP

JSR

LDC

JMP @aa:24

2

JMP @@aa:8

1

JSR @ERn

1

JSR @aa:24

2

JSR @@aa:8

LDC #xx:8, CCR

LDC Rs, CCR

LDC@ERs, CCR

LDC@(d:16, ERs), CCR

LDC@(d:24,ERs), CCR

LDC@ERs+, CCR

LDC@aa:16, CCR

LDC@aa:24, CCR

MOV.B #xx:8, Rd

MOV.B Rs, Rd

1

2

MOV

MOV.B @ERs, Rd

MOV.B @(d:16, ERs), Rd

MOV.B @(d:24, ERs), Rd

MOV.B @ERs+, Rd

MOV.B @aa:8, Rd

MOV.B @aa:16, Rd

MOV.B @aa:24, Rd

MOV.B Rs, @Erd

MOV.B Rs, @(d:16, ERd)

MOV.B Rs, @(d:24, ERd)

MOV.B Rs, @-ERd

MOV.B Rs, @aa:8

1

2

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

MOV

MOV.B Rs, @aa:16

2

3

2

1

2

4

1

2

3

1

2

4

1

2

3

1

2

3

5

2

3

4

2

3

5

2

3

4

2

1

MOV.B Rs, @aa:24

MOV.W #xx:16, Rd

MOV.W Rs, Rd

MOV.W @ERs, Rd

1

MOV.W @(d:16,ERs), Rd

MOV.W @(d:24,ERs), Rd

MOV.W @ERs+, Rd

MOV.W @aa:16, Rd

MOV.W @aa:24, Rd

MOV.W Rs, @ERd

2

MOV.W Rs, @(d:16,ERd)

MOV.W Rs, @(d:24,ERd)

MOV.W Rs, @-ERd

MOV.W Rs, @aa:16

MOV.W Rs, @aa:24

MOV.L #xx:32, ERd

MOV.L ERs, ERd

MOV

2

MOV.L @ERs, ERd

MOV.L @(d:16,ERs), ERd

MOV.L @(d:24,ERs), ERd

MOV.L @ERs+, ERd

MOV.L @aa:16, ERd

MOV.L @aa:24, ERd

MOV.L ERs,@ERd

2

MOV.L ERs, @(d:16,ERd)

MOV.L ERs, @(d:24,ERd)

MOV.L ERs, @-ERd

MOV.L ERs, @aa:16

MOV.L ERs, @aa:24

MOVFPE @aa:16, Rd*²

MOVTPE Rs,@aa:16*²

2

MOVFPE

MOVTPE

1

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

MULXS

MULXU

NEG

MULXS.B Rs, Rd

2

1

2

1

3

2

1

2

1

2

1

12

20

12

20

MULXS.W Rs, ERd

MULXU.B Rs, Rd

MULXU.W Rs, ERd

NEG.B Rd

NEG.W Rd

NEG.L ERd

NOP

NOT

NOP

NOT.B Rd

NOT.W Rd

NOT.L ERd

OR

OR.B #xx:8, Rd

OR.B Rs, Rd

OR.W #xx:16, Rd

OR.W Rs, Rd

OR.L #xx:32, ERd

OR.L ERs, ERd

ORC #xx:8, CCR

POP.W Rn

ORC

POP

1

2

1

2

POP.L ERn

PUSH

ROTL

PUSH.W Rn

PUSH.L ERn

ROTL.B Rd

ROTL.W Rd

ROTL.L ERd

ROTR.B Rd

ROTR

ROTR.W Rd

ROTR.L ERd

ROTXL.B Rd

ROTXL.W Rd

ROTXL.L ERd

ROTXL

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

ROTXR

ROTXR.B Rd

ROTXR.W Rd

ROTXR.L ERd

RTE

1

2

1

2

3

5

2

3

4

1

2

1

3

1

RTE

2

1

2

RTS

SHAL

SHAL.B Rd

SHAL.W Rd

SHAL.L ERd

SHAR

SHLL

SHLR

SHAR.B Rd

SHAR.W Rd

SHAR.L ERd

SHLL.B Rd

SHLL.W Rd

SHLL.L ERd

SHLR.B Rd

SHLR.W Rd

SHLR.L ERd

SLEEP

STC

SLEEP

STC CCR, Rd

STC CCR, @ERd

STC CCR, @(d:16,ERd)

STC CCR, @(d:24,ERd)

STC CCR,@-ERd

STC CCR, @aa:16

STC CCR, @aa:24

SUB.B Rs, Rd

SUB.W #xx:16, Rd

SUB.W Rs, Rd

SUB.L #xx:32, ERd

SUB.L ERs, ERd

SUBS #1/2/4, ERd

1

2

SUB

SUBS

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Appendix

Instruction Branch

Stack

Byte Data

Word Data Internal

Fetch

I

Addr. Read Operation Access

Access

M

Operation

N

Instruction Mnemonic

J

K

L

SUBX

SUBX #xx:8, Rd

1

2

1

2

1

3

2

1

SUBX. Rs, Rd

TRAPA

XOR

TRAPA #xx:2

1

2

4

XOR.B #xx:8, Rd

XOR.B Rs, Rd

XOR.W #xx:16, Rd

XOR.W Rs, Rd

XOR.L #xx:32, ERd

XOR.L ERs, ERd

XORC #xx:8, CCR

XORC

Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed

n+1 times respectively.

2. Cannot be used in this LSI.

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Appendix

A.4

Combinations of Instructions and Addressing Modes

Table A.5 Combinations of Instructions and Addressing Modes

Addressing Mode

Functions

Instructions

Data

transfer

instructions

MOV

BWL BWL BWL BWL BWL BWL

B

BWL BWL

—

WL

—

POP, PUSH

MOVFPE,

MOVTPE

ADD, CMP

SUB

—

Arithmetic

operations

BWL BWL

WL BWL

—

ADDX, SUBX

ADDS, SUBS

INC, DEC

DAA, DAS

MULXU,

B

L

—

BWL

B

BW

MULXS,

DIVXU,

DIVXS

NEG

—

B

BWL

WL

BWL

B

—

B

—

W

—

W

—

W

—

B

—

W

—

EXTU, EXTS

AND, OR, XOR

NOT

Logical

operations

Shift operations

Bit manipulations

Branching

instructions

BCC, BSR

—

JMP, JSR

RTS

—

W

—

System

control

instructions

TRAPA

RTE

—

W

—

SLEEP

LDC

—

B

STC

—

B

—

ANDC, ORC,

XORC

NOP

—

Block data transfer instructions

BW

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Appendix

Appendix B I/O Port Block Diagrams

B.1

I/O Port Block Diagrams

RES goes low in a reset, and SBY goes low in a reset and in standby mode.

Internal data bus

RES

SBY

PUCR

PMR

Pull-up MOS

PDR

PCR

IRQ

TRGV

[Legend]

PUCR: Port pull-up control register

PMR: Port mode register

PDR: Port data register

PCR: Port control register

Figure B.1 Port 1 Block Diagram (P17)

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Appendix

Internal data bus

RES

SBY

PUCR

PMR

Pull-up MOS

PDR

PCR

IRQ

[Legend]

PUCR: Port pull-up control register

PMR: Port mode register

PDR: Port data register

PCR: Port control register

Figure B.2 Port 1 Block Diagram (P14)

Rev. 3.00 Sep. 14, 2006 Page 380 of 408

REJ09B0105-0300

Appendix

Internal data bus

SBY

PMR

PDR

PCR

SCI3

TXD

[Legend]

PMR: Port mode register

PDR: Port data register

PCR: Port control register

Figure B.3 Port 2 Block Diagram (P22)

Rev. 3.00 Sep. 14, 2006 Page 381 of 408

REJ09B0105-0300

Appendix

SBY

Internal data bus

PDR

PCR

SCI3

RE

RXD

[Legend]

PDR: Port data register

PCR: Port control register

Figure B.4 Port 2 Block Diagram (P21)

Rev. 3.00 Sep. 14, 2006 Page 382 of 408

REJ09B0105-0300

Appendix

SBY

SCI3

SCKIE

SCKOE

Internal data bus

PDR

PCR

SCKO

SCKI

[Legend]

PDR: Port data register

PCR: Port control register

Figure B.5 Port 2 Block Diagram (P20)

Rev. 3.00 Sep. 14, 2006 Page 383 of 408

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Appendix

Internal data bus

SBY

PDR

PCR

IIC2

ICE

SDAO/SCLO

SDAI/SCLI

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group)

Rev. 3.00 Sep. 14, 2006 Page 384 of 408

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Appendix

Internal data bus

SBY

PDR

PCR

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group)

Rev. 3.00 Sep. 14, 2006 Page 385 of 408

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Appendix

Internal data bus

RES

SBY

PUCR

PMR

Pull-up MOS

PDR

PCR

WKP

ADTRG

[Legend]

PUCR: Port pull-up control register

PMR: Port mode register

PDR: Port data register

PCR: Port control register

Figure B.7 Port 5 Block Diagram (P55)

Rev. 3.00 Sep. 14, 2006 Page 386 of 408

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Appendix

Internal data bus

SBY

Timer V

OS3

OS2

OS1

OS0

PDR

PCR

TMOV

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.8 Port 5 Block Diagram (P76)

Rev. 3.00 Sep. 14, 2006 Page 387 of 408

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Appendix

Internal data bus

SBY

PDR

PCR

Timer V

TMCIV

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.9 Port 7 Block Diagram (P75)

Rev. 3.00 Sep. 14, 2006 Page 388 of 408

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Appendix

Internal data bus

SBY

PDR

PCR

Timer V

TMRIV

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.10 Port 7 Block Diagram (P74)

Rev. 3.00 Sep. 14, 2006 Page 389 of 408

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Appendix

Internal data bus

SBY

Timer W

Output

control signal

A to D

PDR

PCR

FTIOA to D

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.11 Port 8 Block Diagram (P84 to P81)

Rev. 3.00 Sep. 14, 2006 Page 390 of 408

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Appendix

Internal data bus

SBY

PDR

PCR

Timer W

FTCI

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.12 Port 8 Block Diagram (P80)

Rev. 3.00 Sep. 14, 2006 Page 391 of 408

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Appendix

Internal data bus

A/D converter

CH3 to CH0

SCAN

DEC

VIN

Low voltage

detection circuit

VDDII

ExtD, ExtU

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.13 Port B Block Diagram (PB3, PB2)

Internal data bus

A/D converter

SCAN

CH3 to CH0

DEC

VIN

Figure B.14 Port B Block Diagram (PB1, PB0)

Rev. 3.00 Sep. 14, 2006 Page 392 of 408

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Appendix

SBY

Internal data bus

CPG

PDR

PCR

φ

PMRC1

PMRC0

XTALI

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.15 Port C Block Diagram (PC1)

Rev. 3.00 Sep. 14, 2006 Page 393 of 408

REJ09B0105-0300

Appendix

SBY

Internal data bus

PDR

PCR

CPG

PMRC0

EXTALI

[Legend]

PDR: Portdata register

PCR: Portcontrol register

Figure B.16 Port C Block Diagram (PC0)

B.2

Port States in Each Operating State

Port

Reset

Active

Sleep

Subsleep

Retained

Standby

P17, P14

P22 to P20

P57 to P55

P76 to P74

P84 to P80

High impedance

Functioning Retained

High impedance*

High impedance

High impedance*

High impedance

PB3 to PB0 High impedance

High

impedance impedance

PC1, PC0

Note:

High impedance

Functioning Retained

Retained

High impedance

*

High level output when the pull-up MOS is in on state.

Rev. 3.00 Sep. 14, 2006 Page 394 of 408

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Appendix

Appendix C Product Code Lineup

Product Type

Product Code

Model Marking

Package Code

H8/36912 Flash memory HD64F36912G

version

HD64F36912GFH

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

HD64F36912GTP

HD64F36912GP

Masked ROM HD64336912G

version

HD64336912G (***) FH

HD64336912G (***) TP

HD64336911G (***) FH

HD64336911G (***) TP

HD64F36902GFH

H8/36911 Masked ROM HD64336911G

version

H8/36902 Flash memory HD64F36902G

version

HD64F36902GTP

HD64F36902GP

Masked ROM HD64336902G

version

HD64336902G (***) FH

HD64336902G (***) TP

HD64336901G (***) FH

HD64336901G (***) TP

HD64336900G (***) FH

HD64336900G (***) TP

H8/36901 Masked ROM HD64336901G

version

H8/36900 Masked ROM HD64336900G

version

[Legend]

(***): ROM code

Rev. 3.00 Sep. 14, 2006 Page 395 of 408

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Appendix

Appendix D Package Dimensions

The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have

priority.

Unit: mm

20.45

20.95 Max

17

32

1

16

14.14 0.30

1.42

1.00 Max

0˚ – 8˚

0.10

M

0.80 0.20

1.27

*

0.40 0.08

0.38 0.06

0.15

Package Code

JEDEC

JEITA

FP-32D

Conforms

—

*Dimension including the plating thickness

Base material dimension

Mass (reference value)

1.3 g

Figure D.1 FP-32D Package Dimensions

Rev. 3.00 Sep. 14, 2006 Page 396 of 408

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Appendix

Unit: mm

9.0 0.2

7

24

17

25

32

16

9

1

8

0.70

*

0.35 0.05

0.37 0.05

0.20 M

1.0

0 ~ 10˚

0.5 0.1

0.10

Package Code

FP-32A

FP-32AV

—

JEDEC

*Dimension including the plating thickness

JEITA

—

Base material dimension

Mass (reference value)

0.2 g

Figure D.2 FP-32A Package Dimension

Rev. 3.00 Sep. 14, 2006 Page 397 of 408

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Appendix

Unit: mm

32

17

1

16

D

e

b1

b

b2

SEATING PLANE

Dimension in Millmeters

Symbol

Min

−

0.51

Nom

−

Max

5.08

−

A

A1

A2

b

b1

b2

c

D

E

e

e1

L

−

3.8

0.45

1.0

0.73

0.27

28.0

8.9

1.778

10.16

−

0.35

0.9

0.63

0.22

27.8

8.75

−

0.55

1.3

1.03

0.34

28.2

9.05

−

Package Code

JEDEC

32P4B

—

−

3.0

−

JEITA

Mass (reference value)

—

2.2

θ

0˚

−

15˚

Figure D.3 32P4B Package Dimension

Rev. 3.00 Sep. 14, 2006 Page 398 of 408

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Main Revisions and Additions in this Edition

Item

Page Revision (See Manual for Details)

When using an on-chip emulator (E7, E8) for H8/36912,

H8/36902 program development and debugging, the following

restrictions must be noted.

Preface



1.The NMI pin is reserved for the E7 or E8, and cannot be

used.

2.Area H'2000 to H'2FFF is used by the E7 or E8, and is not

available to the user.

3.Area H'F980 to H'FD7F must on no account be accessed.

4.When the E7 or E8 is used, address breaks can be set as

either available to the user or for use by the E7 or E8. If

address breaks are set as being used by the E7 or E8, the

address break control registers must not be accessed.

5.When the E7 or E8 is used, NMI is an input/output pin (open-

drain in output mode).

•

On-chip memory

1.1 Features

1

Product Classification

Remarks

Masked ROM

version

H8/36912

Under planning

H8/36911

H8/36902

H8/36901

H8/36900

2

On-chip oscillator

Frequency accuracy:

(Flash memory version): 8MHz 3ꢀ

8MHz 1ꢀ (Typ.) Vcc = 5.0 V, Ta = 25˚C

Vcc = 4.0 to 5.0 V, Ta = −20 to 75˚C

10MHz 4ꢀ (Typ.) Vcc = 4.0 to 5.0 V, Ta = −20 to 75˚C

Package

LQFP-32

SOP-32

SDIP-32

Code

FP-32A

FP-32D

32P4B

•

Compact package

2

Package

LQFP-32

SOP-32

SDIP-32*

Note: * Flash memory version only

Rev. 3.00 Sep. 14, 2006 Page 399 of 408

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Item

Page Revision (See Manual for Details)

Figure 1.1 Internal Block

Diagram of H8/36912 Group

3, 4

E10T_0

E10T_1

E10T_2

*

System

clock

generator

CPU

H8/300H

On-chip

oscillator

Figure 1.2 Internal Block

Diagram of H8/36902 Group

Data bus (lower)

Port C

Port B

Note:

* Can also be used for the E7 or E8 emulator.

Figure 1.3 Pin Arrangement 5, 6

of H8/36912 Group (FP-32A)

P76/TMOV

PB3/AN3/ExtU

PB2/AN2/ExtD

PB1/AN1

28

29

30

31

32

13

12

11

10

9

E10T_2*

E10T_1*

E10T_0*

H8/36912 Group

(Top view)

Figure 1.4 Pin Arrangement

of H8/36902 Group (FP-32A)

P17/IRQ3/TRGV

PB0/AN0

NMI

Note:

* Can also be used for the E7 or E8 emulator.

Figure 1.5 Pin Arrangement 7, 8

of H8/36912 Group (FP-32D,

32P4B),

P57/SCL

E10T_0*

E10T_1*

15

16

18

17

E10T_2*

Figure 1.6 Pin Arrangement

of H8/36902 Group (FP-32D,

32P4B)

Note:

*

Can also be used for the E7 or E8 emulator.

Table 1.1 Pin Functions

9, 10

Pin No.

Type Symbol FP-32D, 32P4B FP-32A Functions

E7, E8 E10T_0, 15, 16, 17

11, 12, Interface pins

E10T_1,

E10T_2

13

for the E7 or E8

emulator

•

High-speed operation

Section 2 CPU

11



All frequently-used instructions execute in two or four states

Figure 2.1 Memory Map (1) 12

H8/36912

H8/36902

H8/36912F

H8/36902F

(Masked ROM version

(under planning))

(Flash memory version)

H'0000

H'0045

H'0046

H'0000

H'0045

H'0046

Interrupt vector

H'1FFF

H'2000

H'1FFF

E7 or E8 control

program area

(4 kbytes)

Not used

H'2FFF

H'F980

Not used

(E7 or E8 work area,

for flash memory

programming:

1 kbyte)

Not used

Rev. 3.00 Sep. 14, 2006 Page 400 of 408

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Item

Page Revision (See Manual for Details)

Figure 2.1 Memory Map (2) 13

H8/36911

H8/36901

H8/36900

(Masked ROM version

(under planning))

(Masked ROM version

(under planning))

H'0000

H'0045

H'0046

H'0000

H'0045

H'0046

Interrupt vector

Table 3.1 Exception Sources 48

and Vector Address

Relative Module

Exception Sources

IIC2*

IIC_2 transmit data empty

IIC_2 transmit end

IIC_2 receive error

Timer B1*

Timer B1 overflow

Note: * Available for the H8/36912 Group only.

Figure 5.1 Block Diagram of 69

Clock Pulse Generators

System

clock

Duty

correction

circuit

OSC

1

2

φ

OSC

oscillator

R

OSC

ROSC

On-chip

oscillator

Clock

divider

OSC/2

OSC/4

5.2.1 RC Control Register

(RCCR)

71

Description

Bit

1

Bit Name

RCPSC1

RCPSC0

Division Ratio Select for On-chip Oscillator

0

The division ratio of R_OSCchanges right after

rewriting this bit.

These bits can be written to only when the CKSTA

bit in CKCSR is 0.

0X: R_OSC(not divided)

10: R_OSC/2

11: R_OSC/4

5.2.2 RC Trimming Data

Protect Register

(RCTRMDPR)

73

Bit

Bit Name

Description

4

TRMDRWE Trimming Date Register Write Enable

This register can be written to when the LOCKDW

bit is 0 and this bit is 1.

[Setting condition]

•

When writing 0 to the WRI bit while writing 1 to

the TRMDRWE bit while the PRWE bit is 1

[Clearing conditions]

•

Reset

When writing 0 to the WRI bit and writing 0 to

the TRMDRWE bit while the PRWE bit is 1

Rev. 3.00 Sep. 14, 2006 Page 401 of 408

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Item

Page Revision (See Manual for Details)

5.2.3 RC Trimming Data

Register (RCTRMDR)

73

Bit

7

Bit Name Description

TRMD7

TRMD6

TRMD5

TRMD4

TRMD3

TRMD2

TRMD1

TRMD0

Trimming Data

6

In the flash memory version, the trimming

data is loaded from the flash memory to this

register right after a reset. These bits are

always read as undefined value.

5

4

3

As for the masked ROM version (under

planning), the on-chip oscillator frequency

can be trimmed by rewriting these bits.

2

1

0

5.2.4 Clock Control/Status

Register (CKCSR)

74

78

Bit

7

Bit Name Description

PMRC1

PMRC0

Port C Function Select 1 and 0

6

Note: *The φ halt duration is the duration from the timing when the

φ clock stops to the first

Figure 5.5 Timing Chart of

Switching On-chip Oscillator

Clock to External Clock

rising edge of the φ_OSCclock after six clock cycles of the φ_RC

clock have elapsed.

Table 5.1 Crystal Resonator 82

Parameters

Frequency (MHz) 12

R_S(Max.)

50 Ω

The features of the 12-kbyte (including 4 kbytes as the E7 or E8

control program area) flash memory built into the HD64F36912G

and HD64F36902G are summarized below.

Section 7 ROM

97

Figure 7.1 Flash Memory

Block Configuration

98

← Programming unit: 64 kbytes →

Table 7.3 System Clock

Frequencies for which

Automatic Adjustment of LSI

Bit Rate is Possible

105

Host Bit Rate System Clock Frequency Range of LSI

9600bps

4800bps

2400bps

8 MHz (on-chip oscillator clock)

Figure 7.4 Erase/Erase-

Verify Flowchart

111

115

Read verify data

No

Verify data = all 1s ?

Increment address

Yes

Note: * When the E7 or E8 is used, area H'F980 to H'FD7F must

Section 8 RAM

not be accessed.

Rev. 3.00 Sep. 14, 2006 Page 402 of 408

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Item

Page Revision (See Manual for Details)

13.2.1 Timer Control/Status 192

Register WD (TCSRWD)

Bit Bit Name Description

4

TCSRWE Timer Control/Status Register WD Write Enable

The WDON and WRST bits can be written when

the TCSRWE bit is set to 1.

When writing data to this bit, the value for bit 5

must be 0.

14.8.2 Mark State and Break 236

Sending

Replaced

15.3.5 I²C Bus Status

Register (ICSR)

251

Bit Bit Name Description

3

STOP

Stop Condition Detection Flag

[Setting conditions]

•

In master mode, when a stop condition is

detected after frame transfer

•

In slave mode, when a stop condition is

detected after the general call address or

the first byte slave address, next to

detection of start condition, accords with the

address set in SAR

……

Figure 15.15 Receive Mode 265

Operation Timing

7

8

1

2

SCL

SDA

(Input)

Bit 6

Bit 7

Bit 0

Bit 1

MST

15.7 Usage Notes

272

Added

There are four 16-bit read-only ADDR registers; ……

16.3.1 A/D Data Registers A 276

to D (ADDRA to ADDRD)

Therefore, byte access to ADDR should be done by reading the

upper byte first then the lower one. ADDR is initialized to H'0000.

Figure 17.2 Block Diagram

of Power-On Reset Circuit

and Low-Voltage Detection

Circuit

287

RES

CRES

20.3 Electrical Characteristics (Masked ROM Version) [Preliminary]

20.3 Electrical

331

Characteristics (Masked

ROM Version)

The guarantee value for the electrical characteristics of masked ROM

version is preliminary.

20.3.1 Power Supply Voltage and Operating Ranges

Rev. 3.00 Sep. 14, 2006 Page 403 of 408

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Item

Page Revision (See Manual for Details)

Table 20.13 AC

Characteristics

339

Values

Item

Symbol

f_RC

Min. Typ. Max.

7.6

9.4

8.0

8.4

On-chip oscillator oscillation

frequency

10.0 10.6

Table A.1 Instruction Set

353

Addressing Mode and

Instruction Length (bytes)

No. of

States^*1

Condition Code

Mnemonic

Operation

•

Arithmetic instructions

I

H

N

Z

V

C

ADD.B #xx:8, Rd

INC.L #2, ERd

DAA Rd

B

L

2

Rd8+#xx:8 → Rd8

ERd32+2 → ERd32

—

2

ADD

DAA

2

—

B

Rd8 decimal adjust

*

→ Rd8

Product Type

Model Marking

Package Code

Appendix C Product Code 395

Lineup

H8/36912 Flash memory HD64F36912GFH

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

LQFP-32 (FP-32A)

SOP-32 (FP-32D)

SDIP-32 (32P4B)

version

HD64F36912GTP

HD64F36912GP

Masked ROM HD64336912G(***) FH

version

HD64336912G(***) TP

HD64336912G(***) P

H8/36911 Masked ROM HD64336911G(***) FH

version

HD64336911G(***) TP

HD64336911G(***) P

H8/36902 Flash memory HD64F36902GFH

version

HD64F36902GTP

HD64F36902GP

Masked ROM HD64336902G(***) FH

version

HD64336902G(***) TP

HD64336902G(***) P

H8/36901 Masked ROM HD64336901G(***) FH

version

HD64336901G(***) TP

HD64336901G(***) P

H8/36900 Masked ROM HD64336900G(***) FH

version

HD64336900G(***) TP

HD64336900G(***) P

Figure D.3 32P4B Package 398

Dimension

Package Code

JEDEC

32P4B

—

JEITA

—

Mass (reference value)

2.2

Rev. 3.00 Sep. 14, 2006 Page 404 of 408

REJ09B0105-0300

Index

Exception handling ...................................47

Reset exception handling ......................54

Stack status ...........................................58

Trap instruction.....................................47

A

A/D converter ......................................... 273

A/D conversion time........................... 280

External trigger input.......................... 281

Sample-and-hold circuit...................... 280

Scan mode........................................... 279

Single mode........................................ 279

Acknowledge.......................................... 255

Address break ........................................... 63

Addressing modes

F

Flash memory ...........................................97

Boot mode...........................................102

Boot program ......................................102

Erase/erase-verify ...............................109

Erasing units .........................................97

Error protection...................................112

Hardware protection............................112

Program/program-verify .....................107

Programming units................................97

Programming/erasing in user program

mode....................................................106

Software protection.............................112

Absolute address................................... 33

Immediate............................................. 34

Memory indirect ................................... 34

Program-counter relative ...................... 34

Register direct....................................... 32

Register indirect.................................... 33

Register indirect with displacement...... 33

Register indirect with post-increment... 33

Register indirect with pre-decrement.... 33

B

G

Bit Synchronous Circuit ......................... 271

General registers .......................................15

C

I

Clock pulse generators

I/O ports..................................................117

I/O port block diagrams ......................379

I²C Bus Format .......................................254

I²C Bus Interface 2 (IIC2).......................239

Instruction set............................................21

Arithmetic operations instructions........23

Bit Manipulation instructions................26

Block data transfer instructions.............30

Branch instructions ...............................28

Data Transfer instructions.....................22

Logic Operations instructions...............25

System Prescaler S................................ 83

Clocked Synchronous Serial Format ...... 263

Condition field.......................................... 31

Condition-code register (CCR)................. 16

CPU .......................................................... 11

E

Effective address....................................... 35

Effective address extension ...................... 31

Rev. 3.00 Sep. 14, 2006 Page 405 of 408

REJ09B0105-0300

Shift Instructions .................................. 25

System control instructions................... 29

Internal power supply step-down

Power-down modes................................... 85

Sleep mode............................................ 93

Standby mode ....................................... 93

Subsleep mode...................................... 94

Power-on reset ........................................ 285

Power-on reset circuit ............................. 291

Product code lineup ................................ 395

Program counter (PC) ............................... 16

PWM operation....................................... 176

circuit...................................................... 299

Interrupt

Internal interrupts ................................. 56

Interrupt response time ......................... 59

IRQ3 to IRQ0 interrupts....................... 55

NMI interrupt........................................ 55

WKP5 to WKP0 interrupts................... 55

R

L

Register

Low-voltage detection circuit................. 285

LVDI .............................................. 293, 295

LVDI (interrupt by low voltage detect)

circuit.............................................. 293, 295

LVDR..................................................... 292

LVDR (reset by low voltage detect)

circuit...................................................... 292

ABRKCR...................... 64, 304, 308, 310

ABRKSR ...................... 66, 304, 308, 310

ADCR ......................... 278, 303, 307, 310

ADCSR....................... 276, 303, 307, 310

ADDRA ...................... 275, 303, 307, 310

ADDRB ...................... 275, 303, 307, 310

ADDRC ...................... 275, 303, 307, 310

ADDRD ...................... 275, 303, 307, 310

BARH ........................... 66, 304, 308, 310

BARL............................ 66, 304, 308, 310

BDRH ........................... 66, 304, 308, 310

BDRL............................ 66, 304, 308, 310

BRR ............................ 206, 303, 307, 310

EBR1........................... 101, 303, 307, 309

FENR.......................... 101, 303, 307, 309

FLMCR1....................... 99, 303, 307, 309

FLMCR2..................... 100, 303, 307, 309

GRA............................ 171, 303, 306, 309

GRB............................ 171, 303, 306, 309

GRC............................ 171, 303, 307, 309

GRD............................ 171, 303, 307, 309

ICCR1......................... 242, 302, 306, 309

ICCR2......................... 245, 302, 306, 309

ICDRR........................ 253, 302, 306, 309

ICDRS................................................. 253

ICDRT ........................ 253, 302, 306, 309

ICIER.......................... 248, 302, 306, 309

M

Memory map ............................................ 12

Module standby function.......................... 95

N

Noise Canceler........................................ 265

O

On-board programming modes............... 102

Operation field.......................................... 30

P

Package....................................................... 2

Package dimensions................................ 396

Rev. 3.00 Sep. 14, 2006 Page 406 of 408

REJ09B0105-0300

ICMR.......................... 246, 302, 306, 309

ICSR ........................... 250, 302, 306, 309

IEGR1........................... 49, 304, 308, 311

IEGR2........................... 50, 304, 308, 311

IENR1........................... 50, 304, 308, 311

IRR1 ............................. 52, 305, 308, 311

IWPR............................ 53, 305, 308, 311

LVDCR....................... 288, 302, 306, 309

LVDSR....................... 290, 302, 306, 309

MSTCR1....................... 89, 305, 308, 311

MSTCR2....................... 90, 305, 308, 311

PCR1........................... 119, 304, 308, 311

PCR2........................... 122, 304, 308, 311

PCR5........................... 125, 304, 308, 311

PCR7........................... 128, 304, 308, 311

PCR8........................... 131, 304, 308, 311

PDR1 .......................... 119, 304, 308, 310

PDR2 .......................... 122, 304, 308, 310

PDR5 .......................... 126, 304, 308, 310

PDR7 .......................... 129, 304, 308, 310

PDR8 .......................... 131, 304, 308, 310

PDRB.......................... 134, 304, 308, 310

PMR1.......................... 118, 304, 308, 311

PMR5.......................... 125, 304, 308, 311

PUCR1........................ 120, 304, 308, 310

PUCR5........................ 126, 304, 308, 310

RDR............................ 200, 303, 307, 310

RSR..................................................... 200

SAR ............................ 252, 302, 306, 309

SCR3........................... 202, 303, 307, 310

SMR............................ 201, 303, 307, 310

SPMR ......................... 211, 303, 307, 310

SSR............................. 204, 303, 307, 310

SYSCR1 ....................... 86, 304, 308, 311

SYSCR2 ....................... 88, 304, 308, 311

TCB1 .......................... 141, 302, 306, 309

TCNT.................................. 171, 306, 309

TCNTV....................... 147, 303, 307, 310

TCORA....................... 148, 303, 307, 310

TCORB....................... 148, 303, 307, 310

TCRV0........................ 148, 303, 307, 309

TCRV1........................ 151, 303, 307, 310

TCRW......................... 164, 302, 306, 309

TCSRV........................ 150, 303, 307, 310

TCSRWD.................... 192, 303, 307, 310

TCWD......................... 194, 304, 307, 310

TDR ............................ 200, 303, 307, 310

TIERW........................ 165, 302, 306, 309

TIOR0......................... 168, 303, 306, 309

TIOR1......................... 169, 303, 306, 309

TLB1...................................................141

TMB1.......................... 140, 302, 306, 309

TMRW........................ 163, 302, 306, 309

TMWD........................ 194, 304, 307, 310

TSR.....................................................200

TSRW ......................... 166, 302, 306, 309

Register field.............................................30

S

Serial communication interface 3

(SCI3) .....................................................197

Asynchronous mode............................212

Bit rate.................................................206

Break...................................................236

Clocked synchronous mode ................219

Framing error ......................................216

Multiprocessor communication

function...............................................227

Overrun error ......................................216

Parity error ..........................................216

Slave address...........................................255

Stack pointer (SP) .....................................16

Start condition.........................................255

Stop condition.........................................255

System clocks ...........................................69

Rev. 3.00 Sep. 14, 2006 Page 407 of 408

REJ09B0105-0300

T

Timer B1................................................. 139

Auto-reload timer operation ............... 142

Interval timer operation ...................... 142

Timer V .................................................. 145

Timer W ................................................. 159

Transfer Rate .......................................... 244

V

Vector address........................................... 47

W

Watchdog timer....................................... 191

Rev. 3.00 Sep. 14, 2006 Page 408 of 408

REJ09B0105-0300

Renesas 16-Bit Single-Chip Microcomputer

Hardware Manual

H8/36912 Group, H8/36902 Group

Publication Date: Rev.1.00, Nov. 07, 2003

Rev.3.00, Sep. 14, 2006

Published by:

Sales Strategic Planning Div.

Renesas Technology Corp.

Customer Support Department

Global Strategic Communication Div.

Renesas Solutions Corp.

Edited by:

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon 6.0

H8/36912 Group, H8/36902 Group

Hardware Manual

1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan

REJ09B0105-0300


型号：	HD64F36902GP
厂家：	RENESAS TECHNOLOGY CORP
描述：	16-BIT, FLASH, 12MHz, MICROCONTROLLER, PDIP32, 0.400 INCH, 1.78 MM PITCH, SDIP-32 光电二极管
文件：	总442页 (文件大小：2618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD64F36902GP [RENESAS]

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