HD66120TA3 [RENESAS]
LIQUID CRYSTAL DISPLAY DRIVER, UUC269, SLIM, TCP-269;
| 型号： | HD66120TA3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC269, SLIM, TCP-269 驱动 |
| 文件： | 总21页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD66120T
(240-Channel Segment Driver for Dot-Matrix Graphic Liquid
Crystal Display)
ADE-207-283(Z)
'99.9
Rev. 0.0
Description
The HD66120T is a segment driver for dot-matrix graphic liquid crystal display (LCD). It features a
maximum driving voltage of 40V, enabling a high duty cycle. This driver operates at about 3V, making it
suitable for battery-driven applications that make use of the low power dissipation of liquid crystal
elements. The HD66120T, packaged in a fine-pitch slim tape carrier package (TCP), helps to reduce the
size of the frame around an LCD panel.
Features
•
•
•
•
•
•
Duty cycle: 1/100 to 1/480
High LCD driving voltage: 14 to 40V
240 LCD drive circuits
Low operating voltage: 2.7 to 5.5V
4- and 8-bit data bus interface
High-speed shift clocks
10 MHz (max) at 3-V operation
20 MHz (max) at 5-V operation
Display off function
•
•
•
•
Slim-TCP package
Fine output lead pitch: 70 µm/74 µm
Compact user area : 7.3 mm (when output lead pitch is 70 µm)
: 7.6 mm (when output lead pitch is 74 µm)
Internal chip enable signal generator
Standby function
•
•
1
HD66120T
Ordering Information
Type No.
Outer Lead Pitch (µm)
HD66120TA3
HD66120TA4
70
74
2
HD66120T
Pin Arrangement
Top view
Note: This figure does not specify the TCP dimensions; other TCP shapes are also possible.
3
HD66120T
Block Diagram
Y1–Y240
V1L–V4L
M
V1R–V4R
LCD drive circuit
Level shifter
VLCD1
VCC
VLCD2
GND2
DISP
GND1
CL1
Latch circuit 2
BS
Latch circuit 1
Latch circuit 1
D0–D7
Data shifter
SHL
CL2
Shift register
EIO2
EIO1
4
HD66120T
Block Functions
LCD Drive Circuit
The 240-bit LCD drive circuit generates four voltage levels V1, V2, V3, and V4, for driving an LCD panel.
One of the four levels is output to the corresponding Y pin, depending on the combination of the M signal
and the data in latch circuit 2.
Level Shifter
The level shifter changes 5-V signals into high-voltage signals for the LCD drive circuit.
Latch Circuit 2
240-bit latch circuit 2 latches data input from latch circuit 1, and outputs the latched data to the level
shifter, both at the falling edge of each clock 1 (CL1) pulse.
Latch Circuit 1
240-bit latch circuit 1 latches 4-bit or 8-bit parallel data input via the D0 to D7 pins at the timing generated
by the shift register.
Shift Register
The 60-bit shift register generates and outputs data latch signals for latch circuit 1 at the falling edge of
each clock 2 (CL2) pulse.
Data Shifter
The data shifter shifts the destinations of display data output, when necessary.
5
HD66120T
Pin Description
Symbol
VCC
Pin No.
247
Pin Name
VCC
Input/Output
—
Classification
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
GND1, GND2
VLCD1, VLCD2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
CL1
246, 264
241, 269
242, 268
245, 265
243, 267
244, 266
260
GND1, GND2
VLCD1, VLCD2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
Clock 1
—
—
Input
Input
Input
Input
Input
CL2
258
Clock 2
Input
M
262
M
Input
D0–D7
250–257
263
Data 0–data 7
Shift left
Input
SHL
Input
EIO1, EIO2
261, 249
Enable IO 1,
enable IO 2
Input/output
DISP
259
Display off
Bus select
Y1–Y240
Input
Control signal
Control signal
LCD drive output
BS
248
Input
Y1–Y240
1–240
Output
6
HD66120T
Pin Functions
Power Supply
VCC, VLCD, GND: VCC–GND1, GND2 supplies power to the internal logic circuits. VLCD–GND supplies
power to the LCD drive circuits. See Figure 1.
V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R: Supply different levels of power to drive the LCD. V1 and
V2 are selected levels, and V3 and V4 are non-selected levels.
Control Signals
CL1: Inputs display data latch pulses for latch circuit 2. Latch circuit 2 latches display data input from
latch circuit 1, and outputs LCD drive signals corresponding to the latched data, both at the falling edge of
each CL1 pulse.
CL2: Inputs display data latch pulses for latch circuit 1. Latch circuit 1 latches display data input via D0–
D7 at the falling edge of each CL2 pulse.
M: Changes LCD drive outputs to AC.
D0–D7: Input display data. High-voltage level (VCC level) of data corresponds to a selected level and turns
an LCD pixel on, and low-voltage level (GND level) data corresponds to a non-selected level and turns an
LCD pixel off.
SHL: Shifts the destinations of display data output, and determines which chip enable pin (EIO1 or EIO2)
is an input and which is an output. See Figure 2.
EIO1, EIO2: If SHL is VCC level, EIO1inputs the chip enable signal, and EIO2 outputs the signal. If SHL
is GND level, EIO1 outputs the chip enable signal, and EIO2 inputs the signal. The chip enable input pin of
the first HD66120T must be grounded, and those of the other HD66120Ts must be connected to the chip
enable output pin of the previous HD66120T. The chip enable output pin of the last HD66120T must be
open.
DISP: A low DISP sets LCD drive outputs Y1–Y240 to V2 level.
BS: Selects either the 4-bit or 8-bit display data bus interface. If BS is VCC level, the 8-bit bus is selected,
and if BS is GND level, the 4-bit bus is selected. In 4-bit bus mode, data is latched via D0–D3; D4–D7
must be grounded.
LCD Drive Output
Y1–Y240: Each Y outputs one of the four voltage levels V1, V2, V3, or V4, depending on the combination
of the M signal and display data levels. See Figure 3.
7
HD66120T
VLCD
VCC
GND, GND2
Figure 1 Power Supply for Logic and LCD Drive Circuits
SHL = VCC, BS = GND
Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233
Y8 Y7
D0 D1
Y6 Y5
D2 D3
Y4
Y3
Y2 Y1
D0
D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Last data
1st data
EIO1: chip enable input
EIO2: chip enable output
SHL = GND, BS = GND
Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233
Y8 Y7
D3 D2
Y6 Y5
D1 D0
Y4
Y3
Y2 Y1
D3
D2 D1 D0
D3 D2 D1 D0
D3 D2 D1 D0
1st data
Last data
EIO2: chip enable input
EIO1: chip enable output
SHL = VCC, BS = VCC
Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233
Y8 Y7
D0 D1
Y6 Y5
D2 D3
Y4
Y3
Y2 Y1
D0
D1 D2 D3
D4 D5 D6 D7
D4 D5 D6 D7
Last data
1st data
EIO1: chip enable input
EIO2: chip enable output
SHL = GND, BS = VCC
Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233
Y8 Y7
D7 D6
Y6 Y5
D5 D4
Y4
Y3
Y2 Y1
D7
D6 D5 D4
D3 D2 D1 D0
D3 D2 D1 D0
1st data
Last data
EIO2: chip enable input
EIO1: chip enable output
Figure 2 Selection of Destinations of Display Data Output
1
0
M
1
0
1
0
D
Y output level
V1
V3
V2
V4
Figure 3 Selection of LCD Drive Output Level
8
HD66120T
Operation Timing
4-Bit Bus Mode (BS = GND)
Figure 4 shows 4-bit data latch timing when SHL = GND, that is, the EIO2 pin is a chip enable input and
EIO1 pin is a chip enable output. When SHL = VCC, the EIO1 pin is a chip enable input and EIO2 pin is a
chip enable input.
When a low chip enable signal is input via the EIO1 pin, the HD66120T is first released from data standby
state, and, at the falling edge of the following CL2 pulse, it is released entirely from standby state and starts
latching data. It simultaneously latches 4 bits of data at the falling edge of each CL2 pulse. When it has
latched 236 bits of data, it sets the EIO2 signal low. When it has latched 240 bits of data, it automatically
stops and enters standby state, initiating the next HD66120T, as long as its EIO2 pin is connected to the
EIO1 pin of the next HD66120T.
The HD66120Ts output one line of data from the Y1–Y240 pins at the falling edge of each CL1 pulse. Data
d1 is output from Y1, and d240 from Y240 when SHL = GND, and d1 is output from Y240, and d240 from
Y1 when SHL = VCC. Data output level is either VLCD, V2, V3, or V4 depending on the combination of
the M signal and the data level.
1 line
CL2
1
2
3
59
60
d240
61
62
479 480 481
d4
d8
d12
D0
d1
d5
d9
d237
D3
CL1
EIO2
(No.1)
HD66120T no.1
latches data
EIO2
(No.2)
HD66120T no.2
latches data
EIO2
(No.3)
HD66120T no.3
latches data
EIO2
(No.8)
HD66120T no.8
latches data
Y1–Y240
Figure 4 4-Bit Data Latch Timing (BS = GND, 1 Line: 640-by-3 Dots)
9
HD66120T
8-Bit Bus Mode (BS = VCC
)
The operation is the same as that in 4-bit bus mode except that 8 bits of data are latched simultaneously.
1 line
CL2
1
2
3
29
30
d240
31
32
239 240 241
d8
d16
d24
D0
d1
d9
d17
d233
D7
CL1
EIO2
(No.1)
HD66120T no.1
latches data
EIO2
(No.2)
HD66120T no.2
latches data
EIO2
(No.3)
IHD66120T no.3
latches data
EIO2
HD66120T no.8
latches data
(No.8)
Y1–Y240
Figure 5 8-Bit Data Latch Timing (BS = VCC, 1 Line: 640-by-3 Dots)
10
HD66120T
Application Example
DISP
D0–D7
M
seg1920
seg1919
seg1918
CL2
CL1
V4L, R
V3L, R
V2L, R
V1L, R
640 × 3 × 480 LCD panel;
1/480 duty cycle
DISP
D0–D7
M
CL2
CL1
V4L, R
V3L, R
V2L, R
V1L, R
seg3
seg2
seg1
DISP
D0–D7
M
CL2
CL1
V4L, R
V3L, R
V2L, R
V1L, R
X1–X160
X1–X160
SHL
DIO1
CH
SHL
DIO1
CH
DIO2
DIO2
VLCD1,2
GND1, 2
VCC
VLCD1,2
GND1, 2
VCC
R1
R1
R2
R1
R1
+5V +40V
LCD controller
Notes: 1. The resistances of R1 and R2 depend on the type of the LCD panel used. For example, for an LCD panel with a 1/20
bias, R1 and R2 must be 3 kΩ and 48 kΩ, respectively. That is, R1/(4 • R1 + R2) should be 1/20.
2. To stabilize the power supply, place two 0.1-µF capacitors near each HD66120T, one between the VCC and GND
pins, and the other between the VLCD and GND pins.
3. The load must be less than 30 pF between the EIO2 and EIO1 connections of HD66120Ts.
11
HD66120T
Absolute Maximum Ratings
Item
Symbol
VCC
Rating
Unit
V
Notes
1, 4
Power supply voltage for logic circuits
Power supply voltage for LCD drive circuits
Input voltage 1
–0.3 to + 7.0
–0.3 to + 42
–0.3 to VCC + 0.3
–0.3 to VLCD + 0.3
–30 to +75
VLCD
VT1
V
1, 4
V
1, 2
Input voltage 2
VT2
V
1, 3
Operating temperature
Storage temperature
Topr
°C
°C
Tstg
–55 to +110
Notes: 1. The reference point is GND (0V).
2. Applies to input pins for logic circuits.
3. Applies to V1L, V1R, V2L, V2R, V3L, V3R, V4L, and V4R pins.
4. Power should be applied to VCC–GND first, and then VLCD–GND. It should be disconnected in
the reverse way.
5. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It
should always be used within its electrical characteristics in order to prevent malfunctioning or
degradation of reliability.
12
HD66120T
Electrical Characteristics
DC Characteristics 1 (VCC = 2.7 to 4.5V, VLCD–GND = 14 to 40V, and Ta = –30 to +75°C, unless
otherwise noted)
Item
Symbol Pins
Min
Max
Unit
V
Test Condition
Notes
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Vi–Yj on resistance
Input leakage current 1
Input leakage current 2
Current consumption 1
VIH
VIL
VOH
VOL
RON
IIL1
1
1
2
2
3
1
4
—
0.8 × VCC VCC
0
0.2 × VCC
V
VCC – 0.4
—
—
V
IOH = –0.4 mA
IOL = 0.4 mA
0.4
3.0
5.0
100
3.3
V
—
kΩ
µA
µA
mA
ION = 150 µA
1
–5.0
–100
—
VIN = VCC to GND
VIN = VLCD to GND
VCC = 3.0V
IIL2
2
2
ICC
f
f
CL2 = 10 MHz
CL1= 36 kHz
fM = 75 Hz
Current consumption 2
Current consumption 3
ILCD
IST
—
—
—
—
3.8
mA
mA
Same as above
Same as above
2
0.45
2, 3
Pins and notes at the end of the DC characteristics 2 table.
13
HD66120T
DC Characteristics 2 (VCC = 5V ± 10%, VLCD–GND = 14 to 40V, and Ta = –30 to +75°C, unless
otherwise noted)
Item
Symbol Pins
Min
Max
Unit
V
Test Condition
Notes
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Vi–Yj on resistance
Input leakage current 1
Input leakage current 2
Current consumption 1
VIH
VIL
VOH
VOL
RON
IIL1
1
0.8 × VCC VCC
1
0
0.2 × VCC
V
2
VCC – 0.4 —
V
IOH = –0.4 mA
IOL = 0.4 mA
2
—
0.4
V
3
—
3.0
5.0
100
10
kΩ
µA
µA
mA
ION = 150 µA
1
1
–5.0
–100
—
VIN = VCC to GND
VIN = VLCD to GND
fCL2 = 12 MHz
IIL2
4
2
2
ICC
247
f
CL1 = 36 kHz
fM = 75 Hz
Current consumption 2
Current consumption 3
ILCD
IST
241,
269
—
—
3.8
1.0
mA
mA
Same as above
2
247
Same as above
2, 3
Pins: 1. CL1, CL2, M, SHL, BS, EIO1, EIO2, DISP, D0–D7
2. EIO1, EIO2
3. Y1–Y240, VLCD1, VLCD2, V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R
4. V1L, V1R, V2L, V2R, V3L, V3R, V4L, V4R
Notes: 1. Indicates the resistance between one pin from Y1–Y240 and another pin from V1–V4, when load
current is applied to the Y pin; defined under the following conditions.
VLCD–GND = 40V
V1, V3 = VLCD – {1/20(VLCD–GND)}
V2, V4 = GND + {1/20(VLCD–GND)}
V1 and V3 should be near VLCD level, and V2 and V4 should be near GND level (Figure 6). All
voltage must be within ∆V. ∆V is the range within which RON, the LCD drive circuits’ output
impedance, is stable. Note that ∆V depends on power supply voltage VLCD–GND (Figure 7).
2. Input and output current is excluded. When a CMOS input is floating, excess current flows from
the power supply through the input circuit. To avoid this, VIH and VIL must be held to VCC and
GND levels, respectively.
3. Applies to standby mode.
14
HD66120T
VLCD
V1
V3
∆V
∆V
V4
V2
GND
Figure 6 Relation between Driver Output Waveform and Level Voltages
6.2
∆V (V)
Level voltage range
3.0
14
40
VLCD–GND (V)
Figure 7 Relation between VLCD–GND and ∆V
15
HD66120T
AC Characteristics 1 (VCC = 2.7 to 4.5V, VLCD–GND = 14 to 40V, and Ta = –30 to +75°C, unless
otherwise noted)
Item
Symbol
tCYC
tCWH2
tCWL2
tCWH1
tSCL
tHCL
tr
Pins
Min
100
37
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Clock cycle time
Clock high-level width 1
Clock low-level width 1
Clock high-level width 2
Clock setup time
Clock hold time
CL2
CL2
—
CL2
37
—
CL1
50
—
CL1, CL2
CL1, CL2
CL1, CL2
CL1, CL2
D0–D7, CL2
D0–D7, CL2
M, CL1
100
100
—
—
—
Clock rise time
50*1
50*1
—
Clock fall time
tf
—
Data setup time
tDS
35
Data hold time
tDH
35
—
M phase difference time
Output delay time 1
Output delay time 2
tCM
—
300
1.2
1.2
tpd1
CL1, Y1–Y240
M, Y1–Y240
—
tpd2
—
Notes at the end of the AC characteristics 2 table.
AC Characteristics 2 (VCC = 5V ± 10%, VLCD–GND = 14 to 40V, and Ta = –30 to +75°C, unless
otherwise noted)
Item
Symbol
tCYC
tCWH2
tCWL2
tCWH1
tSCL
tHCL
tr
Pins
Min
50
15
15
15
100
100
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Clock cycle time
Clock high-level width 1
Clock low-level width 1
Clock high-level width 2
Clock setup time
Clock hold time
CL2
CL2
—
CL2
—
CL1
—
CL1, CL2
CL1, CL2
CL1, CL2
CL1, CL2
D0–D7, CL2
D0–D7, CL2
M, CL1
—
—
Clock rise time
50*1
50*1
—
Clock fall time
tf
—
Data setup time
tDS
5
Data hold time
tDH
15
—
—
M phase difference time
Output delay time 1
Output delay time 2
tCM
300
0.7
0.7
tpd1
CL1, Y1–Y240
M, Y1–Y240
—
tpd2
—
Notes: 1. The clock rise and fall times (tr, tf) must satisfy the following relationships:
tr, tf < (tCYC – tCWH2 – tCWL2)/2
tr, tf ≤ 50 ns
2. The load must be less than 30 pF between the EIO2 and EIO1 connections of HD66120Ts.
16
HD66120T
tr
tCWH2
tf
tCWL2
tCYC
0.8 VCC
CL2
0.2 VCC
tDS
tDH
0.8 VCC
0.2 VCC
D0–D7
tCWH1
0.8 VCC
CL1
CL2
M
0.2 VCC
tSCL
tHCL
0.2 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tCM
CL1
M
0.2 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tpd1
tpd2
tpd1
tpd2
Y (n)
Figure 8 LCD Controller Interface Timing
17
HD66120T
LCD Driver LSI Power Supply Pin Connection
A feature of the LCD driver is the LCD drive power supply. As the number of pixel drives per LSI
increases, so does the voltage and number of outputs.
Consequently, if multi-output CMOS circuits are switched simultaneously, a wiring voltage drop may
occurs due to transient currents, and the potential between the LCD drive circuit power supply (VLCD) and
LCD drive level power supplies (V1, V6, and V3) or GND and the LCD level power supplies (V2, V5, and
V4) may be inverted, resulting in latchup breakdown. To prevent this, it is recommended that, when
designing the LCD drive power supply and board power supply wiring, the power supply wiring be
designed as low-impedance and capacitors be inserted in the wiring between VLCD and V1, V3, V6, and
between V2, V4, V5 and GND. In set evaluation, it is recommended that a check be carried out to confirm
that there is no inversion of the LCD drive power supply and level power supplies in the period between
when the LCD drive power supply is turned on and turned off.
Example of capacitor insertion (when VLCD = V1 and GND = V2)
VLCD, V1 pins
(COM, SEG)
+
–
+
–
+
–
V6 pin (COM)
V3 pin (SEG)
V4 pin (SEG)
V5 pin (COM)
+
–
Electrolytic capacitor
Ceramic capacitor
+
–
+
–
GND, V2 pins
(COM, SEG)
Figure 9 Example of Capacitor Insertion
18
HD66120T
Notes on Power-On/Off of the LCD Driver
To prevent an LCD driver display error at power on/off, the sequence for power-on signal activation must
be as follows (see figure 10):
2.7V
2.7V
VCC
0ms
0ms
0ms
0ms
VLCD
DISP
Input signals such as
CL1, CL2, and Data
Signal non-fixed Initializing period
period
(1frame or longer)
Figure 10 Sequence of Power-On/Off
At Power On
(1) Power on VCC. At this time, input 0 to the DISP pin.
(2) Display-off function forces the LCD driver to output a V2 level (lowest level).
(3) Display-off function takes priority even if the input signal status becomes irregular immediately after
VCC power-on.
(4) Input the specified signals to initialize registers of the LCD driver. Its period must be 1 frame or longer.
(5) Set the DISP level to 1 to cancel display-off function after steps (1) to (4). At this time, VLCD and each
V pin input must be at the specified levels.
19
HD66120T
At Power Off
Basically, the power-off procedure is the reverse of the power-on procedure.
(1) Set the DISP level to 0.
(2) Lower LCD driver power supply to 0V
(3) Lower VCC and each input signals to 0V
At this time, each V pin input must be at 0V. Display-off function stops when VCC falls to 0V, and
therefore, the LCD driver may output a level other than V2 (lowest level). As a result, a display error may
be caused at power-off or power-on.
20
HD66120T
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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