HD74AC112FPEL [RENESAS]

AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16;


型号：	HD74AC112FPEL
厂家：	RENESAS TECHNOLOGY CORP
描述：	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 光电二极管输出元件
文件：	总10页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

REJ03D0244–0200Z

(Previous ADE-205-364 (Z))

Rev.2.00

Jul.16.2004

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-

flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs

may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum

setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Features

•

Outputs Source/Sink 24 mA

HD74ACT112 has TTL-Compatible Inputs

•

Ordering Information: Ex. HD74AC112

Part Name

Package Type

Package Code Package Abbreviation Taping Abbreviation (Quantity)

HD74AC112FPEL SOP-16 pin (JEITA) FP-16DAV

HD74AC112RPEL SOP-16 pin (JEDEC) FP-16DNV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Pin Arrangement

CP₁

K₁

16 V_CC

15 C_D1

14 C_D2

13 CP₂

12 K₂

J₁

S_D1

Q₁

11 J₂

Q₂

10 S_D2

GND

9 Q₂

(Top view)

Rev.2.00, Jul.16.2004, page 1 of 7

HD74AC112/HD74ACT112

Logic Symbol

S_D1

S_D2

J₁

Q₁

J₂

Q₂

CP₁

CP₂

K₁

Q₁

K₂

Q₂

C_D1

C_D2

V_CC= Pin16

GND = Pin8

Pin Names

J₁, J₂, K₁, K₂

CP₁, CP₂

C_D1, C_D2

Data Inputs

Clock Pulse Inputs (Active Falling Edge)

Direct Clear Inputs (Active Low)

Direct Set Inputs (Active Low)

S_D1, S_D2

Q₁, Q₂, Q₁, Q ₂Outputs

Asynchronous Inputs:

Low input to S_Dsets Q to High level

Low input to C_Dsets Q to Low level

Clear and Set are independent of clock

Simultaneous Low on C_Dand S_Dmakes both Q and Q High

Truth Table

Inputs

@ t_n

Outputs

@ t_{n + 1}

t_n

t_{n + 1}

Bit time before clock pulse.

Bit time after clock pulse.

High Voltage Level

Low Voltage Level

Rev.2.00, Jul.16.2004, page 2 of 7

HD74AC112/HD74ACT112

Logic Diagram

S_D

C_D

#CP

Absolute Maximum Ratings

Item

Supply voltage

Symbol

Ratings

Unit

Condition

V_CC

–0.5 to 7

DC input diode current

I_IK

–20

V_I= –0.5V

V_I= Vcc+0.5V

DC input voltage

V_I

–0.5 to Vcc+0.5

DC output diode current

I_OK

–50

V_O= –0.5V

V_O= Vcc+0.5V

DC output voltage

V_O

–0.5 to Vcc+0.5

±50

DC output source or sink current

DC V_CCor ground current per output pin

Storage temperature

I_O

°C

I_CC, I_GND

Tstg

±50

–65 to +150

Recommended Operating Conditions: HD74AC112

Item

Symbol

V_CC

Ratings

Unit

Condition

Supply voltage

2 to 6

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

ns/V

Input rise and fall time

(except Schmitt inputs)

tr, tf

V_CC= 3.0V

V_CC= 4.5 V

V_CC= 5.5 V

V_IN30% to 70% V_CC

Rev.2.00, Jul.16.2004, page 3 of 7

HD74AC112/HD74ACT112

DC Characteristics: HD74AC112

Item

Sym-

bol

Vcc

(V)

Ta = 25°C

Ta = –40 to

Unit

Condition

+85°C

min.

2.1

3.15

3.85

—

typ.

1.5

max.

—

min.

2.1

3.15

3.85

—

max.

—

Input Voltage

V_IH

V_IL

3.0

V_OUT= 0.1 V or V_CC–0.1 V

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

2.25

2.75

1.50

2.25

2.75

2.99

4.49

5.49

—

0.9

1.35

1.65

—

0.9

1.35

1.65

—

V_OUT= 0.1 V or V_CC–0.1 V

—

Output voltage

V_OH

2.9

4.4

5.4

2.58

3.94

4.94

—

2.9

4.4

5.4

2.48

3.80

4.80

—

V_IN= V_ILor V_IH

I_OUT= –50 µA

—

V_IN= V_ILor V_IH

I_OH= –12 mA

—

I_OH= –24 mA

—

V_OL

0.002 0.1

0.001 0.1

0.1

0.37

±1.0

V_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.32

—

V_IN= V_ILor V_IH

I_OL= 12 mA

I_OL= 24 mA

—

0.32

±0.1

—

Input leakage

current

I_IN

—

µA

V_IN= V_CCor GND

Dynamic output

current*

I_OLD

I_OHD

I_CC

5.5

—

µA

V_OLD= 1.1 V

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

4.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

Recommended Operating Conditions: HD74ACT112

Item

Symbol

V_CC

Ratings

Unit

Condition

Supply voltage

2 to 6

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

ns/V

Input rise and fall time

(except Schmitt inputs)

tr, tf

_CC= 4.5V

_CC= 5.5V

V_IN0.8 to 2.0 V

Rev.2.00, Jul.16.2004, page 4 of 7

HD74AC112/HD74ACT112

DC Characteristics: HD74ACT112

Item

Sym-

bol

V_CC

(V)

Ta = 25°C

Ta = –40 to

Unit

Condition

+85°C

min.

2.0

—

typ.

1.5

4.49

5.49

—

max.

—

min.

2.0

—

max.

—

Input voltage

V_IH

V_IL

4.5

_OUT= 0.1 V or Vcc–0.1 V

_IN= V_ILor V_IH

5.5

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

—

0.8

—

0.8

—

Output voltage

V_OH

4.4

5.4

3.94

4.94

—

4.4

5.4

3.80

4.80

—

I_OUT= –50 µA

—

V_IN= V_IL

I_OH= –24 mA

—

V_OL

0.001 0.1

0.1

0.37

±1.0

1.5

—

V_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.6

—

0.32

—

V_IN= V_IL

I_OL= 24 mA

—

0.32

±0.1

—

Input current

I_IN

—

µA

V_IN= V_CCor GND

V_IN= V_CC–2.1 V

V_OLD= 1.1 V

I_CC/input current

I_CCT

I_OLD

I_OHD

I_CC

—

µA

Dynamic output

current*

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

—

4.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

AC Characteristics: HD74AC112

Ta = +25°C

C_L= 50 pF

Typ

Ta = –40°C to +85°C

C_L= 50 pF

Item

Maximum clock

frequency

Symbol V_CC(V)*¹

Min

125

Max

Min

Max

Unit

f_max

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

—

100

125

1.0

—

MHz

150

1.0

—

Propagation delay

t_PLH

t_PHL

t_PLH

t_PHL

11.0

8.5

11.0

8.5

9.5

7.0

11.5

9.0

14.0

11.0

14.0

11.0

12.5

9.5

15.0

12.0

15.0

12.0

13.5

10.5

15.5

12.5

C_Pto Q or Q

Propagation delay

C_Pto Q or Q

Propagation delay

C_D, S_Dto Q or Q

Propagation delay

C_D, S_Dto Q or Q

14.5

11.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Rev.2.00, Jul.16.2004, page 5 of 7

HD74AC112/HD74ACT112

AC Operating Requirements: HD74AC112

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

Setup time

J or K to C_P

Hold time

t_su

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.0

2.0

5.5

6.0

4.5

0.0

7.0

5.0

3.5

3.0

4.5

0.0

5.5

4.5

3.5

3.0

t_h

–1.5

–0.5

2.0

C_Pto J or K

Pulse width

t_w

C_Por C_Dor S_D

Recovery time

C_Dor S_Dto C_P

2.0

t_rec

1.5

1.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics: HD74ACT112

Ta = +25°C

C_L= 50 pF

Ta = –40°C to +85°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Min

100

Typ

Max

Min

Max

Unit

Maximum clock

frequency

f_max

5.0

—

MHz

Propagation delay

C_Pto Q or Q

Propagation delay

C_Pto Q or Q

Propagation delay

C_D, S_Dto Q or Q

Propagation delay

t_PLH

t_PHL

t_PLH

t_PHL

1.0

10.5

8.0

13.0

1.0

14.0

11.0

13.5

13.0

10.0

12.5

10.5

C_D, S_Dto Q or Q

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74ACT112

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

Setup time

J or K to C_P

Hold time

C_Pto J or K

Pulse width

C_Por C_Dor S_D

Recovery time

C_D, S_Dto C_P

t_su

5.0

2.5

0.0

7.0

8.0

1.5

8.0

3.0

t_h

1.5

7.0

3.0

t_w

4.5

t_rec

–2.5

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

Capacitance

Item

Input capacitance

Symbol

Typ

Unit

Condition

C_IN

4.5

V_CC= 5.5 V

V_CC= 5.0 V

Power dissipation capacitance

C_PD

35.0

Rev.2.00, Jul.16.2004, page 6 of 7

HD74AC112/HD74ACT112

Package Dimensions

As of January, 2003

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0˚ – 8˚

1.27

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

Package Code

JEDEC

FP-16DAV

—

JEITA

Mass (reference value)

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

1.27

+ 0.10

6.10

– 0.30

1.08

0.635 Max

0˚ – 8˚

+ 0.67

0.60

– 0.20

*0.40 ± 0.06

0.15

0.25

Package Code

JEDEC

JEITA

FP-16DNV

Conforms

0.15 g

*Ni/Pd/Au plating

Mass (reference value)

Rev.2.00, Jul.16.2004, page 7 of 7

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HD74AC112FPEL [RENESAS]

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