HD74AC112T-EL [RENESAS]

AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, TTP-16DA;


型号：	HD74AC112T-EL
厂家：	RENESAS TECHNOLOGY CORP
描述：	AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, TTP-16DA 光电二极管输出元件逻辑集成电路触发器
文件：	总10页 (文件大小：57K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to

each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level

of the J and K inputs may change when the clock is High and the bistable will perform according to the

Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs

on the falling edge of the clock pulse.

Features

•

Outputs Source/Sink 24 mA

HD74ACT112 has TTL-Compatible Inputs

Pin Arrangement

CP₁

K₁

16 V_CC

15 C_D1

14 C_D2

13 CP₂

12 K₂

J₁

S_D1

Q₁

11 J₂

Q₂

10 S_D2

9 Q₂

GND

(Top view)

HD74AC112/HD74ACT112

Logic Symbol

S_D1

S_D2

J₁

Q₁

J₂

Q₂

CP₁

CP₂

K₁

K₂

C_D1

C_D2

V_CC= Pin16

GND = Pin8

Pin Names

J₁, J₂, K₁, K₂

CP₁, CP₂

C_D1, C_D2

Data Inputs

Clock Pulse Inputs (Active Falling Edge)

Direct Clear Inputs (Active Low)

Direct Set Inputs (Active Low)

S_D1, S_D2

Q₁, Q₂, Q₁, Q₂Outputs

Asynchronous Inputs:

Low input to S_Dsets Q to High level

Low input to C_Dsets Q to Low level

Clear and Set are independent of clock

Simultaneous Low on C_Dand S_Dmakes both Q and Q High

HD74AC112/HD74ACT112

Truth Table

Inputs

Outputs

@t_n

@t_{n + 1}

t_n

Bit time before clock pulse.

t_{n + 1}

Bit time after clock pulse.

High Voltage Level

Low Voltage Level

Logic Diagram

S_D

C_D

#CP

DC Characteristics (unless otherwise specified)

Item

Symbol Max

Unit

Condition

Maximum quiescent supply current

I_CC

I_CCT

µA

V_IN= V_CCor ground, V_CC= 5.5 V,

Ta = Worst case

Maximum quiescent supply current

8.0

1.5

µA

V_IN= V_CCor ground, V_CC= 5.5 V,

Ta = 25°C

Maximum additional I_CC/input

(HD74ACT112)

V_IN= V_CC– 2.1 V, V_CC= 5.5 V

Ta = Worst case

HD74AC112/HD74ACT112

AC Characteristics: HD74AC112

Ta = +25°C

Ta = –40°C to +85°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Min

125

150

1.0

Typ

Max

—

Min

100

125

1.0

Max

—

Unit

Maximum clock

frequency

f_max

t_PLH

t_PHL

t_PLH

t_PHL

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

—

MHz

—

Propagation delay

C_Pto Q or Q

11.0

8.5

11.0

8.5

9.5

7.0

11.5

9.0

14.0

11.0

14.0

11.0

12.5

9.5

15.0

12.0

15.0

12.0

13.5

10.5

15.5

12.5

Propagation delay

C_Pto Q or Q

Propagation delay

C_D, S_Dto Q or Q

Propagation delay

C_D, S_Dto Q or Q

14.5

11.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74AC112

Ta = –40°C

to +85°C

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹Typ

Guaranteed Minimum

Unit

Setup time

J or K to C_P

Hold time

t_su

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.0

5.5

4.5

0.0

5.5

4.5

3.5

3.0

6.0

4.6

0.0

7.0

5.0

3.5

3.0

2.0

t_h

–1.5

–0.5

2.0

C_Pto J or K

Pulse width

C_Por C_Dor S_D

Recovery time

C_Dor S_Dto C_P

t_w

2.0

t_rec

–1.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

HD74AC112/HD74ACT112

AC Characteristics: HD74ACT112

Ta = +25°C

Ta = –40°C to +85°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Min

Typ

Max

Min

Max

Unit

Maximum clock

frequency

f_max

t_PLH

t_PHL

t_PLH

t_PHL

5.0

100

—

MHz

Propagation delay

C_Pto Q or Q

1.0

10.5

8.0

13.0

10.0

12.5

1.0

14.0

11.0

13.5

Propagation delay

C_Pto Q or Q

Propagation delay

C_D, S_Dto Q or Q

Propagation delay

10.5

C_D, S_Dto Q or Q

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74ACT112

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹Typ

Guaranteed Minimum

Unit

Setup time

J or K to C_P

t_su

5.0

2.5

0.0

4.5

–2.5

7.0

1.5

7.0

3.0

8.0

1.5

8.0

3.0

Hold time

C_Pto J or K

t_h

Pulse width

C_Por C_Dor S_D

t_w

Recovery time

t_rec

C_D, S_Dto C_P

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

Capacitance

Item

Symbol

C_IN

Typ

4.5

Unit

Condition

V_CC= 5.5 V

V_CC= 5.0 V

Input capacitance

Power dissipation capacitance

C_PD

35.0

Unit: mm

19.20

20.00 Max

1.3

1.11 Max

7.62

+ 0.13

– 0.05

0.25

2.54 ± 0.25

0.48 ± 0.10

0° – 15°

Hitachi Code

DP-16

JEDEC

EIAJ

Conforms

Weight (reference value) 1.07 g

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0° – 8°

1.27

0.70 ± 0.20

*0.42 ± 0.08

0.40 ± 0.06

0.15

0.12

Hitachi Code

JEDEC

EIAJ

FP-16DA

—

Conforms

*Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.24 g

Unit: mm

9.9

10.3 Max

1.27

+ 0.10

6.10

– 0.30

1.08

0.635 Max

0° – 8°

+ 0.67

0.60

– 0.20

*0.42 ± 0.08

0.40 ± 0.06

0.15

0.25

Hitachi Code

JEDEC

EIAJ

FP-16DN

Conforms

*Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.15 g

Unit: mm

5.00

5.30 Max

0.65

0.13 M

0.65 Max

1.0

+ 0.08

– 0.07

*0.22

0.20 ± 0.06

6.40 ± 0.20

0° – 8°

0.50 ± 0.10

0.10

Hitachi Code

JEDEC

EIAJ

TTP-16DA

—

*Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.05 g

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

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Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

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Tel: 535-2100

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