HD74AC123ARPEL [RENESAS]
Dual Retriggerable Resettable Multivibrator; 双可重触发复位多谐振荡器
| 型号： | HD74AC123ARPEL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Retriggerable Resettable Multivibrator |
| 文件： | 总7页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC123A
Dual Retriggerable Resettable Multivibrator
REJ03D0245–0200Z
(Previous ADE-205-365 (Z))
Rev.2.00
Jul.16.2004
Description
Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding
Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth
Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output
pulse period (Q High, Q Low) can be made as long as desired. Alternatively, a delay period can be terminated at any
time by a Low signal on CD, which also inhibits triggering. An internal connection from CD to the input gate makes it
possible to trigger the circuit by a positive-going signal on CD, as shown in the Truth Table. For timing capacitor values
greater than 1000 pF, the output pulse width is defined as follows.
Where tw is in ns, RX is in kΩ and CX is in pF.
tw = RXCX
Features
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
HD74AC123AP
Package Type
DIP-16 pin
Pacation Taping Abbreviation (Quantity)
D
—
HD74AC123AFPEL SOP-16 pin (JEITA)
HD74AC123ARPEL SOP-16 pin (JEDE
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Notes: 1. Please consult the sales ailability.
2. The packages with leom the conventional products by adding V at the end of
the package code.
Pin Arrangemen
B1
1
2
3
4
5
6
7
8
16 VCC
15 RX1CX1
14 CX1
13 Q1
CD1
Q1
Q2
12 Q2
CX2
11 CD2
10 B2
RX2CX2
GND
9
A2
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 6
HD74AC123A
Logic Symbol
7 6
(15) (14)
RXCX
CX
Q
5(13)
12(4)
A
B
9(1)
10(2)
Q
CD
11
(3)
VCC = Pin16
GND = Pin8
Pin Names
A1, A 2
B1, B2
CD1, CD2
Q1, Q2
Q1, Q 2
Trigger Inputs (Active Falling Edge)
Trigger Inputs (Active Rising Edge)
Direct Clear Inputs (Active Low)
Positive Pulse Outputs
Negative Pulse Outputs
Triggering Truth Table
Inputs
A
CD
Response
No trigger
No trigger
Trigger
No trigger
Trigger
X
L
X
H
X
H
H
L
L
H
Trigger
H : High Voltage Level
L
X
:
:
:
Low Voltage Level
Immaterial
Low-to-High Transition
:
High-to-Low Transition
Rev.2.00, Jul.16.2004, page 2 of 6
HD74AC123A
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
Symbol
VCC
IIK
Ratings
–0.5 to 7
–20
Unit
Condition
VI = –0.5V
V
mA
mA
V
20
VI = Vcc+0.5V
DC input voltage
VI
–0.5 to Vcc+0.5
DC output diode current
IOK
–50
50
mA
mA
V
mA
mA
°C
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
VO
IO
ICC, IGND
Tstg
–0.5 to Vcc+0.5
±50
±50
DC output source or sink current
DC VCC or ground current per output pin
Storage temperature
–65 to +150
Recommended Operating Conditions
Item
Symbol
Ratings
2 to 6
Unit
Condition
Supply voltage
VCC
Input and output voltage
Operating temperature
VI, VO
Ta
tr, tf
0 to VCC
–40 to +85
8
Input rise and fall time
(except Schmitt inputs)
VCC = 3.0V
CC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
DC Characteristics
Item
Sym-
bol
Vcc
(V)
Ta = 2
nit
Condition
min.
2.1
85
—
x.
—
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.
4.
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
49
5.49
—
—
1.65
—
—
—
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
Output voltage
.94
4.94
—
—
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
V
VIN = VIL or VIH
IOUT = –50 µA
VIN = VIL or VIH
IOH = –12 mA
—
—
IOH = –24 mA
IOH = –24 mA
VOL
0.002 0.1
0.001 0.1
0.001 0.1
—
—
—
—
VIN = VIL or VIH
IOUT = 50 µA
0.32
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
0.32
0.32
±0.1
—
—
—
—
Input leakage
current
IIN
µA
VIN = VCC or GND
Dynamic output
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
—
—
—
130
86
–75
—
—
—
220
mA
mA
µA
VOLD = 1.1 V
VOHD = 3.85 V
VIN = VCC or ground
current*
Quiescent supply
current
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 3 of 6
HD74AC123A
AC Characteristics: HD74AC123A
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1 Min
Typ
Max
19.0
15.0
19.0
15.0
15.0
12.0
15.0
12.0
Min
1.0
Max
22.0
Unit
ns
Condition
Cext = 0 pF
Rest = 5 kΩ
Propagation delay
A or B to Q
Propagation delay
A or B to Q
tPLH
tPHL
tPLH
tPHL
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
—
—
—
—
—
—
—
1.0
1.0
1.0
1.0
1.0
1.0
1.0
17.0
22.0
17.0
18.0
13.5
18.0
13.5
ns
ns
ns
Propagation delay
C
Dn to Q
Propagation delay
Dn to Q
C
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC123A
T
Ta = +25°C
CL = 50 pF
Item
Pulse width
A or B or CDn
Symbol VCC (V)*1
Typ
Guara
Condition
tw
3.3
5.0
3.3
5.0
—
—
—
—
5.0
ext = 0 pF
Rext = 5 kΩ
4.
Recovery time
trec
s
CDn to A or B
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = –40°C
to +85°C
CL = 50 pF
Item
Output pulse width TWQ
Symbo
Max
Min
Max
Unit
ms
Condition
—
—
—
1.10
350
300
—
—
Cext = 0.1 µF
Rext = 10 kΩ
Cext = 28 pF
RΩext = 2 k
0.85
170
140
1.15
380
330
Minimum output
pulse width
ns
Note: 1. Voltage Range V
Voltage Range 5.0 0.5 V
Cext and Rext should be connectes close to the IC terminals as possible, in order to prevent malfunction.
Rev.2.00, Jul.16.2004, page 4 of 6
HD74AC123A
Package Dimensions
As of January, 2003
Unit: mm
19.2
20.32 Max
16
9
1
8
1.3
0.89
7.62
0.48 ± 0.1
2.54 ± 0.25
ms
orms
05 g
Unit: mm
19
20.
16
8
7.62
*0.25 ± 0.06
*0.48 ± 0.08
2.54 ± 0.25
0˚ – 15˚
Package Code
JEDEC
JEITA
DP-16FV
Conforms
Conforms
1.05 g
*NI/Pd/AU Plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 5 of 6
HD74AC123A
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Packag
JED
6DAV
JE
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9
10.
16
+ 0.10
6.10
– 0.30
1.08
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.4
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 6 of 6
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technolproduct best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belons Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party'in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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5. Renesas Technology Corp. semiconductors are not designed or manufactureder circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an autstributor when considering the use of a
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