HD74ACT107RPEL [RENESAS]

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SOP-14;


型号：	HD74ACT107RPEL
厂家：	RENESAS TECHNOLOGY CORP
描述：	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SOP-14 光电二极管输出元件逻辑集成电路触发器
文件：	总7页 (文件大小：208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74AC107/HD74ACT107

Dual JK Flip-Flop (with Separate Clear and Clock)

REJ03D0243–0200Z

(Previous ADE-205-363 (Z))

Rev.2.00

Jul.16.2004

Description

The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the

master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors

which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2)

enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave.

Features

•

Outputs Source/Sink 24 mA

HD74ACT107 has TTL-Compatible Inputs

•

Ordering Information: Ex. HD74AC107

Part Name

Package Type

Package Code Package Abbreviation Taping Abbreviation (Quantity)

HD74AC107FPEL SOP-14 pin (JEITA) FP-14DAV

HD74AC107RPEL SOP-14 pin (JEDEC) FP-14DNV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Pin Arrangement

J₁

K₁

Q₂

14 V_CC

13 C_D1

12 CP₁

11 K₂

10 C_D2

CP₂

GND 7

J₂

(Top view)

Rev.2.00, Jul.16.2004, page 1 of 6

HD74AC107/HD74ACT107

Logic Symbol

J₁

Q₁

J₂

Q₂

CP₁

CP₂

K₁

Q₁

K₂

Q₂

C_D1

C_D2

V_CC= Pin14

GND = Pin7

Pin Names

J₁, J₂, K₁, K₂

CP₁, CP₂

Data Inputs

Clock Pulse Inputs (Active Falling Edge)

Direct Clear Inputs (Active Low)

C_D1, C_D2

Q₁, Q₂, Q₁, Q ₂Outputs

Truth Table

Inputs

Outputs

@ t_{n + 1}

@ t_n

t_n

t_{n + 1}

High Voltage Level

Low Voltage Level

Bit time before clock pulse.

Bit time after clock pulse.

Logic Diagram

C_D

#CP

Rev.2.00, Jul.16.2004, page 2 of 6

HD74AC107/HD74ACT107

Absolute Maximum Ratings

Item

Supply voltage

Symbol

V_CC

Ratings

–0.5 to 7

Unit

Condition

V_I= –0.5V

DC input diode current

I_IK

–20

V_I= Vcc+0.5V

DC input voltage

V_I

–0.5 to Vcc+0.5

DC output diode current

I_OK

–50

V_O= –0.5V

V_O= Vcc+0.5V

DC output voltage

V_O

–0.5 to Vcc+0.5

±50

DC output source or sink current

DC V_CCor ground current per output pin

Storage temperature

I_O

°C

I_CC, I_GND

Tstg

±50

–65 to +150

Recommended Operating Conditions: HD74AC107

Item

Symbol

V_CC

Ratings

Unit

Condition

Supply voltage

2 to 6

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

ns/V

Input rise and fall time

(except Schmitt inputs)

tr, tf

V_CC= 3.0V

V_CC= 4.5 V

V_CC= 5.5 V

V_IN30% to 70% V_CC

DC Characteristics: HD74AC107

Item

Sym-

bol

Vcc

(V)

Ta = 25°C

Ta = –40 to

+85°C

min. max.

Unit

Condition

min.

2.1

3.15

3.85

—

typ.

1.5

max.

—

Input Voltage

V_IH

V_IL

3.0

2.1

3.15

3.85

—

V_OUT= 0.1 V or V_CC–0.1 V

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

2.25

2.75

1.50

2.25

2.75

2.99

4.49

5.49

—

0.9

1.35

1.65

—

0.9

1.35

1.65

—

Output voltage

V_OH

2.9

4.4

5.4

2.58

3.94

4.94

—

2.9

4.4

5.4

2.48

3.80

4.80

—

V_IN= V_ILor V_IH

I_OUT= –50 µA

—

V_IN= V_ILor V_IH

I_OH= –12 mA

—

I_OH= –24 mA

—

V_OL

0.002 0.1

0.001 0.1

0.1

0.37

±1.0

V_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.32

—

V_IN= V_ILor V_IH

I_OL= 12 mA

I_OL= 24 mA

—

0.32

±0.1

—

Input leakage

current

I_IN

—

µA

V_IN= V_CCor GND

Dynamic output

current*

I_OLD

I_OHD

I_CC

5.5

—

µA

V_OLD= 1.1 V

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

4.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

Rev.2.00, Jul.16.2004, page 3 of 6

HD74AC107/HD74ACT107

Recommended Operating Conditions: HD74ACT107

Item

Symbol

V_CC

Ratings

Unit

Condition

Supply voltage

2 to 6

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

Input rise and fall time

(except Schmitt inputs)

tr, tf

ns/V

_CC= 4.5V

_CC= 5.5V

V_IN0.8 to 2.0 V

DC Characteristics: HD74ACT107

Item

Sym-

bol

V_CC

(V)

Ta = 25°C

Ta = –40 to

+85°C

min. max.

Unit

Condition

min.

2.0

—

typ.

1.5

4.49

5.49

—

max.

—

Input voltage

V_IH

V_IL

4.5

2.0

—

_OUT= 0.1 V or Vcc–0.1 V

_IN= V_ILor V_IH

5.5

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

—

0.8

—

0.8

—

Output voltage

V_OH

4.4

5.4

3.94

4.94

—

4.4

5.4

3.80

4.80

—

I_OUT= –50 µA

—

V_IN= V_IL

I_OH= –24 mA

—

V_OL

0.001 0.1

0.1

0.37

±1.0

1.5

—

_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.6

—

0.32

—

V_IN= V_IL

I_OL= 24 mA

—

0.32

±0.1

—

Input current

I_IN

—

µA

V_IN= V_CCor GND

V_IN= V_CC–2.1 V

V_OLD= 1.1 V

I_CC/input current

I_CCT

I_OLD

I_OHD

I_CC

—

µA

Dynamic output

current*

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

—

4.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

AC Characteristics: HD74AC107

Ta = +25°C

C_L= 50 pF

Typ

Ta = –40°C to +85°C

C_L= 50 pF

Item

Maximum clock

frequency

Symbol V_CC(V)*¹

Min

125

Max

Min

Max

Unit

f_max

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

—

100

125

1.0

—

MHz

150

1.0

—

Propagation delay

t_PLH

t_PHL

t_PLH

t_PHL

9.5

7.5

10.0

8.0

9.5

7.5

9.5

7.5

13.0

10.0

13.5

10.5

13.0

10.0

13.0

10.0

14.0

11.0

14.5

11.5

14.0

11.0

14.0

11.0

C_Pto Q or Q

Propagation delay

C_Pto Q or Q

Propagation delay

C_Dto Q

Propagation delay

C_Dto Q

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Rev.2.00, Jul.16.2004, page 4 of 6

HD74AC107/HD74ACT107

Operating Requirements: HD74AC107

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

Setup time

J or k to C_P

Hold time

C_Pto J or k

Pulse width

C_Por C_D

t_su

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.0

2.0

5.5

6.0

4.5

0.0

7.0

5.0

3.0

4.0

0.0

5.5

4.5

3.0

t_h

–1.5

–0.5

2.0

t_w

2.0

Recovery time

t_rec

1.5

C_Dto C_P

1.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics: HD74ACT107

Ta = +25°C

C_L= 50 pF

Ta = –40°C to +85°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Min

100

Typ

Max

Min

Max

Unit

Maximum clock

frequency

f_max

5.0

—

MHz

Propagation delay

C_Pto Q or Q

Propagation delay

C_Pto Q or Q

Propagation delay

t_PLH

t_PHL

t_PLH

t_PHL

1.0

9.5

10.5

8.5

12.5

1.0

13.5

14.0

12.0

13.0

11.0

C_Dto Q

Propagation delay

C_Dto Q

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

Operating Requirements: HD74ACT107

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

Setup time

J or k to C_P

Hold time

C_Pto J or k

Pulse width

C_Por C_D

Recovery time

t_su

5.0

2.5

0.0

4.5

—

7.0

8.0

1.5

8.0

3.0

t_h

1.5

7.0

3.0

t_w

t_rec

C_Dto C_P

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

Capacitance

Item

Input capacitance

Symbol

Typ

Unit

Condition

C_IN

4.5

V_CC= 5.5 V

V_CC= 5.0 V

Power dissipation capacitance

C_PD

35.0

Rev.2.00, Jul.16.2004, page 5 of 6

HD74AC107/HD74ACT107

Package Dimensions

As of January, 2003

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

1.42 Max

1.15

0˚ – 8˚

1.27

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

Package Code

JEDEC

FP-14DAV

—

JEITA

Mass (reference value)

Conforms

0.23 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

8.65

9.05 Max

+ 0.10

6.10

– 0.30

0.635 Max

1.08

0˚ – 8˚

+ 0.67

1.27

*0.40 ± 0.06

0.60

– 0.20

0.15

0.25

Package Code

JEDEC

JEITA

FP-14DNV

Conforms

0.13 g

*Ni/Pd/Au plating

Mass (reference value)

Rev.2.00, Jul.16.2004, page 6 of 6

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HD74ACT107RPEL [RENESAS]

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