HD74ALVCH16260T_技术文档

HD74ALVCH16260

12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs

ADE-205-135B (Z)

3rd. Edition

December 1999

Description

The HD74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two

separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical

applications include multiplexing and / or demultiplexing of address and data information in

microprocessor or bus interface applications. This device is also useful in memory interleaving

applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and /

or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.

The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and / or data

information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and

LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is

transparent. When the latch enable input goes low, the data present at the inputs is latched and remains

latched until the latch enable input is returned high. Active bus hold circuitry is provided to hold unused or

floating data inputs at a valid logic level.

Features

•

V_CC= 2.3 V to 3.6 V

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

Typical V_OHundershoot > 2.0 V (@V_CC= 3.3 V, Ta = 25°C)

High output current ±24 mA (@V_CC= 3.0 V)

Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

HD74ALVCH16260

Function Table

Inputs

Output A

1B

H

L

2B

X

SEL

H

LE1B

LE2B

OEA

H

L

X

H

L

H

L

X

H

*1

X

H

A₀

X

H

L

X

H

L

X

L

*1

X

L

A₀

X

Z

B-to-A (OEB = H)

Inputs

Outputs

A

H

L

LEA1B

LEA2B

OE1B

OE2B

1B

H

L

2B

H

L

H

L

H

L

H

L

*1

H

L

H

L

2B₀

*1

L

2B₀

*1

H

L

H

L

1B₀

H

L

*1

L

1B₀

*1

X

L

1B₀

2B₀

X

H

Z

H

Active

Z

L

Active

L

Active

A-to-B (OEA = H)

H : High level

L : Low level

X : Immaterial

Z : High impedance

Note: 1. Output level before the indicated steady state input conditions were established.

2

HD74ALVCH16260

Pin Arrangement

OE2B

OEA 1

56

LE1B 2

55 LEA2B

54

53

52

51

50

2B4

GND

2B5

2B6

V_CC

2B3

GND

2B2

3

4

5

6

2B1

V_CC

7

8

A1

A2

49 2B7

2B8

2B9

GND

9

48

47

46

10

11

12

A3

GND

A4

45 2B10

2B11

2B12

1B12

44

43

42

A5 13

A6 14

A7

A8

A9

15

41 1B11

1B10

16

17

40

39 GND

38 1B9

37 1B8

GND

A10

18

19

20

A11

A12 21

1B7

36

35

34

33

32

31

30

29

V_CC

1B1

22

23

24

25

26

27

28

V_CC

1B6

1B2

1B5

GND

1B3

GND

1B4

LE2B

SEL

LEA1B

OE1B

(Top view)

3

HD74ALVCH16260

Absolute Maximum Ratings

Item

Symbol

Ratings

–0.5 to 4.6

–0.5 to V_CC+0.5

–50

Unit

V

Conditions

Supply voltage

Input voltage ^{*1, 2}

V_CC

V_I

V

Except I/O ports

I/O ports

Output voltage ^{*1, 2}

V_O

V

Input clamp current

I_IK

mA

W

V_I< 0

Output clamp current

Continuous output current

V_CC, GND current / pin

I_OK

±50

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

I_O

±50

I_CCor I_GND

P_T

±100

Maximum power dissipation

1

TSSOP

at Ta = 55°C (in still air) ^*3

Storage temperature

Tstg

–65 to 150

°C

Notes:

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or

any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp

current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C

and a board trace length of 750 mils.

Recommended Operating Conditions

Item

Symbol

V_CC

Min

2.3

0

Max

3.6

V_CC

–12

–24

12

Unit

V

Conditions

Supply voltage

Input voltage

V_I

V

Output voltage

High level output current

V_O

0

V

I_OH

—

0

mA

V_CC= 2.3 V

V_CC= 2.7 V

V_CC= 3.0 V

V_CC= 2.3 V

V_CC= 2.7 V

V_CC= 3.0 V

Low level output current

I_OL

mA

12

24

Input transition rise or fall rate

Operating temperature

∆t / ∆v

10

ns / V

Ta

–40

85

°C

Note: Unused control inputs must be held high or low to prevent them from floating.

4

HD74ALVCH16260

Logic Diagram

2

LE1B

27

LE2B

30

LEA1B

55

LEA2B

56

OE2B

29

OE1B

1

OEA

28

SEL

C1

1D

C1

1D

G1

8

23

1

1B1

A1

1

6

2B1

C1

1D

C1

1D

To eleven other channels

5

HD74ALVCH16260

Electrical Characteristics (Ta = –40 to 85°C)

Item

Symbol V_CC(V) ^*1

Min

Max

—

Unit Test Conditions

Input voltage

V_IH

2.3 to 2.7 1.7

2.7 to 3.6 2.0

V

—

V_IL

2.3 to 2.7

2.7 to 3.6

—

0.7

0.8

—

Output voltage

V_OH

Min to Max V_CC–0.2

V

I_OH= –100 µA

2.3

2.7

3.0

2.0

1.7

2.2

2.4

2.0

—

I_OH= –6 mA, V_IH= 1.7 V

I_OH= –12 mA, V_IH= 1.7 V

I_OH= –12 mA, V_IH= 2.0 V

I_OH= –24 mA, V_IH= 2.0 V

I_OL= 100 µA

—

V_OL

Min to Max —

0.2

0.4

0.7

0.4

0.55

±5

2.3

—

I_OL= 6 mA, V_IL= 0.7 V

I_OL= 12 mA, V_IL= 0.7 V

I_OL= 12 mA, V_IL= 0.8 V

I_OL= 24 mA, V_IL= 0.8 V

V_IN= V_CCor GND

V_IN= 0.7 V

2.3

—

2.7

—

3.0

—

Input current

I_IN

3.6

—

µA

I_{IN (hold)}

2.3

45

–45

75

–75

—

2.3

—

V_IN= 1.7 V

3.0

—

V_IN= 0.8 V

3.0

—

V_IN= 2.0 V

3.6

±500

±10

40

V_IN= 0 to 3.6 V

Off state output current ^*2I_OZ

Quiescent supply current I_CC

3.6

—

µA

V_OUT= V_CCor GND

V_IN= V_CCor GND

3.6

—

∆I_CC

3.0 to 3.6

—

750

V_IN= one input at (V_CC–0.6) V,

other inputs at V_CCor GND

Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

2. For I/O ports, the parameter I_OZincludes the input leakage current.

6

HD74ALVCH16260

Switching Characteristics (Ta = –40 to 85°C)

Item

Symbol V_CC(V) Min

Typ

Max

Unit FROM

(Input)

TO

(Output)

Maximum clock frequency f_max

2.5±0.2 150

2.7 150

—

3.5

9.0

—

MHz

—

3.3±0.3 150

2.5±0.2 1.2

—

Propagation delay time

t_PLH

t_PHL

5.6

5.1

4.3

6.2

5.2

4.4

6.9

6.6

5.6

6.7

6.4

5.4

5.7

5.0

4.6

—

ns

A or B

LE

B or A

A or B

A

2.7

—

3.3±0.3 1.2

2.5±0.2 1.0

2.7

—

3.3±0.3 1.0

2.5±0.2 1.2

SEL

OE

2.7

—

3.3±0.3 1.1

2.5±0.2 1.0

Output enable time

Output disable time

Setup time

t_ZH

t_ZL

ns

A or B

2.7

—

3.3±0.3 1.0

2.5±0.2 1.7

t_HZ

t_LZ

OE

2.7

—

3.3±0.3 1.3

2.5±0.2 1.4

t_su

2.7

1.1

—

3.3±0.3 1.1

2.5±0.2 1.6

—

Hold time

t_h

—

2.7

1.9

—

3.3±0.3 1.5

2.5±0.2 3.3

—

Pulse width

t_w

—

2.7

3.3

—

3.3±0.3 3.3

—

Input capacitance

Output capacitance

C_IN

3.3

—

pF

Control inputs

A or B ports

C_{IN / O}

—

7

HD74ALVCH16260

• Test Circuit

See under table

500 Ω

S1

OPEN

GND

*1

C_L= 50 pF

500 Ω

Load Circuit for Outputs

Vcc=2.7V,

Vcc=2.5±0.2V

Symbol

3.3±0.3V

t_PLH/ t_PHL

t_su/ t_h/ t_w

OPEN

t_ZH/ t_HZ

t_ZL/ t_LZ

GND

4.6 V

GND

6.0 V

Note: 1. C_Lincludes probe and jig capacitance.

8

HD74ALVCH16260

• Waveforms – 1

tr

tf

V

IH

90 %

V_ref

90 %

V_ref

Input

10 %

GND

t_PHL

t_PLH

V_OH

Output

V_ref

V_OL

• Waveforms – 2

tr

V

IH

90 %

V_ref

Timing Input

10 %

t_su

GND

t_h

V

IH

V_ref

Data Input

GND

t_w

V

IH

V_ref

Input

GND

9

HD74ALVCH16260

• Waveforms – 3

tf

tr

V

IH

90 %

V_ref

Output

Control

V_ref

10 %

t_ZL

10 %

GND

t_LZ

≈V_OH1

V_ref

Waveform - A

Waveform - B

V_OL+ 0.3 V

V_OH– 0.3 V

V_OL

V_OH

t_ZH

t_HZ

V_ref

≈V_OL1

Vcc=2.7V,

Vcc=2.5±0.2V

2.3 V

TEST

3.3±0.3V

V_IH

2.7 V

V_ref

1.2 V

1.5 V

3.0 V

GND

V_OH1

V_OL1

2.3 V

GND

Notes: 1. All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

2. Waveform – A is for an output with internal conditions such that the output is low

except when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high

except when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

10

HD74ALVCH16260

Package Dimensions

Unit : mm

+0.3

–0.1

14.00

56

29

28

1

0.50

+0.1

–0.05

M

0.08

0.20

8.10 ± 0.3

0.40 Max

10° Max

0.50 ± 0.1

0.10

Hitachi code

EIAJ code

JEDEC code

TTP-56D

—

11

HD74ALVCH16260

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

copyright, trademark, or other intellectual property rights for information contained in this document.

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/index.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

Group III (Electronic Components)

7/F., North Tower, World Finance Centre,

Harbour City, Canton Road, Tsim Sha Tsui,

Kowloon, Hong Kong

Tel: <852> (2) 735 9218

Fax: <852> (2) 730 0281

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Electronic components Group

Dornacher Stra§e 3

D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

179 East Tasman Drive,

San Jose,CA 95134

Tel: <1> (408) 433-1990

Fax: <1>(408) 433-0223

Fax: 535-1533

Hitachi Asia Ltd.

Taipei Branch Office

3F, Hung Kuo Building. No.167,

Tun-Hwa North Road, Taipei (105)

Tel: <886> (2) 2718-3666

Fax: <886> (2) 2718-8180

Telex: 40815 HITEC HX

Hitachi Europe Ltd.

Electronic Components Group.

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Fax: <44> (1628) 778322

12


型号：	HD74ALVCH16260T
厂家：	RENESAS TECHNOLOGY CORP
描述：	ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, TTP-56D 光电二极管输出元件逻辑集成电路
文件：	总12页 (文件大小：57K)
中文：	中文翻译
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HD74ALVCH16260T [RENESAS]

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