HD74HC668FP [RENESAS]
暂无描述;
| 型号： | HD74HC668FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 暂无描述 计数器 |
| 文件： | 总11页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74HC668, HD74HC669
Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
REJ03D0638-0200
(Previous ADE-205-520)
Rev.2.00
Mar 30, 2006
Description
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-speed counting
applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of
operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock)
counters.
A buffered clock input triggers the four master-slave flip-flops on the rising (oing) edge of the clock
waveform. This counter is fully programmable; that is, the outputs may eaither level. The load input
circuitry allows loading with the carry-enable output of cascaded counthronous, setting up a low
level at the load input disables the counter and causes the outputs to fter the next clock pulse.
The carry look-ahead circuitry provides for cascading countercations without additional
gating. Instrumental in accomplishing this function are twarry output. Both count enable
inputs (P and T) must be low to count. The direction of he level of the up/down input.
when the input is high, the counter counts up; when T is fed forward to enable the carry
output. The carry output thus enabled will produwith a duration approximately equal to the
high portion of the QA output when counting o the low portion of the QA output when
counting down. This low level overflow cble successive cascaded stages. Transitions at
the enable P or T inputs are allowed regock input. All inputs are diode-clamped to minimize
transission-line effects, thereby simcounter features a fully independent clock circuit.
Changes at control inputs (enabl) that will modify the operating mode have no effect until
clocking occurs. The functioabled, disabled, loading, or counting) will be dictated solely
by the conditions meeting es.
Features
•
•
•
•
•
•
High Speed Operation
High Output Current: Fanout of LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
Part Name
HD74HC669P
Package Type
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
—
PRSP0016DH-B
(FP-16DAV)
HD74HC669FPEL SOP-16 pin (JEITA)
FP
RP
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
HD74HC668RPEL
SOP-16 pin (JEDEC)
HD74HC669RPEL
PRSP0016DG-A
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
Rev.2.00 Mar 30, 2006 page 1 of 10
HD74HC668, HD74HC669
Pin Arrangement
HD74HC668
U/D
CK
A
1
2
3
4
5
6
7
8
16 VCC
Ripple
carry
output
15
14 QA
B
13 QB
Data
inputs
Outputs
C
12 QC
D
11 QD
10 Enable T
Enable P
GND
9
Loa
(Top view)
HD74HC669
U/D
CK
1
7
8
C
Ripple
carry
output
5
14 QA
13 QB
12 QC
11 QD
Da
i
Outputs
10
9
Enable T
Enabl
GND
Load
(Top view)
Rev.2.00 Mar 30, 2006 page 2 of 10
HD74HC668, HD74HC669
Logic Diagram
HD74HC668
L
T
Q
QA
U/D
IN
Q
CK
DA
Load
L
Enable P
Enable T
T
Q
QB
IN
Q
CK
DB
L
T
Q
QC
IN
Q
CK
DC
VCC
L
T
Q
QD
DD
RCO
CK
HD74HC669
T
Q
QA
U/D
IN
Q
DA
Load
Enab
E
T
Q
QB
IN
Q
T
Q
QC
IN
Q
DC
T
Q
QD
IN
Q
DD
RCO
VCC
CK
Rev.2.00 Mar 30, 2006 page 3 of 10
HD74HC668, HD74HC669
Timing Chart
HD74HC668
Load
A
B
Data
inputs
C
D
Clock
U/D
Enable P and T
QA
QB
QC
QD
Ripple
carry
output
7
8
2
1
0
9
8
7
Inhibit
Count down
L
Rev.2.00 Mar 30, 2006 page 4 of 10
HD74HC668, HD74HC669
HD74HC669
Load
A
B
Data
inputs
C
D
Clock
U/D
P and T
QA
QB
QC
QD
Ripple
carry
output
13
14
15
0
0
15
14
13
Count down
Load
Absolute Maximum
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
ymbol
VCC
Ratings
Unit
–0.5 to 7.0
V
V
VIN, VOUT
IIK, IOK
IO
–0.5 to VCC +0.5
±20
±25
mA
mA
mA
mW
°C
VCC, GND current
ICC or IGND
PT
±50
Power dissipation
500
Storage temperature
Tstg
–65 to +150
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00 Mar 30, 2006 page 5 of 10
HD74HC668, HD74HC669
Recommended Operating Conditions
Item
Supply voltage
Symbol
VCC
Ratings
2 to 6
Unit
V
Conditions
Input / Output voltage
Operating temperature
VIN, VOUT
Ta
0 to VCC
–40 to 85
0 to 1000
0 to 500
0 to 400
V
°C
VCC = 2.0 V
VCC = 4.5 V
Input rise / fall time*1
tr, tf
ns
VCC = 6.0 V
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C
Typ Max
Ta = –40 to+85°C
Item
Symbol VCC (V)
VIH
Unit
Test Conditions
Min
1.5
3.15
4.2
—
Min
1.5
3.15
4.2
—
Max
—
Input voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
—
—
—
—
V
—
—
—
—
VIL
—
0.5
1.35
1.8
—
0
—
—
—
—
—
—
Output voltage
VOH
1.9
4.4
5.9
4.18
5.68
—
2.0
4.5
6.0
—
1
IH or VIL IOH = –20 µA
—
—
IOH = –4 mA
IOH = –5.2 mA
—
VOL
.0
0.1
0.1
0.33
0.33
±1.0
40
V
Vin = VIH or VIL IOL = 20 µA
—
IOL = 4 mA
—
IOL = 5.2 mA
Input current
Iin
—
µA Vin = VCC or GND
Quiescent supply
current
ICC
—
µA Vin = VCC or GND, Iout = 0 µA
Rev.2.00 Mar 30, 2006 page 6 of 10
HD74HC668, HD74HC669
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Typ Max
Ta = –40 to +85°C
Item
Maximum clock
Frequency
Symbol VCC (V)
Unit
Test Conditions
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
16
14
100
20
17
150
30
26
15
Min
—
Max
4
fmax
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.
4.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
27
32
200
40
34
225
45
38
150
30
26
200
40
34
—
MHz
—
21
25
250
50
43
280
56
48
190
38
33
250
50
4
—
Propagation delay
time
tPLH
tPHL
—
ns Clock to Ripple carry out
—
—
tPLH
tPHL
—
ns Clock to Q
—
—
tPLH
tPHL
—
ns Enable T to Ripple carry out
—
—
tPLH
tPHL
—
ns U/D to Ripple carry out
—
—
Pulse width
Setup time
tw
tsu
tsu
tsu
tsu
th
100
20
1
33
190
38
33
5
—
—
—
ta to Clock
—
ns Enable P, T to Clock
—
—
ns Loadk to Clock
—
—
—
ns U/D to Clock
—
—
—
Hold time
—
—
ns
ns
pF
—
5
—
—
5
—
Output rise/fall
time
tTLH
tTHL
—
—
—
—
75
15
13
10
—
95
19
16
10
—
—
5
—
Input capacitance
Cin
—
Rev.2.00 Mar 30, 2006 page 7 of 10
HD74HC668, HD74HC669
Test Circuit
VCC
VCC
Output
Output
Output
Output
Output
QA
QB
QC
QD
U/D
Clock
A
Input
CL = 50 pF
Pulse Generator
Ω
B
Zout
= 50
CL = 50 pF
C
Input
D
CL = 50 pF
Enable P
Load
Pulse Generator
Zout
Ω
= 50
CL = 50 pF
Ripple
Carry
Enable T
CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 8 of 10
HD74HC668, HD74HC669
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
16
9
1
8
b 3
0.89
Z
Dimension in Millimeters
Min Nom Max
7.62
Reference
Symbol
e1
D
E
19.2 20.32
6.3 7.4
5.06
bp
e
A
A1
bp
b3
c
0.51
0.40 0.48 0.56
1.30
0.19 0.25 0.31
θ
0° 15°
2.29 2.54 2.79
e
Z
1.12
2.54
L
JEITA Package Code
RENESAS Code
PRSP0016DH-B
Previo
F
P-SOP16-5.5x10.06-1.27
*
F
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
16
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
8
bp
*3
e
Dimension in Millimeters
Reference
Symbol
Z
x
M
Min Nom Max
L1
D
E
10.06 10.5
5.50
A2
A1
A
bp
b1
c
0.00 0.10 0.20
2.20
0.34 0.40 0.46
y
L
0.15 0.20 0.25
c1
θ
Detail F
0° 8°
7.50 7.80 8.00
HE
e
x
1.27
0.12
0.15
y
Z
L
L1
0.80
0.50 0.70 0.90
1.15
Rev.2.00 Mar 30, 2006 page 9 of 10
HD74HC668, HD74HC669
JEITA Package Code
RENESAS Code
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
P-SOP16-3.95x9.9-1.27
PRSP0016DG-A
*1
D
F
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
16
9
b p
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
1
8
Min Nom Max
*3
e
Z
bp
x
M
D
E
9.90 10.30
3.95
L1
A2
A1
A
bp
b1
c
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
c1
θ
y
0° 8°
5.80 6.10 6.20
HE
e
x
1.27
0.25
0.15
y
Z
L
L1
0.635
0.40 0.60 1.27
1.08
Rev.2.00 Mar 30, 2006 page 10 of 10
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Colophon .6.0
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