HD74LV393AFP-E [RENESAS]
LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, FP-14DAV;
| 型号： | HD74LV393AFP-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, FP-14DAV 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
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Notes regarding these materials
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Technology Corporation product best suited to the customer's application; they do not convey any
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contained therein.
HD74LV393A
Dual 4-bit Binary Counters
ADE-205-276A (Z)
2nd. Edition
Jul. 2001
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single
divide-by-256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and
each has an independent clear input. When clear is set high all four bits of each counter are set to a low
level. This enables count trucation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current 6 mA (@VCC = 3.0 V to 3.6 V), 12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV393A
Function Table
Inputs
CLK
X
CLR
Output
H
L
L
L
L
L
H
No change
No change
No change
Count up
L
↑
↓
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Pin Arrangement
1
14 VCC
1
2
3
4
5
6
7
13
12
11
10
9
1CLR
1QA
1QB
1QC
1QD
GND
2
2CLR
2QA
2QB
2QC
2QD
8
(Top view)
Rev.1, Jul. 2001, page 2 of 2
HD74LV393A
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
V
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
V
VO
V
Output: H or L
VCC: OFF
Input clamp current
IIK
IOK
IO
mA
mA
mA
mA
VI < 0
Output clamp current
Continuous output current
50
VO < 0 or VO > VCC
VO = 0 to VCC
25
Continuous current through
VCC or GND
I
CC or IGND
50
Maximum power dissipation
PT
785
mW
°C
SOP
at Ta = 25°C (in still air)*3
500
TSSOP
Storage temperature
Tstg
–65 to 150
Notes: The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.1, Jul. 2001, page 3 of 3
HD74LV393A
Recommended Operating Conditions
Item
Symbol
Min
2.0
0
Max
5.5
5.5
VCC
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
VCC
VI
V
VO
IOH
0
V
H or L
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–6
–12
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
6
12
Input transition rise or fall rate
∆t /∆v
200
100
20
ns/V
0
0
Operating free-air temperature Ta
–40
85
°C
Note: Unused or floating inputs must be held high or low.
Logic Diagram
CK
CK
CK
CK
R
R
R
R
CLR
QA
QB
QC
QD
Rev.1, Jul. 2001, page 4 of 4
HD74LV393A
Timing Diagram
CLR
QA
QB
QC
QD
Rev.1, Jul. 2001, page 5 of 5
HD74LV393A
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
—
—
—
—
—
—
—
—
—
Max
—
Unit
Test Conditions
Input voltage
VIH
2.0
1.5
V
2.3 to 2.7 VCC × 0.7
3.0 to 3.6 VCC × 0.7
4.5 to 5.5 VCC × 0.7
—
—
—
VIL
2.0
—
0.5
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
—
VCC × 0.3
VCC × 0.3
VCC × 0.3
—
—
—
Output voltage
VOH
Min to
Max
VCC – 0.1
V
V
IOL = –50 µA
2.3
3.0
4.5
2.0
2.48
3.8
—
—
—
—
—
—
—
—
0.1
IOL = –2 mA
IOL = –6 mA
IOL = –12 mA
IOL = 50 µA
VOL
Min to
Max
2.3
—
—
—
—
—
—
—
—
—
—
0.4
0.44
0.55
1
IOL = 2 mA
3.0
IOL = 6 mA
4.5
IOL = 12 mA
Input current
IIN
0 to 5.5
5.5
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
Quiescent
ICC
20
supply current
Output leakage IOFF
current
0
—
—
—
5
µA
VI or VO = 0 V to 5.5 V
VI = VCC or GND
Input
CIN
3.3
1.7
—
pF
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
Rev.1, Jul. 2001, page 6 of 6
HD74LV393A
Switching Characteristics
VCC = 2.5 0.2 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
(Output)
Item
Symbol Min Typ
Max Min
Max
Unit
Test Conditions
Maximum
clock
fmax
50
90
—
40
—
MHz
CL = 15 pF
frequency
30
60
—
25
—
CL = 50 pF
CL = 15 pF
Propa-
gation
t
PLH/./tPHL
—
11.8 17.7 1.0
20.5
ns
CLK
QA
delay time
—
—
—
—
—
—
—
—
—
6.0
5.0
15.1 21.3 1.0
13.4 20.3 1.0
16.7 23.9 1.0
14.9 22.5 1.0
18.2 26.1 1.0
16.2 24.2 1.0
19.5 27.8 1.0
10.8 14.8 1.0
14.2 17.4 1.0
24.5
23.5
27.5
26.0
30.0
28.0
32.0
17.0
20.0
—
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
QB
QC
QD
Qn
tPHL
CLR
Setup time tsu
—
—
—
—
6.0
5.0
ns
ns
CLR L before CLK ↓
Pulse
width
tw
—
CLR H
5.0
—
—
5.0
—
CLK H or L
Rev.1, Jul. 2001, page 7 of 7
HD74LV393A
Switching Characteristics (cont)
VCC = 3.3 0.3 V
Ta = 25°C
Ta = –40 to 85°C
FROM
TO
Item
Symbol Min Typ
Max Min
Max
Unit
Test Conditions
(Input)
(Output)
Maximum
clock
fmax
75
120
—
65
—
MHz
CL = 15 pF
frequency
45
65
—
35
—
CL = 50 pF
CL = 15 pF
Propa-
gation
t
PLH/./tPHL
—
8.6
13.2 1.0
15.5
ns
CLK
QA
delay time
—
—
—
—
—
—
—
—
—
5.0
5.0
11.1 16.7 1.0
10.2 15.8 1.0
12.7 19.3 1.0
11.7 18.0 1.0
14.2 21.5 1.0
13.0 19.7 1.0
15.5 23.2 1.0
19.0
18.5
22.0
21.0
24.5
23.0
26.5
14.5
18.0
—
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
QB
QC
QD
Qn
tPHL
7.9
12.3 1.0
CLR
10.4 15.8 1.0
Setup time tsu
—
—
—
—
5.0
5.0
ns
ns
CLR L before CLK ↓
Pulse
width
tw
—
CLR H
5.0
—
—
5.0
—
CLK H or L
Rev.1, Jul. 2001, page 8 of 8
HD74LV393A
Switching Characteristics (cont)
VCC = 5.0 0.5 V
Ta = 25°C
Ta = –40 to 85°C
FROM
(Input)
TO
(Output)
Item
Symbol Min Typ
fmax 125 170
Max Min
Max
Unit
Test Conditions
Maximum
clock
—
105
—
MHz
CL = 15 pF
frequency
85
115
5.8
—
75
—
CL = 50 pF
CL = 15 pF
Propa-
gation
t
PLH/./tPHL
—
8.5
1.0
10.0
ns
CLK
QA
delay time
—
—
—
—
—
—
—
—
—
4.0
5.0
7.3
6.8
8.3
7.7
9.2
8.5
10.5 1.0
9.8 1.0
12.0
11.5
13.5
13.0
15.0
14.5
16.5
9.5
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
QB
QC
QD
Qn
11.8 1.0
11.2 1.0
13.2 1.0
12.5 1.0
10.0 14.5 1.0
tPHL
5.4
6.9
—
8.1
1.0
CLR
10.1 1.0
11.5
—
Setup time tsu
—
—
4.0
5.0
ns
ns
CLR L before CLK ↓
Pulse
width
tw
—
—
CLR H
5.0
—
—
5.0
—
CLK H or L
Operating Characteristics
CL = 50 pF
Ta = 25°C
Min
Item
Symbol
VCC (V)
Typ
Max
Unit
Test Conditions
Power
CPD
3.3
—
12.0
—
pF
f = 10 MHz
dissipation
capacitance
5.0
—
15.0
—
Rev.1, Jul. 2001, page 9 of 9
HD74LV393A
Noise Characteristics
CL = 50 pF
Ta = 25°C
Min
Item
Symbol
VCC = (V)
Typ
Max
Unit
Test Conditions
Quiet output,
maximum
dynamic VOL
VOL (P)
3.3
3.3
3.3
3.3
3.3
—
0.4
0.8
V
Quiet output,
minimum
dynamic VOL
VOL (V)
VOH (V)
VIH (D)
VIL (D)
—
–0.4
3.2
—
–0.8
—
Quiet output,
minimum
dynamic VOH
—
High-level
dynamic
input voltage
2.31
—
—
Low-level
dynamic
—
0.99
input voltage
Test Circuit
Measurement point
*
C L
Note: CL includes the probe and jig capacitance.
Rev.1, Jul. 2001, page 10 of 10
HD74LV393A
•
Waveforms
CLR
− 1
tr
tf
VCC
0 V
VCC
0 V
90 %
50 % VCC
10 %
10 %
tf
tw
tr
90 %
90 %
50 % VCC
50 % VCC
10 %
tsu
tw
tw
tPLH
tPHL
VOH
Qn
50 % VCC
50 % VCC
VOL
•
Waveforms
CLR
− 2
tr
tf
VCC
VCC
0 V
90 %
50 % VCC
90 %
50 % VCC
10 %
10 %
tPHL
0 V
VOH
Qn
50 % VCC
tPLH
VOL
tPHL
VOH
VOH
50 % VCC
50 % VCC
Qn
Qn
VOL
VOL
Notes:1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 3 ns, t f ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.1, Jul. 2001, page 11 of 11
HD74LV393A
Package Dimensions
As of July, 2001
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 0.20
*0.40 0.06
0.15
M
0.12
Hitachi Code
JEDEC
FP-14DAV
—
JEITA
Mass (reference value)
Conforms
0.23 g
*Pd plating
Rev.1, Jul. 2001, page 12 of 12
HD74LV393A
As of July, 2001
Unit: mm
8.65
9.05 Max
8
14
1
7
+ 0.10
6.10
– 0.30
0.635 Max
1.08
0˚ – 8˚
+ 0.67
1.27
0.60
– 0.20
*0.40 0.06
0.15
M
0.25
Hitachi Code
JEDEC
JEITA
FP-14DNV
Conforms
Conforms
0.13 g
*Pd plating
Mass (reference value)
As of July, 2001
Unit: mm
5.00
5.30 Max
14
8
1
7
0.65
1.0
+0.08
*0.22
–0.07
0.13 M
0.20 0.06
6.40 0.20
0.83 Max
0˚ – 8˚
0.50 0.10
0.10
Hitachi Code
JEDEC
TTP-14D
—
JEITA
Mass (reference value)
—
0.05 g
*Dimension including the plating thickness
Base material dimension
Rev.1, Jul. 2001, page 13 of 13
HD74LV393A
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safe
devices, so that the equipment incorporating the Hitachi product does not cause bodily injury, fire or
other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
Asia
: http://semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
: http://sicapac.hitachi-asia.com
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
Hitachi Europe GmbH
Hitachi Asia Ltd.
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower,
(America) Inc.
Electronic Components Group
Hitachi Tower
179 East Tasman Drive, Dornacher Stra§e 3
San Jose,CA 95134
Tel: <1> (408) 433-1990 Germany
Fax: <1>(408) 433-0223 Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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Tel : <65>-538-6533/538-8577
Fax : <65>-538-6933/538-3877
URL : http://www.hitachi.com.sg
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Harbour City, Canton Road
Tsim Sha Tsui, Kowloon,
Hong Kong
Tel : <852>-(2)-735-9218
Fax : <852>-(2)-730-0281
URL : http://www.hitachi.com.hk
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road,
Hung-Kuo Building,
Taipei (105), Taiwan
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
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Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 2.0
Rev.1, Jul. 2001, page 14 of 14
相关型号：
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LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, SOP-16
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