HD74LV393ATELL-E [RENESAS]
暂无描述;型号: | HD74LV393ATELL-E |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 暂无描述 计数器 |
文件: | 总11页 (文件大小:85K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HD74LV393A
Dual 4-bit Binary Counters
REJ03D0333–0300Z
(Previous ADE-205-276A (Z))
Rev.3.00
Jun. 28, 2004
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-
256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV393AFPEL
HD74LV393ARPEL
HD74LV393ATELL
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
FP–14DAV
FP–14DNV
TTP–14DV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.3.00 Jun. 28, 2004 page 1 of 10
HD74LV393A
Function Table
Inputs
Output
CLK
CLR
X
H
L
L
L
L
L
H
No change
No change
No change
Count up
L
↑
↓
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Pin Arrangement
1
2
3
4
5
6
7
14 VCC
1CLK
1CLR
1QA
13
12
11
10
9
2CLK
2CLR
2QA
2QB
2QC
2QD
1QB
1QC
1QD
GND
8
(Top view)
Rev.3.00 Jun. 28, 2004 page 2 of 10
HD74LV393A
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
V
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
V
VO
V
Output: H or L
VCC: OFF
Input clamp current
IIK
IOK
IO
mA
mA
mA
mA
VI < 0
Output clamp current
±50
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through
±25
ICC or
IGND
±50
VCC or GND
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
785
mW
SOP
500
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
VCC
VI
Min
2.0
0
Max
5.5
5.5
VCC
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
V
VO
0
V
H or L
IOH
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–6
–12
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
6
12
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
200
100
20
ns/V
°C
0
0
Ta
–40
85
Note: Unused or floating inputs must be held high or low.
Rev.3.00 Jun. 28, 2004 page 3 of 10
HD74LV393A
Logic Diagram
D
D
D
D
CK
CK
CK
CK
CLK
Q
Q
Q
Q
R
R
R
R
CLR
QA
QB
QC
QD
Timing Diagram
CLK
CLR
QA
QB
QC
QD
Rev.3.00 Jun. 28, 2004 page 4 of 10
HD74LV393A
DC Electrical Characteristics
Ta = –40 to 85°C
Unit Test Conditions
Item
Symbol
VCC (V)*
Min
Typ Max
Input voltage
VIH
2.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
V
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIL
—
—
—
—
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
V
V
V
CC × 0.3
CC × 0.3
CC × 0.3
Output voltage
VOH
Min to Max VCC – 0.1
—
V
V
IOH = –50 µA
IOH = –2 mA
2.3
2.0
2.48
3.8
—
—
3.0
—
IOH = –6 mA
4.5
—
IOH = –12 mA
IOL = 50 µA
VOL
Min to Max
2.3
0.1
0.4
0.44
0.55
±1
—
IOL = 2 mA
3.0
—
IOL = 6 mA
4.5
—
IOL = 12 mA
Input current
IIN
0 to 5.5
5.5
—
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
Quiescent supply
current
ICC
—
20
Output leakage
current
IOFF
0
—
—
5
µA
VI or VO = 0 V to 5.5 V
Input capacitance
CIN
3.3
—
1.7
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
VCC = 2.5 ± 0.2 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
—
Maximum clock
frequency
fmax
50
30
—
—
—
—
—
—
—
—
—
—
6.0
5.0
5.0
90
60
—
—
40
25
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH/tPHL
11.8 17.7 1.0
15.1 21.3 1.0
13.4 20.3 1.0
16.7 23.9 1.0
14.9 22.5 1.0
18.2 26.1 1.0
16.2 24.2 1.0
19.5 27.8 1.0
10.8 14.8 1.0
14.2 17.4 1.0
20.5
24.5
23.5
27.5
26.0
30.0
28.0
32.0
17.0
20.0
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
QA
QB
QC
QD
Qn
tPHL
CLR
Setup time
Pulse width
tsu
tw
—
—
—
—
—
—
6.0
5.0
5.0
ns
ns
CLR L before CLK ↓
CLR H
—
—
CLK H or L
Rev.3.00 Jun. 28, 2004 page 5 of 10
HD74LV393A
Switching Characteristics (cont)
VCC = 3.3 ± 0.3 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
—
Maximum clock
frequency
fmax
75
45
—
—
—
—
—
—
—
—
—
—
5.0
5.0
5.0
120
65
—
—
65
35
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH/tPHL
8.6
13.2 1.0
15.5
19.0
18.5
22.0
21.0
24.5
23.0
26.5
14.5
18.0
—
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
QA
QB
QC
QD
Qn
11.1 16.7 1.0
10.2 15.8 1.0
12.7 19.3 1.0
11.7 18.0 1.0
14.2 21.5 1.0
13.0 19.7 1.0
15.5 23.2 1.0
tPHL
7.9
12.3 1.0
CLR
10.4 15.8 1.0
Setup time
Pulse width
tsu
tw
—
—
—
—
—
—
5.0
5.0
5.0
ns
ns
CLR L before CLK ↓
CLR H
—
—
CLK H or L
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
TO
Item
Symbol
Unit
Conditions
(Output)
Min Typ Max Min
Max
—
Maximum clock
frequency
fmax
125 170
—
105
75
MHz CL = 15 pF
CL = 50 pF
85
—
—
—
—
—
—
—
—
—
—
4.0
5.0
5.0
115
5.8
7.3
6.8
8.3
7.7
9.2
8.5
—
—
Propagation
delay time
tPLH/tPHL
8.5
1.0
10.0
12.0
11.5
13.5
13.0
15.0
14.5
16.5
9.5
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CLK
QA
QB
QC
QD
Qn
10.5 1.0
9.8 1.0
11.8 1.0
11.2 1.0
13.2 1.0
12.5 1.0
10.0 14.5 1.0
tPHL
5.4
6.9
—
8.1
1.0
CLR
10.1 1.0
11.5
—
Setup time
Pulse width
tsu
tw
—
—
—
4.0
5.0
5.0
ns
ns
CLR L before CLK ↓
CLR H
—
—
—
—
CLK H or L
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Unit
pF
Test Conditions
Min
—
Typ
12.0
15.0
Max
—
Power dissipation capacitance CPD
3.3
5.0
f = 10 MHz
—
—
Rev.3.00 Jun. 28, 2004 page 6 of 10
HD74LV393A
Noise Characteristics
CL = 50 pF
Test Conditions
Ta = 25°C
Min
Item
Symbol
VCC = (V)
Unit
Typ
Max
Quiet output, maximum
dynamic VOL
VOL (P)
3.3
—
0.4
0.8
V
Quiet output, minimum
dynamic VOL
VOL (V)
VOH (V)
VIH (D)
VIL (D)
3.3
3.3
3.3
3.3
—
–0.4
3.2
—
–0.8
—
V
V
V
V
Quiet output, minimum
dynamic VOH
—
High-level dynamic input
voltage
2.31
—
—
Low-level dynamic input
voltage
—
0.99
Test Circuit
Measurement point
*
C L
Note: CL includes the probe and jig capacitance.
Rev.3.00 Jun. 28, 2004 page 7 of 10
HD74LV393A
•
Waveforms − 1
tr
tf
VCC
0 V
VCC
0 V
90 %
50 % VCC
CLR
10 %
10 %
tf
tw
tr
90 %
50 % VCC
90 %
50 % VCC
CLK
10 %
tsu
tw
tw
tPLH
tPHL
VOH
Qn
50 % VCC
50 % VCC
VOL
•
Waveforms
CLR
− 2
tr
tf
VCC
VCC
0 V
90 %
50 % VCC
90 %
50 % VCC
CLK
10 %
10 %
tPHL
0 V
VOH
Qn
50 % VCC
tPLH
VOL
tPHL
VOH
VOH
50 % VCC
50 % VCC
Qn
Qn
VOL
VOL
Notes:1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 3 ns, t f ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jun. 28, 2004 page 8 of 10
HD74LV393A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-14DAV
—
JEITA
Mass (reference value)
Conforms
0.23 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
8.65
9.05 Max
8
14
1
7
+ 0.10
6.10
– 0.30
0.635 Max
1.08
0˚ – 8˚
+ 0.67
1.27
0.60
– 0.20
*0.40 ± 0.06
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-14DNV
Conforms
Conforms
0.13 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.3.00 Jun. 28, 2004 page 9 of 10
HD74LV393A
As of January, 2003
Unit: mm
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
0.83 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-14DV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.3.00 Jun. 28, 2004 page 10 of 10
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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Colophon .1.0
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