HD74LV595ATELL [RENESAS]

8-bit Shift Registers with 3-state Outputs; 8位移位寄存器3态输出


型号：	HD74LV595ATELL
厂家：	RENESAS TECHNOLOGY CORP
描述：	8-bit Shift Registers with 3-state Outputs 8位移位寄存器3态输出移位寄存器
文件：	总14页 (文件大小：109K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74LV595A

8-bit Shift Registers with 3-state Outputs

REJ03D0335–0200Z

(Previous ADE-205-281 (Z))

Rev.2.00

Jun. 28, 2004

Description

This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The

storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage

Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both

clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and

high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power

consumption extends the battery life.

Features

•

V_CC= 2.0 V to 5.5 V operation

All inputs V_IH(Max.) = 5.5 V (@V_CC= 0 V to 5.5 V)

All outputs V_O(Max.) = 5.5 V (@V_CC= 0 V)

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

Typical V_OHundershoot > 2.3 V (@V_CC= 3.3 V, Ta = 25°C)

Output current ±6 mA (@V_CC= 3.0 V to 3.6 V), ±12 mA (@V_CC= 4.5 V to 5.5 V)

Ordering Information

Part Name

Package Type

Package Code

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LV595AFPEL

HD74LV595ARPEL

HD74LV595ATELL

SOP–16 pin (JEITA)

SOP–16 pin (JEDEC)

TSSOP–16 pin

FP–16DAV

FP–16DNV

TTP–16DAV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

ELL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

Inputs

Function

SER

SRCLK

SRCLR

RCLK

↑

Force outputs into high-impedance state

Enable parallel output

Reset shift register

Shift data into shift register

↑

Shift data into shift register

↓

Shift register remains unchanged

Transfer shift register contents to latch register

Latch register remains unchanged

↓

Note: H: High level

L: Low level

X: Immaterial

↑: Low to high transition

↓: High to low transition

Rev.2.00 Jun. 28, 2004 page 1 of 13

HD74LV595A

Pin Arrangement

16 V_CC

Q_B

Q_C

Q_A

Q_D

SER

Q_E

RCLK

SRCLK

SRCLR

Q_H'

Q_F

Q_G

Q_H

GND

(Top view)

Absolute Maximum Ratings

Item

Symbol

Ratings

Unit

Conditions

Supply voltage range

Input voltage range*¹

Output voltage range*^{1, 2}

V_CC

V_I

–0.5 to 7.0

–0.5 to V_CC+ 0.5

–0.5 to 7.0

–20

V_O

Output: H or L

Output: Z or V_CC: OFF

V_I< 0

Input clamp current

I_IK

I_OK

I_O

Output clamp current

±50

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

Continuous output current

Continuous current through

±25

I_CCor I_GND±70

V_CCor GND

Maximum power dissipation at P_T

Ta = 25°C (in still air)*³

785

SOP

500

TSSOP

Storage temperature

Tstg

–65 to 150

°C

Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are

observed.

2. This value is limited to 5.5 V maximum.

3. The maximum package power dissipation was calculated using a junction temperature of 150°C.

Rev.2.00 Jun. 28, 2004 page 2 of 13

HD74LV595A

Recommended Operating Conditions

Item

Symbol

V_CC

Min

2.0

Max

5.5

V_CC

5.5

–50

–2

Unit

Conditions

Supply voltage range

Input voltage range

Output voltage range

V_I

V_O

H or L

High impedance state

V_CC= 2.0 V

Output current

I_OH

—

µA

V_CC= 2.3 to 2.7 V

V_CC= 3.0 to 3.6 V

V_CC= 4.5 to 5.5 V

V_CC= 2.0 V

–6

–12

I_OL

µA

V_CC= 2.3 to 2.7 V

V_CC= 3.0 to 3.6 V

V_CC= 4.5 to 5.5 V

V_CC= 2.3 to 2.7 V

V_CC= 3.0 to 3.6 V

Input transition rise or fall rate

Operating free-air temperature

∆t /∆v

200

100

ns/V

°C

V_CC= 4.5 to 5.5 V

–40

Note: Unused or floating inputs must be held high or low.

Rev.2.00 Jun. 28, 2004 page 3 of 13

HD74LV595A

Logic Diagram

(13)

(12)

RCLK

(10)

SRCLR

(11)

(14)

SRCLK

SER

(15)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(9)

Rev.2.00 Jun. 28, 2004 page 4 of 13

HD74LV595A

Timing Diagram

SRCLK

SER

RCLK

SRCLR

Q_A

Q_B

Q_C

Q_D

Q_E

Q_F

Q_G

Q_H

Q_H'

SHIFT

HIGH IMPEDANCE

CLEAR

DC Electrical Characteristics

Ta = –40 to 85°C

Item

Symbol

V_CC(V)

2.0

Min

1.5

Typ Max

Unit Test Conditions

Input voltage

V_IH

—

0.5

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.0

_CC× 0.7

V_IL

—

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

_CC× 0.3

Output voltage

V_OH

Min to Max V_CC– 0.1

—

I_OH= –50 µA

I_OH= –2 mA

I_OH= –6 mA

I_OH= –12 mA

I_OL= 50 µA

2.3

2.0

2.48

3.8

—

3.0

—

4.5

—

V_OL

Min to Max

2.3

0.1

0.4

0.44

0.55

±1

—

I_OL= 2 mA

3.0

—

I_OL= 6 mA

4.5

—

I_OL= 12 mA

Input current

I_IN

0 to 5.5

5.5

—

µA

V_IN= 5.5 V or GND

V_O= V_CCor GND

Off-state output

current

I_OZ

—

±5

Quiescent supply

current

I_CC

5.5

—

µA

V_IN= V_CCor GND, I_O= 0

V_Ior V_O= 0 to 5.5 V

V_I= V_CCor GND

Output leakage

current

I_OFF

C_IN

—

Input capacitance

3.3

3.5

—

Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.

Rev.2.00 Jun. 28, 2004 page 5 of 13

HD74LV595A

Switching Characteristics

V_CC= 2.5 ± 0.2 V

Ta = 25°C

Ta = –40 to 85°C

Test

FROM

Item

Symbol

Unit

Conditions (Input)

(Output)

Min Typ Max Min

Max

—

Maximum

clock frequency

f_max

—

MHz C_L= 15 pF

C_L= 50 pF

—

Propagation

delay time

t_PLH/t_PHL

11.6 16.4 1.0

14.8 19.4 1.0

10.5 15.3 1.0

13.7 18.3 1.0

11.2 16.2 1.0

14.4 19.2 1.0

10.3 14.8 1.0

12.2 17.7 1.0

19.5

22.5

18.0

21.0

18.2

21.2

17.5

20.5

13.5

19.2

—

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

SRCLK

RCLK

SRCLK

Q_H'

—

Q_A– Q_H

Q_H'

—

t_PHL

—

Enable time

Disable time

Setup time

t_ZH

t_ZL

t_HZ

t_LZ

t_SU

—

Q_A– Q_H

—

7.6

11.5 1.0

—

14.4 18.2 1.0

5.5

10.0

5.0

—

5.5

SER before SRCLK ↑

10.5

11.0

5.0

—

SRCLK ↑ before RCLK ↑

SRCLR low before RCLK ↑

SRCLR high (inactive)

before SRCLK ↑

—

Hold time

t_h

2.0

0.5

7.0

6.0

—

2.0

0.5

7.5

6.5

—

SER after SRCLK ↑

SRCLK ↑ after RCLK ↑

SRCLR low after RCLK ↑

RCLK high or low

Pulse width

t_w

SRCLK high or low

SRCLR low

Rev.2.00 Jun. 28, 2004 page 6 of 13

HD74LV595A

Switching Characteristics (cont)

V_CC= 3.3 ± 0.3 V

Ta = 25°C

Ta = –40 to 85°C

Test

FROM

Item

Symbol

Unit

Conditions (Input)

(Output)

Min Typ Max Min

Max

—

Maximum

clock frequency

f_max

—

150

130

8.8

—

MHz C_L= 15 pF

C_L= 50 pF

—

Propagation

delay time

t_PLH/t_PHL

13.0 1.0

15.0

18.5

13.5

17.0

13.7

17.2

13.5

17.0

13.5

16.2

—

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

SRCLK

RCLK

SRCLK

Q_H'

—

11.3 16.5 1.0

7.7 11.9 1.0

10.2 15.4 1.0

8.4 12.8 1.0

10.9 16.3 1.0

—

Q_A– Q_H

Q_H'

—

t_PHL

—

Enable time

Disable time

Setup time

t_ZH

t_ZL

t_HZ

t_LZ

t_SU

—

7.5

9.0

5.9

11.5 1.0

15.0 1.0

11.7 1.0

Q_A– Q_H

—

12.1 15.7 1.0

3.5

8.0

3.0

—

3.5

8.5

9.0

3.0

SER before SRCLK ↑

—

SRCLK ↑ before RCLK ↑

SRCLR low before RCLK ↑

SRCLR high (inactive)

before SRCLK ↑

—

Hold time

t_h

1.5

0.0

5.0

—

1.5

0.0

5.0

—

SER after SRCLK ↑

SRCLK ↑ after RCLK ↑

SRCLR low after RCLK ↑

RCLK high or low

Pulse width

t_w

SRCLK high or low

SRCLR low

Rev.2.00 Jun. 28, 2004 page 7 of 13

HD74LV595A

Switching Characteristics (cont)

V_CC= 5.0 ± 0.5 V

Ta = 25°C

Ta = –40 to 85°C

Test

FROM

Item

Symbol

Unit

Conditions (Input)

(Output)

Min Typ Max Min

Max

—

Maximum

lock frequency

f_max

135 185

—

115

MHz C_L= 15 pF

C_L= 50 pF

—

155

6.2

7.7

5.4

6.9

5.9

7.4

4.8

8.3

4.8

7.6

—

Propagation

delay time

t_PLH/t_PHL

8.2

1.0

9.4

11.4

8.5

10.5

9.1

11.1

10.0

12.0

10.0

11.0

—

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

C_L= 15 pF

C_L= 50 pF

SRCLK

RCLK

SRCLK

Q_H'

—

10.2 1.0

—

7.4

9.4

8.0

1.0

Q_A– Q_H

Q_H'

—

t_PHL

—

10.0 1.0

8.6 1.0

10.6 1.0

8.6 1.0

11.0 1.0

Enable time

Disable time

Setup time

t_ZH

t_ZL

t_HZ

t_LZ

t_SU

—

Q_A– Q_H

—

3.0

5.0

2.5

—

3.0

5.0

2.5

SER before SRCLK ↑

—

SRCLK ↑ before RCLK ↑

SRCLR low before RCLK ↑

SRCLR high (inactive)

before SRCLK ↑

—

Hold time

t_h

2.0

0.0

5.0

—

2.0

0.0

5.0

—

SER after SRCLK ↑

SRCLK ↑ after RCLK ↑

SRCLR low after RCLK ↑

RCLK high or low

Pulse width

t_w

SRCLK high or low

SRCLR low

Output-skew Characteristics

C_L= 50 pF

Ta = 25°C

Ta = –40 to 85°C

Item

Symbol

V_CC= (V)

Unit

Min

—

Max

Min

—

Max

2.0

1.5

1.0

Output skew

t_{sk (O)}

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

2.0

1.5

1.0

—

Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted

but not production tested.

Rev.2.00 Jun. 28, 2004 page 8 of 13

HD74LV595A

Operating Characteristics

C_L= 50 pF

Ta = 25°C

Item

Symbol

V_CC= (V)

Unit

Test Conditions

f = 10 MHz

Min

—

Typ

32.7

33.1

Max

—

Power dissipation capacitance C_PD

3.3

5.0

—

Noise Characteristics

C_L= 50 pF

Test Conditions

Ta = 25°C

Min

Item

Symbol

V_CC= (V)

Unit

Typ

Max

Quiet output, maximum

dynamic V_OL

V_{OL (P)}

V_{OL (V)}

V_{OH (V)}

V_{IH (D)}

V_{IL (D)}

3.3

—

0.65

0.8

Quiet output, minimum

dynamic V_OL

3.3

—

–0.59 –0.8

Quiet output, minimum

dynamic V_OH

—

2.84

—

High-level dynamic input

voltage

2.31

—

Low-level dynamic input

voltage

—

0.99

Test Circuit

Output

Ω

1 K

OPEN

GND

V_CC

C_L

TEST

t_PLH/ t_PHL

t_ZH/ t_HZ

t_ZL/ t_LZ

OPEN

GND

V_CC

Note: C_Lincludes the probe and jig capacitance.

Rev.2.00 Jun. 28, 2004 page 9 of 13

HD74LV595A

Waveform

− 1

t_r

t_f

V_CC

90%

SRCLK

50% V_CC

10%

GND

t_w

1/f_max

t_PLH

t_PHL

90%

50% V_CC

Q_H'

10%

t_TLH

t_THL

Waveform

− 2

t_w

50% V_CC

SRCLR

V_CC

GND

t_PHL

Q_H'

50% V_CC

t_su

V_CC

50% V_CC

SRCLK

GND

Waveform

− 3

V_CC

RCLK

50% V_CC

GND

t_PLH/t_PHL

Q_A-Q_H

50% V_CC

Rev.2.00 Jun. 28, 2004 page 10 of 13

HD74LV595A

Waveform

− 4

t_f

t_r

V_CC

0 V

90 %

50 % V_CC

10 %

50 % V_CC

10 %

t_ZL

t_LZ

V_CC

V_OL

V_OH

0 V

50 % V_CC

Waveform

−

_OL+ 0.3 V

t_ZH

t_HZ

V_OH− 0.3 V

50 % V_CC

Waveform

− 5

Valid

50% V_CC

V_CC

SER

GND

V_CC

t_su

t_h

SRCLK

50% V_CC

GND

Waveform

− 6

V_CC

50% V_CC

SRCLK

RCLK

GND

V_CC

t_su

50%

V_CC

GND

t_w

Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns

2. Waveform A is for an output with internal conditions such that the output is low except when disabled

by the output control.

3. Waveform B is for an output with internal conditions such that the output is high except when disabled

−

by the output control.

4. The output are measured one at a time with one transition per measurement.

Rev.2.00 Jun. 28, 2004 page 11 of 13

HD74LV595A

Package Dimensions

As of January, 2003

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0˚ – 8˚

1.27

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

Package Code

JEDEC

FP-16DAV

—

JEITA

Mass (reference value)

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

1.27

+ 0.10

6.10

– 0.30

1.08

0.635 Max

0˚ – 8˚

+ 0.67

0.60

– 0.20

*0.40 ± 0.06

0.15

0.25

Package Code

JEDEC

JEITA

FP-16DNV

Conforms

0.15 g

*Ni/Pd/Au plating

Mass (reference value)

Rev.2.00 Jun. 28, 2004 page 12 of 13

HD74LV595A

As of January, 2003

Unit: mm

5.00

5.30 Max

0.65

0.13 M

0.65 Max

1.0

*0.20 ± 0.05

6.40 ± 0.20

0˚ – 8˚

0.50 ± 0.10

0.10

Package Code

JEDEC

TTP-16DAV

—

JEITA

—

*Ni/Pd/Au plating

Mass (reference value)

0.05 g

Rev.2.00 Jun. 28, 2004 page 13 of 13

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

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HD74LV595ATELL [RENESAS]

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