HD74LV74A [RENESAS]
Dual D-type Flip Flops with Preset and Clear; 双D-型触发器与预置和清除
| 型号： | HD74LV74A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual D-type Flip Flops with Preset and Clear |
| 文件： | 总10页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV74A
Dual D–type Flip Flops with Preset and Clear
REJ03D0312–0300Z
(Previous ADE-205-244A (Z))
Rev.3.00
Jun. 02, 2004
Description
The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The input
data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed operation is
suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
battery life.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV74AFPEL
HD74LV74ARPEL
HD74LV74ATELL
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
FP–14DAV
FP–14DNV
TTP–14DV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Outputs
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
Q
L
H
H
L
X
L
H*1
H
H*1
L
L
X
H
H
↑
H
L
H
H
↑
L
H
H
H
↓
X
Q0
Q0
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Q0: The level of Q immediately before the input conditions shown in the above table is determined.
1.: Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset
and Clear go HIGH simultaneously.
Rev.3.00 Jun. 02, 2004 page 1 of 9
HD74LV74A
Pin Arrangement
1
2
3
4
5
6
7
14 VCC
1CLR
1D
13 2CLR
12
11
10
9
2D
1CLK
1PRE
1Q
2CLK
2PRE
2Q
1Q
2Q
GND
8
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage range
Input voltage range*1
Output voltage range*1, 2
VCC
VI
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
V
V
V
VO
Output: H or L
VCC: OFF
Input clamp current
IIK
IOK
IO
mA
mA
mA
mA
VI < 0
Output clamp current
Continuous output current
±50
VO < 0 or VO > VCC
VO = 0 to VCC
±25
Continuous current through
VCC or GND
ICC or IGND
±50
Maximum power dissipation at PT
Ta = 25°C (in still air)*3
785
mW
SOP
500
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.3.00 Jun. 02, 2004 page 2 of 9
HD74LV74A
Recommended Operating Conditions
Item
Symbol
VCC
VI
Min
2.0
0
Max
5.5
5.5
VCC
–50
–2
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
V
VO
0
V
IOH
—
—
—
—
—
—
—
—
0
µA
mA
VCC = 2.0 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.0 V
–6
–12
50
IOL
µA
2
mA
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 2.3 to 2.7 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
6
12
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
200
100
20
ns/V
°C
0
0
Ta
–40
85
Note: Unused or floating inputs must be held high or low.
Logic Diagram
PRE
C
CLK
C
C
Q
TG
C
C
C
C
TG
TG
TG
D
Q
C
C
C
CLR
Rev.3.00 Jun. 02, 2004 page 3 of 9
HD74LV74A
DC Electrical Characteristics
Ta = –40 to 85°C
Unit Test Conditions
V
Item
Symbol
V
CC (V)*
Min
Typ Max
Input voltage
VIH
2.0
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.3
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
V
V
V
CC × 0.8
CC × 0.8
CC × 0.8
VIL
—
—
—
—
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
V
V
V
CC × 0.2
CC × 0.2
CC × 0.2
Output voltage
VOH
Min to Max VCC – 0.1
—
V
IOL = –50 µA
IOL = –2 mA
2.3
2.0
2.48
3.8
—
—
3.0
—
IOL = –6 mA
4.5
—
IOL = –12 mA
IOL = 50 µA
VOL
Min to Max
2.3
0.1
0.4
0.44
0.55
±1
—
IOL = 2 mA
3.0
—
IOL = 6 mA
4.5
—
IOL = 12 mA
Input current
IIN
0 to 5.5
5.5
—
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND, IO = 0
Quiescent supply
current
ICC
—
20
Output leakage
current
IOFF
0
—
—
5
µA
VI or VO = 0 V to 5.5 V
Input capacitance
CIN
3.3
—
2.0
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.3.00 Jun. 02, 2004 page 4 of 9
HD74LV74A
Switching Characteristics
VCC = 2.5 ± 0.2 V
TO
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
(Output)
Min Typ Max Min
Max
—
Maximum clock
frequency
tmax
50
30
—
100
70
—
—
40
25
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH
tPHL
9.8
14.8 1.0
17.0
19.0
20.0
23.0
—
ns
CL = 15 pF
PRE/CLR Q or Q
CLK
—
11.1 16.4 1.0
13.0 17.4 1.0
14.2 20.0 1.0
—
CL = 50 pF
PRE/CLR Q or Q
CLK
—
Setup time
tsu
8.0
7.0
0.5
8.0
8.0
—
—
—
—
—
—
—
—
—
—
9.0
7.0
0.5
9.0
9.0
ns
Data
—
PRE or CLR inactive
Hold time
th
—
ns
ns
Pulse width
tw
—
PRE or CLR “L”
CLK “H” or “L”
—
VCC = 3.3 ± 0.3 V
TO
(Output)
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
Min Typ Max Min
Max
—
Maximum clock
frequency
tmax
80
50
—
140
90
—
—
70
45
MHz CL = 15 pF
CL = 50 pF
—
Propagation
delay time
tPLH
tPHL
6.9
7.9
9.2
12.3 1.0
11.9 1.0
15.8 1.0
14.5
14.0
18.0
17.5
—
ns
CL = 15 pF
PRE/CLR Q or Q
CLK
—
—
CL = 50 pF
PRE/CLR Q or Q
CLK
—
10.2 15.4 1.0
Setup time
tsu
6.0
5.0
0.5
6.0
6.0
—
—
—
—
—
—
—
—
—
—
7.0
5.0
0.5
7.0
7.0
ns
Data
—
PRE or CLR inactive
Hold time
th
—
ns
ns
Pulse width
tw
—
PRE or CLR “L”
CLK “H” or “L”
—
VCC = 5.0 ± 0.5 V
TO
(Output)
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
(Input)
Item
Symbol
Unit Conditions
Min Typ Max Min
Max
—
Maximum clock
frequency
tmax
130 180
—
110
75
MHz CL = 15 pF
CL = 50 pF
90
—
140
5.0
5.6
6.6
7.2
—
—
—
Propagation
delay time
tPLH
tPHL
7.7
7.3
9.7
9.3
—
1.0
1.0
1.0
1.0
5.0
3.0
0.5
5.0
5.0
9.0
8.5
11.0
10.5
—
ns
CL = 15 pF
PRE/CLR Q or Q
CLK
—
—
CL = 50 pF
PRE/CLR Q or Q
CLK
—
Setup time
tsu
5.0
3.0
0.5
5.0
5.0
ns
Data
—
—
—
PRE or CLR inactive
Hold time
th
—
—
—
ns
ns
Pulse width
tw
—
—
—
PRE or CLR “L”
CLK “H” or “L”
—
—
—
Rev.3.00 Jun. 02, 2004 page 5 of 9
HD74LV74A
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Unit
Test Conditions
f = 10 MHz
Min
—
Typ
21.0
23.0
Max
—
Power dissipation capacitance CPD
3.3
5.0
pF
—
—
Noise Characteristics
CL = 50 pF
Test Conditions
Ta = 25°C
Item
Symbol
VCC (V)
Unit
Min
Typ
Max
Quiet output, maximum
dynamic VOL
VOL (P)
VOL (V)
VOH (V)
VIH (D)
VIL (D)
3.3
—
0.1
0.8
V
Quiet output, minimum
dynamic VOL
3.3
3.3
3.3
3.3
—
0
–0.8
—
V
V
V
V
Quiet output, minimum
dynamic VOH
—
3.2
—
—
High-level dynamic input
voltage
2.31
—
—
Low-level dynamic inout
voltage
0.99
Test Circuit
Measurement point
*
C L
Note: CL includes the probe and jig capacitance.
Rev.3.00 Jun. 02, 2004 page 6 of 9
HD74LV74A
• Waveform − 1
tr
tf
VCC
0 V
VCC
0 V
90%
50% VCC
90%
50% VCC
Timming input
Data input
10%
tsu
10%
th
50% VCC
50% VCC
tw
VCC
0 V
Input
50% VCC
50% VCC
• Waveform − 2
tr
tf
VCC
0 V
90%
50% VCC
90%
50% VCC
Input
10%
10%
tPHL
tPLH
VOH
Same-phase output
50% VCC
50% VCC
50% VCC
tPLH
VOL
tPHL
VOH
50% VCC
Opposite-phase output
VOL
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jun. 02, 2004 page 7 of 9
HD74LV74A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
14
1
7
+ 0.20
7.80
– 0.30
1.42 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
Package Code
JEDEC
FP-14DAV
—
JEITA
Mass (reference value)
Conforms
0.23 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
8.65
9.05 Max
8
14
1
7
+ 0.10
6.10
– 0.30
0.635 Max
1.08
0˚ – 8˚
+ 0.67
1.27
0.60
– 0.20
*0.40 ± 0.06
0.15
M
0.25
Package Code
JEDEC
JEITA
FP-14DNV
Conforms
Conforms
0.13 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.3.00 Jun. 02, 2004 page 8 of 9
HD74LV74A
As of January, 2003
Unit: mm
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
0.83 Max
0˚ – 8˚
0.50 ± 0.10
0.10
Package Code
JEDEC
TTP-14DV
—
JEITA
—
*Ni/Pd/Au plating
Mass (reference value)
0.05 g
Rev.3.00 Jun. 02, 2004 page 9 of 9
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