HM6287HLP-25 [RENESAS]
64KX1 CACHE SRAM, 25ns, PDIP22, 0.300 INCH, PLASTIC, DIP-22;
| 型号： | HM6287HLP-25 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 64KX1 CACHE SRAM, 25ns, PDIP22, 0.300 INCH, PLASTIC, DIP-22 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM6287, HM6287H Series
65536-word × 1-bit High Speed CMOS Static RAM
Description
The Hitachi HM6287/HM6287H is a high speed 64 k static RAM organized as 64-kword × 1-bit. It realizes
high speed access time (25/35/45/55/70 ns) and low power consumption, employing CMOS process
technology and high speed circuit design technology. It is most advantageous for high speed and high density
memory, such as cache memory for mainframes or 32-bit MPUs. The HM6287/HM6287H is packaged in a
300-mil plastic DIP and SOJ, and is available for high density mounting. The low power version retains data
with battery backup.
Features
•
•
•
Single 5 V supply and high density 22-pin DIP and 24-pin SOJ
High speed: Fast access time 25/35/45/55/70 ns (max)
Low power
Operation: 300 mW (typ)
Standby: 100 µW (typ)/10 µW (typ) (L-version)
Completely static memory
•
•
•
•
•
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible: All inputs and outputs
Battery backup capability (L-version)
HM6287, HM6287H Series
Ordering Information
Type No.
Access Time
Package
HM6287P-45
HM6287P-55
HM6287P-70
45 ns
55 ns
70 ns
300-mil, 22-pin plastic DIP (DP-22N)
HM6287LP-45
HM6287LP-55
HM6287LP-70
45 ns
55 ns
70 ns
HM6287HP-25
HM6287HP-35
25 ns
35 ns
300-mil, 22-pin plastic DIP (DP-22NB)
300-mil, 24-pin SOJ (CP-24D)
HM6287HLP-25
HM6287HLP-35
25 ns
35 ns
HM6287HJP-25
HM6287HJP-35
25 ns
35 ns
HM6287HLJP-25
HM6287HLJP-35
25 ns
35 ns
Pin Arrangement
HM6287P/HP Series
HM6287HJP
A0
A1
1
VCC
24
23
A0
A1
1
VCC
22
21
20
19
18
17
16
15
14
13
12
2
3
A15
A14
A2
2
3
A15
A14
22
21
20
19
18
17
16
15
14
A2
A3
4
A13
A12
NC
A11
A10
A9
A3
4
A13
A12
A11
A10
A9
A4
5
A4
5
A5
6
A5
6
NC
A6
7
7
8
A6
8
A7
9
A7
9
A8
Dout
WE
10
11
12
A8
Dout
WE
Din
10
11
Din
CS
VSS
13
CS
VSS
(Top view)
(Top view)
2
HM6287, HM6287H Series
Pin Description
Pin Name
A0–A15
Din
Function
Address
Input
Dout
CS
Output
Chip select
Write enable
Power supply
Ground
WE
VCC
VSS
Block Diagram
A0
VCC
VSS
A1
A2
A3
A4
A5
A6
Memory array
128 × 512
Row
decoder
Dout
Column I/O
Din
Column decoder
CS
WE
A7
A15
Truth Table
CS
H
WE
Mode
Standby
Read
VCC current
ISB, ISB1
ICC
Dout pin
Ref. Cycle
—
×
H
L
High-Z
Dout
L
Read cycle 1, 2
Write cycle 1, 2
L
Write
ICC
High-Z
Note: ×: Don't care.
3
HM6287, HM6287H Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
–0.5* to +7.0
Unit
V
Voltage any pin relative to VSS
Power dissipation
PT
1.0
W
Operating temperature
Storage temperature
Storage temperature under bias
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
°C
°C
°C
Note: VT min: –3.5 V for pulse width ≤ 20 ns (HM6287 Series)
VT min: –2.0 V for pulse width ≤ 10 ns (HM6287H Series)
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
V
Supply voltage
VSS
V
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
2.2
–0.5*1
—
6.0
0.8
V
VIL
—
V
Note: 1. VIL min: –3.0 V for pulse width ≤ 20 ns (HM6287 Series)
VIL min: –2.0 V for pulse width ≤ 10 ns (HM6287H Series)
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM6287
HM6287H
Typ*1 Max Unit Test Conditions
Parameter
Symbol Min
Typ*1 Max Min
Input leakage current
|ILI|
—
—
2.0
—
—
2.0
µA VCC = Max
Vin = VSS to VCC
Output leakage current |ILO|
—
—
—
2.0
—
—
—
2.0
µA CS = VIH, VI/O = VSS to VCC
Operating VCC current
ICC
60
100
60
120
mA CS = VIL, Iout = 0 mA,
min cycle
Standby VCC current
ISB
—
10
30
—
15
30
mA CS = VIH, min. cycle
mA CS ≥ VCC – 0.2 V
Standby VCC current (1) ISB1
—
—
0.02 2.0
—
—
0.02 2.0
0.02*2 0.1*2
0.02*2 0.1*2 mA 0 V ≤ Vin ≤ 0.2 V
or VCC – 0.2 V≤ Vin
Output low voltage
Output high voltage
VOL
VOH
—
—
—
0.4
—
—
—
—
0.4
—
V
V
IOL = 8 mA
2.4
2.4
IOH = –4.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. These characteristics are guaranteed only for L-version.
4
HM6287, HM6287H Series
Capacitance (Ta = 25°C, f = 1.0 MHz)*1
HM6287
HM6287H
Parameter
Symbol
Cin
Min
—
Max
5
Min
—
Max
6
Unit Test Conditions
Input capacitance
Output capacitance
pF
pF
Vin = 0 V
Cout
—
7.5
—
8
Vout = 0 V
Note: 1. These parameters are sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: VSS to 3.0 V
Input and output timing reference levels: 1.5 V
Input rise and fall time: 5 ns
Output load: See figure
+ 5 V
+ 5 V
480 Ω
480 Ω
Dout
Dout
30 pF *1
5 pF *1
255 Ω
255 Ω
Output load (A)
Output load (B)
(for tHZ, tLZ, WZ and tOW )
t
Note: 1. Including scope and jig
5
HM6287, HM6287H Series
Read Cycle
HM6287H- HM6287H- HM6287- HM6287- HM6287-
25 35 45 55 70
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Read cycle time
tRC
tAA
25
—
—
3
—
25
25
—
35
—
—
5
—
35
35
—
45
—
—
5
—
45
45
—
55
—
—
5
—
55
55
—
70
—
—
5
—
70
70
—
ns
ns
ns
ns
2
Address access time
Chip select access time
tACS
Output hold from address tOH
change
Chip selection to output in tLZ
low-Z
5
—
12
—
25
5
—
20
—
30
5
—
30
—
40
5
—
30
—
40
5
—
30
—
40
ns
ns
ns
ns
1, 3, 4
Chip deselection to output tHZ
in high-Z
0
0
0
0
0
1, 3, 4
Chip selection to power- tPU
up time
0
0
0
0
0
4
4
Chip deselection to power tPD
down time
—
—
—
—
—
Notes: 1. Transistion is measured +200 mV from steady state voltage with load (B).
2. All read cycle timing is referenced from last valid address to the first transitioning address.
3. At any given temperature and voltage condition, tHZ max, is less the tLZ min both for a given device
and from device to device.
4. These parameters are sampled and not 100% tested.
Read Timing Waveform (1)
tRC
Address
Dout
tAA
tOH
tOH
Previous data valid
Valid Data
Notes: 1. WE is high for read cycle.
2. Device is continously selected, CS = VIL.
3. All read cycle timing is referred from last valid address to the first transitioning address.
6
HM6287, HM6287H Series
Read Timing Waveform (2)
tRC
CS
tHZ
tACS
tLZ
Valid Data
Dout
VCC
supply
current
ISB
High impedance
tPU
High
impedance
tPD
ICC
50%
50%
Notes: 1. WE is high for read cycle.
2. Address valid prior to or coincident with CS transistion low.
Write Cycle
HM6287H- HM6287H- HM6287- HM6287- HM6287-
25 35 45 55 70
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Write cycle time
tWC
tCW
25
20
—
—
35
30
—
—
45
40
—
—
55
50
—
—
70
55
—
—
ns
ns
1
Chip selection to endof
write
Address valid to end of
write
tAW
20
—
30
—
40
—
50
—
55
—
ns
Address setup time
Write pulse width
Write recovery time
tAS
0
—
—
—
—
—
8
0
—
—
—
—
—
10
0
—
—
—
—
—
25
0
—
—
—
—
—
25
0
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
tWP
tWR
20
0
30
0
25
0
35
0
40
0
Data valid to end of write tDW
Data hold time tDH
15
0
20
0
25
0
25
0
30
0
Write enabled to output in tWZ
high-Z
0
0
0
0
0
2
2
Output active from end of tOW
write
5
—
5
—
0
—
0
—
0
—
ns
Notes: 1. All write cycle timing is referenced from the last valid address to first transitioning address.
2. Transition is measured ±200 mV from steady state voltage with load B. These parameters are
sampled and not 100% tested.
7
HM6287, HM6287H Series
Write Timing Waveform (1) (WE Controlled)
tWC
Address
tCW
CS
tAW
*2
tWR
tAS
*1
tWP
WE
tDH
tDW
Valid Data
Din
*3
tWZ
tOW
High impedance
tOH
Dout
Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP).
2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
3. Dout is the same phase of write data of this write cycle, if tWR is long enough.
8
HM6287, HM6287H Series
Write Timing Waveform (2) (CS Controlled)
tWC
Address
tAW
*2
tWR
tAS
tCW
CS
*1
tWP
WE
tDW
tDH
Din
Valid Data
High impedance *3
Dout
Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP).
2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
3. If CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output buffers remain in a high impedance state.
9
HM6287, HM6287H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
These specifications are guaranteed only for L-version.
Parameter
Symbol
Min
Typ
Max Unit Test conditions
VCC for data retention
VDR
2.0
—
—
V
CS ≥ VCC – 0.2 V,
0 V ≥ Vin – 0.2 V,
or 0 V ≤ Vin ≤ 0.2V
Data retention current
ICCDR
—
—
0
—
—
—
—
50*2
35*3
—
µA
µA
ns
ns
Chip deselect to data retention time
Operation recovery time
tCDR
tR
See retention waveform
*1
tRC
—
Notes: 1. tRC = Read cycle time
2. VCC = 3.0 V
3. VCC = 2.0 V
Low VCC Data Retention Waveform
Data retention mode
VCC
4.5 V
tCDR
tR
VDR
2.2 V
CS ≥ VDR – 0.2 V
CS
0 V
10
HM6287, HM6287H Series
Package Dimensions
HM6287P/LP Series (DP-22N)
Unit: mm
27.08
27.90 Max
12
11
22
1
0.88
1.3
1.30 Max
7.62
+ 0.11
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
HM6287HP/HLP Series (DP-22NB)
Unit: mm
27.08
27.90 Max
22
12
1
11
0.88
1.3
1.30 Max
7.62
+ 0.11
– 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
11
HM6287, HM6287H Series
HM6287HJP/HLJP Series (CP-24D)
Unit: mm
15.63
16.00 Max
13
12
24
1
0.74
1.30 Max
+ 0.35
– 0.16
1.27
0.43 ± 0.10
6.76
0.10
12
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