HM64YGB36100BP-33 [RENESAS]
32M Synchronous Late Write Fast Static RAM (1-Mword 】 36-bit); 32M同步后写高速静态RAM （ 1 - Mword 】 36位）
| 型号： | HM64YGB36100BP-33 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 32M Synchronous Late Write Fast Static RAM (1-Mword 】 36-bit) |
| 文件： | 总21页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM64YGB36100 Series
32M Synchronous Late Write Fast Static RAM
(1-Mword × 36-bit)
REJ03C0271-0100
(Previous ADE-203-1374 (Z) Rev. 0.0)
Rev.1.00
Jun.27.2005
Description
The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword × 36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V ± 5% operation and 1.5 V (VDDQ)
32-Mbit density
Synchronous register to register operation
Internal self-timed late write
Byte write control (4 byte write selects, one for each 9-bit)
Optional ×18 configuration
HSTL compatible I/O
Programmable impedance output drivers
Differential HSTL clock inputs
Asynchronous G output control
Asynchronous sleep mode
FC-BGA 119pin package with SRAM JEDEC standard pinout
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Ordering Information
Type No.
Organization Access time
1M × 36 1.6 ns
Cycle time
3.3 ns
Package
119-bump 1.27 mm
HM64YGB36100BP-33
14 mm × 22 mm BGA
PRBG0119DC-A (BP-119F)
Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, G: Late Write SRAM, B: VDDQ = 1.5 V
Rev.1.00 Jun 27, 2005 page 1 of 19
HM64YGB36100 Series
Pin Arrangement
1
2
3
4
NC
5
6
7
A
B
C
D
E
F
VDDQ
NC
SA14
SA15
SA16
DQc8
DQc6
DQc4
DQc2
DQc0
VDD
SA13
SA12
SA11
VSS
SA6
SA5
SA4
VSS
SA7
VDDQ
NC
SA20
VDD
ZQ
SA9
NC
SA8
NC
DQc7
DQc5
VDDQ
DQc3
DQc1
VDDQ
DQd1
DQd3
VDDQ
DQd5
DQd7
NC
DQb8
DQb6
DQb4
DQb2
DQb0
VDD
DQb7
DQb5
VDDQ
DQb3
DQb1
VDDQ
DQa1
DQa3
VDDQ
DQa5
DQa7
NC
VSS
SS
G
VSS
VSS
VSS
G
H
J
SWEc
VSS
NC
SWEb
VSS
NC
VREF
VSS
VDD
K
VREF
VSS
K
L
DQd0
DQd2
DQd4
DQd6
DQd8
SA10
NC
DQa0
DQa2
DQa4
DQa6
DQa8
SA1
SWEd
VSS
K
SWEa
VSS
M
N
P
R
T
SWE
SA17
SA19
VDD
SA3
TCK
VSS
VSS
VSS
VSS
M1
M2
NC
SA18
TDI
SA2
TDO
NC
ZZ
U
VDDQ
TMS
NC
VDDQ
(Top view)
Block Diagram
Read
add. reg.
SA1 to SA20
Write
add. reg.
1
0
Memory array
1M × 36
SA1 to SA20
compare
Match0
0
1
SWEx
1st reg.
SWEx
2nd reg.
Byte write
control
(x: a to d)
Din
reg.
Output
reg.
SS
reg.
SWE
reg.
Output enable
K
Impedance
control
ZQ
DQxn
(x: a to d,
n: 0 to 8)
Rev.1.00 Jun 27, 2005 page 2 of 19
HM64YGB36100 Series
Pin Descriptions
Name
I/O type
Supply
Descriptions
Notes
VDD
VSS
VDDQ
VREF
K
Core power supply
Ground
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Output power supply
Input reference, provides input reference voltage
Clock input, active high
K
SS
Clock input, active low
Synchronous chip select
SWE
SAn
SWEx
G
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
n: 1 to 20
x: a to d
ZZ
ZQ
Output impedance control
1
DQxn
Synchronous data input/output
x: a to d
n: 0 to 8
M1, M2
TMS
TCK
TDI
Input
Input
Input
Input
Output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
TDO
NC
M1
M2
Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or open, output
buffer impedance will be maximum.
2. Mode control input pins M1 and M2 are set at power-up and will not change the states during the SRAM
operates.
This SRAM supports only single clock, pipelined read protocol.
Other settings are not applicable.
Mode control pin M2 can be set to VDDQ instead of VDD
.
Rev.1.00 Jun 27, 2005 page 3 of 19
HM64YGB36100 Series
Truth Table
ZZ
SS
×
G
×
SWE
×
SWEa
SWEb
SWEc
SWEd
K
K
×
Operation
DQ (n)
DQ (n+1)
High-Z
H
×
×
×
×
×
Sleep
mode
High-Z
L
L
L
L
L
L
L
L
H
×
L
L
L
L
L
L
×
H
L
×
×
×
×
×
×
H
H
L
L
L
L
L
×
×
×
L
H
L
L
L
×
×
×
L
L
H
L
L
×
×
×
L
L
L
H
L
×
×
×
L
L
L
L
H
L-H
×
H-L Dead
(not
×
High-Z
selected)
Dead
×
High-Z
×
×
(dummy
read)
L-H
L-H
L-H
L-H
L-H
L-H
H-L Read
H-L Write
DOUT
(a, b, c, d)
0 to 8
High-Z
High-Z
High-Z
High-Z
High-Z
DIN
(a, b, c, d)
0 to 8
a, b, c, d
byte
H-L Write
b, c, d
DIN
(b, c, d)
0 to 8
byte
H-L Write
a, c, d
DIN
(a, c, d)
0 to 8
byte
H-L Write
a, b, d
DIN
(a, b, d)
0 to 8
byte
H-L Write
a, b, c
DIN
(a, b, c)
0 to 8
byte
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
×
×
×
×
×
×
×
×
L
L
L
L
L
L
L
L
H
L
H
H
L
L
H
H
L
L
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
H-L Write
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DIN (c, d)
0 to 8
c, d byte
H-L Write
a, d byte
H-L Write
a, b byte
H-L Write
b, c byte
DIN (a, d)
0 to 8
L
H
H
L
DIN (a, b)
0 to 8
H
H
H
H
L
L
DIN (b, c)
0 to 8
H
H
L
H
L
H-L Write
d byte
DIN (d)
0 to 8
H
H
H
H-L Write
c byte
DIN (c)
0 to 8
H
H
H-L Write
b byte
DIN (b)
0 to 8
H
H-L Write
a byte
DIN (a)
0 to 8
Notes: 1. H: VIH, L: VIL, ×: VIH or VIL
2. SWE, SS, SWEa to SWEd and SA are sampled at the rising edge of K clock.
Rev.1.00 Jun 27, 2005 page 4 of 19
HM64YGB36100 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The
value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching
with a tolerance of 15% is 250 Ω typical. If the status of ZQ pin is open, output impedance is maximum value.
Maximum impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when
the SRAM is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z,
therefore will trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance
to be completely updated.
Absolute Maximum Ratings
Parameter
Symbol
VIN
Rating
−0.5 to VDDQ + 0.5
−0.5 to +3.13
−0.5 to +2.1
0 to +85
Unit
Notes
1, 4
Input voltage on any pin
Core supply voltage
Output supply voltage
Operating temperature
Storage temperature
Output short-circuit current
Latch up current
V
V
V
VDD
1
VDDQ
TOPR
TSTG
IOUT
1, 4
°C
−55 to +125
25
°C
mA
ILI
200
mA
Package junction to top thermal resistance
Package junction to board thermal resistance
θJ-top
θJ-board
6.5
°C/W
°C/W
5
5
12
Notes: 1. All voltage is referenced to VSS
.
2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for
extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the
tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the
instantaneous value of VDDQ
5. See figure below.
.
θJ-top
θJ-board
Thermocouple
Thermo grease
Teflon block
Thermocouple
SRAM
Water
Water
Cold plate
SRAM
Water
Water
Cold plate
JEDEC/2S2P BGA
Thermal board
JEDEC/2S2P
Thermal board
BGA
Thermo grease
Teflon block
Rev.1.00 Jun 27, 2005 page 5 of 19
HM64YGB36100 Series
Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse
air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions
(Ta = 0 to +85°C)
Parameter
Power supply voltage: core
Power supply voltage: I/O
Input reference voltage: I/O
Input high voltage
Symbol
VDD
Min
Typ
Max
Unit
Notes
2.38
1.40
0.60
2.50
1.50
0.75
2.63
1.60
0.90
V
VDDQ
VREF
VIH
V
V
V
V
V
V
1
4
4
VREF + 0.10
−0.30
VDDQ + 0.30
REF − 0.10
Input low voltage
VIL
V
Clock differential voltage
Clock common mode voltage
VDIF
VCM
0.10
VDDQ + 0.30
0.90
2, 3
3
0.60
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
2. Minimum differential input voltage required for differential input clock operation.
3. See figure below.
.
4. VREF = 0.75 V (typ).
Differential Voltage / Common Mode Voltage
VDDQ
VDIF
VCM
VSS
Rev.1.00 Jun 27, 2005 page 6 of 19
HM64YGB36100 Series
DC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Min Max Unit Notes
µA
Parameter
Symbol
Input leakage current
Output leakage current
Standby current
ILI
2
5
1
2
3
4
5
6
ILO
µA
mA
mA
mA
W
ISBZZ
IDD
150
550
200
2.3
VDD operating current, excluding output drivers
Quiescent active power supply current
IDD2
P
Maximum power dissipation, including output drivers
Parameter
Output low voltage
Symbol
VOL
Min
Typ
Max
Unit Notes
VSS
DDQ − 0.4
VSS + 0.4
VDDQ
V
7
8
Output high voltage
ZQ pin connect resistance
Output “Low” current
Output “High” current
VOH
RQ
IOL
V
V
250
Ω
(VDDQ/2) / {(RQ/5) − 15%}
(VDDQ/2) / {(RQ/5) + 15%}
mA 9, 11
IOH
(VDDQ/2) / {(RQ/5) + 15%}
(VDDQ/2) / {(RQ/5) − 15%}
mA 10, 11
Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin)
2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z
3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is
guaranteed at +75°C junction temperature.
4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle
5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz
6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer
to determine electrical and package requirements for the SRAM device.
7. RQ = 250 Ω, IOL = 6.8 mA
8. RQ = 250 Ω, IOH = −6.8 mA
9. Measured at VOL = 1/2 VDDQ
10.Measured at VOH = 1/2 VDDQ
11.The total external capacitance of ZQ pin must be less than 7.5 pF.
Rev.1.00 Jun 27, 2005 page 7 of 19
HM64YGB36100 Series
AC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Single Differential Clock Register-Register Mode
HM64YGB36100BP
-33
Parameter
Symbol
tKHKH
Unit
ns
Notes
Min
Max
CK clock cycle time
3.3
1.3
1.3
0.3
0.3
0.6
0.6
CK clock high width
tKHKL
tKLKH
tAVKH
tDVKH
tKHAX
tKHDX
tKHQV
tKHQX
tKHQX2
tKHQZ
tGLQX
tGLQV
tGHQZ
tZZR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK clock low width
Address setup time
2
2
Data setup time
Address hold time
Data hold time
Clock high to output valid
Clock high to output hold
Clock high to output low-Z (SS control)
Clock high to output high-Z
Output enable low to output low-Z
Output enable low to output valid
Output enable high to output high-Z
Sleep mode recovery time
Sleep mode enable time
Notes: 1. See figure in ”AC Test Conditions”.
1.6
2.0
1
0.65
0.65
0.65
0.1
1, 6
1, 4, 6
1, 3, 6
1, 4, 6
1, 4
2.0
2.0
1, 3
20.0
5
tZZE
15.0
1, 3, 5
2. Parameters may be guaranteed by design, i.e., without tester guardband.
3. Transitions are measured ±50 mV of output high impedance from output low impedance.
4. Transitions are measured ±50 mV from steady state voltage.
5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
6. Minimum value is verified by design and tested without guardband.
Rev.1.00 Jun 27, 2005 page 8 of 19
HM64YGB36100 Series
Timing Waveforms
Read Cycle-1
tKHKH
tKHKL
tKLKH
K,
tAVKH
tKHAX
A1
A2
A3
A4
SA
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX
DQ
Q1
Q2
tKHQV
Read Cycle-2 (SS Controlled)
tKLKH
tKHKH
tKHKL
K,
tAVKH
tKHAX
A1
A3
A4
SA
tAVKH
tKHAX
tAVKH
tKHAX
tKHQX2
tKHQZ
Q0
Q1
Q3
DQ
Rev.1.00 Jun 27, 2005 page 9 of 19
HM64YGB36100 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
A1
A2
A3
A4
SA
tAVKH
tAVKH
tGLQX
tGHQZ
Q1
DQ
Q0
Q3
tGLQV
Read operation
During read cycle, the address is registered during the first rising clock edge, the internal array is read between this
first edge and second edge, and data is captured in the output register.
Rev.1.00 Jun 27, 2005 page 10 of 19
HM64YGB36100 Series
Write Cycle
tKHKH
tKHKL
tKLKH
K,
tAVKH
tAVKH
tAVKH
tAVKH
tKHAX
A1
A2
A3
A4
SA
tKHAX
tKHAX
tKHAX
tDVKH
tKHDX
D0
D1
D2
D3
DQ
Notes: ZZ = VIL, x: a to d
Write operation
During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during
the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation
the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is
needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of
the same address.
Rev.1.00 Jun 27, 2005 page 11 of 19
HM64YGB36100 Series
Read-Write Cycle
READ
DEAD
( control)
READ
tKHKH
WRITE
READ
WRITE
(
control)
tKHKL tKLKH
K,
tAVKH
tKHAX
tKHAX
tKHAX
tKHAX
SA
A1
A3
A4
A6
A7
tAVKH
tAVKH
tAVKH
tKHQV
tGHQZ tDVKH tKHDX
D3
tGLQV
DQ
Q0
Q1
Q4
Q6
tGLQX
tKHQX
tKHQZ
Notes: ZZ = VIL, x: a to d
ZZ Control
tKHKL
tKLKH
tKHKH
K,
tAVKH
tAVKH
tAVKH
tKHAX
SA
A1
tKHAX
tKHAX
ZZ
Sleep active
Sleep off
Q1
Sleep active
DQ
tZZE
tZZR
Notes: G = VIL, x: a to d
When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
Rev.1.00 Jun 27, 2005 page 12 of 19
HM64YGB36100 Series
Input Capacitance
(VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Min Max Unit
Pin name
SAn, SS, SWE, SWEx
K, K
Notes
1, 3
4
5
5
pF
pF
pF
Clock input capacitance
I/O capacitance
CCLK
CIO
1, 2, 3
1, 3
DQxn
Notes: 1. This parameter is sampled and not 100% tested.
2. Exclude G
3. Connect pins to GND, except VDD, VDDQ, and the measured pin.
AC Test Conditions
Parameter
Symbol
VREF
Conditions
Unit Note
Input and output timing reference levels
Input signal amplitude
Input rise / fall time
0.75
V
VIL, VIH
tr, tf
0.25 to 1.25
0.5 (10% to 90%)
Differential cross point
0.75
V
ns
Clock input timing reference level
VDIF to clock
V
V
VCM to clock
0.75
Output loading conditions
See figure below
Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V.
Output Loading Conditions
50 Ω
16.7 Ω
16.7 Ω
50 Ω
50 Ω
0.75 V
0.75 V
16.7 Ω
5 pF
5 pF
DQ
50 Ω
0.75 V
Rev.1.00 Jun 27, 2005 page 13 of 19
HM64YGB36100 Series
Boundary Scan Test Access Port Operations
Overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access
port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all
of the functions required for 1149.1 compliance. The HM64YGB series contains a TAP controller. Instruction register,
boundary scans register, bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
TMS
TDI
Test clock
Test mode select
Test data in
TDO
Test data out
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected.
To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V.
TAP DC Operating Characteristics
(Ta = 0 to +85°C)
Max Notes
Parameter
Boundary scan input high voltage
Symbol
Min
1.4 V
VIH
VIL
ILI
3.6 V
0.8 V
+10 µA
0.2 V
Boundary scan input low voltage
Boundary scan input leakage current
Boundary scan output low voltage
Boundary scan output high voltage
Notes: 1. 0 ≤ VIN ≤ 3.6 V for all logic input pin
2. IOL = 2 mA at VDD = 2.5 V.
−0.3 V
−10 µA
1
2
3
VOL
VOH
2.1 V
3. IOH = −2 mA at VDD = 2.5 V.
Rev.1.00 Jun 27, 2005 page 14 of 19
HM64YGB36100 Series
TAP AC Operating Characteristics
(Ta = 0 to +85°C)
Unit Note
Parameter
Test clock cycle time
Symbol
Min
Max
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
67
30
30
10
10
10
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test clock high pulse width
Test clock low pulse width
Test mode select setup
Test mode select hold
Capture setup
1
1
Capture hold
tCH
TDI valid to TCK high
TCK high to TDI don’t care
TCK low to TDO unknown
TCK low to TDO valid
tDVTH
tTHDX
tTLQX
tTLQV
20
Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP AC Test Conditions
(VDD = 2.5 V)
Temperature
0°C ≤ Ta ≤ +85°C
1.1 V
Input timing measurement reference level
Input pulse levels
0 to 2.5 V
Input rise/fall time
1.5 ns typical (10% to 90%)
1.25 V
Output timing measurement reference level
Test load termination supply voltage (VT)
Output load
1.25 V
See figure below
Boundary Scan AC Test Load
VT
DUT
50 Ω
Z0 = 50 Ω
TDO
Rev.1.00 Jun 27, 2005 page 15 of 19
HM64YGB36100 Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
tMVTH tTHMX
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
tCS tCH
RAM
ADDRESS
Test Access Port Registers
Register name
Instruction register
Length
Symbol
Note
3 bits
1 bit
IR [2:0]
BP
Bypass register
ID register
32 bits
70 bits
ID [31:0]
Boundary scan register
BS [70:1]
TAP Controller Instruction Set
IR2 IR1 IR0
Instruction
SAMPLE-Z
Operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tristate all data drivers and capture the pad value
Tristate all data drivers and capture the pad value
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
BYPASS
PRIVATE
BYPASS
Do not use. They are reserved for vendor use only
Note: This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE
1149.1.
Rev.1.00 Jun 27, 2005 page 16 of 19
HM64YGB36100 Series
Boundary Scan Order (HM64YGB36100)
Bit #
Bump ID
Signal name
Bit #
Bump ID
Signal name
1
5R
4P
4T
6R
5T
7T
6P
7P
6N
7N
6M
6L
M2
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4B
4H
4M
3L
SA12
SA15
SA13
SA11
SA16
SA14
DQc8
DQc7
DQc6
DQc5
DQc4
DQc2
DQc3
DQc0
DQc1
SWEc
ZQ
2
SA19
SA3
3
4
SA1
5
SA2
6
ZZ
7
DQa8
DQa7
DQa6
DQa5
DQa4
DQa2
DQa3
DQa0
DQa1
SWEa
K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7L
6K
7K
5L
4L
4K
4F
5G
7H
6H
7G
6G
6F
7E
6E
7D
6D
6A
6C
5C
5A
6B
5B
K
SS
SA20
G
SWEb
DQb1
DQb0
DQb3
DQb2
DQb4
DQb5
DQb6
DQb7
DQb8
SA7
NC
SWE
SWEd
DQd1
DQd0
DQd3
DQd2
DQd4
DQd5
DQd6
DQd7
DQd8
SA18
SA10
SA17
M1
1K
2K
1L
2L
2M
1N
2N
1P
2P
3T
2R
4N
3R
SA8
SA4
SA6
SA9
SA5
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register
by a “Place Holder”. Place holder registers are internally connected to VSS
.
3. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite
logic levels for the reliable operation.
4. ZZ must remain VIL during boundary scan.
5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results.
6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.
Rev.1.00 Jun 27, 2005 page 17 of 19
HM64YGB36100 Series
ID Register
Revision
number
(31:28)
Device density
and configuration
(27:18)
Vendor
definition
(17:12)
Vendor JEDEC
code (11:1)
Start
bit (0)
Part
HM64YGB36100
0000
0100000100
xxxxxx
00000000111
1
TAP Controller State Diagram
Test-logic-
1
reset
0
1
1
1
Run-test/
idle
Select-
DR-scan
Select-
IR-scan
0
0
0
1
1
Capture-DR
0
Capture-IR
0
Shift-DR
1
Shift-IR
1
0
0
0
0
1
1
Exit1-DR
0
Exit1-IR
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the
time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high
for at least five rising edges of TCK.
Rev.1.00 Jun 27, 2005 page 18 of 19
HM64YGB36100 Series
Package Dimensions
HM64YGB36100BP Series (PRBG0119DC-A / Previous Code: BP-119F)
JEITA Package Code
P-BGA119-14x22-1.27
RENESAS Code
PRBG0119DC-A
Previous Code
BP-119F
MASS[Typ.]
1.0g
D
A
B
INDEX
×4
v
y1
S
S
y
S
e
U
T
Dimension in Millimeters
R
P
N
M
L
Reference
Symbol
Min
Nom
14.00
22.00
Max
D
E
K
J
v
0.20
w
H
G
F
A
1.78
0.58
1.98
0.66
1.27
0.90
2.18
0.74
A 1
e
E
D
C
B
A
b
0.84
0.96
0.30
0.20
0.35
x
y
1
2
3
4
5
6
7
y 1
S D
S E
Z D
Z E
φ b
φ
×
M
S A B
φ
0.15 M
S
Rev.1.00 Jun 27, 2005 page 19 of 19
Revision History
HM64YGB36100 Series Data Sheet
Description
Summary
Rev.
0.0
1.00
Date
Page
Dec. 5, 2002
Jun. 27, 2005
Initial issue
Change format issued by Renesas Technology Corp.
Ordering Information
Addition of Renesas package codes
Change of
1
5
Programmable Impedance
Output Drivers
19
Package Dimensions
Addition of Renesas package codes
Changed to Renesas formats
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