HN29V128A0ABP-5E [RENESAS]
8MX16 FLASH 3.3V PROM, PBGA95, 10 X 11.50 MM, 0.80 MM PITCH, LEAD FREE, CSP-95;
| 型号： | HN29V128A0ABP-5E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8MX16 FLASH 3.3V PROM, PBGA95, 10 X 11.50 MM, 0.80 MM PITCH, LEAD FREE, CSP-95 可编程只读存储器 内存集成电路 |
| 文件： | 总53页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN29V128A1A (3.3 V/×8)
HN29V128A0A (3.3 V/×16)
HN29A128A1A (1.8 V/×8)
HN29A128A0A (1.8 V/×16)
128M superAND Flash Memory
(with internal sector management)
REJ03C0031-0300Z
Rev. 3.00
Jun. 09, 2004
Description
The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash
memory, which uses cost effective and high performance AND type multi-level memory cell technology.
Current AND flash memory requires us to support complicated operations such as sector management for
defect sector and error check correction. But this series doesn’t need such operations. Beside it supports
wear leveling function, which is sector replacement function in case of that certain sector, reaches certain
erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest
sector(2k byte) without command and address data input when power is on.
Note: This product is authorized for using consumer application such as cellular phone,
Therefore, please contact Renesas Technology’s sales office before using other applications.
Rev.3.00, Jun.09.2004, page 1 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Features
•
On-board single power supply (VCC): VCC = 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A)
: VCC = 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A)
•
•
Operating temperature range: Ta = 0 to +70 °C
Program/erase, rewrite endurance
105 times
•
Access time
First access
80 µs (typ) (3.3 V, ×8/×16)
150 µs (typ) (1.8 V, ×8/×16)
Serial read cycle
50 ns (min) (3.3 V, ×8/×16)
100 ns (min) (1.8 V, ×8/×16)
maximum transfer rate (sequential read)
20.0 Mbyte/s (3.3 V, ×8)
40.0 Mbyte/s (3.3 V, ×16)
10.0 Mbyte/s (1.8 V, ×8)
20.0 Mbyte/s (1.8 V, ×16)
•
•
•
Program time
1.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
2.0 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
Erase time
2.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
Rewrite time
2.2 ms (typ) /sector (2048 byte) (3.3 V, ×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V, ×8/×16)
Rev.3.00, Jun.09.2004, page 2 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
•
Low power dissipation (3.3 V and 1.8 V)
Standby current
ICCS1 = 1 mA (max)
ICCS2 = 50 µA (max) (CMOS level)
ICCS3 = 10 µA (max) (3.3 V), 15µA (max) (1.8 V) (deep standby)
Serial read operation current
ICC1 = 30 mA (max)
Program/erase/rewrite operation current
ICC2/3/4 = 60 mA (max) (program/erase/rewrite)
Sector management
•
Following functions are build-in flash memory component.
Sector management:
If certain sector had been damaged, it would be replaced by the spare sector automatically.
Always 100% of sector number are available up to 105 erase/write cycles per device.
Error check and correction:
ECC code is generated at the time of programming, and data error is checked at the time of read
operation. If data error occurs, the data will be corrected automatically.
(ECC: 1-byte error correction, 2-byte error detection per 512byte page)
Wear leveling:
To avoid erase/program/rewrite operation converge on the particular physical sector, The number of
erase/program/rewrite operation will be leveled automatically by changing internal logical sector
address.
•
Package line up
CSP: CSP 95-bump (TBP-95V)
Ordering Information
Type No.
Operating voltage (VCC) Organization
Package
HN29V128A1ABP-5E
HN29V128A0ABP-5E
HN29A128A1ABP-8E
HN29A128A0ABP-8E
3.3 V
3.3 V
1.8 V
1.8 V
×8
10.0 × 11.50 mm2, 95-bump
0.8 mm ball pitch CSP (TBP-95V)
Lead free
×16
×8
×16
Rev.3.00, Jun.09.2004, page 3 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Arrangement 95-bump CSP
95-bump CSP
1
2
3
4
5
6
7
8
9
10
11
12
DU
DU
DU
DU
DU
DU
DU
DU
DU
A
B
C
D
E
F
VSS
DU DU
DU DU
DU WE
DU
DU
DU
DU
DU
DU DU
DU
DU I/O15
I/O8 I/O7 DU
MRES
I/O14
DU
R/B DU
DU I/O13 I/O6
I/O16 DU
VCC DU
VSS DSE DU PRE I/O5 DU
DU WP
DU DU
DU CLE
DU ALE
DU
DU
DU
DU
DU
DU I/O3 DU I/O11 I/O4 I/O12 DU
G
H
J
DU
DU
DU
DU
DU
DU
I/O1 I/O9 I/O2 I/O10 DU
DU DU
DU VSS
DU
DU
DU
DU
DU
DU
RE
CE
K
L
DU
DU
DU
DU
DU
M
(TOP View)
Rev.3.00, Jun.09.2004, page 4 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Description
Name
I/O1 to I/O8
I/O9 to I/O16
CLE
Description
Command, address, data input/output
Data input/output (×8 device: DU)
Command latch enable
Address latch enable
Chip enable
ALE
CE
RE
Read enable
WE
Write enable
WP
Write protect
R/B
Ready/busy
PRE
Power on auto read enable
Master reset output
Deep standby enable
Power supply
MRES
DSE
VCC
VSS
Ground
DU
Don’t use
Note: 1. All VSS pins should be connected respectively.
Rev.3.00, Jun.09.2004, page 5 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Function
Chip enable :CE
CE is for selecting a chip and making the device in the active state.
During command waiting state, CE=H makes the device standby state.
During command execution such as erase, program and rewrite, CE=H can’t stop command operation
itself.
Read enable :RE
RE is output enable pin and also controls read timing. Clocking RE increments the internal address and
reads out each data.
Write enable :WE
Commands, address, and program data are latched into the device at the rising edge of WE.
Command latch enable :CLE
CLE specifies the command data. When CLE=H, data on I/O bus will be recognized as the command data.
The command data is latched on the rising edge of WE with CLE=H.
Address latch enable :ALE
ALE specifies the address data. When ALE=H, data on I/O bus will be recognized as the address data.
The address data is latched on the rising edge of WE with ALE=H.
Write protect :WP
WP=L disables erase, program and rewrite operation.
Ready/busy :R/B
R/B is the output signal. It shows the internal status of the device to be ready or busy.
It is an open-drain signal and should be pulled up to VCC via suitable resistance.
Power on auto read enable :PRE
PRE is control pin with active high signal. PRE active Power on auto read mode and Auto read mode. If
Power on auto read mode and Auto read mode are unnecessary, PRE pin should be connected to VSS or
open.
Master reset output :MRES
MRES is the output signal and for providing a reset signal to CPU when Power on auto read mode and auto
read mode are activated. MRES going from low to high indicates that the data is ready for reading.
If Power on auto read mode and Auto read mode are not activated, MRES going from low to high indicates
that the device initialization is completed after power is on.
Deep standby enable :DSE
DSE must be low when power is on. The device is initialized by DSE signal low to high after power is on.
During command waiting state or standby state, DSE = L makes the device deep standby state. When DSE
goes to high, the device returns from the deep standby state. During command execution, DSE = L stops
command operation and makes the device deep standby state.
Input/output pins :I/O1 to I/O16
The I/O pins are used as input/output data and also as command and address.
I/O pins are tri-state pins and transit to the high impedance state when disabled by CE and RE.
I/O9 to 16 are effective for ×16 product, but they are applied for data only.
Only I/O1 to 8 pins are used as command and address inputs for ×16 product.
Rev.3.00, Jun.09.2004, page 6 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Block Diagram
VCC VSS
Data output
buffer
Y-address counter
I/O1
to
Y-decoder
Y-gating
Data input
buffer
Input data
control
I/O8
×8
Multiplexer
I/O9
to
×16
I/O16
Data register 2,048 Byte
R/B
MRES
CE
CLE
ALE
Memory matrix
8,192 × 2,048 × 8
8,192 × 1,024 × 16
Control
Read/Program/Erase
control
WE
RE
WP
signal buffer
PRE
DSE
Rev.3.00, Jun.09.2004, page 7 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Memory Map and Address
1FFF
1FFE
1FFD
1FFF
1FFE
1FFD
0002
0001
0000
0002
0001
0000
512 bytes
256 words
2,048 bytes
1,024 words
(×8 device)
(×16 device)
(1) ×8 device
Page size : (512) bytes
(2) ×16 device
Page size : (256) words
Sector size : (2,048) bytes
Total device capacity : 2,048 bytes × 8,192 sectors
Sector size : (1,024) words
Total device capacity : 1,024 words × 8,192 sectors
Address Input
Case of HN29V128A1A/HN29A128A1A (×8 device)
Clock Cycle
I/O8
A7
I/O7
A6
I/O6
A5
I/O5
A4
I/O4
A3
I/O3
A2
I/O2
A1
I/O1
A0
First cycle (CA1)
Second cycle (CA2)
Third cycle (SA1)
Fourth cycle (SA2)
L*
L*
L*
L*
L*
A10
A13
A21
A9
A8
A18
L*
A17
L*
A16
L*
A15
A23
A14
A22
A12
A20
A11
A19
Notes: 1. A0 to A8: Column address
A11 to A23: Sector address
A9 to A10: Page address
2. L* must be set to “Low”.
Case of HN29V128A0A/HN29A128A0A (×16 device)
Clock Cycle
I/O8
A7
I/O7
A6
I/O6
A5
I/O5
A4
I/O4
A3
I/O3
A2
I/O2
A1
I/O1
A0
First cycle (CA1)
Second cycle (CA2)
Third cycle (SA1)
Fourth cycle (SA2)
L*
L*
L*
L*
L*
L*
A9
A8
A17
L*
A16
L*
A15
L*
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
Notes: 1. A0 to A7: Column address
A10 to A22: Sector address
A8 to A9: Page address
2. I/O9 to I/O16: VIH or VIL
3. L* must be set to “Low”.
Rev.3.00, Jun.09.2004, page 8 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Mode Selection
The address input, command input and data input/output operations of the device are controlled by CLE,
ALE, CE, WE, RE WP and DSE signals. The following table shows the operation logic table.
Mode
CLE
ALE
CE
WE
RE
WP
DSE
I/O
Power
Command input
H
L
L
H
×
H
Input
Active
Address input
Data input
L
L
L
H
L
L
L
L
H
H
×
×
×
H
H
H
Input
Active
Active
Active
Input
Data output
L
H
Output
High-Z
Output deselect
L
L
L
H
H
×
H
H
Active
Active
During
rewriting/erasing
×
×
×
×
×
H
Input/
output
Write protect
×
×
×
×
×
L
H
Input/
output
Active/
standby
Standby
×
×
×
×
H
×
×
×
×
×
×
H
L
High-Z
High-Z
Standby*2
Deep standby
×
Deep
standby*3
Notes: 1. H: VIH (DSE: VIHP), L: VIL (DSE: VILP), ×: VIH or VIL
2. When setting CE = H during the read operation, even if it is in ready state, the device becomes
the following data output waiting state and doesn’t become standby mode. It becomes standby
mode to set CE = H in ready state after read stop command execution.
3. The device can transfer only from command waiting state or standby state to deep standby state.
Command Definition
Mode
First cycle Second cycle
Acceptance in the busy state
Acceptance (in Read busy state only)*1
Acceptance
Data input
80H
00H
0FH
F0H
10H
60H
1FH
70H
90H
C1H
C0H
D0H
Read mode
Sequential read mode
Read stop
Program
Erase
Rewrite
Status read
ID read
Deep standby (release)
Deep standby (setup)
Note: 1. Not acceptable during the busy state in the sequential read mode.
Rev.3.00, Jun.09.2004, page 9 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
State transition diagram
Power off
VCC, DSE
VCC, DSE
Deep standby (ICCS3
)
DSE
DSE
PRE
DSE DSE
CE
CE
Standby
(ICCS1/2
)
PRE
Command
deep standby
70H
RE
C0H
Status
read
PRE
Auto read
Ready
*SRD setup
(ICCS3
)
C1H, Ready
Ready,00H
Data output
PRE
F0H
RE
Sector read-(Auto read)
RE
PRE
RE
RE
C
O
M
M
A
F0H
Read
Data output
Ready
N
D
Ready, 00H
RE
CA
SA
70H
70H
W
A
I
T
I
Read setup
CA input
SA input
SA input
SRD setup
Status read
00H
0FH
SA
RE
CA
Sequential
read setup
CA input
SRD setup
Status read
N
G
Sector End
Sequential read
Ready, 00H
PRE
F0H
SA
D0H
70H
70H
70H
Erase setup
Erase start
SA input
60H
80H
Erase finish
CA
SA
10H
1FH
Data input
setup
CA input
SA input
Data input
Program start
Rewrite start
Program finish
Rewrite finish
Ready
*SRD setup
RE
70H
90H
*SRD setup
Status
read
RE
RE
Status
read
RE
ID read setup
Address input
ID read
Note: SRD = Status read data
Rev.3.00, Jun.09.2004, page 10 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Absolute Maximum Ratings
If exceeded the following specification, the device may be damaged.
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V)
HN29V128A0A (3.3 V) HN29A128A0A (1.8 V)
Parameter
Symbol Value
Value
Unit
V
Notes
VCC voltage
VCC
VSS
VIN
−0.6 to +4.6
0
−0.6 to +2.45
0
1
VSS voltage
V
Input voltage
Input/output voltage
−0.6 to +4.6
−0.6 to +2.45
V
1, 2
VI/O
−0.6 to VCC + 0.3
(≤ 4.6)
−0.6 to VCC + 0.3
(≤ 2.45)
V
Operating temperature range Topr
Storage temperature range Tstg
Notes: 1. Relative to VSS
2. VIN, VOUT = −2.0 V for pulse width ≤ 20 ns
0 to +70
0 to +70
°C
°C
−55 to +125
−55 to +125
3
.
3. Device storage temperature range before programming.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol Min
Typ
Max
10
Unit
pF
Test conditions
VIN = 0 V
Input capacitance
Output capacitance
CIN
COUT
10
pF
VOUT = 0 V
Rev.3.00, Jun.09.2004, page 11 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
DC Characteristics
DC Characteristics (1)
(Ta = 0 to +70°C)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V)
HN29V128A0A (3.3 V) HN29A128A0A (1.8 V)
Test
Unit conditions
Parameter
Symbol Min
Typ
3.3
Max
Min
Typ
1.8
Max
Power supply voltage VCC
2.7
3.6
1.70
1.95
V
V
High input voltage
Low input voltage
VIH
VCC
0.8
×
×
VCC
0.3
+
VCC
0.8
×
VCC
0.3
+
VIL
−0.3
VCC
0.2
×
+
×
−0.3
VCC
0.2
×
+
×
V
V
V
High input voltage
(DSE, PRE pin)
Low input voltage
(DSE, PRE pin)
VIHP
VILP
VCC
0.9
VCC
0.3
VCC
0.9
×
VCC
0.3
−0.3
VCC
0.1
−0.3
VCC
0.1
Input leakage current ILI
2
2
2
2
µA
µA
VIN = 0 V to VCC
Output leakage
current
ILO
VOUT = 0 V to VCC
Operating current
(Serial read)
ICC1
30
30
mA CE = VIL
RE = VIH
(Program)
(Erase)
ICC2
ICC3
ICC4
60
60
60
60
60
60
mA
mA
mA
(Rewrite)
Rev.3.00, Jun.09.2004, page 12 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
DC Characteristics (2)
(Ta = 0 to +70°C)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V)
HN29V128A0A (3.3 V) HN29A128A0A (1.8 V)
Test
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit conditions
Standby current
(Standby state)
ICCS1
1
1
mA CE = VIH, WP = VIH or
VIL, PRE = VIHP or VILP
or open, DSE = VIHP
ICCS2
50
10
10
50
15
15
µA CE = VCC − 0.2 V,
WP = VCC 0.2 V or
VSS 0.2 V, PRE =
VCC 0.2 V or VSS
0.2 V or open, DSE =
VCC 0.2 V
Deep standby
current
(Deep standby
command)
ICCS3
ICCS3
VOH
µA CE = VCC 0.2 V,
PRE = VCC 0.2 V or
VSS 0.2 V or open,
DSE = VCC 0.2 V,
WP = VCC 0.2 V or
VSS 0.2 V
Deep standby
current
(DSE control)
µA CE = VCC 0.2 V,
PRE = VCC 0.2 V or
VSS 0.2 V or open,
DSE = VSS 0.2 V,
WP = VCC 0.2 V or
VSS 0.2 V
High-level output
voltage
VCC
0.2
−
VCC
0.2
−
V
IOH = −100 µA
Low-level output voltage VOL
0.2
0.2
V
IOL = 100 µA
Rev.3.00, Jun.09.2004, page 13 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
AC Characteristics (Ta = 0 to +70°C)
Test Conditions
•
V
CC : 2.7 V to 3.6 V (HN29V128A1A(×8)/HN29V128A0A(×16))
: 1.70 V to 1.95 V (HN29A128A1A(×8)/HN29A128A0A(×16))
•
•
•
•
Input pulse levels: 0 V, VCC
Input rise and fall time: 3 ns
Input and Output reference levels: 1/2 VCC / 1/2 VCC
Output load :
VCC
R1 = 3kΩ
Dout
50 pF
R2 = 3kΩ
Rev.3.00, Jun.09.2004, page 14 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
AC Characteristics (1)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V)
HN29V128A0A (3.3 V) HN29A128A0A (1.8 V)
Parameter
Symbol Min
Typ
Max
Min
0
Typ
Max
Unit
ns
Note
CLE setup time
CLE hold time
CE setup time
CE hold time
tCLS
tCLH
tCS
0
10
0
20
0
ns
ns
tCH
10
15
500
20
25
1000
ns
CE high hold time
tCEH
ns
CE high hold time in Sequential tCEHS
ns
1
read stop cycle
Write pulse width
ALE setup time
tWP
25
0
65
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
tALS
tALH
tDS
ALE hold time
10
20
10
50
15
50
1
20
50
20
100
35
100
2
Data setup time
Data hold time
tDH
Write cycle time
WE high hold time
RE high to WE low time
tWC
tWH
tRHW
tRHWS
RE high to WE low time in
1
Sequential read cycle
Ready to WP low time
Ready to RE fall time
Read pulse time
tRW
tRR
tRP
0
35
0
80
ns
ns
ns
ns
ns
20
35
50
20
80
100
Read cycle time
tRC
tREA
RE access time
(serial data access)
RE access time
tREAID
tRSTO
tOH
35
35
80
80
ns
ns
(ID read)
RE access time
(Status read)
Output data hold time
10
15
30
30
45
45
10
20
ns
ns
ns
ns
ns
ns
RE high to output high-Z time tRHZ
CE high to output high-Z time tCHZ
RE high hold time
CE access time
80
80
tREH
tCEA
100
100
CE access time
tCSTO
(status read)
WE high to CE low time
tWHC
30
50
ns
Note: 1. tCEHS, tRHWS applies to Sequential read mode only.
Rev.3.00, Jun.09.2004, page 15 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
AC Characteristics (2)
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V)
HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter
Symbol Min
Typ
Max
Min
100
100
Typ
Max
Unit
ns
Note
WE high to RE low time tWHR
30
ALE low to RE low time tAR1
100
ns
(ID read)
ALE low to RE low time tAR2
50
100
80
100
100
ns
ns
µs
ns
ns
(read cycle)
CE low to RE low time tCR
(ID read)
Start address access
from memory cell array
tR
250
200
200
150
400
200
500
WE high to Busy output tWB
time
RE high to Busy output tSRB
time in Sequential read
cycle
1
Power on to DSE High tDSE
0
0
ns
ns
time
DSE high to PRE high tPD
50
100
delay
DSE high to busy time tDB
5
5
5
5
ms
ms
ns
Power on busy time
tBSY
30
50
50
100
Ready to MRES high
tRMRES
time
Deep standby busy
Auto read busy time
PRE pulse width
WP setup time
WP hold time
Read stop time
tDBSY
tARBSY
tPRE
50
100
100
0
300
1
500
1
µs
ms
ns
ns
ns
µs
ns
100
100
100
0
tWPS
tWPH
tRSTP
tCHWS
250
400
CE high to WE low
5
5
setup time
WE high to CE low hold tWHCH
5
5
5
5
5
ns
ns
ns
µs
time
CE high to RE low setuptCHRS
5
time
RE high to CE low hold tRHCH
5
time
Ready to WE low time tRWS
in Sequential read stop
cycle
10
Note: 1. tSRB applies to Sequential read mode only.
Rev.3.00, Jun.09.2004, page 16 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Program/Erase/Rewrite Characteristics
(HN29V128A1A, HN29V128A0A: 2.7 V to 3.6 V,
HN29A128A1A, HN29A128A0A: 1.70 V to 1.95 V,
Ta = 0 to +70 °C)
HN29V128A1A (3.3 V)
HN29V128A0A (3.3 V)
HN29A128A1A (1.8 V)
HN29A128A0A (1.8 V)
Parameter
Rewrite time
Erase time
Symbol Min
Typ
2.2
2.2
1.2
Max
100
100
30
Min
Typ
3.5
3.5
2.0
Max
150
150
45
Unit
ms
Note
tREWRITE
tERS
tPROG
NPPS
ms
Program time
ms
Number of partial
program cycles in the
same sector
4
4
cycles
Number of partial
program cycles in the
same page
NPPP
1
1
cycles
Note: 1. The data transfer time is not included.
Rev.3.00, Jun.09.2004, page 17 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Timing Waveforms
Power on and off
VCC min
VCC
0V
0V
Don't care
Don't care
CE, WE, RE, WP,
CLE, ALE, PRE
tDSE
VIHP
DSE
VILP
VILP
tBSY
tDB
Invalid
R/B
tRMRES
Operation
MRES
Basic timing for command, address and data latch
CLE
ALE
RE
CE
tCEH
tCEH
Setup time
Hold tim
e
WE
tDS
tDH
I/O1 to
I/O8
DIN
I/O9 to
I/O16
(×16)
DIN
VIH or VIL
Rev.3.00, Jun.09.2004, page 18 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Command input cycle
tCLH
tCH
tCLS
CLE
tCS
CE
tWP
WE
tALS
tALH
ALE
tDS
tDH
I/O1 to
I/O8
DIN
I/O9 to
I/O16
(×16)
VIH or VIL
Rev.3.00, Jun.09.2004, page 19 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Command input cycle after data output cycle
CLE
tCLH
tCH
tCLS
tCS
CE
tWP
WE
tALS
tALH
ALE
tRHW, tRHWS
RE
tDS
tDH
I/O1 to
DOUT
I/O8
DIN
I/O9 to
I/O16
(×16)
DOUT
VIH or VIL
Rev.3.00, Jun.09.2004, page 20 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Address input cycle
tCLS
tCS
tCH
CLE
tCS
tWC
tCH
tWP
tWH
tALH
tALH
tALS
ALE
tDS tDH
CA(1)
I/O1 to
I/O8
CA(2)
SA(1)
SA(2)
I/O9 to
I/O16
( 16)
VIH or VIL
Data input cycle
tCS
tCLH
tCS
tCH
CLE
tWC
tCH
tWP
tWH
tALS
ALE
tDS tDH
I/O1 to
I/O8
DIN0
DIN1
DIN1
DIN2
DIN2
DIN M
tDS tDH
I/O9 to
I/O16
( 16)
DIN0
DIN M
VIH or VIL
Rev.3.00, Jun.09.2004, page 21 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Serial read cycle
tCHZ
tCEA
tCEA
CE
RE
tRP
tREH
tOH
tRHZ
I/O1 to
I/O8
DOUT
DOUT
DOUT
tREA
tREA
I/O9 to
I/O16
(×16)
DOUT
DOUT
DOUT
tRR
R/B
tRC
V
IH or VIL
Rev.3.00, Jun.09.2004, page 22 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Invalid input cycle
CE
tWHCH
tCHWS
ALE
CLE
WE
I/O1 to
I/O8
DIN
(Invalid)
I/O9 to
I/O16
(×16)
VIH or VIL
Invalid output cycle
CE
tRHCH
tCHRS
ALE
CLE
RE
I/O1 to
I/O8
I/O9 to
I/O16
(×16)
VIH or VIL
Rev.3.00, Jun.09.2004, page 23 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Status read
This device automatically performs rewriting, programming, erasing, and verification after the operation.
This device provides the status read function to indicate the device status and the execution result. The
device status is output through the I/O pins by issuing command 70H then inputting the RE clock. The
following timing shows the status as the output through the I/O pins.
Status read cycle
tCLS
CLE
tCHZ
tCLS
tCS
tCLH
tCH
tCSTO
CE
tWP
WE
RE
tWHC
tRHZ
tRSTO
tWHR
tOH
Status
tDS
tDH
I/O1 to
I/O8
70H
output
I/O9 to
I/O16
(×16)
00H
VIH or VIL
Pin
Status
Passed or failed
Output
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Passed: 0, failed: 1
Not used. Reserved for future use
Not used. Reserved for future use
Not used. Reserved for future use
Not used. Reserved for future use
Not used. Reserved for future use
Ready or busy
0
0
0
0
0
Ready: 1, busy: 0
Protected: 0, not protected: 1
00H
Write protection
I/O9 to I/O16
Not used
Note: 1. The passed or failed status indicated through the I/O1 is only valid while the device is in the
ready state.
Rev.3.00, Jun.09.2004, page 24 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
ID read
This device holds the ID code which indicates the manufacturer and device information to the application
system. The ID code can be read in the following timing.
ID read cycle
tCLS
CLE
tCLS
tCLH
tCH
tCS
tCH
tCR
tCS
CE
WE
ALE
RE
tALH
tALS
tALH tAR1
tREAID
tREAID
tDS tDH
90H
Manufacturer
code
Device
code
I/O1 to
I/O8
00H
07H
I/O9 to
I/O16
00H
00H
VIH or VIL
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hexadecimal
Manufacturer code
Device code
0
0
0
0
0
1
1
1
07H
I/O (×8) 3.3 V device
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
51H
52H
53H
54H
I/O (×8) 1.8 V device
I/O (×16) 3.3 V device 0
I/O (×16) 1.8 V device 0
Note: 1. Output of I/O9 to I/O16 at manufacturer code and device code is “00H”.
Rev.3.00, Jun.09.2004, page 25 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Read mode
The device enters into the read mode by command 00H. Read command operation is performed per every
page. Start address in the page can be specified in a CA (Column address). The operating timing is shown
below.
CLE
CE
WE
ALE
RE
Busy
R/B
N
Sector address
SA1 SA2
Address input
00H
CA1
CA2
N
N+1
N+2
N+3
I/O
Read mode
command
VIH or VIL
Note : Read mode: When start address N is specified serial read is 512-N cycles in case of ×8 or 256-N cycles in case of ×16.
Rev.3.00, Jun.09.2004, page 26 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Read cycle
CLE
CE
WE
tALH
tALH
tAR2
tRC
tRHZ
ALE
tWB
tALS
RE
tRR
N
Sector address
I/O1 to
I/O8
DOUT
M
DOUT
N+1
DOUT
N+2
DOUT
N
00H CA1 CA2 SA1 SA2
I/O9 to
I/O16
(×16)
DOUT
M
DOUT
N+1
DOUT
N+2
DOUT
N
tR
R/B
Note : M is end of page.
VIH or VIL
Rev.3.00, Jun.09.2004, page 27 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Status read during the read operation
The device status can be read out by inputting the status read command 70H in the read mode. Once the
device has been set to the status read mode by 70H command, the device will not return to the read mode
automatically. However, when the read command 00H is input after ready, the status read mode is reset and
the device returns to the read mode.
Status read during read mode
Ready
00H
Input address
70H
00H
R/B
RE
DOUT
DOUT
DOUT
DOUT
Output data
Status read mode
Normal read mode
Rev.3.00, Jun.09.2004, page 28 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Read stop cycle
Read stop command F0H enables to finish read mode.
Read stop command F0H can be accepted in the busy state.
Read stop
cycle
Standby
mode
Read cycle
CLE
CE
WE
ALE
RE
Read Stop
command
N
Sector address
I/O1 to
I/O8
DOUT DOUT
N+1
DOUT
M
00H CA1 CA2 SA1 SA2
F0H
N
I/O9 to
I/O16
(×16)
DOUT DOUT
N+1
DOUT
M
N
tRSTP
tWB
R/B
VIH or VIL
Note: M is end of page.
Rev.3.00, Jun.09.2004, page 29 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Sequential read mode
The device enters into the sequential read mode by command 0FH. This mode performs continuously
reading through the pages and the sectors without additional command/address inputs. Start address in the
page can be specified in a CA. The operating timing and block diagram are shown below.
CLE
CE
WE
ALE
RE
Busy
R/B
N
Sector address
SA1 SA2
Address input
0FH
CA1
CA2
N
N+1
M
0
1
M
I/O
Sequential
read command
VIH or VIL
Note : M is end of sector.
Column address
N
Start
address
Sector address
End of sector address
(1FFFH)
Stop sequential read
Rev.3.00, Jun.09.2004, page 30 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Sequential read cycle
CLE
CE
WE
tALH
tALH
tAR2
tRC
tRHZ
ALE
tWB
tALS
RE
tRR
N
Sector address
I/O1 to
I/O8
DOUT
M
DOUT
N
DOUT
N+1
0FH CA1 CA2 SA1 SA2
I/O9 to
I/O16
(×16)
DOUT
N
DOUT
N+1
DOUT
M
tR
tR
tSRB
R/B
VIH or VIL
Note : M is end of sector.
Status read during the sequential read operation
The device status can be read out by inputting the status read command 70H in the sequential read mode.
Once the device has been set to the status read mode by 70H command, the device will not return to the
sequential read mode automatically. However, when the read command 00H is input after ready state, the
status read mode is reset and the device returns to the sequential read mode.
Ready
00H
Ready
00H
0FH
Input address
70H
70H
R/B
RE
Output data
DOUT
DOUT DOUT
DOUT
DOUT
DOUT DOUT
DOUT
Status read
mode
Sequential read mode
(Start sector data)
Status read
mode
Sequential read mode
(Next sector data)
Rev.3.00, Jun.09.2004, page 31 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Sequential read stop cycle
Read stop command F0H enables to finish sequential read mode.
After inputting read stop command F0H, the device becomes busy state. And then, the sequential read
mode ends and becomes command waiting state when the status returns to ready.
Stop after reading middle data of sector
Read stop
Sequential read cycle
cycle
tCLH
CLE
tCEHS
tCH
CE
WE
ALE
tRHWS
RE
Sequential
read
Middle of
Read Stop
command
sector
data
N
command
Sector address
DOUT DOUT
N N+1
DOUT
M-x
I/O1 to
I/O8
0FH CA1 CA2 SA1 SA2
F0H
DOUT DOUT
DOUT
M-x
I/O9 to
I/O16
(×16)
N
N+1
tRSTP
tWB
R/B
VIH or VIL
Note: M is end of sector, × ≥ 1
Rev.3.00, Jun.09.2004, page 32 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Stop after reading last data of sector
Read stop
cycle
Sequential read cycle
tCLH
CLE
tCH
CE
tCEHS
WE
ALE
tRHWS
tRWS
RE
Sequential
read
Read Stop
command
N
command
Sector address
End of Sector
I/O1 to
I/O8
DOUT DOUT
N+1
DOUT
M
0FH CA1 CA2 SA1 SA2
F0H
N
I/O9 to
I/O16
(×16)
DOUT DOUT
N+1
DOUT
M
N
tRSTP
tR
tSRB
R/B
Note: M is end of sector
VIH or VIL
Rev.3.00, Jun.09.2004, page 33 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Power on auto read / Auto read
Power on auto read mode enables to read the data of the lowest sector(2k byte) without command and
address data input when power is on.
Auto read mode enables to read the data of the lowest sector (2k byte) without command and address data
input in the normal operation.
Power on auto read and Auto read are activated when power is on.
Power on auto read is available and Auto read operates until power is off when these are activated.
These are activated after PRE high signal right after DSE goes high. (DSE must be low until Power
reaches VCCmin).
MRES going low to high indicates that the data is ready for reading.
The data of the lowest sector (2k byte) can be output by RE clock without command and address input.
After power on read operation, PRE should be kept high.
During the normal operation, keeping PRE low for tPRE makes the device transfer to the auto read mode and
the data of the lowest sector (2k byte) can be output by RE clock without command and address input.
If power on auto read and auto read operation is unnecessary, PRE pin should be connected to VSS or open.
Power on auto read
VCC min
VCC
CLE
CE
WE
ALE
t
DSE
V
IHP
DSE
V
ILP
t
PD
V
IHP
PRE
RE
I/O1 to
I/O8
DOUT
0
DOUT
1
DOUT
2
DOUT
M
I/O9 to
I/O16
(×16)
DOUT
0
DOUT
1
DOUT
2
DOUT
M
t
t
DB
BSY
R/B
t
RMRES
MRES
Note : M ≤ 2047 (
×
8 device)
16 device)
M ≤ 1023 (
×
Rev.3.00, Jun.09.2004, page 34 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Auto read
Case of tPRE < tARBSY
VCC
DSE
CE
VIHP
WE
VIH
ALE
CLE
VIL
VIL
t
PRE
PRE
RE
I/O1 to
I/O8
I/O9 to
I/O16
(×16)
t
WB
DOUT
0
DOUT
1
DOUT
M
DOUT
0
DOUT
1
DOUT
M
t
ARBSY
R/B
t
RMRES
MRES
Note : M ≤ 2047 (
×
8 device)
×16 device)
VIH or VIL
M ≤ 1023 (
Rev.3.00, Jun.09.2004, page 35 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Case of tPRE ≥ tARBSY
VCC
DSE
CE
VIHP
VIH
VIL
VIL
WE
ALE
CLE
t
PRE
PRE
RE
I/O1 to
I/O8
I/O9 to
I/O16
(×16)
t
WB
DOUT
0
DOUT
1
DOUT
M
DOUT
0
DOUT
1
DOUT
M
t
ARBSY
R/B
t
RMRES
MRES
Note : M ≤ 2047 (×8 device)
M ≤ 1023 (×16 device)
VIH or VIL
Note: 1. When PRE is turned low during busy, after the operation performed now is completed, this device
transfer to the auto read mode.
Rev.3.00, Jun.09.2004, page 36 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Auto read (Deep standby mode which transferred by the command)
Case of tPRE < tARBSY
VCC
DSE
CE
VIHP
WE
ALE
CLE
t
PRE
PRE
RE
I/O1 to
I/O8
I/O9 to
I/O16
(×16)
t
WB
DOUT
0
DOUT
1
DOUT
M
DOUT
0
DOUT
1
DOUT
M
t
ARBSY
R/B
t
RMRES
MRES
Note : M ≤ 2047 (
×
8 device)
×16 device)
VIH or VIL
M ≤ 1023 (
Rev.3.00, Jun.09.2004, page 37 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Case of tPRE ≥ tARBSY
VCC
DSE
CE
VIHP
WE
ALE
CLE
t
PRE
PRE
RE
I/O1 to
I/O8
I/O9 to
I/O16
(×16)
t
WB
DOUT
0
DOUT
1
DOUT
M
DOUT
0
DOUT
1
DOUT
M
t
ARBSY
R/B
t
RMRES
MRES
Note : M ≤ 2047 (
×
8 device)
×16 device)
VIH or VIL
M ≤ 1023 (
Rev.3.00, Jun.09.2004, page 38 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Auto read stop cycle
Read stop command F0H enables to finish power on auto read mode and auto read mode.
Read stop Standby
cycle mode
Power on auto read mode
or Auto read mode
CLE
CE
WE
ALE
VIL
RE
Read Stop
command
I/O1 to
I/O8
D
OUT DOUT
DOUT
M
F0H
0
1
I/O9 to
I/O16
(×16)
DOUT DOUT
DOUT
M
0
1
tRSTP
tWB
R/B
VIHP
PRE
Note : M ≤ 2047 (
×
8 device)
×16 device)
VIH or VIL
M ≤ 1023 (
Rev.3.00, Jun.09.2004, page 39 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Program mode
The program mode is organized by the data input and the program. Data input command 80H is for the
input address and the program data. And program command 10H makes the device start the program
(Please refer to the next page). The maximum data size is 2 kbyte (1 kword for ×16 device).
One sector is divided by 4 pages. The size of page is 512byte. Each page is programmable just one time as
well as the normal 2 kbyte programming (Please refer to the figure below).
The data at applied sector for program must be erased.
The data of erased sector is [FF]. The programmed bits in the sector goes “1” to “0”when they are
programmed.
0 to 2047 (
0 to 1023 (
×
8 device)
×16 device)
0
0
511 512
255 256
1023 1024
511 512
1535 1536
767 768
2047
1023
(
×8)
(×16)
Original data pattern
in a sector
FF pattern
FF pattern
FF pattern
FF pattern
Input data1
Data1 Pattern
after program
FF pattern
FF pattern
FF pattern
Data1
Input data2
Data2 Pattern
after program
FF pattern
FF pattern
Data2
Data1
Note: Input only program data. It is not necessary to mask of the previous programmed data.
Rev.3.00, Jun.09.2004, page 40 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Program cycle
CLE
CE
WE
tWB
ALE
RE
tPROG
Output
status
data
CA CA SA SA
(1) (2) (1) (2)
D
D
D
D
D
I/O1 to
I/O8
IN IN
N+1
IN IN
10H
80H
70H
N
M-1 M
Column
address
Sector
address
I/O9 to
I/O16
(×16)
D
D
D
IN
M
IN IN
N+1
IN
M-1
00H
N
R/B
Note : N ≤ M ≤ 2047 (
×
8 device)
VIH or VIL
N ≤ M ≤ 1023 (
×16 device)
Rev.3.00, Jun.09.2004, page 41 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Erase mode
The erase mode is entered by command 60H. After inputting sector address, command D0H erases the
sector data. The erase size is always 2 kbyte and the erase operation must be done in the sector.
Erase cycle
CLE
CE
WE
tERS
ALE
tWB
RE
Status
SA SA
Status
output
read
command
70H
I/O1 to
I/O8
60H
D0H
(1)
(2)
I/O9 to
I/O15
00H
R/B
VIH or VIL
Rev.3.00, Jun.09.2004, page 42 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rewrite mode
The rewrite mode is organized by the data input and the rewrite. Data input command 80H is for the input
address and the rewrite data to be changed. And rewrite command 1FH makes the device start the rewrite
(Please refer to the next page). The maximum data size is 2 kbyte (1 kword in case of ×16 device). By
using rewrite, erase is automatically executed before programming, and the data can be rewritten for the
sector. So the data before the programming operation can be either “1” or “0” (Please refer to the figure
below).
N
M
Pass
DIN
DIN
Data input
80H
CA1
CA2
SA1
SA2
1FH
70H
I/O
I/O
Data input
command
Automatic
Rewriting
command
Status read
command
Address
0 to 2047 (×8 device/sector)
0 to 1023 (×16 device/sector)
Fail
R/B
0 to 2047 (×8 device)
0 to 1023 (×16 device)
0
Original
Data Pattern
N
Input
Data Pattern
Data Pattern
after rewrite
Rev.3.00, Jun.09.2004, page 43 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Rewrite cycle
CLE
CE
WE
tWB
ALE
RE
tREWRITE
Output
status
data
CA CA SA SA
(1) (2) (1) (2)
D
D
D
D
D
I/O1 to
I/O8
IN IN
N+1
IN IN
1FH
80H
70H
N
M-1 M
Column
address
Sector
address
I/O9 to
I/O16
(×16)
D
D
D
IN
M
IN IN
N+1
IN
M-1
00H
N
R/B
Note : N ≤ M ≤ 2047 (
×
8 device)
VIH or VIL
N ≤ M ≤ 1023 (
×
16 device)
Rev.3.00, Jun.09.2004, page 44 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Notes on usage
1. Prohibition of undefined command input
The commands listed in the command definition can only be used in this device. It is prohibited to issue a
command that is not defined in the list. If an undefined command is issued, the data held in the device may
be lost.
2. Limitation of command input in the busy state
In the busy state, following two commands are acceptable. Do not issue any other command except below
two commands.
•
•
Status read 70H
Read stop F0H (during read operation)
3. Commands that can be issued after the serial input command (80H)
After the serial input command (80H) is issued, the rewriting and programming command (1FH, 10H) can
be issued; do not issue any other command except 1FH and 10H after 80H.
4. R/B(Ready/busy) pin handing
R/B is an open-drain output pin, and it should be pulled up to VCC with a resistance(more than 2kΩ).
5. Notes on turning power on and off
The input signal levels may be unstable after power is on or off.
In order to prevent unexpected operation, use DSE as shown below.
VCC min
VCC
0V
0V
Don't care
Don't care
CE, WE, RE, WP,
CLE, ALE, PRE
tDSE
VIHP
DSE
VILP
VILP
tBSY
tDB
Invalid
R/B
tRMRES
Operation
MRES
Rev.3.00, Jun.09.2004, page 45 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
6. Notes on WP signal
When WP is at the low level, the rewriting operation is disabled.
When using WP to control the operation, satisfy the timing shown below.
Operation enable
WE
1st com
2nd com
DIN
WP
R/B
tRW
tWPS
Operation disable
WE
1st com
2nd com
DIN
WP
tWPH
Program
R/B
Erase
Rewrite
80H
tWPS
1st com
2nd com
60H
D0H
80H
10H
1FH
7. Notes on RE signal
If the RE clock is sent before the address is input, the internal read operation may start unintentionally.
Be sure to send the RE clock after the address is input.
Rev.3.00, Jun.09.2004, page 46 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
8. Deep standby mode
During command waiting or standby state, when DSE pin goes to low, the device transfers to deep standby
state.
When DSE goes to high, the device returns from the deep standby state.
During command execution, going DSE low stops command operation. If DSE goes to low during
erase/program/rewrite operation, the command operation is forced to terminate and the applied sector data
is not guaranteed.
Standby state
Deep standby state
t
DBSY
Standby state
DSE
R/B
When CE becomes high after the C0H command input, the state of this device transfers to the deep standby
state.
When CE becomes high after the C1H command input, the state of this device transfers from the deep
standby state to the standby state.
Deep standby
Deep standby
release command
setup command
t
DBSY
Deep standby state
Standby state
Standby state
DIN
C0H
C1H
CE, WE
R/B
Rev.3.00, Jun.09.2004, page 47 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
9. Notes on the power supply down
Please do not turn off a power supply in busy status.
It is recommended to take either of following (1) or (2) measures on system side for unexpected power
down.
(1) Please set DSE=L when detecting the power down.
And erase any sector after the power supply is on.
The other sectors data is protected though applied sector data is invalid by doing this.
VCC
2.4V (3.3V device)
1.6V (1.8V device)
1ms min
DSE
(2) Please store the operation record for back up.
When the power down is recognized to have occurred during erase/program/rewrite operation,
erase applied sector after the power on.
The other sectors data is protected though applied sector data is invalid by doing this.
Rev.3.00, Jun.09.2004, page 48 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Package Dimensions
HN29V128A1ABP, HN29V128A0ABP, HN29A128A1ABP, HN29A128A0ABP Series (TBP-95V)
Unit: mm
B
10.00
0.20 S B
0.80
0.60
12
11
10
9
A
8
7
6
A
5
4
3
INDEX
2
1
M
L
K
J
H G F E D C B A
0.15
4×
0.20 S
95 × φ0.40 0.05
φ0.08
S A B
M
S
S
0.10
Details of the part A
Note: DatumA, B are defined as center line of terminal matrix.
Package CODE
JEDEC
TBP-95V
–
JEITA
–
Mass (reference value)
0.25 g
Rev.3.00, Jun.09.2004, page 49 of 49
Revision History
HN29V128A1A/HN29V128A0A/HN29A128A1A/HN29A128A0A Series Data Sheet
Rev. Date
Contents of Modification
Page Description
0.00 Jun. 10, 2002
0.01 Jun. 10, 2002
Initial issue
18
Correct of page numbers
Change of Timing Waveforms
Sequential read mode, Sequential read cycle,
Stop sequential read cycle
0.02 Sep. 20, 2002
1
Change of Description
2
Change of Features
3
4
Change of Ordering Information
Change of Pin Description
6
Change of Pin Function
8
Change of Address Input
9
9
Change of Mode Selection
Change of Command Definition
Change of Absolute Maximum Ratings
Change of DC Characteristics
Change of AC Characteristics
Change of Program/Erase/Rewrite Characteristics
Timing Waveforms
11
12
13
17
18
Change of Status read cycle
Change of ID read cycle
Change of Read mode
Change of Read cycle
Change of Sequential read mode
Change of Sequential read cycle
Change of Stop sequential read cycle
Change description for Program mode
Change description for Erase mode
Change description for Rewrite mode
Notes on usage
45
Change of description
Change of Notes on WP signal
0.03 Jun. 06, 2003
4
Change format issued by Renesas Technology Corp.
Change of Description
2
Features
Access time: Change of Serial read cycle
Change of Low power dissipation
Deletion of TSOP package (TFP-48DA)
Addition of CSP package (TBP-95V)
Ordering Information
3
Deletion of HN29V128A1AT-50,
HN29V128A0AT-50, HN29A128A1AT-80,
HN29A128A0AT-80
Addition of HN29V128A1ABP-5E,
HN29V128A0ABP-5E, HN29A128A1ABP-8E,
HN29A128A0ABP-8E
Rev. Date
Contents of Modification
Page Description
0.03 Jun. 06, 2003
4
Pin Arrangement
Deletion of 48-pin TSOP
Addition of 95-bump CSP
5
Change of Pin Description
6
Change of Pin Function
8
9
9
10
12
14
Address Input: Addition of notes3
Mode Selection: Addition of notes2, 3
Command Definition: Addition of Read stop
Addition of State transition diagram
Change of DC Characteristics (1), (2)
AC Characteristics
Change of Test Condition
Change of AC Characteristics (1), (2)
Change of Program/Erase/Rewrite Characteristics
Timing Waveforms
17
18
Change of Basic timing for command,
address and data latch
Addition of command input cycle after data
output cycle
Addition of Invalid input cycle, Invalid output
cycle
Change of Status read cycle
Change of ID read cycle
Addition of Read stop cycle
Change of Sequential read stop cycle
Addition of Power on auto read
Change of Auto read (Deep standby mode
which transferred the command)
Change of Auto read
Change of Rewrite cycle
45
Notes on usage
2. Limitation of command input in the busy state:
Change of description
Change of 3. Commands that can be issued
after the serial input command (80H)
4. R/B (Ready/busy) pin handing:
Change of description
Change of 5. Notes on turning power on and off
Change of 6. Notes on WP signal
Change of 8. Deep standby mode
Package Dimensions
Deletion of TFP-48DA
Addition of TBP-95V
49
8
1.00 Jul. 16, 2003
Memory Map and Address
Address Input (×8 device): Deletion of Notes3
Mode Selection: Change of Notes1
AC Characteristics(1)
9
14
Addition of tCEHS
tRHWS min: 200/250 ns to 1/2 µs
AC Characteristics(2): Deletion of tARAS
16
Rev. Date
Contents of Modification
Page Description
2.00 Aug. 26, 2003 18
Timing Waveforms
Change of Timing Waveforms
Change description for
Power on auto read/Auto read
Notes on usage
45
Change of 5. Notes on turning power on and off
AC Characteristics (2): Addition of tSRB
Timing Waveforms
16
18
Change of Sequential read cycle
Sequential read stop cycle
Change of Stop in Busy state
3.00 Jun. 09, 2004
9
Command Definition
Addition of Note:1
AC Characteristics
AC Characteristics (2)
Addtion of tRWS
16
32, 33 Timing Waveforms
Sequential read stop cycle
Change of Sequential read stop cycle
Change of Stop after reading last data of sector
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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