HN58X2402ST [RENESAS]
I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, TSSOP-8;
| 型号： | HN58X2402ST |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, TSSOP-8 内存集成电路 光电二极管 双倍数据速率 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总18页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN58X2402SFPIAG
HN58X2404SFPIAG
Two-wire serial interface
2k EEPROM (256-word × 8-bit)
4k EEPROM (512-word × 8-bit)
REJ03C0133-0400
Rev.4.00
Jul.13.2005
Description
HN58X24xxSFPIAG series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM).
They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory
technology and CMOS process and low voltage circuitry technology. They also have a 8-byte page programming
function to make their write operation faster.
Features
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2CTM serial bus*1)
Clock frequency: 400 kHz
Power dissipation:
Standby: 3 µA (max)
Active (Read): 1 mA (max)
Active (Write): 3 mA (max)
Automatic page write: 8-byte/page
Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V)
Endurance: 105 Cycles (Page write mode)
Data retention: 10 Years
Small size packages: SOP 8-pin
Shipping tape and reel: 2,500 IC/reel
Lead free products.
•
•
•
•
•
•
•
Note: 1. I2C is a trademark of Philips Corporation.
Ordering Information
Type No.
Internal organization
Operating voltage Frequency
1.8 V to 5.5 V 400 kHz
Package
HN58X2402SFPIAGE
2k bit (256 × 8-bit)
150 mil 8-pin plastic SOP
PRSP0008DF-B (FP-8DBV)
Lead free
HN58X2404SFPIAGE
4k bit (512 × 8-bit)
Rev.4.00, Jul.13.2005, page 1 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Pin Arrangement
8-pin SOP
1
2
3
4
A0
A1
8
VCC
WP
7
6
5
A2
SCL
SDA
VSS
(Top view)
Pin Description
Pin name
Function
A0 to A2
SCL
SDA
WP
Device address
Serial clock input
Serial data input/output
Write protect
VCC
Power supply
VSS
Ground
Block Diagram
High voltage generator
Memory array
VCC
VSS
WP
A0, A1, A2
SCL
Control
logic
Y-select & Sense amp.
Serial-parallel converter
SDA
Absolute Maximum Ratings
Parameter
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*1
Storage temperature range
Symbol
VCC
Value
Unit
V
−0.6 to +7.0
−0.5*2 to +7.0*3
−40 to +85
Vin
V
Topr
Tstg
°C
°C
−65 to +125
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
Rev.4.00, Jul.13.2005, page 2 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
DC Operating Conditions
Parameter
Symbol
VCC
Min
1.8
Typ
0
Max
5.5
Unit
V
Supply voltage
VSS
0
0
V
Input high voltage
Input low voltage
VIH
VCC × 0.7
−0.3*1
−40
VCC + 1.0
VCC × 0.3
+85
V
VIL
V
Operating temperature
Topr
°C
Note: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns.
DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Min
Typ
1.0
Max
2.0
20
Unit
Test conditions
Input leakage current
ILI
µA VCC = 5.5 V, Vin = 0 to 5.5 V (SCL, SDA)
µA VCC = 5.5 V, Vin = 0 to 5.5 V (A0 to A2, WP)
µA VCC = 5.5 V, Vout = 0 to 5.5 V
µA Vin = VSS or VCC
mA VCC = 5.5 V, Read at 400 kHz
mA VCC = 5.5 V, Write at 400 kHz
Output leakage current
Standby VCC current
Read VCC current
ILO
ISB
2.0
3.0
1.0
3.0
0.4
ICC1
ICC2
VOL2
Write VCC current
Output low voltage
V
VCC = 4.5 to 5.5 V, IOL = 1.6 mA
V
V
CC = 2.7 to 4.5 V, IOL = 0.8 mA
CC = 1.8 to 2.7 V, IOL = 0.4 mA
VOL1
0.2
V
VCC = 1.8 to 2.7 V, IOL = 0.2 mA
Capacitance (Ta = +25°C, f = 1 MHz)
Test
Parameter
Symbol
Min
Typ
Max
6.0
Unit
pF
conditions
Input capacitance (A0 to A2, SCL, WP)
Output capacitance (SDA)
Cin*1
Vin = 0 V
1
CI/O
*
6.0
pF
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.4.00, Jul.13.2005, page 3 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
VIL = 0.2 × VCC
VIH = 0.8 × VCC
•
•
•
Input rise and fall time: ≤ 20 ns
Input and output timing reference levels: 0.5 × VCC
Output load: TTL Gate + 100 pF
Parameter
Symbol
Min
1200
600
100
1200
600
600
0
Typ
Max
400
Unit
kHz
ns
Notes
Clock frequency
fSCL
tLOW
tHIGH
tI
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
ns
50
900
300
300
10
15
ns
1
tAA
ns
Bus free time for next mode
Start hold time
tBUF
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
ns
Start setup time
ns
Data in hold time
ns
Data in setup time
Input rise time
100
600
50
ns
ns
1
1
Input fall time
tF
ns
Stop setup time
tSU.STO
tDH
ns
Data out hold time
Write protect hold time
Write protect setup time
ns
tHD.WP
tSU.WP
tWC
1200
0
ns
ns
Write cycle time
VCC = 2.7 V to 5.5 V
VCC = 1.8 V to 2.7 V
ms
ms
2
2
tWC
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
Rev.4.00, Jul.13.2005, page 4 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Timing Waveforms
Bus Timing
1/fSCL
tLOW
tR
tF
tHIGH
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
tSU.WP
tHD.WP
WP
Write Cycle Timing
Stop condition
Start condition
SCL
D0 in
SDA
tWC
(Internally controlled)
Write data
(Address (n))
ACK
Rev.4.00, Jul.13.2005, page 5 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.
Serial Input/Output data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-
drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be
completed during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
Data
change
change
Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.
Rev.4.00, Jul.13.2005, page 6 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Device Address (A0, A1, A2)
UP to eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to
different combinations. The levels on these pins are compared with the device address code which are input through
the SDA pin. The device is selected if the compare is successfully done. These pins are internally pulled-down to VSS.
The device read these pins as Low if unconnected. As for 4k, it is unnecessary for the A0 pin to be connected because
the corresponding device address code is used as memory address a8.
Pin Connections for A0 to A2
Pin connection
Memory size
Max connect
number
A2
A1
A0
Notes
1
2k bit
4k bit
8
4
VCC/VSS
*
VCC/VSS VCC/VSS
×*2
VCC/VSS VCC/VSS
Use A0 for memory address a8
Notes: 1. “VCC/VSS” means that the device address pins are connected to VCC or VSS. These pins are VSS if
unconnected.
2. × = Don’t care (Open is also approval.)
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protections feature is enabled and operates as shown in the
following table. When the WP is low, write operations for all memory array are allowed. The read operation is always
activated irrespective of the WP pin status. The WP pin is internally pull-down to VSS. Write operations for all
memory array are allowed if unconnected.
Write Protect Area
Write protect area
WP pin status
2k bit
4k bit
VIH
VIL
Entire (2k bit)
Entire (4k bit)
Normal read/write operation
Rev.4.00, Jul.13.2005, page 7 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start
condition and stop condition)
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read
sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place
the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified
as tWC, the device enters a standby mode. (See write cycle timing)
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Stop condition
Rev.4.00, Jul.13.2005, page 8 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to
acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to
receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to
acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after
receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open.
If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives
acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a
stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus
open without sending read data.
Acknowledge Timing Waveform
1
2
8
9
SCL
SDA IN
Acknowledge
out
SDA OUT
Rev.4.00, Jul.13.2005, page 9 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a
write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit
read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and
this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code in the
order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus.
This means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired
A2-A0 pin status. As for the 4kbit EEPROMs, some bits of their device address code may be used as the memory
address bits. For example, A0 is used as a8 of memory address for the 4kbit. The eighth bit of the device address word
is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is
high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the
zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address
code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
Device address code*1
R/W code*2
R/W
2k
4k
1
1
0
0
1
1
0
0
A2
A2
A1
A1
A0
a8
R/W
Notes: 1. A2 to A0 are device address and a8 are memory address.
2. R/W=“1” is read and R/W = “0” is write.
Rev.4.00, Jul.13.2005, page 10 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, EEPROMs receive 8-bit memory address word. Upon receipt of this memory
address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write
data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The
EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
Device
Memory
address
address (n)
Write data (n)
2k, 4k
Start
1 0 1 0
W
ACK
R/W
ACK
ACK
Stop
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a
single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The
page write is initiated by a start condition, device address word, memory address(n) and write data(Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write
data(Dn+1) instead of receiving a stop condition. The a0 to a2 address bits are automatically incremented upon
receiving write data(Dn+1). The EEPROM can continue to receive write data up to 8 bytes. If the a0 to a2 address bits
reaches the last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and
enters internally-timed write cycle.
Page Write Operation
Device
Memory
address
address (n)
Write data (n)
Write data (n+m)
2k, 4k
Start
W
1 0 1 0
Stop
ACK
ACK
R/W
ACK
ACK
Rev.4.00, Jul.13.2005, page 11 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is
initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start
condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”.
Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and
acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK.
Write Cycle Polling using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
No
No
ACK
returned
Yes
Next operation is
addressing the memory
Yes
Send
Send
Send
memory address
start condition
stop condition
Send
stop condition
Proceed random address
read operation
Proceed write operation
Rev.4.00, Jul.13.2005, page 12 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations are initiated
the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation, with
incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a
start condition and the device address word(R/W is “1”), the EEPROM outputs the 8-bit current address data from the
most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no
acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby
state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current
address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at
previous write operation, the current address will roll over within page addressing and returns to the first address in the
same page. The current address is valid while power is on. The current address after power on will be indefinite. The
random read operation described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Read data (n+1)
ACK No ACK
2k, 4k
Start
Note: 1. Don‘t care bit for 4k.
1 0 1 0
R
Stop
R/W
Rev.4.00, Jul.13.2005, page 13 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read address. The
EEPROM receives a start condition, device address word(R/W=0) and memory address sequentially. The EEPROM
outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start
condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After
receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random
read operation and returns to a standby state.
Random Read Operation
Device
Memory
Device
address
address (n)
address
Read data (n)
ACK No ACK
@@@
# # #
2k, 4k
Start
W
R
1 0 1 0
1 0 1 0
Start
ACK
R/W
Stop
R/W
ACK
Dummy write
Currect address read
Note: 1. 2nd device address code (#) should be same as 1st (@).
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out.
This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and
returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over.
The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following
stop condition.
Sequential Read Operation
Device
address
Read data (n) Read data (n+1) Read data (n+2) Read data (n+m)
2k, 4k
Start
R
1 0 1 0
ACK
ACK
R/W
ACK
ACK
No ACK
Stop
Rev.4.00, Jul.13.2005, page 14 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Notes
Data protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset
function to operate correctly.
•
SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC
on/off may cause the trigger for the unintentional programming.
•
•
V
CC should be turned off after the EEPROM is placed in a standby state.
V
CC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional
programming mode.
•
VCC turn on speed should be longer than 10 µs.
Write/Erase Endurance and Data retention Time
The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1% cumulative
failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be
careful not to allow noise of width more than 50 ns.
Rev.4.00, Jul.13.2005, page 15 of 16
HN58X2402SFPIAG/HN58X2404SFPIAG
Package Dimensions
HN58X2402SFPIAGE / HN58X2404SFPIAGE (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code
P-SOP8-3.9x4.89-1.27
RENESAS Code
PRSP0008DF-B
Previous Code
FP-8DBV
MASS[Typ.]
0.08g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
D
F
8
5
b
p
Dimension in Millimeters
Reference
Symbol
Min
Nom
4.89
3.90
Max
5.15
Index mark
Terminal cross section
( Ni/Pd/Au plating )
D
E
A 2
A 1
A
1
4
0.102
0.35
0.15
0.14
0.40
0.20
0.254
1.73
0.45
*3
e
bp
Z
x
M
b p
b 1
c
L1
0.25
c
1
θ
H E
e
0
°
8°
5.84
6.02
1.27
6.20
x
0.25
0.10
L
y
y
Z
0.69
Detail F
L
0.406
0.60
1.06
0.889
L
1
Rev.4.00, Jul.13.2005, page 16 of 16
Revision History
HN58X2402SFPIAG/HN58X2404SFPIAG
Data Sheet
Rev.
Date
Contents of Modification
Description
Page
1.0
Mar. 30, 2001
Oct. 24, 2003
Initial issue
2.00
Change format issued by Renesas Technology Corp.
Ordering Information
2
Addition of HN58X2402SFPIAGE, HN58X2404SFPIAGE
Package Dimensions
17
2
FP-8DB to FP-8DB, FP-8DBV
3.00
4.00
Dec.14.2004
Jul.13.2005
Ordering Information
Deletion of HN58X2402SFPIAG, HN58X2404SFPIAG
Package Dimensions
17
Deletion of FP-8DB
1
4
Ordering Information
Addition of Renesas package codes
AC Characteristics
Addition of tHD.WP
Addition of tSU.WP
5
Timing Waveforms
Addition of WP
16
Package Dimensions
Addition of Renesas package codes
Changed to Renesas formats
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cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
Renesas Technology Malaysia Sdn. Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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