HN58X24256AFPI [RENESAS]
Two-wire serial interface 256k EEPROM (32-kword 】 8-bit); 两线串行接口256K EEPROM （ 32千字× 8位）
| 型号： | HN58X24256AFPI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Two-wire serial interface 256k EEPROM (32-kword 】 8-bit) |
| 文件： | 总22页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN58X24256A
Two-wire serial interface
256k EEPROM (32-kword × 8-bit)
REJ03C0315-0001
Preliminary
Rev.0.01
Mar.22.2007
Description
HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 64-byte page programming function to make their write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as
cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology’s
sales office before using industrial applications such as automotive systems, embedded controllers,
and meters.
Features
•
•
•
•
Single supply: 1.8 V to 5.5 V
Two-wire serial interface (I2C serial bus)
Clock frequency: 400 kHz
Power dissipation:
Standby: 3 µA (max)
Active (Read): 1 mA (max)
Active (Write): 5 mA (max)
Automatic page write: 64-byte/page
Write cycle time: 5 ms
•
•
•
•
Endurance: 106 Cycles
Data retention: 10 Years
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology’s Sales Dept. regarding specifications.
Rev.0.01, Mar.22.2007, page 1 of 20
HN58X24256A
•
•
Small size packages: SOP-8pin, TSSOP-14pin
Shipping tape and reel
TSSOP 14-pin: 2,000 IC/reel
SOP 8-pin: 2,500 IC/reel
Temperature range: −40 to +85°C
Lead free products.
•
•
Ordering Information
Type No.
Internal
Operating voltage Frequency Package
organization
HN58X24256AFPI
256k bit
(32768 × 8-bit)
1.8 V to 5.5 V
400 kHz
150 mil 8-pin plastic SOP
PRSP0008DF-B
(FP-8DBV)
Lead free
HN58X24256ATI
256k bit
(32768 × 8-bit)
1.8 V to 5.5 V
400 kHz
14-pin plastic TSSOP
PTSP0014JA-C
(TTP-14DBV)
Lead free
Pin Arrangement
8-pin SOP
1
14-pin TSSOP
A0
A1
1
2
3
4
5
6
7
8
VCC
WP
A0
A1
14
13
12
11
10
9
VCC
WP
NC
2
3
4
7
6
5
A2
SCL
SDA
NC
NC
NC
A2
VSS
NC
NC
(Top view)
SCL
SDA
VSS
8
(Top view)
Rev.0.01, Mar.22.2007, page 2 of 20
HN58X24256A
Pin Description
Pin name
A0 to A2
SCL
Function
Device address
Serial clock input
Serial data input/output
Write protect
SDA
WP
VCC
Power supply
Ground
VSS
NC
No connection
Block Diagram
High voltage generator
VCC
VSS
Memory array
WP
A0, A1, A2
SCL
Control
logic
Y-select & Sense amp.
Serial-parallel converter
SDA
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Supply voltage relative to VSS
Input voltage relative to VSS
Operating temperature range*1
Storage temperature range
−0.6 to +7.0
−0.5*2 to +7.0*3
−40 to +85
V
Vin
V
Topr
Tstg
°C
°C
−65 to +125
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): −3.0 V for pulse width ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
Rev.0.01, Mar.22.2007, page 3 of 20
HN58X24256A
DC Operating Conditions
Parameter
Symbol
VCC
Min
Typ
0
Max
Unit
V
Supply voltage
1.8
5.5
VSS
0
0
V
Input high voltage
Input low voltage
VIH
VCC × 0.7
−0.3*1
−40
VCC + 0.5
VCC × 0.3
+85
V
VIL
V
Operating temperature
Topr
°C
Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns.
DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Min
Typ
Max
2.0
2.0
3.0
1.0
5.0
0.4
0.2
Unit
µA
µA
µA
mA
mA
V
Test conditions
Input leakage current
Output leakage current
Standby VCC current
Read VCC current
Write VCC current
Output low voltage
ILI
VCC = 5.5 V, Vin = 0 to 5.5 V
VCC = 5.5 V, Vout = 0 to 5.5 V
Vin = VSS or VCC
ILO
ISB
1.0
ICC1
ICC2
VOL2
VOL1
VCC = 5.5 V, Read at 400 kHz
VCC = 5.5 V, Write at 400 kHz
VCC = 2.7 to 5.5 V, IOL = 3.0 mA
VCC = 1.8 to 2.7 V, IOL = 1.5 mA
V
Capacitance (Ta = +25°C, f = 1 MHz)
Test
Parameter
Input capacitance (A0 to A2, SCL, WP) Cin*1
Output capacitance (SDA)
CI/O*1
Symbol Min
Typ
Max
6.0
Unit
pF
conditions
Vin = 0 V
6.0
pF
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.0.01, Mar.22.2007, page 4 of 20
HN58X24256A
AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V)
Test Conditions
•
Input pules levels:
VIL = 0.2 × VCC
VIH = 0.8 × VCC
•
•
•
Input rise and fall time: ≤ 20 ns
Input and output timing reference levels: 0.5 × VCC
Output load: TTL Gate + 100 pF
Parameter
Symbol Min
Typ
106
Max
400
Unit
kHz
ns
Notes
Clock frequency
fSCL
Clock pulse width low
Clock pulse width high
Noise suppression time
Access time
tLOW
tHIGH
tI
1200
600
ns
50
900
ns
1
tAA
100
1200
600
600
0
ns
Bus free time for next mode
Start hold time
tBUF
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
ns
Start setup time
ns
Data in hold time
Data in setup time
Input rise time
ns
100
ns
300
300
ns
1
1
Input fall time
tF
ns
Stop setup time
tSU.STO
tDH
600
50
ns
Data out hold time
Write protect hold time
Write protect setup time
Write cycle time
ns
tHD.WP
tSU.WP
tWC
1200
0
ns
ns
5
ms
cycles
2
3
Erase/Write Endurance
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
3. This parameter is sampled and not 100% tested (Ta = 25°C).
Rev.0.01, Mar.22.2007, page 5 of 20
HN58X24256A
Timing Waveforms
Bus Timing
1/fSCL
tLOW
tR
tF
tHIGH
SCL
tSU.STA
tHD.DAT
tSU.DAT
tHD.STA
tSU.STO
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
tSU.WP
tHD.WP
WP
Write Cycle Timing
Stop condition
Start condition
SCL
SDA
D0 in
tWC
(Internally controlled)
Write data
(Address (n))
ACK
Rev.0.01, Mar.22.2007, page 6 of 20
HN58X24256A
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is
400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and
the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later,
the SDA transition needs to be completed during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
Data
change
change
Note:
High-to-low and low-to-high change of SDA should be done during the SCL low period.
Rev.0.01, Mar.22.2007, page 7 of 20
HN58X24256A
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to VCC or VSS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated.
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2
A1
A0
Note
256k bit
8
VCC/VSS
VCC/VSS
VCC/VSS
Note: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status.
Write Protect Area
Write protect area
WP pin status
256k bit
VIH
VIL
Upper 1/8 (32k bit)
Normal read/write operation
Rev.0.01, Mar.22.2007, page 8 of 20
HN58X24256A
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation
(See start condition and stop condition).
Stop Condition
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts
after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the
write data inputs and place the device in a internally-timed write cycle to the memories. After the
internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle
timing).
Start Condition and Stop Condition
SCL
SDA
(in)
Start condition
Stop condition
Rev.0.01, Mar.22.2007, page 9 of 20
HN58X24256A
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero
to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter
keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation,
EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM
sends a zero to acknowledge after receiving the device address word. After sending read data, the
EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge,
it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment)
and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM
receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending
read data.
Acknowledge Timing Waveform
1
2
8
9
SCL
SDA IN
Acknowledge
out
SDA OUT
Rev.0.01, Mar.22.2007, page 10 of 20
HN58X24256A
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed
by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device
out of all devices which are connected to the bus. This means that the device is selected if the inputted 3-
bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the
device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read
operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters
the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by
state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond
hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
Device address code
A2 A1
R/W code*1
256k
1
0
1
0
A0
R/W
Note: 1. R/W=“1” is read and R/W = “0” is write.
Rev.0.01, Mar.22.2007, page 11 of 20
HN58X24256A
Write Operations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends
acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2
sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs
acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM
outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle.
The EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
W
1 0 1 0
256k
Start
ACK
R/W
ACK
ACK
Stop
Note: 1. Don't care bit
Rev.0.01, Mar.22.2007, page 12 of 20
HN58X24256A
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for
inputting the more write data. The page write is initiated by a start condition, device address word,
memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop
condition. The a0 to a5 address bits are automatically incremented upon receiving write data (Dn+1). The
EEPROM can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches the last
address of the page, the a0 to a5 address bits will roll over to the first address of the same page and
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving
write data and enters internally-timed write cycle.
Page Write Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Write data (n)
ACK
Write data (n+m)
256k
Start
W
1 0 1 0
ACK
R/W
ACK
ACK
ACK
Stop
Note: 1. Don't care bit
Rev.0.01, Mar.22.2007, page 13 of 20
HN58X24256A
Acknowledge Polling:
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.
This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device
address word following the start condition during a internally-timed write cycle. Acknowledge polling
will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM
is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has
completed. See Write Cycle Polling using ACK.
Write Cycle Polling Using ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
No
No
ACK
returned
Yes
Next operation is
addressing the memory
Yes
Send
Send
Send
memory address
start condition
stop condition
Send
stop condition
Proceed random address
read operation
Proceed write operation
Rev.0.01, Mar.22.2007, page 14 of 20
HN58X24256A
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations
are initiated the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation,
with incremented by one. Current address read accesses the address kept by the internal address counter.
After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit
current address data from the most significant bit following acknowledgment “0”. If the EEPROM
receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops
the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of
the last page at previous read operation, the current address will roll over and returns to zero address. In
case the EEPROM has accessed the last address of the page at previous write operation, the current address
will roll over within page addressing and returns to the first address in the same page. The current address
is valid while power is on. The current address after power on will be indefinite. The random read
operation described below is necessary to define the memory address.
Current Address Read Operation
Device
address
Read data (n+1)
ACK No ACK
256k
Start
1 0 1 0
R
Stop
R/W
Rev.0.01, Mar.22.2007, page 15 of 20
HN58X24256A
Random Read:
This is a read operation with defined read address. A random read requires a dummy write to set read
address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 ×
8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters
a current address read with receiving a start condition. The EEPROM outputs the read data of the address
which was defined in the dummy write operation. After receiving acknowledgment “1”(no
acknowledgment) and a following stop condition, the EEPROM stops the random read operation and
returns to a standby state.
Random Read Operation
Device
address
1st Memory
address (n)
2nd Memory
address (n)
Device
address
Read data (n)
No ACK
@@@
# # #
256k
Start
W
R
1 0 1 0
1 0 1 0
R/W
ACK
ACK
R/W
ACK
Start
ACK
Stop
Dummy write
Currect address read
Notes: 1. Don't care bit
2. 2nd device address code (#) should be same as 1st (@).
Rev.0.01, Mar.22.2007, page 16 of 20
HN58X24256A
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are
coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The
address will roll over and returns address zero if it reaches the last address of the last page. The sequential
read can be continued after roll over. The sequential read is terminated if the EEPROM receives
acknowledgment “1” (no acknowledgment) and a following stop condition.
Sequential Read Operation
Device
address
Read data (n) Read data (n+1) Read data (n+2) Read data (n+m)
R
1 0 1 0
256k
Start
ACK
ACK
R/W
ACK
ACK
No ACK
Stop
Rev.0.01, Mar.22.2007, page 17 of 20
HN58X24256A
Notes
Data Protection at VCC On/Off
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)
may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional
programming, this EEPROM has a power on reset function. Be careful of the notices described below in
order for the power on reset function to operate correctly.
•
SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition
during VCC on/off may cause the trigger for the unintentional programming.
•
•
VCC should be turned off after the EEPROM is placed in a standby state.
V
CC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the
unintentional programming mode.
VCC turn on speed should be longer than 10 µs.
•
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than
50 ns. Be careful not to allow noise of width more than 50 ns.
Rev.0.01, Mar.22.2007, page 18 of 20
HN58X24256A
Package Dimensions
HN58X24256AFPI (PRSP0008DF-B / Previous Code: FP-8DBV)
JEITA Package Code
P-SOP8-3.9x4.89-1.27
RENESAS Code
PRSP0008DF-B
Previous Code
FP-8DBV
MASS[Typ.]
0.08g
*1
D
F
NOTE)
8
5
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
b
p
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
1
4
Min Nom Max
*3
bp
x
e
Z
D
M
4.89 5.15
3.90
E
A2
A1
A
bp
b1
c
L1
0.102 0.14 0.254
1.73
0.35 0.40 0.45
0.15 0.20 0.25
L
c1
θ
HE
e
y
0° 8°
5.84 6.02 6.20
1.27
Detail F
x
0.25
y
Z
0.10
0.69
L
L1
0.406 0.60 0.889
1.06
Rev.0.01, Mar.22.2007, page 19 of 20
HN58X24256A
HN58X24256ATI (PTSP0014JA-C / Previous Code: TTP-14DBV)
JEITA Package Code
RENESAS Code
PTSP0014JA-C
Previous Code
TTP-14DBV
MASS[Typ.]
0.05g
P-TSSOP14-4.4x5-0.65
*1
D
F
14
8
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
1
7
Min Nom Max
*3
bp
Z
D
E
5.00 5.30
4.40
x
M
L 1
e
A2
A1
A
bp
b1
c
0.03 0.07 0.10
1.10
0.15 0.20 0.25
0.10 0.15 0.20
L
c1
θ
0° 8°
6.20 6.40 6.60
y
Detail F
HE
e
x
y
0.65
0.13
0.10
Z
L
L1
0.83
0.40 0.50 0.60
1.00
Rev.0.01, Mar.22.2007, page 20 of 20
Revision History
HN58X24256A Data Sheet
Rev. Date
Contents of Modification
Page Description
Initial issue
0.01 Mar. 22, 2007
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0
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