ICL7660AIBA-T13 [RENESAS]
SWITCHED CAPACITOR CONVERTER;
| 型号： | ICL7660AIBA-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SWITCHED CAPACITOR CONVERTER |
| 文件： | 总13页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL7660S, ICL7660A
Data Sheet
January 23, 2013
FN3179.7
Super Voltage Converters
Features
The ICL7660S and ICL7660A Super Voltage Converters are
monolithic CMOS voltage conversion ICs that guarantee
significant performance advantages over other similar
devices. They are direct replacements for the industry
standard ICL7660 offering an extended operating supply
voltage range up to 12V, with lower supply current. A
Frequency Boost pin has been incorporated to enable the
user to achieve lower output impedance despite using smaller
capacitors. All improvements are highlighted in the “Electrical
Specifications” section on page 3. Critical parameters are
guaranteed over the entire commercial and industrial
temperature ranges.
• Guaranteed Lower Max Supply Current for All
Temperature Ranges
• Wide Operating Voltage Range: 1.5V to 12V
• 100% Tested at 3V
• Boost Pin (Pin 1) for Higher Switching Frequency
• Guaranteed Minimum Power Efficiency of 96%
• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%
• Improved SCR Latchup Protection
• Simple Conversion of +5V Logic Supply to ±5V Supplies
The ICL7660S and ICL7660A perform supply voltage
conversions from positive to negative for an input range of
1.5V to 12V, resulting in complementary output voltages of
-1.5V to -12V. Only two non-critical external capacitors are
needed, for the charge pump and charge reservoir functions.
The ICL7660S and ICL7660A can be connected to function
as a voltage doubler and will generate up to 22.8V with a
12V input. They can also be used as a voltage multipliers or
voltage dividers.
• Simple Voltage Multiplication V
= (-)nV
IN
OUT
• Easy to Use; Requires Only Two External Non-Critical
Passive Components
• Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices
• Pb-Free Available (RoHS Compliant)
Applications
Each chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of
5.0V. This frequency can be lowered by the addition of an
external capacitor to the “OSC” terminal, or the oscillator
may be over-driven by an external clock.
• Simple Conversion of +5V to ±5V Supplies
• Voltage Multiplication V
= ±nV
IN
OUT
• Negative Supplies for Data Acquisition Systems and
Instrumentation
• RS232 Power Supplies
• Supply Splitter, V
OUT
= ±V
S
The “LV” terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.
In some applications, an external Schottky diode from V
OUT
to CAP- is needed to guarantee latchup free operation (see
Do’s and Dont’s section on page 8).
Pin Configurations
ICL7660S
(8 LD PDIP, SOIC)
TOP VIEW
ICL7660A
(8 LD PDIP, SOIC)
TOP VIEW
BOOST
CAP+
GND
1
2
3
4
8
7
6
5
V+
NC
1
2
3
4
8
V+
OSC
LV
CAP+
GND
7
6
5
OSC
LV
CAP-
V
CAP-
V
OUT
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1999, 2004, 2005, 2008, 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ICL7660S, ICL7660A
Ordering Information
PART NUMBER
(NOTE 3)
TEMP. RANGE
(°C)
PART MARKING
7660 SCBA
7660 SCBAZ
PACKAGE
PKG. DWG. #
M8.15
ICL7660SCBA (Note 1)
0 to +70
0 to +70
8 Ld SOIC
ICL7660SCBAZ
(Notes 1, 2)
8 Ld SOIC (Pb-free)
M8.15
ICL7660SCPA
7660S CPA
7660S CPAZ
7660 SIBA
0 to +70
0 to +70
8 Ld PDIP
E8.3
ICL7660SCPAZ (Note 2)
ICL7660SIBA (Note 1)
8 Ld PDIP (Pb-free; Note 4)
8 Ld SOIC
E8.3
-40 to +85
-40 to +85
M8.15
M8.15
ICL7660SIBAZ
(Notes 1, 2)
7660 SIBAZ
8 Ld SOIC (Pb-free)
ICL7660SIPA
7660 SIPA
-40 to +85
-40 to +85
8 Ld PDIP
E8.3
E8.3
ICL7660SIPAZ
(Note 2)
7660S IPAZ
8 Ld PDIP (Pb-free; Note 4)
ICL7660ACBA (Note 1)
7660ACBA
0 to 70
0 to 70
8 Ld SOIC (N)
M8.15
M8.15
ICL7660ACBAZA
(Notes 1, 2)
7660ACBAZ
8 Ld SOIC (N) (Pb-free)
ICL7660ACPA
7660ACPA
7660ACPAZ
7660AIBA
0 to 70
0 to 70
8 Ld PDIP
E8.3
ICL7660ACPAZ (Note 2)
ICL7660AIBA (Note 1)
8 Ld PDIP (Pb-free; Note 4)
8 Ld SOIC (N)
E8.3
-40 to 85
-40 to 85
M8.15
M8.15
ICL7660AIBAZA
(Notes 1, 2)
7660AIBAZ
8 Ld SOIC (N) (Pb-free)
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ICL7660S, ICL7660A. For more information on MSL, please see
Tech Brief TB363.
4. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.
FN3179.7
January 23, 2013
2
ICL7660S, ICL7660A
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V
LV and OSC Input Voltage (Note 5)
V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V
V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ -5.5V to V+ +0.3V
Current into LV (Note 5)
Thermal Resistance (Typical, Notes 6, 7)
θ
(°C/W)
θ
(°C/W)
JA
JC
8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . .
8 Ld Plastic SOIC. . . . . . . . . . . . . . . . .
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
110
160
59
48
V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA
Output Short Duration
*Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in reflow solder
processing applications.
V
≤ 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous
SUPPLY
Operating Conditions
Temperature Range
ICL7660SI, ICL7660AI . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ICL7660SC, ICL7660AC . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S and ICL7660A.
6. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
7. For θ , the “case temp” location is taken at the package top center.
JC
8. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.
Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, T = +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit”
A
on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
= ∞, +25°C
(Note 9)
TYP
(Note 9)
UNITS
µA
Supply Current (Note 11)
I+
R
-
80
-
160
180
180
200
12
L
0°C < T < +70°C
-
-
µA
A
-40°C < T < +85°C
-
µA
A
-55°C < T < +125°C
-
-
µA
A
Supply Voltage Range - High
(Note 12)
V+
R = 10k, LV Open, T
< T < T
MAX
3.0
-
V
H
L
MIN
A
Supply Voltage Range - Low
Output Source Resistance
V+
R = 10k, LV to GND, T
MIN
< T < T
MAX
1.5
-
60
-
3.5
100
120
120
150
250
V
Ω
Ω
Ω
Ω
Ω
L
L
A
R
I
I
I
I
I
= 20mA
-
-
-
-
-
OUT
OUT
OUT
OUT
OUT
OUT
= 20mA, 0°C < T < +70°C
A
= 20mA, -25°C < T < +85°C
-
A
= 20mA, -55°C < T < +125°C
A
-
= 3mA, V+ = 2V, LV = GND,
-
0°C < T < +70°C
A
I
= 3mA, V+ = 2V, LV = GND,
-
-
-
-
300
400
Ω
Ω
OUT
-40°C < T < +85°C
A
I
= 3mA, V+ = 2V, LV = GND,
OUT
-55°C < T < +125°C
A
Oscillator Frequency (Note 10)
Power Efficiency
f
C
C
= 0, Pin 1 Open or GND
= 0, Pin 1 = V+
5
-
10
35
-
-
-
-
-
kHz
kHz
%
OSC
OSC
OSC
P
R = 5kΩ
96
95
99
98
EFF
L
T
< T < T
MAX
R = 5kΩ
L
97
-
MIN
A
Voltage Conversion Efficiency
V
EFF R = ∞
99.9
%
OUT
L
FN3179.7
January 23, 2013
3
ICL7660S, ICL7660A
Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, T = +25°C, OSC = Free running (see Figure 12, “ICL7660S Test Circuit”
A
on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7), unless otherwise specified. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
1
(Note 9)
UNITS
MΩ
Oscillator Impedance
Z
V+ = 2V
V+ = 5V
-
-
-
-
OSC
100
kΩ
ICL7660A, V+ = 3V, T = 25°C, OSC = Free running, Test Circuit Figure 13, unless otherwise specified
A
Supply Current (Note 13)
Output Source Resistance
Oscillator Frequency (Note 13)
NOTES:
I+
V+ = 3V, R = ∞, +25°C
-
26
-
100
125
125
150
200
200
-
μA
μA
μA
Ω
L
0°C < T < +70°C
-
-
A
-40°C < T < +85°C
-
A
R
V+ = 3V, I
OUT
= 10mA
-
97
-
OUT
0°C < T < +70°C
-
Ω
A
-40°C < T < +85°C
A
-
-
Ω
f
V+ = 3V (same as 5V conditions)
5.0
3.0
3.0
8
-
kHz
kHz
kHz
OSC
0°C < T < +70°C
-
A
-40°C < T < +85°C
-
-
A
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, on the order of 5pF.
11. The Intersil ICL7660S and ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function
in existing designs that incorporate an external diode with no degradation in overall circuit performance.
12. All significant improvements over the industry standard ICL7660 are highlighted.
13. Derate linearly above 50°C by 5.5mW/°C.
FN3179.7
January 23, 2013
4
ICL7660S, ICL7660A
Functional Block Diagram
V+
8
Q
Q
1
VOLTAGE
LEVEL
TRANSLATOR
OSCILLATOR
AND DIVIDE-BY-
2 COUNTER
OSC
LV
CAP+
GND
2
3
7
6
2
CAP-
Q
4
4
5
INTERNAL SUPPLY
REGULATOR
V
OUT
Q
3
3
SUBSTRATE
LOGIC
NETWORK
3
3
Typical Performance Curves
See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7
12
10
8
250
T
= +125°C
= +25°C
A
200
150
T
A
SUPPLY VOLTAGE RANGE
(NO DIODE REQUIRED)
6
4
T
= -55°C
A
100
50
2
0
0
0
2
4
6
8
10
12
-55
-25
0
25
50
100
125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 1. OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE
FIGURE 2. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
98
350
300
250
96
V+ = 5V
T
= +25°C
A
94
92
90
88
86
84
82
I
= 1mA
OUT
I
= 3mA,
OUT
I
= 20mA,
200
150
100
50
V+ = 2V
OUT
V+ = 5V
I
= 20mA,
OUT
V+ = 5V
I
= 20mA,
OUT
V+ = 12V
80
0
100
1k
OSC FREQUENCY f
10k
50k
-50
-25
0
25
50 75
100
125
TEMPERATURE (°C)
(Hz)
OSC
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE
FIGURE 4. POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSCILLATOR FREQUENCY
FN3179.7
January 23, 2013
5
ICL7660S, ICL7660A
Typical Performance Curves
See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued)
10
9
8
7
6
5
4
3
2
1
0
20
18
16
14
12
10
8
V+ = 5V
= +25°C
T
A
V+ = 10V
V+ = 5V
0
-55
-25
25
50
75
100
125
1
10
100
1k
C
(pF)
OSC
TEMPERATURE (°C)
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSCILLATOR CAPACITANCE
FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A
FUNCTION OF TEMPERATURE
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1
V+ = 5V
T
= +25°C
0
-1
-2
A
-3
-4
-5
V+ = 5V
= +25°C
T
A
0
10
20
30
40
50
60
0
10
20
30
40
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
2
100
90
V+ = 2V
T
= +25°C
A
80
70
60
50
40
30
20
10
0
16
14
12
10
8
1
0
6
-1
-2
V+ = 2V
= +25°C
4
T
A
2
0
0
1.5
3.0
4.5
6.0
7.5
9.0
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT
FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
FN3179.7
January 23, 2013
6
ICL7660S, ICL7660A
Typical Performance Curves
See Figure 12, “ICL7660S Test Circuit” on page 7) and Figure 13 “ICL7660A Test Circuit” on page 7 (Continued)
V+ = 5V
C
= C = 1mF
2
1
T
= +25°C
A
I = 10mA
400
300
200
100
0
C
= C = 10mF
1
2
C
= C = 100mF
2
1
100
1k
10k
100k
OSCILLATOR FREQUENCY (Hz)
FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY
NOTE:
14. These curves include, in the supply current, that current fed directly into the load R from the V+ (see Figure 12). Thus, approximately half the
L
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S and ICL7660A, goes to the negative side
of the load. Ideally, VOUT ∼ 2V , I ∼ 2I , so V x I ∼ V
IN IN
x I .
S
L
S
OUT
L
I
V+
V+
S
(+5V)
1
2
3
4
8
7
6
5
I
V+
S
(+5V)
1
2
3
4
8
I
ICL7660A
L
C
10µF
+
1
I
L
7
6
5
ICL7660S
-
+
C
10µF
1
R
L
R
-
L
-V
OUT
C
OSC
(NOTE)
-V
OUT
-
C
2
+
10µF
-
+
C
10µF
2
NOTE: For large values of C
(>1000pF), the values of C and C
1 2
OSC
should be increased to 100µF.
NOTE: For large values of C
(>1000pF) the values of C and C
1 2
OSC
should be increased to 100μF.
FIGURE 12. ICL7660S TEST CIRCUIT
FIGURE 13. ICL7660A TEST CIRCUIT
FN3179.7
January 23, 2013
7
ICL7660S, ICL7660A
Theoretical Power Efficiency
Detailed Description
Considerations
In theory, a voltage converter can approach 100% efficiency
if certain conditions are met:
The ICL7660S and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of two external capacitors, which may be
inexpensive 10µF polarized electrolytic types. The mode of
operation of the device may best be understood by
considering Figure 14, which shows an idealized negative
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
voltage converter. Capacitor C is charged to a voltage, V+,
1
3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.
for the half cycle, when switches S and S are closed.
1
3
(Note: Switches S and S are open during this half cycle).
2
4
During the second half cycle of operation, switches S and
2
The ICL7660S and ICL7660A approach these conditions for
S are closed, with S and S open, thereby shifting
4
1
3
negative voltage conversion if large values of C and C are
1
2
capacitor C to C such that the voltage on C is exactly V+,
1
2
2
used. ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined as shown in
Equation 1:
assuming ideal switches and no load on C . The ICL7660S
2
and ICL7660A approach this ideal situation more closely
than existing non-mechanical circuits.
8
S
1
2
S
2
1
2
2
2
(EQ. 1)
--
E = C (V – V
)
1
1
2
V
IN
where V and V are the voltages on C during the pump
C
1
2
1
1
3
3
and transfer cycles. If the impedances of C and C are
1
2
relatively high at the pump frequency (see Figure 14)
compared to the value of R , there will be a substantial
C
L
2
difference in the voltages, V and V . Therefore it is not only
S
5
1
2
S
4
3
desirable to make C as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
2
4
V
= -V
IN
OUT
value for C in order to achieve maximum efficiency of
1
operation.
7
Do’s and Don’ts
FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER
1. Do not exceed maximum supply voltages.
In the ICL7660S and ICL7660A, the four switches of
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
Figure 14 are MOS power switches; S is a P-Channel
1
device; and S , S and S are N-Channel devices. The main
+
2
3
4
3. Do not short circuit the output to V supply for supply
difficulty with this approach is that in integrating the switches,
the substrates of S and S must always remain reverse
voltages above 5.5V for extended periods; however,
transient conditions including start-up are okay.
3
4
biased with respect to their sources, but not so much as to
degrade their “ON” resistances. In addition, at circuit start-
4. When using polarized capacitors, the + terminal of C must
1
be connected to pin 2 of the ICL7660S and ICL7660A, and
up, and under output short circuit conditions (V
= V+),
OUT
the + terminal of C must be connected to GND.
2
the output voltage must be sensed and the substrate bias
adjusted accordingly. Failure to accomplish this would result
in high power losses and probable device latch-up.
5. If the voltage supply driving the ICL7660S and ICL7660A
has a large source impedance (25Ω to 30Ω), then a
2.2µF capacitor from pin 8 to ground may be required to
limit the rate of rise of input voltage to less than 2V/µs.
This problem is eliminated in the ICL7660S and ICL7660A by
6. If the input voltage is higher than 5V and it has a rise rate
a logic network that senses the output voltage (V
)
OUT
more than 2V/µs, an external Schottky diode from V
to CAP- is needed to prevent latchup (triggered by
OUT
together with the level translators, and switches the
substrates of S and S to the correct level to maintain
3
4
forward biasing Q4’s body diode) by keeping the output
(pin 5) from going more positive than CAP- (pin 4).
necessary reverse bias.
The voltage regulator portion of the ICL7660S and
ICL7660A is an integral part of the anti-latchup circuitry;
however, its inherent voltage drop can degrade operation at
low voltages. Therefore, to improve low voltage operation,
the “LV” pin should be connected to GND, thus disabling the
regulator. For supply voltages greater than 3.5V, the LV
terminal must be left open to ensure latchup-proof operation
and to prevent device damage.
7. User should ensure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch-up will
occur under these conditions. To provide additional
protection, a 1N914 or similar diode placed in parallel
with C will prevent the device from latching up under
2
these conditions, when the load on V
to pull up V
creates a path
OUT
before the IC is active (anode pin 5,
OUT
cathode pin 3).
FN3179.7
January 23, 2013
8
ICL7660S, ICL7660A
charge the capacitors every cycle. Equation 4 shows a typical
Typical Applications
application where f
= 10kHz and C = C = C = 10µF:
OSC
1
2
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S and ICL7660A for generation of negative supply
voltages. Figure 15 shows typical connections to provide a
negative supply where a positive supply of +1.5V to +12V is
available. Keep in mind that pin 6 (LV) is tied to the supply
negative (GND) for supply voltage below 3.5V.
1
--------------------------------------------------
R
R
≅ 2x23 +
+ 4xESR + ESR
0
C1
C2
3
–6
5 × 10 × 10 × 10
(EQ. 4)
≅ 46 + 20 + 5 × ESR
0
C
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/f
x C term, rendering an
PUMP
1
V+
increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.
1
2
3
4
8
7
6
5
10µF
ICL7660S
ICL7660A
+
-
Output Ripple
R
O
V
OUT
ESR also affects the ripple voltage seen at the output. The
peak-to-peak output ripple voltage is given by Equation 5:
-
V+
+
-
+
V
= -V+
OUT
1
⎛
⎝
⎞
-----------------------------------------
(EQ. 5)
V
≅
+ 2ESR × I
OUT
⎠
10µF
RIPPLE
C2
2 × f
× C
2
PUMP
15A.
15B.
A low ESR capacitor will result in a higher performance
output.
FIGURE 15. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
Paralleling Devices
Any number of ICL7660S and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
The output characteristics of the circuit in Figure 15 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 15B. The voltage source has
capacitor, C , serves all devices, while each device requires
2
its own pump capacitor, C . The resultant output resistance
1
a value of -(V+). The output impedance (R ) is a function of
O
is approximated in Equation 6:
the ON resistance of the internal MOS switches (shown in
Figure 14), the switching frequency, the value of C and C ,
1
2
R
OUT(of ICL7660S)
(EQ. 6)
---------------------------------------------------------
=
OUT
and the ESR (equivalent series resistance) of C and C . A
R
1
2
n(number of devices)
good first order approximation for R is shown in
O
Equation 2:
Cascading Devices
R
≅ 2((R
+ R
+ ESR ) + 2(R
+ R
+ ESR ))
The ICL7660S and ICL7660A may be cascaded as shown to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined as shown in Equation 7:
0
SW1
SW3
C1
SW2
SW4
C1
1
-------------------------------
+ ESR
C2
(EQ. 2)
f
× C
1
PUMP
f
OSC
-------------
f
=
(R
= MOSFET Switch Resistance)
PUMP
SWX
2
(EQ. 7)
V
= –n(V
)
IN
OUT
Combining the four R
Equation 3 that:
terms as R , we see in
SW
SWX
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
1
-------------------------------
+ 4xESR + ESR
C1 C2
R
≅ 2xR
+
(EQ. 3)
0
SW
f
× C
1
PUMP
and ICL7660A R
values.
OUT
Changing the ICL7660S and ICL7660A Oscillator
Frequency
R
, the total switch resistance, is a function of supply
SW
voltage and temperature (see the output source resistance
graphs, Figures 2, 3, and 11), typically 23Ω at +25°C and 5V.
Careful selection of C and C will reduce the remaining
It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods.
1
2
terms, minimizing the output impedance. High value
capacitors will reduce the 1/(f x C ) component, and low
PUMP
ESR capacitors will lower the ESR term. Increasing the
oscillator frequency will reduce the 1/(f x C ) term, but
1
By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3.5 times.
The result is a decrease in the output impedance and ripple.
PUMP
1
may have the side effect of a net increase in output
impedance when C > 10µF and is not long enough to fully
1
FN3179.7
January 23, 2013
9
ICL7660S, ICL7660A
This is of major importance for surface mount applications
Positive Voltage Doubling
where capacitor size and cost are critical. Smaller
capacitors, such as 0.1µF, can be used in conjunction with
the Boost Pin to achieve similar output currents compared to
The ICL7660S and ICL7660A may be employed to achieve
positive voltage doubling using the circuit shown in Figure
18. In this application, the pump inverter switches of the
the device free running with C = C = 10µF or 100µF. (see
1
2
ICL7660S and ICL7660A are used to charge C to a voltage
1
Figure 11).
level of V+ -V , where V+ is the supply voltage and V is the
F
F
forward voltage on C , plus the supply voltage (V+) is
1
Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 16. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10kΩ pull-up
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be one-half of the clock frequency. Output transitions
occur on the positive going edge of the clock.
applied through diode D to capacitor C . The voltage thus
2
2
created on C becomes (2V+) - (2V ) or twice the supply
2
F
voltage minus the combined forward voltage drops of diodes
D and D .
1
2
The source impedance of the output (V
) will depend on
OUT
the output current, but for V+ = 5V and an output current of
10mA, it will be approximately 60Ω.
V+
1
2
3
4
8
7
6
5
V+
V+
D
1
ICL7660S
ICL7660A
1
2
3
4
8
7
6
5
D
V
=
2
OUT
(2V+) - (2V )
1kΩ
CMOS
GATE
F
ICL7660S
ICL7660A
+
+
C
10µF
2
+
-
-
C
1
V
-
OUT
-
+
10µF
NOTE: D AND D CAN BE ANY SUITABLE DIODE.
1
2
FIGURE 18. POSITIVE VOLTAGE DOUBLER
FIGURE 16. EXTERNAL CLOCKING
Combined Negative Voltage Conversion and
Positive Supply Doubling
It is also possible to increase the conversion efficiency of the
ICL7660S and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and
is shown in Figure 17. However, lowering the oscillator
frequency will cause an undesirable increase in the
Figure 19 combines the functions shown in Figure 15 and
Figure 18 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be suitable, for example, for generating +9V and -5V
impedance of the pump (C ) and reservoir (C ) capacitors;
1
2
this is overcome by increasing the values of C and C by
from an existing +5V supply. In this instance, capacitors C
1
2
1
the same factor by which the frequency has been reduced.
For example, the addition of a 100pF capacitor between pin
7 (OSC and V+) will lower the oscillator frequency to 1kHz
from its nominal frequency of 10kHz (a multiple of 10), and
thereby necessitate a corresponding increase in the value of
C and C (from 10µF to 100µF).
and C perform the pump and reservoir functions,
3
respectively, for negative voltage generation, while
capacitors C and C are pump and reservoir, respectively,
2
4
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher, due to the finite impedance of the
common charge pump driver at pin 2 of the device.
1
2
V+
1
2
3
4
8
7
6
5
C
OSC
ICL7660S
ICL7660A
+
-
C
1
V
OUT
-
C
2
+
FIGURE 17. LOWERING OSCILLATOR FREQUENCY
FN3179.7
January 23, 2013
10
ICL7660S, ICL7660A
V+
V+
+
-
50µF
R
L1
V
= -V
IN
1
2
3
4
8
7
6
5
OUT
1
2
3
4
8
7
6
5
-
C
ICL7660S
ICL7660A
3
V+ - V-
D
1
V
=
OUT
+
+
ICL7660S
ICL7660A
2
C
1
+
-
-
50µF
R
L2
D
2
+
-
-
V
= (2V+) -
+
OUT
(V
50µF
) - (V
)
FD1
FD2
C
+
2
V-
C
4
-
D
3
FIGURE 20. SPLITTING A SUPPLY IN HALF
FIGURE 19. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660S and
ICL7660A can be a problem, particularly if the load current
varies substantially. The circuit of Figure 21 can be used to
overcome this by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maintain a nearly constant output voltage. Direct feedback is
inadvisable, since the ICL7660S’s and ICL7660A’s output
does not respond instantaneously to change in input, but
only after the switching delay. The circuit shown supplies
enough delay to accommodate the ICL7660S and
ICL7660A, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and
the values shown provide an output impedance of less than
5Ω to a load of 10mA.
Voltage Splitting
The bidirectional characteristics can also be used to split a
high supply in half, as shown in Figure 20. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 15, +15V can be converted, via +7.5 and
-7.5, to a nominal -15V, although with rather high series
output resistance (∼250Ω).
Other Applications
Further information on the operation and use of the
ICL7660S and ICL7660A may be found in application note
AN051, “Principles and Applications of the ICL7660 CMOS
Voltage Converter”.
50k
+8V
56k
-
+
10µF
+8V
100Ω
50k
-
ICL7611
100k
+
1
2
3
4
8
7
6
5
ICL7660S
ICL7660A
+
ICL8069
100µF
-
V
OUT
-
+
800k
250k
VOLTAGE
ADJUST
100µF
FIGURE 21. REGULATING THE OUTPUT VOLTAGE
FN3179.7
January 23, 2013
11
ICL7660S, ICL7660A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C A B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3179.7
January 23, 2013
12
ICL7660S, ICL7660A
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN3179.7
January 23, 2013
13
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