ICM7243AIPLZ [RENESAS]
8-Character, Microprocessor-Compatible, LED Display Decoder Driver; MQFP44, PDIP40; Temp Range: See Datasheet;
| 型号： | ICM7243AIPLZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-Character, Microprocessor-Compatible, LED Display Decoder Driver; MQFP44, PDIP40; Temp Range: See Datasheet 驱动 光电二极管 接口集成电路 |
| 文件： | 总16页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICM7243
®
Data Sheet
March 4, 2010
FN3162.4
8-Character, Microprocessor-Compatible,
LED Display Decoder Driver
Features
• 14-Segment and 16-Segment Fonts with Decimal Point
The ICM7243 is an 8-character, alphanumeric display driver
and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 14-segment
or 16-segment display. It is primarily intended for use in
microprocessor systems, where it minimizes hardware and
software overhead. Incorporated on-chip are a 64-character
ASClI decoder, 8x6 memory, high power character and
segment drivers, and the multiplex scan circuitry.
• Mask Programmable for Other Font-Sets Up to 64
Characters
• Microprocessor Compatible
• Directly Drives LED Common Cathode Displays
• Cascadable Without Additional Hardware
• Standby Feature Turns Display Off; Puts Chip in Low
Power Mode
6-bit ASCll data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either Sequential
• Sequential Entry or Random Entry of Data Into Display
• Single +5V Operation
(MODE = 1) or Random access mode (MODE = 0). In the
Sequential Access mode the first entry is stored in the
lowest location and displayed in the “left-most” character
position. Each subsequent entry is automatically stored in
the next higher location and displayed to the immediate
“right” of the previous entry. A DISPlay FULL signal is
provided after 8 entries; this signal can be used for
cascading devices together. A CLeaR pin is provided to
clear the memory and reset the location counter. The
Random Access mode allows the processor to select the
memory address and display digit for each input word.
• Character and Segment Drivers, All MUX Scan Circuitry,
8x6 Static Memory and 64-Character ASCll Font
Generator Included On-Chip
• Pb-Free Available (RoHS Compliant)
The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is
provided to avoid display ghosting
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ICM7243BlPL**
ICM7243BlPL
-25 to +85
-25 to +85
-25 to +85
-20 to +85
40 Ld PDIP
E40.6
ICM7243BlPLZ ** (Note)
ICM7243AIM44Z* (Note)
ICM7243AIPLZ** (Note)
ICM7243BlPLZ
ICM7243 AIM44Z
ICM7243AIPLZ
40 Ld PDIP
44 Ld MQFP
40 Ld PDIP
E40.6
Q44.10x10
E40.6
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICM7243
Pinouts
ICM7243A (16-SEGMENT CHARACTER)
(40 Ld PDIP)
TOP VIEW
V
1
2
3
4
5
6
7
8
9
40 SEG l
DD
SEG m
SEG e
39 SEG g2
38 SEG b
37 SEG i
SEG g1
SEG k
36 SEG f
SEG c
35 SEG d2
34 D.P.
SEG d1
SEG a1
SEG a2
33 SEG h
32 SEG j
D0 10
D1 11
31 MODE
30 A0/SEN
29 A1/CLR
28 A2/DISP FULL
27 OSC/OFF
26 CHAR 1
25 CHAR 2
24 CHAR 3
23 CHAR 4
D2 12
D3 13
D4 14
D5 15
CS 16
WR 17
CHAR 8 18
CHAR 7 19
CHAR 6 20
22
V
SS
21 CHAR 5
FN3162.4
March 4, 2010
2
ICM7243
Pinouts (Continued)
ICM7243B (14-SEGMENT CHARACTER)
(40 Ld PDIP)
TOP VIEW
V
1
2
3
4
5
6
7
8
9
40 SEG m
39 SEG l
DD
SEG e
SEG g1
SEG k
SEG c
SEG d
SEG a
D0
38 SEG g2
37 SEG b
36 SEG i
35 SEG f
34 D.P.
33 SEG h
32 SEG j
D1
D2 10
D3 11
31 MODE
30 A0/SEN
29 A1/CLR
28 A2/DISP FULL
27 OSC/OFF
26 CHAR 1
25 CHAR 2
24 CHAR 3
23 CHAR 4
D4 12
D5 13
CS 14
CS 15
CS 16
WR 17
CHAR 8 18
CHAR 7 19
CHAR 6 20
22
V
SS
21 CHAR 5
ICM7243A (16-SEGMENT CHARACTER)
(44 Ld MQFP)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
SEG d1
SEG a1
SEG a2
D0
SEG d2
DP
1
33
32
31
30
29
2
3
4
5
6
7
8
9
SEG h
SEG j
MODE
D1
D2
A0/SEN
A1/CLR
A2/DISP FULL
OSC/OFF
CHAR1
28
27
26
25
24
23
D3
D4
D5
10
11
CS
NC
NC
12 13 14 15 16 17 18 19 20 21 22
FN3162.4
March 4, 2010
3
ICM7243
Functional Block Diagram
17
(Note)
8 x 6
DATA
MEMORY
Q
D1
SEGMENT
OUTPUTS
SEG x
64 x 17
ROM
(NOTE 1)
6
DATA INPUT
D0 - D5
DATA
LATCHES
SEGMENT
DRIVERS
D0
D
CLR
CL
CL
ADR
ONE
SHOT
8
WR
CS
CS
CS
(Note)
CHAR N
CHARACTER
OUTPUTS
CL
8
8
MODE
D
CHARACTER
DRIVERS
3
SEL
SEL
CL
A0/SEN
D
ADDRESS
LATCHES
A1/CLR
MUX
CL
ADDRESS
CL
D
Q
EN
MULITPLEXER
SEQUENTIAL
ADDRESS
COUNTER
CONTROL
LATCH
AND
3
3
DECODER
CLR
A2/DISP FULL
OVERFLOW
CHARACTER
MULTIPLEX
COUNTER
MULTIPLEX
OSCILLATOR
OSC/OFF
INTER-CHARACTER BLANKING
NOTE: ICM7243A has only one CS and no CS.
ICM7243B has 15 Segments.
FN3162.4
March 4, 2010
4
ICM7243
Absolute Maximum Ratings
Thermal Information
Supply Voltage V
Input Voltage (Any Terminal) . . . . . . . . . . V
CHARacter Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
SEGment Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
- V . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
SS
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . .
MQFP Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
q
(°C/W)
50
70
q
(°C/W)
N/A
N/A
DD
JA
JC
+ 0.3V to V - 0.3V
DD
SS
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
PARAMETER
V
= 5V, V = 0V, T = +25°C, Unless Otherwise Specified.
DD SS A
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Voltage (V
- V ), V
SS
4.75
5.0
5.25
-
V
mA
µA
V
DD
SUPP
Operating Supply Current, I
V
V
= 5.25V, 10 Segments ON, All 8 Characters
-
180
DD
Quiescent Supply Current, I
SUPP
= 5.25V, OSC/OFF Pin < 0.5V, CS = V
SS
-
2
30
250
-
STBY
SUPP
Input High Voltage, V
-
IH
Input Low Voltage, V
-
-
-
0.8
+10
-
V
IL
Input Current, I
-10
140
-
µA
mA
µA
mA
µA
V
IN
CHARacter Drive Current, I
V
V
= 5V, V
= 5V, V
= 1V
190
-
CHAR
CHARacter Leakage Current, I
SUPP
SUPP
OUT
OUT
100
-
CHLK
SEGment Drive Current, I
= 2.5V
14
-
19
0.01
-
SEG
SEGment Leakage Current, I
DISPlay FULL Output Low, V
10
0.4
-
SLK
OL
I
= 1.6mA
-
OL
= 100µA
IH
DISPlay FULL Output High, V
l
2.4
-
-
V
OH
Display Scan Rate, f
400
-
Hz
DS
Electrical Specifications Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. V = 5V, T = +25°C,
DD
A
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS
WR, CLeaR Pulse Width Low, t
300
-
250
250
-100
150
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WPI
WR, CLeaR Pulse Width High (Note 1), t
-
WPH
Data Hold Time, t
DH
0
-
Data Setup Time, t
DS
250
125
40
0
-
Address Hold Time, t
-
AH
Address Setup Time, t
15
-
AS
CS, CS Setup Time, t
-
-
CS
Pulse Transition Time, t
-
-
100
T
SEN Setup Time, t
0
-25
480
-
-
SEN
Display Full Delay, t
700
WDF
FN3162.4
March 4, 2010
5
ICM7243
Capacitance
PARAMETER
Input Capacitance, C
TEST CONDITIONS
MIN
TYP
5
MAX
UNITS
pF
(Note 3)
(Note 3)
-
-
-
-
lN
Output Capacitance, C
5
pF
O
NOTES:
2. In Sequential mode WR high must be ≥ t
+t
.
SEN WDF
3. For design reference only, not tested.
Timing Waveforms
CS
t
CS
CS
t
AH
t
AS
ADDRESS
VALID
t
WC
t
t
WHP
WPI
WRITE
t
t
DS
T
t
t
DH
T
DATA
VALID
FIGURE 1. RANDOM ACCESS TIMING
CHAR
1
CHAR
2
CHAR
8
WR
t
t
WPH
SEN
CLEAR
SEN
t
WDF
DISPLAY FULL
FIGURE 2. SEQUENTIAL ACCESS MODE TIMING (MODE = 1)
FN3162.4
March 4, 2010
6
ICM7243
Timing Waveforms (Continued)
~300µs
~5µs
INTERNAL
INTER-CHARACTER
BLANKING
SIGNAL
CHAR 1
CHAR 2
CHAR 3
CHAR 4
CHARACTERS
DRIVE
SIGNALS
CHAR 5
CHAR 6
CHAR 7
CHAR 8
INTER-CHARACTER BLANKING
FIGURE 3. DISPLAY CHARACTERS MULTIPLEX TIMING DIAGRAM
Performance Curves
30
500
V
= 5.5V
DD
V
= 5.5V
DD
20
400
300
5.0V
5.0V
10
200
100
4.5V
4.5V
2
0
0
1
3
0
1
2
3
SEGMENT VOLTAGE (V)
SEGMENT VOLTAGE (V)
FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE
FIGURE 5. CHARACTER CURRENT vs OUPUT VOLTAGE
FN3162.4
March 4, 2010
7
ICM7243
Pin Descriptions
PIN NUMBER
ICM7243B ICM7243A
SYMBOL 40 Ld PDIP 40 Ld PDIP 44 Ld MQFP
DESCRIPTION
V
1
1
10 to 15
16
39
4 to 9
10
-
DD
D0 to D5
CS, CS
WR
8 to 13
15, 16
17
Six-Bit ASCll Data input pins (active high).
Chip Select from µP address decoder, etc.
17
13
WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR
can be used as CS.
MODE
31
31
29
Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is
displayed in “leftmost” character and subsequent entries appear to the “right”. Low selects
the Random Access (RA) mode where data is displayed on the character addressed via
A0 - A2 Address pins.
A0/SEN
30
29
28
27
30
29
28
27
28
27
26
25
In RA mode it is the LSB of the character Address. In SA mode it is used for cascading
devices for displays of more than 8 characters (active high enables device controller).
A1/CLeaR
In RA mode this is the second bit of the address. In SA mode, a low input will CLeaR the
Serial Address Counter, the Data Memory and the display.
A2/DISPlay
FULL
In RA mode this is the MSB of the Address. In SA mode, the output goes high after eight
entries, indicating DISPlay FULL.
OSC/OFF
OSCillator input pin. Adding capacitance to V
will lower the internal oscillator frequency.
DD
An external oscillator can be applied to this pin. A low at this input sets the device into a
(shutdown) mode, shutting OFF the display and oscillator but retaining data stored in
memory.
SEGa -
SEGm
2 to 7,
32, 33,
35 to 40
2 to 9,
32, 33,
35 to 40
1 to 3, 30,
31, 33 to 40,
38 to 44
SEGment driver outputs.
D.P.
34
34
32
CHARacter 23 to 26,
23 to 26, 24, 19 to 21, CHARacter driver outputs.
1 to 8
18 to 21
18 to 21
14 to 17
V
22
22
18
SS
NC
N/A
N/A
22, 23, 11 No Connect
FN3162.4
March 4, 2010
8
ICM7243
Test Circuit
17 SEGMENTS
CHAR 8 CHAR 7 CHAR 6 CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1
SEG l
V
1
2
40
DD
SEG m
SEG e
SEG g1
SEG k
SEG c
SEG d1
SEG a1
SEG a2
D0
SEG g2
39
SEG b
3
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
8 CHARACTERS
SEG i
SEG f
SEG d2
DP
4
SEGMENTS
5
SEGMENTS
6
7
SEG h
SEG j
8
9
MODE (SA/RA)
A0/SEN
10
V
ICM7243A
DD
V
DD
D1
11
12
13
14
15
16
17
18
19
20
D2
A1/CLR
DISPLAY
FULL
OUTPUT
D3
A2/DISP FULL
D4
OSC/OFF
CHAR 1
V
D5
DD
NC (FOR SA MODE)
CS
CHAR 2
CHAR 3
CHAR 4
WR
CHAR 8
CHAR 7
CHAR 6
V
SS
CHAR 5
FIGURE 6.
FN3162.4
March 4, 2010
9
ICM7243
Typical Applications
8 CHARACTERS
8 CHARACTERS
+5V
CHAR
SEG
CHAR
SEG
RRI
RBR8
RBR7
CLR
CS
CLR
CS
ICM7243B
ICM7243B
DISP
FULL
DISP
FULL
SEN
CS,WR
SEN
IM6403
UART
ETC.
CS,WR
D0 - D5
CS
D0 - D5
CS
RBR1 - RBR6
DR
6 BIT BUS
+5V
DRR
OUT
+5V
+5V
D0 - D5
CS
WR
D0 - D5
CS
WR
20K
CS
CS
+
V
SEN
CS
SEN
CS
ETC.
ICM7243B
ICM7243B
TR
DISP
FULL
DISP
FULL
ICL7555
DELAY
CLR
CLR
CHAR
CHAR
SEG
SEG
TH
200pF
8 CHARACTERS
8 CHARACTERS
FIGURE 7. DRIVING TWO ROWS OF CHARACTERS FROM A SERIAL INPUT
FN3162.4
March 4, 2010
10
ICM7243
Typical Applications (Continued)
8-CHARACTER LED DISPLAY
8-CHARACTER LED DISPLAY
8-CHARACTER LED DISPLAY
8
8
8
(Note)
(Note)
(Note)
CLR
CLR
CLR
CLR
CHAR
SEG
CHAR
CHAR
SEG
SEG
+5V
+5V
SEN
DISP FULL
DISP FULL
DISP FULL
SEN
SEN
MODE
WR
+5V
+5V
MODE
WR
+5V
+5V
MODE
WR
+5V
V
V
V
DD
DD
DD
V
V
V
D0 - D5
D0 - D5
D0 - D5
SS
SS
SS
CS
CS
CS
DATA
BUS
6
6
6
WR,
(CS)
CS,
(WR)
FIRST 8 CHARACTERS
SECOND 8 CHARACTERS
NTH 8 CHARACTERS
NOTE: 17 for ICM7243A, 15 for ICM7243B.
FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE
+5V
+5V
+5V
+5V
+5V
1k
1.4A
PEAK
2N6034
100Ω
100Ω
1mA
2N2219
SEG
SEG
300Ω
1k
ICM7243
ICM7243
14Ω (100mA
)
PEAK
25Ω
R
= 4Ω
ON
(100mA
)
PEAK
CHAR
GND
2N2219
CHAR
14mA
R
= 4Ω
2N6034
1.4A
ON
1k
PEAK
GND
GND
GND
GND
FIGURE 9A. COMMON CATHODE DISPLAY
FIGURE 9B. COMMON ANODE DISPLAY
FIGURE 9. DRIVING LARGE DISPLAYS
FN3162.4
March 4, 2010
11
ICM7243
Typical Applications (Continued)
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
8 CHARACTERS
ICM7243A/B
ICM7243A/B
ICM7243A/B
ICM7243A/B
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
CS A2 A1 A0 D0 - D5 WR
P22
P21
P20
80C35
80C48
DB7
DB6
6 BIT BUS
DB5 - DB0
WR
FIGURE 10. RANDOM ACCESS 32-CHARACTER DISPLAY IN A 80C48 SYSTEM
Display Font and Segment Assignments
a1
a2
j
f
h
g1
m
i
l
b
c
g2
k
e
d2
d1
DP
0
0
1
1
0
1
0
1
D5, D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
0
FIGURE 11. ICM7243A 16-SEGMENT CHARACTER FONT WITH DECIMAL POINT
FN3162.4
March 4, 2010
12
ICM7243
Display Font and Segment Assignments (Continued)
h
a
i
j
f
b
c
g1
m
g2
k
e
l
d
DP
0
0
1
1
0
1
0
1
D5, D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
0
NOTE: Segments a and d appear as 2 segments each, but both halves are driven together.
FIGURE 12. ICM7243B 14-SEGMENT CHARACTER FONT WITH DECIMAL POINT
V
DD
SEGMENT
DRIVER
V
R
= 1.6V
LED
= 100µ
TYPICAL
R
SEG x
DISPLAY
CHARACTER
DRIVER
CHAR N
SEGMENT LEDs
R
DS(ON) ~ 4ÞΩ
V
SS
FIGURE 13. SEGMENT AND CHARACTER DRIVERS OUTPUT CIRCUIT
FN3162.4
March 4, 2010
13
ICM7243
Data Entry
Detailed Description
The input Data is latched on the rising edge of WR (or its
equivalent) and then stored in the Data Memory location
determined as described above. The six Data bits can be
multiplexed with the Address information on the same lines
in Random Access mode. Timing is controlled by the WR
input.
WR, CS, CS
These pins are immediately functionally ANDed, so all
actions described as occurring on an edge of WR, with CS
and CS enabled, will occur on the equivalent (last) enabling
or (first) disabling edge of any of these inputs. The delays
from CS pins are slightly (about 5ns) greater than from WR
or CS due to the additional inverter required on the former.
OSC/OFF
The device includes a relaxation oscillator with an internal
capacitor and a nominal frequency of 200kHz. By adding
MODE
The MODE pin input is latched on the falling edge of WR
(or its equivalent, see above). The location (in Data
Memory) where incoming data will be placed is determined
either from the Address pins or the Sequential Address
Counter. This is controlled by MODE input. MODE also
controls the function of A0/SEN, A1/CLR, and A2/DlSPlay
FULL lines.
external capacitance to V
at the OSC/OFF pin, this
DD
frequency can be reduced as far as desired. Alternatively,
an external signal can be injected on this pin. The oscillator
(or external) frequency is pre-divided by 64, and then
further divided by 8 in the Multiplex Counter, to drive the
CHARacter drive lines (see Figure 3). An inter-character
blanking signal is derived from the pre-divider. An
additional comparator on the OSC/OFF input detects a
level lower than the relaxation oscillator's range, and
blanks the display, disables the DISPlay FULL output (if
active), and clears the pre-divider and Multiplex Counter.
This puts the circuit in a low-power-dissipation mode in
which all outputs are effectively open circuits, except for
parasitic diodes to the supply lines. Thus a display
connected to the output may be driven by another circuit
(including another ICM7243) without driver conflicts.
Random Access Mode
When the internal mode latch is set for Random Access
(RA) (MODE latched low), the Address input on A0, A1 and
A2 will be latched by the falling edge of WR (or its
equivalent). Subsequent changes on the Address lines will
not affect device operation. This allows use of a
multiplexed 6-bit bus controlling both address and data,
with timing controlled by WR.
Sequential Access Mode
Display Output
If the internal latch is set for Sequential Access (SA),
(MODE latched high), the Serial ENable input or SEN will
be latched on the falling edge of WR (or its equivalent). The
CLR input is asynchronous, and will force-clear the
Sequential Address Counter to address 000 (CHARacter
1), and set all Data Memory contents to 100000 (blank) at
any time. The DISPlay FULL output will be active in SA
mode to indicate the overflow status of the Sequential
Address Counter. If this output is low, and SEN is (latched)
high, the contents of the Counter will be used to establish
the Data Memory location for the Data input. The Counter
is then incremented on the rising edge of WR. If SEN is
low, or DISPlay FULL is high, no action will occur. This
allows easy “daisy-chaining” of display drivers for multiple
character displays in a Sequential Access mode.
The output of the Multiplex Counter is decoded and
multiplexed into the address input of the Data Memory,
except during WR operations (in Sequential Access mode,
with SEN high and DISPlay FULL low), when it scans
through the display data. The address decoder also drives
the CHARacter outputs, except during the inter-character
blanking interval (nominally about 5μs). Each CHARacter
output lasts nominally about 300μs, and is repeated
nominally every 2.5ms, i.e., at a 400Hz rate (times are
based on internal oscillator without external capacitor).
The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and
SEGment outputs are disabled during WR operations (with
SEN high and DISPlay FULL Low for Sequential Access
mode). The outputs may also be disabled by pulling
OSC/OFF low.
Changing Modes
Care must be exercised in any application involving
changing from one mode to another. The change will occur
only on a falling edge of WR (or its equivalent). When
changing mode from Sequential Access to Random
Access, note that A2/DlSPlay FULL will be an output until
WR has fallen low, and an Address drive here could cause
a conflict. When changing from Random Access to
Sequential Access, A1/CLR should be high to avoid
inadvertent clearing of the Data Memory and Sequential
Address Counter. DISPlay FULL will become active
immediately after the rising edge of WR.
The decode pattern from 6 bits to 17 (15) segments is done
by a ROM pattern according to the ASCll font shown.
Custom decode patterns can be arranged, within these
limitations, by consultation with the factory.
FN3162.4
March 4, 2010
14
ICM7243
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
N
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1
2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.980
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
2.095
-
4.95
0.558
1.77
0.381
53.2
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
50.3
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
E1
e
5
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
40
40
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
perpendicular to datum
7. e and e are measured at the lead tips with the leads
are measured with the leads constrained to be
A
-C-
.
B
C
unconstrained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN3162.4
March 4, 2010
15
ICM7243
Metric Plastic Quad Flatpack Packages (MQFP)
D
Q44.10x10 (JEDEC MS-022AB ISSUE B)
D1
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
-D-
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
-
MAX
2.45
NOTES
A
A1
A2
b
-
0.096
0.010
0.083
0.018
0.016
0.524
0.399
0.523
0.398
0.040
-
0.004
0.077
0.012
0.012
0.515
0.389
0.516
0.390
0.029
0.10
1.95
0.30
0.30
13.08
9.88
13.10
9.90
0.73
0.25
-
-A-
-B-
2.10
-
0.45
6
E
E1
b1
D
0.40
-
13.32
10.12
13.30
10.10
1.03
3
D1
E
4, 5
3
e
E1
L
4, 5
-
PIN 1
N
44
0.032 BSC
44
0.80 BSC
7
e
-
SEATING
PLANE
-H-
A
Rev. 2 4/99
NOTES:
0.076
0.003
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
o
o
-C-
12 -16
0.40
0.016
o
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.20
0.008
MIN
M
C
A-B S D S
0
MIN
b
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
A2
A1
o
o
b1
0 -7
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.13/0.17
0.005/0.007
o
o
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
12 -16
L
BASE METAL
7. “N” is the number of terminal positions.
WITH PLATING
0.13/0.23
0.005/0.009
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3162.4
March 4, 2010
16
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明