IPS2200BI1R [RENESAS]
Inductive Position Sensor IC;
| 型号： | IPS2200BI1R |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Inductive Position Sensor IC |
| 文件： | 总35页 (文件大小：1855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
IPS2200
Inductive Position Sensor IC
Description
Features
The IPS2200 is a magnet-free, inductive position
sensor ICs that can be used for high-speed absolute
position sensing in industrial, medical, and consumer
applications. The IPS2200 uses the physical principle
of eddy currents to detect the position of a simple
metallic target that is moving above a set of coils,
consisting of one transmitter coil and two receiver coils.
Position sensing based on an inductive principle
Cost effective; no magnet required
Immune to magnetic stray fields; no shielding
required
Suitable for harsh environments and extreme
temperatures
Differential and single-ended sine and cosine outputs
Digital incremental outputs: 4 counts per period
The three coils are typically printed as copper traces on
a printed circuit board (PCB). They are arranged such
that the transmitter coil induces a secondary voltage in
the two receiver coils, which depends on the position of
the metallic target above the coils.
Nonvolatile user-configurable memory,
programmable via I2C or SPI interface
Single IC supports on-axis and off-axis rotation,
linear motion, and arc motion sensing
A signal representative of the target’s position over the
coils is obtained by demodulating and processing the
secondary voltages from the receiver coils. The target
can be any kind of metal, such as aluminum, steel, or a
PCB with a printed copper layer.
Adaptable to any full-scale angle range
High accuracy: ≤ 0.2% full scale
Rotation sensing up to 360º angle range
±18V over-voltage and reverse-polarity protection on
output pins
The IPS2200 provides two independent interfaces:
A high-speed analog or digital interface providing
position information in the form of demodulated
analog sine/cosine raw data or digital incremental
outputs
Fast diagnostic alarm through interrupt pin
Wide operation temperature: -40°C up to +125°C
Supply voltage programmable for 3.0V to 3.6V or
An I2C or SPI digital interface for diagnostics and
4.5V to 5.5V
programming
Small 16-TSSOP package (4.4 5.0 mm body)
The IPS2200 operates at rotation speeds up to 250000
RPM (with coil designs using 1 period per turn). An
ultra-low propagation delay down to 10µs or less
provides high dynamic control for fast-moving objects.
Available Support
Renesas provides application modules that
demonstrate IPS2200 position sensing, including
rotary, arc, and linear applications.
The IPS2200 is available in a TSSOP package and is
qualified for industrial use at -40°C to +125°C ambient
temperature.
Application Circuit Example
Typical Applications
1
2
16
15
CSN_IRQN
RX1
SIO_SDA
SCK_SCL
Rotor position detection for brushless DC motors;
adaptable to any pole pair count
Rx
(sin)
3
4
RX2
RX3
14
13
12
11
SIN
SINN
COS
Replacement of brushless resolvers
Magnet-free rotor speed sensors
Rx
(cos)
5
6
RX4
TX1
COSN
3.3V / 5V
CVD
Tx
CT
10
9
7
8
VDD
GND
TX2
VDDA
CVA
Jan.19.21
Page 1
Datasheet
IPS2200
Inductive Position Sensor IC
Contents
1. Pin Assignments............................................................................................................................................ 5
2. Pin Descriptions ............................................................................................................................................ 5
3. Absolute Maximum Ratings.......................................................................................................................... 7
4. Operating Conditions.................................................................................................................................... 7
5. Ambient Temperature Range........................................................................................................................ 8
6. Electrical Characteristics.............................................................................................................................. 9
7. Circuit Description....................................................................................................................................... 14
7.1 Overview.............................................................................................................................................. 14
8. Sampling Rate, Resolution, Output Data Rate, and Propagation Delay ................................................ 17
9. Output Modes............................................................................................................................................... 18
9.1 Analog Differential Sine-Cosine Analog Output Mode ........................................................................ 18
9.2 Analog Single Ended Sine-Cosine Analog Output Mode .................................................................... 19
9.3 Digital Incremental Differential AB Mode............................................................................................. 19
10. Operating at High Speed............................................................................................................................. 20
11. Digital Diagnostics and Programming Interfaces .................................................................................... 21
11.1 Block Diagram ..................................................................................................................................... 21
12. Connection Options .................................................................................................................................... 22
13. Digital Diagnostics and Programming Interfaces .................................................................................... 24
13.1 Supply Voltage Operation: 3.3V or 5V ................................................................................................ 24
13.2 Half-Duplex SPI Interface.................................................................................................................... 24
13.3 I2C Interface ........................................................................................................................................ 25
13.3.1. I2C with Address Selection (Programming Option) .............................................................. 26
13.3.2. I2C Interface with Interrupt (Programming Option)............................................................... 26
14. Protection and Diagnostics ........................................................................................................................ 27
14.1 I/O Protection....................................................................................................................................... 27
15. Programming Options................................................................................................................................. 27
15.1 Lock Feature (Cyber Security)............................................................................................................. 27
16. Diagnostics................................................................................................................................................... 28
16.1 Internal Register and Memory Errors .................................................................................................. 29
16.2 LC Oscillator Frequency Out of Range ............................................................................................... 29
17. Application Examples ................................................................................................................................. 30
18. Electromagnetic Compatibility (EMC) ....................................................................................................... 31
19. Package Outline Drawings.......................................................................................................................... 31
20. Marking Diagram.......................................................................................................................................... 31
20.1 Marking of Production Parts ................................................................................................................ 31
Jan.19.21
Page 2
IPS2200 Datasheet
21. Ordering Information................................................................................................................................... 32
22. Revision History .......................................................................................................................................... 32
Figures
Figure 1. Pin Assignments for 4.4mm 5.0mm 16-TSSOP Package – Top View...................................................5
Figure 2. LC Oscillator Connection with a Single Capacitor...................................................................................10
Figure 3. LC Oscillator Connection with Split TX Capacitors .................................................................................11
Figure 4. Parallel Resonator Circuit........................................................................................................................11
Figure 5. Response of the IPS2200 .......................................................................................................................15
Figure 6. Coil Design for a Linear Motion Sensor...................................................................................................16
Figure 7. Coil Design for a 360° Rotary Sensor .....................................................................................................16
Figure 8. Data Update Rate vs. LC Oscillator Frequency vs. Integration Factor ...................................................18
Figure 9. Sine-Cosine Analog Mode Output Signals..............................................................................................18
Figure 10. Sine-Cosine Analog Mode Output Signals............................................................................................19
Figure 11. Digital Incremental Differential AB Mode Output Signals......................................................................19
Figure 12. Block Diagram .......................................................................................................................................21
Figure 13. Analog Interface with Diagnostics Mode, Fixed Configuration..............................................................22
Figure 14. Analog and Digital Interface, On-The-Fly Gain and Offset Correction, Extended Diagnostics.............23
Figure 15. Analog and Digital Interface, On-The-Fly Gain and Offset Correction, Extended Diagnostics with MCU
Interrupt...................................................................................................................................................................23
Figure 16. Half Duplex 3-3 Wire SPI Interface .......................................................................................................24
Figure 17. Half Duplex 3-3 Wire SPI Multi-slave Interface.....................................................................................25
Figure 18. I2C Interface with Address Select .........................................................................................................26
Figure 19. I2C Interface Configuration with Interrupt on a Single Slave ................................................................26
Figure 20. I2C Interface Configuration with Multi-slave Interrupt ...........................................................................27
Figure 21. Coil Design and Signal Output for a 360° Rotary Sensor .....................................................................30
Figure 22. Coil Design and Signal Output for a 2 180° Rotary Sensor ...............................................................30
Figure 23. Coil Design and Signal Output for a 3 120° Rotary Sensor ...............................................................30
Figure 24. Coil Design and Signal Output for a 4 90° Rotary Sensor .................................................................31
Tables
Table 1. Pin Descriptions..........................................................................................................................................5
Table 2. Buffered Output Configuration....................................................................................................................6
Table 3. Digital Interface and Interrupt Output Configuration...................................................................................6
Table 4. Absolute Maximum Ratings........................................................................................................................7
Table 5. Operating Conditions..................................................................................................................................7
Table 6. IPS2200 Electrical Characteristics, 3.3V Mode..........................................................................................9
Table 7. IPS2200 Electrical Characteristics, 5.0V Mode..........................................................................................9
Table 8. LC Oscillator Specifications......................................................................................................................10
Table 9. Coil Receiver Front-End Specifications....................................................................................................12
Table 10. Diagnostic Checks..................................................................................................................................12
Table 11. Back-End Specification, Analog Outputs SIN, SINN, COS, COSN........................................................12
Table 12. Back-End Specification, Quadrature Pulse Output Option, Pins A, A_N, B, and B_N...........................13
Jan.19.21
Page 3
IPS2200 Datasheet
Table 13. Digital Control Interface, Pins CSN_IRQN, SIO_SDA, SCK_SCL .........................................................13
Table 14. Nonvolatile Memory................................................................................................................................13
Table 15. Electrostatic Discharges (ESD) ..............................................................................................................14
Table 16. Output Data Rate, Propagation Delay....................................................................................................17
Table 17. Output Status in AB Incremental Mode ..................................................................................................19
Table 18. Output Modes and Maximum Speed......................................................................................................20
Table 19. SPI Interface Parameters .......................................................................................................................25
Table 20. I2C Interface Parameters .......................................................................................................................25
Table 21. Programming Options Overview.............................................................................................................27
Table 22. Diagnostic Features................................................................................................................................28
Jan.19.21
Page 4
IPS2200 Datasheet
1. Pin Assignments
The IPS2200 is available in a 16-TSSOP 4.4 5.0 mm RoHS package. It is qualified for an ambient temperature
of -40°C to +125°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CSN_IRQN
RX1
SIO_SDA
SCK_SCL
OUT4
RX2
RX3
OUT3
RX4
OUT2
TX1
OUT1
TX2
VDD
VDDA
GND
Figure 1. Pin Assignments for 4.4mm 5.0mm 16-TSSOP Package – Top View
2. Pin Descriptions
Table 1. Pin Descriptions
Pin Number
1
Name
CSN_IRQN
Type
Digital
Input/Output
Description
Chip select input for the SPI interface; external pull-up resistor required.
Push/pull interrupt output for I2C or SPI interface.
Programmable options, see Table 3.
2
3
4
5
6
7
RX1
Analog Input
Analog Input
Connect the receiver coil 1 (sine) between the RX2 and RX1 pins.
Connect the receiver coil 2 (cosine) between the RX4 and RX3 pins.
RX2
RX3
RX4
TX1
TX2
Connect the transmitter coil between the TX1 and TX2 pins. The resonant frequency
is adjusted with a parallel capacitor CT between TX1 and TX2 or with capacitors CT1
from TX2 to GND and CT2 from TX1 to GND.
Analog
Input/Output
8
VDDA
GND
Supply
Supply
Supply
Internal analog voltage supply. Connect a capacitor CVA to the GND pin.
Common ground connection.
9
10
11
VDD
External supply voltage. Connect two parallel capacitors CVD to the GND pin.
Buffered analog or digital output; see Table 2.
OUT1
Analog
Output, Digital
Output
12
13
14
15
OUT2
Analog
Output, Digital
Output
Buffered analog or digital output; see Table 2.
Buffered analog or digital output; see Table 2.
Buffered analog or digital output; see Table 2.
OUT3
Analog
Output, Digital
Output
OUT4
Analog
Output, Digital
Output
SCK_SCL
Digital Input
Clock input for digital programming and diagnostic interfaces:
I2C interface: SCL clock input; external pull-up resistor mandatory,
see Figure 18, Figure 19, and Figure 20.
SPI interface: SCK clock input; external pull-up resistor is optional,
see Figure 16 and Figure 17.
Jan.19.21
Page 5
IPS2200 Datasheet
Pin Number
16
Name
SIO_SDA
Type
Digital
Input/Output
Description
Bi-directional data I/O line for digital programming and diagnostic interfaces:
I2C interface: SDA open drain data line; external pull-up resistor is mandatory,
see Figure 18, Figure 19, and Figure 20.
SPI interface: SIO bi-directional push-pull data line; external pull-up resistor is
optional,
see Figure 16 and Figure 17.
Table 2. Buffered Output Configuration
Pin (See Figure 1)
Output Depending on Mode[a]
Diagnostic State
Pin Number
Pin Name
OUT4
Analog Differential Analog Single-Ended Digital AB Incremental
All Modes, if enabled
LOW
14
13
12
11
SIN
SIN
A
OUT3
SINN
COS
COSN
REF_SIN
COS
A_N
B
LOW
HIGH
HIGH
OUT2
OUT1
REF_COS
B_N
[a] Abbreviations used in Table 2:
SIN:
Demodulated and buffered output of RX1 (sine, non-inverted)
Demodulated and buffered output of RX2 (sine, inverted)
Demodulated and buffered output of RX3 (cosine, non-inverted)
Demodulated and buffered output of RX4 (cosine, inverted)
SINN:
COS:
COSN:
REF_SIN: Bias voltage of sine signal, typical VDD/2
REF_COS: Bias voltage of cosine signal, typical VDD/2
A:
Sign output of RX1 (A, non-inverted): HIGH if positive, LOW if negative
Sign output of RX2 (A, inverted): HIGH if positive, LOW if negative
Sign output of RX3 (B, non-inverted): HIGH if positive, LOW if negative
Sign output of RX4 (B, inverted): HIGH if positive, LOW if negative
A_N:
B:
B_N:
Diagnostic state: Alarm status indication if an enabled alarm occurs
Table 3. Digital Interface and Interrupt Output Configuration
Pin (See Figure 1)
TSSOP
Input/Output Depending on Interface Mode [a]
Half Duplex SPI
with Interrupt
SIO
I2C with Address
Select
Pin Number
Pin Name
SIO_SDA
SCK_SCL
CSN_IRQN
Half Duplex SPI
SIO
I2C with Interrupt
SDA (PU)
16
15
1
SDA (PU)
SCL (PU)
SEL
SCK
CSN (PU)
SCK
SCL (PU)
IRQN
CSN/IRQN (PU)
[a] Abbreviations used in Table 3:
CSN: Chip-Select Input
CSN/IRQN: Combined Chip-Select Input and Interrupt Output
SIO:
Serial Bi-directional Data I/O Port for SPI Modes
Serial Clock Input for SPI Modes
SCK:
SEL:
SDA:
SCL:
IRQN:
PU:
Hardware Address-Select Input for I2C Mode (two address options)
Serial Bi-directional Data I/O Port for I2C Modes`
Serial Clock Input for I2C Modes
Interrupt Output
External Pull-up resistor required
Jan.19.21
Page 6
IPS2200 Datasheet
3. Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause
permanent damage to the device. Functional operation of the IPS2200 at the absolute maximum ratings is not
implied. Exposure to absolute maximum rating conditions could affect device reliability.
Table 4. Absolute Maximum Ratings
Symbol
VVDDmax
Parameter
External supply voltage
Conditions
Minimum
-18
Maximum
Units
Continuous
7.5
7.5
18
V
V
V
IC not supplied, permanent
IC supplied, permanent
-18
OUT1, OUT2, OUT3, and OUT4 output
voltage
VOUT
-15
VRX1
Receiver coil pin: RX1
Receiver coil pin: RX2
Receiver coil pin: RX3
Receiver coil pin: RX4
VRX2
-12
12
18
V
VRX3
VRX4
VDIGITAL
Digital IO pins: SCK_SCL, SIO_SDA,
CSN_IRQN
-0.3
V
V
VCSN_IRQN
Digital IO pin CSN_IRQN
When used as input for I2C
Refer to VVDDmax
address selection and tied to VDD
directly or with pull-up resistor.
VVDDAmax
VDDA internal LDO output
VDDA is internally regulated, no
connection to external voltage
Refer to VVDDA in Table
5
V
4. Operating Conditions
Conditions: VDD = 5V ±10%, TAMB = -40°C to +125°C, unless otherwise noted.
Table 5. Operating Conditions
Note: See important notes at the end of the table.
Symbol
TAMB_TSSOP
TJ
Parameter
Ambient temperature: 16-TSSOP
Junction temperature
Conditions
Minimum Typical
-40
-40
Maximum
125
Units
ºC
145
ºC
TSTOR
Storage temperature
Unmounted units must be
limited to 10 hours at
-55
150
ºC
temperatures above 125°C
RTHJA_TSSOP
tpup
Thermal resistance junction to
ambient: 16-TSSOP package
Start-up time
JEDEC MO-153
89
ºC/W
ms
Power-on reset (POR) to valid
output signal
3
VEL
Input rotational velocity
Electrical speed
Sine or cosine periods per
minute
250000
rpm
VVDDA_TH_H
Power on reset, high threshold
Power on reset, low threshold
The device is activated when
VDDA increases above this
threshold
2.6
V
V
VVDDA_TH_L:
The device is deactivated when
VDDA decreases below this
threshold
2.1
50
VDDAPOR_HYST
IVDDA
Power-on reset hysteresis
VDDA load current limitation
At VDDA pin
mV
mA
mA
75
8.4
Without coils. no load
12
Programmable transmitter coil
drive current (depending on
inductance of transmitter coil)
IDD
Current consumption
For values, refer to Table 8
mA
CVA
Capacitor from VDDA pin to GND
Capacitor from VDD pin to GND
100
nF
CVD
70
nF
INLUV3V
Accuracy, 3.3V mode, VDD=
under-voltage alarm level to 3.0V
±0.3
% FS [a]
With ideal coil input signals,
relative to an output signal of
1.8Vpp
INL3V
Accuracy, 3.3V mode,
VDD= 3.0 to 3.6V
±0.2
% FS
Jan.19.21
Page 7
IPS2200 Datasheet
Symbol
Parameter
Conditions
Minimum Typical
Maximum
Units
INLOV3V
INLUV5V
INL5V
Accuracy, 3.3V mode, VDD=
3.6V to over-voltage alarm level
±0.3
% FS
Accuracy, 5V mode, VDD=
under-voltage alarm level to 4.5V
±0.3
±0.2
±0.3
% FS
% FS
% FS
With ideal coil input signals,
relative to an output signal of
3.0Vpp
Accuracy, 5.0V mode,
VDD= 4.5 to 5.5V
INLOV5V
Accuracy, 5.0V mode, VDD=
5.5V to over-voltage alarm level
[a] % FS = percent of full scale = accuracy in % per period, where 100% is the angle range of one electrical period.
For rotary multi-period designs, one electrical period = 360° (one full turn) divided by the number of periods per turn.
Examples:
.
.
A 3-periodic coil design (3 120°) has a typical mechanical accuracy of ±0.2% per 120° = ±0.24°
A 4-periodic coil design (4 90°) has a typical mechanical accuracy of ±0.2% per 90° = ±0.18°
5. Ambient Temperature Range
The minimum ambient temperature for the IPS2200 is -40°C.
The maximum ambient temperature depends on the following factors:
The maximum junction temperature. See Table 5 for details.
The selected transmitter coil current. The total power consumption of the chip depends on the internal power
consumption and the user programmable current for the transmitter coil.
The minimum usable coil current in a given application. Note that smaller coil inductances require more
transmitter coil current, and larger coil inductances can operate with less coil current. The maximum allowed
transmitter coil current is shown in Table 5.
The Renesas internal part qualification. The IPS2200 is qualified for -40°C to +125°C ambient temperature.
Jan.19.21
Page 8
IPS2200 Datasheet
6. Electrical Characteristics
The following electrical specifications are valid for the operating conditions as specified in Table 5: (TAMB = -40°C
to 125°C).
Table 6. IPS2200 Electrical Characteristics, 3.3V Mode
Symbol
VDD3
Parameter
Supply voltage
Conditions
Minimum
3.0[a]
Typical
3.3
Maximum Units
3.6[b]
V
V
VDDA3
Analog supply voltage
Internally regulated. Connect a
CVA = 100nF capacitor from VDDA to
GND.
2.85
3.0
3.1
V3OVR
Over-voltage detection,
VDD rising
An over-voltage alarm is created if
VDD rises above these limits.
An over-voltage alarm is cleared if
VDD falls below these limits.
3.8
4.3
4.1
V
V3OVF
Over-voltage detection,
VDD falling
3.5[c]
150
2.2
V
V3OVH
Over-voltage detection
hysteresis
mV
V
V3UVR
Under-voltage detection,
VDD falling
An under-voltage alarm is created if
VDD falls below these limits.
2.95
3.1[d]
V3UVF
Under-voltage detection,
VDD rising
An under-voltage alarm is cleared if
VDD rises above these limits.
2.6
V
V3UVH
Under-voltage detection
hysteresis
100
2.6
mV
V
V3VDDAUVF
V3VDDAUVRr
VDDA under-voltage
detection
An under-voltage alarm is created if
VDDA falls below these limits.
2.85
2.9
VDDA under-voltage
detection
An under-voltage alarm is created if
VDDA rises above these limits.
2.7
V
[a] If the VDD under-voltage alarm is enabled, the VDD3 must be at least 3.1V.
[b] If the VDD over-voltage alarm is enabled, the VDD3 must be maximum 3.5V.
[c] If the VDD over-voltage alarm is enabled, the VDD3 must be maximum 3.5V.
[d] If the VDD under-voltage alarm is enabled, the VDD3 must be at least 3.1V.
Table 7. IPS2200 Electrical Characteristics, 5.0V Mode
Symbol
VDD5
Parameter
Supply voltage
Conditions
Minimum
4.5[a]
Typical
5.0
Maximum Units
5.5
4.1
V
V
VDDA5
Analog supply voltage
Internally regulated. Connect a
CVA = 100nF capacitor from VDDA to
GND.
3.9
4.0
V5OVR
Over-voltage detection,
VDD rising
An over-voltage alarm is created if
VDD rises above these limits.
6.2
6.9
6.6
V
V5OVF
Over-voltage detection,
VDD falling
An over-voltage alarm is cleared if
VDD falls below these limits.
5.9
V
V5OVH
Over-voltage detection
hysteresis
150
3.8
mV
V
V5UVR
Under-voltage detection,
VDD falling
An under-voltage alarm is created if
VDD falls below these limits.
4.4
V5UVF
Under-voltage detection,
VDD rising
An under-voltage alarm is cleared if
VDD rises above these limits.
4.0
4.6[b]
V
V5UVH
Under-voltage detection
hysteresis
100
3.45
mV
V
V5VDDAUVF
VDDA under-voltage
detection
A VDDA under-voltage alarm is
triggered when VDDA falls below
these limits.
3.9
3.9
V5VDDAUVRr
VDDA under-voltage
detection
A VDDA under-voltage alarm is
cleared if VDDA rises above these
limits.
3.5
V
[a] If the VDD under-voltage alarm is enabled, the VDD5 must be at least 4.6V.
[b] If the VDD under-voltage alarm is enabled, the VDD5 must be at least 4.6V.
Jan.19.21
Page 9
IPS2200 Datasheet
Table 8. LC Oscillator Specifications
Symbol
RP,eq
Parameter
Equivalent parallel
resistance of the LC
resonant circuit
Conditions
See Equation 1 and Equation 2.
Minimum
100
Typical
Maximum Units
Ω
fLC
Excitation frequency
LC oscillator; determined by external
components L and C.
1.7
-10
5.8
10
MHz
%
FOSC_ACC
fLC_DIAG_L
fLC_DIAG_H
VTX_P
Accuracy of transmitter
oscillator frequency
measurement
Gated by the internal oscillator.
LC oscillator lower
frequency diagnostics
range
0.007
Programmable frequency where an
out-of-range frequency diagnostics
alarm can be enabled.
MHz
LC oscillator upper
frequency diagnostics
range
10
11
LC oscillator amplitude
Peak-to-peak voltage; pins TX1 vs.
TX2; all modes. The coil current is
user programmable.
Vpp
mA
mA
ILC
Programmable transmitter
coil drive current
Equivalent DC current.
Programmable, depending on
transmitter coil inductance.
0
3
20
22
ILCmax
Maximum transmitter coil
drive current tolerance
At room temperature
18
20
Configuration with a single capacitor CT in the LC
oscillator.
1
2
16
15
CSN_IRQN
RX1
SIO_SDA
SCK_SCL
Rx
(sin)
The oscillator frequency is determined by the values of
coil L and capacitor CT:
3
4
RX2
RX3
14
13
12
11
SIN
SINN
COS
1
Rx
(cos)
푓푇푋
=
5
6
2휋 퐿퐶
√
RX4
TX1
푇
COSN
Where:
fTX = Oscillator frequency in MHz
L = Coil impedance in µHenry
CT = Capacitance in µFarad
3.3V / 5V
CVD
L
CT
10
9
7
8
VDD
GND
TX2
VDDA
CVA
Figure 2. LC Oscillator Connection with a Single Capacitor
Jan.19.21
Page 10
IPS2200 Datasheet
Configuration with split capacitors CT1 and CT2 for
improved EMC performance. Both capacitors must
have the same capacitance.
1
16
15
CSN_IRQN
SIO_SDA
SCK_SCL
2
RX1
The oscillator frequency is determined by the values of
coil L and capacitors CT1 and CT2:
Rx
(sin)
3
4
RX2
RX3
14
13
12
11
SIN
SINN
COS
ꢀ
푓푇푋
=
ꢄ∗ꢅ ∗ꢅ
ꢆꢇ ꢆꢈ
ꢁꢂ
ꢃ
Rx
(cos)
ꢅ
+ꢅ
ꢆꢇ ꢆꢈ
5
6
ꢀ
RX4
TX1
for CT1 = CT2 : 푓푇푋 =
COSN
ꢅ
ꢆꢇ
ꢈ
ꢃ
ꢁꢂ ꢉ
3.3V / 5V
CVD
L
10
9
7
8
VDD
GND
TX2
Where:
CT1
CT2
fTX = Oscillator frequency in MHz
L = Coil impedance in µHenry
CT1, CT2 = Capacitance in µFarad
VDDA
CVA
Figure 3. LC Oscillator Connection with Split TX Capacitors
The equivalent parallel resistance RPeq of the LC oscillator can be calculated using Equation 2:
1
L
Equation 1
RPeq
RS =
=
×
R
C
S
1
L
Equation 2
×
R
C
Peq
Where
RPeq Equivalent parallel resistance of the LC oscillator.
RS Serial resistance of the transmitter coil at the transmitter frequency.
L
Coil reactance at the resonant frequency.
C
Capacitance of the parallel capacitor CT.
Note that the capacitor losses are not included in the equation.
L
C
C
L
RPeq
V
V
RS
Figure 4. Parallel Resonator Circuit
Jan.19.21
Page 11
IPS2200 Datasheet
Table 9. Coil Receiver Front-End Specifications
Symbol
VRX
Parameter
Receiver coil amplitude
Conditions
Input signal full range.
Minimum
Typical Maximum Units
5[a]
0
5200[a]
mVpp
Vout = 3.0Vpp (single ended)
ΑIN_MM
Amplitude mismatch
correction range
11
%
Programmable individual gain
mismatch correction of Receiver
coil signals (SIN and COS)
AMM_RES
Amplitude mismatch
correction granularity
7
Bit
%
AIN_OFFSET_MIN
AIN_OFFSET_MAX
Input offset minimum
correction range
Offset of sine and cosine signal,
percentage of transmitter coil
amplitude.
Minimum and maximum values
depend on the Rx gain setting.
-0.09
-0.27
+0.09
+0.27
Input offset maximum
correction range
%
OFFCORR_RES
RRX
Input offset correction
granularity
Programmable step size.
7
Bit
Coil receiver DC input
resistance
Single-ended to GND.
Differential.
200
800
kΩ
kΩ
[a] Minimum and maximum Receiver voltage input levels depend on front-end gain setting, integration cycles, and LC oscillator
frequency
Table 10. Diagnostic Checks
Symbol
tFAIL
Parameter
Failure reaction time (time
to flag an error condition at
the IRQN pin)
Conditions
Chip internal diagnostic checks.
Minimum
Typical
Maximum
500
Units
µs
Rx coil short/open error flag activated.
Rx coil short/open error flag cleared.
Rx coil short/open error flag activated.
Rx coil short/open error flag cleared.
2200
630
k
k
k
k
Resistance of Rx coil, open
coil detection
R_OPEN_TH
354
19
External resistance from
any coil input to GND, short
to ground detection
R_SHORT_GND
Rx coil short short/open error flag
activated;
160
k
External resistance from
any coil input to VDD, short
to VDD detection
VDD = 2.7 to 6.4V.
R_SHORT_VDD
Rx coil short/open error flag cleared.
VDD = 2.7 to 6.4V
840
35
20
100
0
k
R1R2 short error flag threshold;
VDD = 3.0 to 3.6V.
140
70
410
180
200
3
k
External resistance between
coils for detection of a short
between coils
R_SHORT_TH
R1R2 short error flag threshold;
VDD = 4.5 to 5.5V.
k
DCOFF_AL
DiagLO
DiagHI
DC common mode output
offset alarm limits
Absolute value relative to VDD/2.
Output offset alarm flag activated.
mV
Diagnostic Low indication
SIN, SINN, A, AN Outputs, ILOAD = 1mA
sink current
1
%VDD
%VDD
Diagnostic High indication
COS, COSN, B, BN Outputs
ILOAD = 1mA source current
97
98.6
100
Table 11. Back-End Specification, Analog Outputs SIN, SINN, COS, COSN
Symbol
V3OUT
Parameter
Conditions
Minimum
GND +
0.7
Typical Maximum
Units
Analog output range, 3.3V option
VDD – 0.4
V
-1mA ≤ IOUT ≤ 1mA
GND +
1.0
V5OUT
Analog output range, 5V option
VDD – 1.0
V
V3OUT_PP
Analog output voltage amplitude, 3.3V
option
0.9
1.275
1.95
1.65
2.5
VPP
Single ended peak-to-
peak voltage range
V5OUT_PP
Analog output voltage amplitude, 5V
option
1.4
VPP
VDDOUT_CM
Output DC offset voltage, common
mode voltage
All modes
47.5
52.5
%VDD
DCOFFDRIFT
DCOFF
DC offset voltage drift
Over temperature range
-50
-6
50
6
μV/°C
At trim temperature,
over gain range and
DC offset voltage after trimming
mV
Jan.19.21
Page 12
IPS2200 Datasheet
Symbol
Parameter
Conditions
Minimum
Typical Maximum
Units
transmitter frequency
range, VDD= 3.0 to 5.5V
IOUT3
IOUT5
IOL
Output current; 3.3V option
Output current; 5V option
Output overload current,
Capacitive load, EMC filters
-1
-2
20
+1
+2
30
47
mA
Output load current
mA
mA
nF
CRAW_l
Refer to section 18 for
CO1 to CO4
Noise
Device output noise
Maximum gain,
2
mVrms
maximum setting for
integration cycles, no
output filtering, shorted
coil inputs
Table 12. Back-End Specification, Quadrature Pulse Output Option, Pins A, A_N, B, and B_N
Symbol
VQUAD_OH
VQUAD_OL
IO_QUAD3
Parameter
Conditions
Minimum
70
0
Typical
Maximum
100
30
Units
High level output voltage
Low level output voltage
Output current; 3.3V option
Output current; 5V option
Sign of demodulated input voltage:
high = positive; low = negative
%VDD
-0.5
-1
+0.5
+1
mA
mA
nF
V
Output load current
IO_QUAD5
CRAW_l
Capacitive load
Output switching positive
threshold
22
VQUAD_TH_POS
VOUT_CM
0.05
+
Comparator levels for changing
state of A, A_N, B, B_N digital
outputs, relative to amplified input
voltage
VQUAD_TH_NEG
VQUAD_TH_HYST
Output switching negative
threshold
VOUT_CM
0.05
-
V
Quadrature pulse
hysteresis
Relative to opposite channel
R1(Sin) vs. R2(Cos)
5
%
[a] See Table 2 regarding which of the pins OUT1, OUT2, OUT3, and OUT4 are assigned as A, A_N, B, and B_N.
Table 13. Digital Control Interface, Pins CSN_IRQN, SIO_SDA, SCK_SCL
Symbol
Parameter
High level input voltage,
all modes
Conditions
Minimum
Typical
Maximum
100
Units
%VDD
VIH
70
0
CSN_IRQN address
select input,
SCK_SCL clock input,
SIO_SDA data input
VIL3
VIL3
ILEAK
Low level input voltage,
3.3V mode
30
20
5
%VDD
%VDD
Low level input voltage,
5V mode
0
Input leakage current
-5
µA
VI_HYST
VOH
Input hysteresis
SCK_SCL clock input
All modes
100
80
0
mV
High level output voltage
Low level output voltage
– push/pull
100
20
%VDD
%VDD
VOL_PP
Push/pull output
CSN_IRQN
VOL_OD
VIRQN_H
RPULLUP
Low level output voltage
– open drain
Open-drain output
SIO_SDA, 3mA sink
current
0
0.4
7.9
V
Over-voltage detection at
CSN_IRQN, SCK_SCL,
or SIO_SDA
Over-voltage on these
pins can be monitored
as a diagnostic feature
6.9
7.4
V
Pull-up resistors for data
and chip select lines
SIO_SDA for I2C Mode; 1.8
CSN_IRQN for SPI
Mode.
10
kΩ
IOUT_SIO_SDA
CL
Digital interface output
current
Pin SIO_SDA
-2
2
mA
pF
Capacitive load
All modes
400
Table 14. Nonvolatile Memory
Symbol
Parameter
Data retention
Conditions
According to AEC Q100
Minimum
Typical
Maximum
> 100 at 25°C
>13 at 85°C
Units
Years
Jan.19.21
Page 13
푃표푠푖푡푖표푛 = 푎푟푐푡푎푛
(
)
IPS2200 Datasheet
Symbol
Parameter
Write
temperature
Conditions
Allowed ambient
temperature range for read
and write access
Minimum
-40
Typical
Maximum
125
Units
°C
°C
Read
temperature
Endurance[a]
-40
125
100
Over product lifetime
NVM Write Cycles
NVM Read events
Read Cycles
5x 1011
1x 1012
[a] Verified number of program/erase cycles. Qualified with 200 cycles
Table 15. Electrostatic Discharges (ESD)
Symbol
VESD,OUT
Parameter
ESD tolerance for pins OUT1, OUT2,
OUT3, OUT4, CSN_IRQN, VDD
Conditions
According to AEC-Q100-002 / JS-001,
Classification
Units
V
3A: 4000 to < 8000
2: 2000 to < 4000
1A: 250 to < 500
HBM100pF/1.5kΩ
VESD
ESD tolerance for pins RX1, RX2, RX3,
RX4, VDDA, SCK_SCL, SIO_SDA
VESD,OSC
ESD tolerance for pins TX1, TX2
[a] When handling semiconductor devices such as IPS2200, always observe ESD guidelines to avoid electrostatic discharges on
these parts.
7. Circuit Description
7.1
Overview
The IPS2200 sensor circuit consists of one transmitter coil and two receiver coils, which are typically designed
as traces on a printed circuit board. The two receiver coils have a sinusoidal shape and are shifted by 90° with
respect to each other; refer to Figure 6 and Figure 7 for typical coil shapes. A metal target is placed above the
coil arrangement.
Circuit signal flow:
1. The IPS2200 drives AC current into the transmitter coil and generates an alternating magnetic field.
2. The magnetic field induces voltages in the receiver coils. Without a metallic target, due to the balanced, anti-
serial connection of their segments, the voltages are compensated to achieve zero output at each pair of
terminals.
3. If a metal target is placed above the coils:
a. The magnetic field induces eddy currents on the surface of the metal target.
b. The eddy currents generate a counter magnetic field, thus reducing the total flux density underneath.
c. The voltage induced in the receiver coil areas underneath the target is reduced, creating an imbalance in
the anti-serial coil segment voltages
d. An output voltage occurs on the terminals, changing amplitude and polarity with the target position.
4. The IPS2200 IC amplifies, rectifies, and filters the receiver voltages and outputs them for external signal
processing.
Due to the 90° phase shift of the two receiver coils, the output signals also have a 90° phase shift in relation to
the target position, generating ratiometric sine and cosine signals. The signals can be converted into an absolute
position, for example by applying an arctangent operation of Vsin and Vcos.
푉푠푖푛
Equation 3
푉푐표푠
Jan.19.21
Page 14
IPS2200 Datasheet
VDD
CSN_IRQN
SIO_SDA
SCK_SCL
Digital Interface for
Diagnostics and
Programming
Power
Supply
VDDA
GND
Tx
CT
Transmitter
OUT2
OUT1
Rx
(cos)
Receiver
Coil 1
Analog Output
for Position and
Diagnostics
OUT4
OUT3
Rx Receiver
(sin) Coil 2
IPS2200
Position, Rotation Angle
Position, Rotation Angle
Note: See Table 2 for definitions of the OUT1, OUT2, OUT3, and OUT4 pins.
Figure 5. Response of the IPS2200
Figure 6 shows an example of a linear motion sensor with one transmitter coil (transmitter loop) and two receiver
coils (Sin loop and Cos loop). Due to the alternating clockwise and counterclockwise winding direction of each
segment in a loop (for example RxCos = clockwise Cos Loop1 + counterclockwise Cos Loop 2), the induced
voltages in each segment have alternating opposite polarity.
VCos Loop1 = -VCos Loop2
Equation 4
If no target is present, the secondary voltages cancel each other:
VCos = VCos Loop1 – VCos Loop2 = 0V
Equation 5
With a target placed above the coils, the secondary voltage induced in the covered area is lower than the
secondary voltage without a target above it.
VCos Loop1 ≠ -VCos Loop2
Equation 6
This creates an imbalance of the secondary voltage segments, and thus, a secondary voltage ≠ 0V is generated,
depending on the location of the target.
VCos = VCos Loop1 – VCos Loop2 ≠ 0V
Equation 7
Jan.19.21
Page 15
IPS2200 Datasheet
Cos Loop 1
(cw)
Cos Loop 2
(ccw)
Tx Loop
RxCos
Tx
RxSin
Metallic Target
Sin Loop 2
(ccw)
Sin Loop 3
(cw)
Sin Loop 1
(cw)
Figure 6. Coil Design for a Linear Motion Sensor
The same principles shown for the linear motion sensor in Figure 6 can be applied to an arc or rotary sensor as
shown in Figure 7.
Sin Loop 1
(cw)
Tx Loop
Cos Loop 1
(cw)
Cos Loop 2
(ccw)
Metallic
Target
Sin Loop 2
(ccw)
Figure 7. Coil Design for a 360° Rotary Sensor
Jan.19.21
Page 16
IPS2200 Datasheet
8. Sampling Rate, Resolution, Output Data Rate, and Propagation Delay
Since the IPS2200 uses analog signal processing (no ADC), there is no sampling rate and the resolution is
virtually infinite.
Due to the internal chopping and demodulation processes, there is a programmable output data rate and
corresponding propagation delay.
The overall signal processing is very fast, allowing operation at very high speeds up to 250000 rpm (electrical)
and more with very fast update rates and propagation delays in the range of 4.3µs to 7.7µs for the shortest
integration factor (5) and 13.6µs to 31.3µs for the longest integration factor (31).
The coil receiver circuit automatically locks to the transmitter coil oscillator frequency. It automatically corrects for
LC oscillator frequency drifts due to temperature changes or air gap changes for the target. Consequently, the
demodulator at the receiver is also dependent on the LC oscillator frequency.
In addition to the LC oscillator frequency, a second contributing factor is the integration factor of the demodulator
(essentially a digital filtering process). The data rate and propagation delay are defined as a step response on
the input when the output reaches > 90% of the maximum signal level.
It can be calculated via Equation 8:
(퐼퐹ꢊꢀ)
Output Data Rate [µs] =
Equation 8
Equation 9
ꢋ
ꢄꢅ
ꢁ∙(퐼퐹ꢊꢀ)
Data Propagation Delay [µs] =
ꢌ 1 ∙ 휏
ꢋ
ꢄꢅ
Where
IF Integration factor: a programmable factor of 5 to 31
fLC LC oscillator frequency
τ
Internal time constant (tau) = 2.2µs
Table 16. Output Data Rate, Propagation Delay
Symbol
Parameter
Conditions
Minimum Typical
Maximum
Units
fLC = 5.6MHz, integration factor =
5 to 31 (programmable)
fLC = 2.2MHz, integration factor =
5 to 31 (programmable)
4.3
13.6
µs
Raw data update rate, propagation
delay of R1 and R2 input signals at
output.
tPD
7.65
31.3
µs
Jan.19.21
Page 17
IPS2200 Datasheet
Figure 8. Data Update Rate vs. LC Oscillator Frequency vs. Integration Factor
9. Output Modes
9.1
Analog Differential Sine-Cosine Analog Output Mode
In this mode, both sine and cosine signals are available as full differential outputs. This configuration is
recommended for best signal integrity and EMC performance.
COS
SIN
COS_N SIN_N
Vout
VDD
VDD/2
0V
α (el), 1 period
0°
90°
180°
270°
360°
Figure 9. Sine-Cosine Analog Mode Output Signals
Jan.19.21
Page 18
IPS2200 Datasheet
9.2
Analog Single Ended Sine-Cosine Analog Output Mode
In single ended mode, the SIN and COS signals are available with respect to GND. SIN_N and COS _N signals
provide a buffered reference signal (VDD/2).
COS
SIN
COS_N
SIN_N
Vout
VDD
VDD/2
0V
α (el), 1 period
0°
90°
180°
270°
360°
Figure 10. Sine-Cosine Analog Mode Output Signals
9.3
Digital Incremental Differential AB Mode
In AB incremental mode, four digital output signals have one symmetric period in every 360° electrical period.
Signal B is shifted by 90° (electrical) relative to signal A, allowing four states per 360° (electrical period), see
Table 17.
Table 17. Output Status in AB Incremental Mode
State #
Position (Electrical)
0° >pos >=90°
Signal A
Signal A_N
Signal B
Signal B_N
1
2
3
4
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
0
90° >pos >=180°
180° >pos >=270°
270° >pos >=360°
Signals A_N and B_N are the inverted signals of A and B, allowing differential signal transmission for best signal
integrity and EMC performance.
By having A and B phase shifted, the direction of rotation can be determined:
Clockwise rotation: signal B is high at rising edge of A as shown in Figure 11 at 360° where moving from left to
right (0° to 360°)
Counter clockwise rotation: signal B is low at rising edge of A as shown in Figure 11 at 180° where moving
from right to left (360° to 0°)
Vdig
A
VOH
VOL
VOH
VOL
A_N
VOH
VOL
B
VOH
VOL
B_N
α (el), 1 period
0°
90°
180°
270°
360°
Figure 11. Digital Incremental Differential AB Mode Output Signals
Note that the AB output provides only one pulse per phase on each output. The number of pulses per revolution
can be increased by coil designs having multiple periods per turn.
Jan.19.21
Page 19
IPS2200 Datasheet
10. Operating at High Speed
The IPS2200 uses analog signal processing, so it can handle inputs signals at very high speed. The input signal
can have a frequency of up to 4.16kHz, which is equivalent to 250000 RPM (electrical phases per minute). Even
higher frequencies and therefore higher speeds are possible, but with reduced performance and signal
amplitude.
The mechanical rotor speed can be calculated with Equation 10:
( )
rpm el
rpm(mech)=
Equation 10
coil periods
Where
rpm (mech) Rotation speed of the rotor (and target) in revolutions per minute.
rpm (el) Maximum electrical input frequency of the sensor in rpm (electrical)
= 250000 electrical periods per minute (rpm)
= 4166 electrical periods per second = 4.166kHz
coil periods Number of electrical periods per turn
= number of coil periods per 360° circle
= number of metal target segments
Figure 23 shows a design for a 6 pole motor (having 3 pole pairs) using a 3-periodic coil design.
The maximum mechanical rotation speed of this motor is calculated according to Equation 11.
250000 rpm
=83333 rpm
3
Equation 11
Table 18. Output Modes and Maximum Speed
SIN/COS Output Mode
AB Output Mode
Maximum Rotor Speed
Target Design
(metal/no metal)
Sine, Cosine Cycles
per Revolution
Quadrature Pulses per
Revolution
Quadrature Counts
per Revolution
Mechanical
Speed
1 (180° / 180°)
2 (90° / 90°)
3 (60° / 60°)
4 (45° / 45°)
6 (30° / 30°)
8 (22.5° / 22.5°)
10 (18° / 18°)
…
1 360°
2 180°
3 120°
4 90°
1
4
250000 rpm
2
8
125000 rpm
3
12
83333 rpm
4
16
62500 rpm
6 60°
6
24
41666 rpm
8 45°
8
32
31250 rpm
10 36°
1 cycle per target
10
40
25000 rpm
1 pulse per target
4 counts per target
250000 RPM / targets per wheel
Jan.19.21
Page 20
IPS2200 Datasheet
11. Digital Diagnostics and Programming Interfaces
In order to program the IPS2200 and to enable fast diagnostics without interrupting the analog high speed signal
path, an additional digital serial interface is available.
The IPS2200 offers four modes of digital communication for the diagnostics and programming interface:
Half duplex SPI interface (default setting).
Half duplex SPI interface with interrupt (programming option).
I2C interface with interrupt (programming option).
I2C interface with address select (programming option).
11.1 Block Diagram
Figure 12 shows the block diagram of the IPS2200.
VDDA
VDD
GND
VDDDigital
IPS2200
Power
Management
offset Sin
offset Cos
Offset
Control
OUT4
OUT3
OUT2
OUT1
Gain
Control
gain Sin
gain Cos
Sin_n / A_n
RX1
RX2
Protection
Rx Sine
Analog Front-End,
Demodulation,
Gain Adjustment
RX3
RX4
Rx
Cosine
TX1
TX2
SIO_SDA
SCK_SCL
Configuration,
NVM
Programming
Interface (SPI, I2C)
Tx
Oscillator
Diagnostics, Timer
CSN_IRQN
(SSN chip select for SPI or
IRQN interrupt for I2C or SPI)
Figure 12. Block Diagram
The main building blocks include the following:
Power Management: power-on-reset (POR) circuit; low drop-out (LDO) regulators for analog and digital
supplies.
Oscillator: generation of the transmitter coil signal.
Analog Front-End:
o Input filter, offset, and gain setting: analog AM signal preconditioning.
o Synchronous integrator: demodulation of the AM signal.
Offset Control: correction of offsets at the receiver coil inputs RX1/RX2 and RX3/RX4.
Gain Control: correction of amplitude mismatching from RX1/RX2 and RX3/RX4 input signals.
Configuration, NVM: nonvolatile storage of factory and user-programmable settings.
Programming Interface: configuration, communication, and diagnostics via selectable I2C or SPI bidirectional
interface.
Diagnostics, Timer: Diagnostics for critical blocks to ensure functional safety and watchdog timer.
Protection: over-voltage, reverse polarity and short circuit protection.
Jan.19.21
Page 21
IPS2200 Datasheet
There are four interface options for the OUT1, OUT2, OUT3, and OUT4 pins (see Table 2):
Differential analog output
Single-ended analog output with reference
Incremental digital AB pulse output (one pulse per phase)
12. Connection Options
Note: In Figure 13, Figure 14, and Figure 15, the active function of dual function pins is shown in bold font.
The IPS2200 must be programmed to match to the correct VDD voltage supply level (3.3V or 5.0V).
SIN
SIN
SINN
SINN
Position,
Diagnostics (0/1)
COS
COS
COSN
COSN
I2C Programming:
fixed gain, offset, coil
current, ...
SIO_SDA
SCK_SCL
VDD
GND
VDD
GND
CVD
SIN
SIN
SINN
SINN
Position,
Diagnostics (0/1)
COS
COS
COSN
COSN
SIO_SDA
SCK_SCL
CSN_IRQN
SPI Programming:
fixed gain, offset, coil
current, ...
VDD
GND
VDD
GND
CVD
Figure 13. Analog Interface with Diagnostics Mode, Fixed Configuration
When using the digital interface pins as shown in Figure 14 and Figure 15, IPS2200 and ECU must share the
same VDD voltage supply level to match the digital HIGH and LOW signal levels.
Jan.19.21
Page 22
IPS2200 Datasheet
SIN
SIN
SIN_
SINN
Position,
Diagnostics (0/1)
COS
COS
COS_
COSN
I2C Interface:
NVM programming
SDA
SCL
SIO_SDA
SCK_SCL
on-the-fly gain and offset.
coil current, Tx frequency,
diagnostics (detailed)
VDD
GND
VDD
GND
CVD
SIN
SIN
SINN
SINN
Position,
Diagnostics (0/1)
COS
COS
COSN
COSN
SPI Interface:
NVM programming
on-the-fly gain and offset.
coil current, Tx frequency,
diagnostics (detailed)
SIO_SDA
SCK_SCL
CSN_IRQN
SIO_SDA
SCK_SCL
CSN_IRQN
VDD
GND
VDD
GND
CVD
Figure 14. Analog and Digital Interface, On-The-Fly Gain and Offset Correction, Extended Diagnostics
SIN
SIN
SINN
SINN
Position,
Diagnostics (0/1)
COS
COS
COSN
COSN
I2C Interface:
NVM programming
on-the-fly gain and offset.
coil current, Tx frequency,
diagnostics (detailed)
SDA
SCL
SIO_SDA
SCK_SCL
CSN_IRQN
Immediate alert
IRQN
VDD
VDD
CVD
GND
GND
SIN
SIN
SINN
SINN
Position,
Diagnostics (0/1)
COS
COS
COSN
COSN
SPI Interface:
NVM programming
on-the-fly gain and offset.
coil current, Tx frequency,
diagnostics (detailed)
SIO_SDA
SCK_SCL
CSN_IRQN
SIO
SCK
CSN
IRQN
VDD
Immediate alert
VDD
GND
CVD
GND
Figure 15. Analog and Digital Interface, On-The-Fly Gain and Offset Correction, Extended Diagnostics with MCU
Interrupt
Jan.19.21
Page 23
IPS2200 Datasheet
13. Digital Diagnostics and Programming Interfaces
In order to program the chip and to enable fast diagnostics without interrupting the analog high speed signal
path, an additional digital serial interface is available.
The IPS2200 offers four modes of digital communication for the diagnostics and programming interface:
1. Half duplex SPI interface (programming option)
2. Half duplex SPI interface with interrupt (programming option)
3. I2C interface with interrupt (programming option)
4. I2C interface with address select (default interface)
13.1 Supply Voltage Operation: 3.3V or 5V
The IPS2200 can be programmed to operate with either a 3.3V ±10% or a 5.0V ±10% supply voltage.
If the IPS2200 is programmed for the 5V operation, but connected to a 3.3V supply, it will be in a 5V under-
voltage state. However, it can still be programmed for 3.3V operation. After the next power-on-reset, the
IPS2200 boots as a 3.3V device.
If the IPS2200 is programmed for 3.3V operation, but connected to a 5V supply, it will be in a 3.3V over-voltage
state. However, it can still be programmed for 5.0V operation. After the next power-on-reset, the IPS2200 boots
as a 5.0V device.
13.2 Half-Duplex SPI Interface
This is a standard bi-directional, half-duplex SPI interface.
Note: By default, I2C is enabled as the standard communication interface. To enable communication over SPI, it
must be enabled through programming over the I2C interface.
To operate the I2C interface, pull-up resistors are required for pins SIO_SDA and SCK_SCL. Optionally, these
two resistors can either remain active or be removed for SPI operation. A pull-up resistor is always required for
pin CSN, see Figure 16.
After re-programming, the SPI interface becomes active with the next POR and the chip remains with SPI
enabled as communication interface.
VDD
4.7k ꢀ
4.7k ꢀ
4.7k ꢀ
SIO_SDA
SCK_SCL
CSN_IRQN
Data In/Out
Clock
DIO
IPS2200
MCU
SCK
CSN
Chip Select
Figure 16. Half Duplex 3-3 Wire SPI Interface
Jan.19.21
Page 24
IPS2200 Datasheet
A master can communicate with multiple slaves. Each slave device has an independent CSN line but shares the
SCK and SIO lines with all slaves. A slave is only addressed when the corresponding CSN pin is pulled low.
VDD
4.7k ꢀ
Data In/Out
4.7k
SIO_SDA
SCK_SCL
CSN_IRQN
DIO
IPS2200
#1
Clock
SCK
MCU
Chip Select #1
SSN1
SSN2
SIO_SDA
SCK_SCL
CSN_IRQN
IPS2200
#2
Chip Select #2
Figure 17. Half Duplex 3-3 Wire SPI Multi-slave Interface
The SPI slave module is activated by the SPI 3-wire master, which initiates the transaction by pulling the chip-
select pin low (CSN_IRQN, pin 1). A serial clock (SCK_SCL, pin 15), is driven by the master. The Serial Data
In/Out line (SIO_SDA, pin 16) is a bidirectional data line between master and slave. In a typical scenario, the
master transmits a command with a specified length of 8-bit over the SIO line. If it is a write command, the
master keeps transmitting data over the same line. If the first bits were a READ command, the slave transmits a
fixed length of data over the SIO line to the master.
Table 19. SPI Interface Parameters
Symbol
CL_SPI
Parameter
SPI clock rate
Conditions
Minimum Typical
Maximum
100
35
Units
Kbit/s
ns
tR_SIO
Rise time of SIO
Signal level change from 10 to
90%; ≤15pF capacitive load
tF_SIOL
Fall time of SDA or SCL
Signal level change from 90 to
10%;
35
ns
≤15pF capacitive load
Note: In Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20, for IPS2200 pins that have dual functions, the
function that is active is shown in bold font.
For a detailed description of the SPI interface, refer to the IPS2200 Programming Guide.
13.3 I2C Interface
The IPS2200 includes a standard I2C interface as the default interface. The I2C address is programmable. In
addition, the CSN_IRQN pin can be programmed as either an I2C address selection (SEL) pin or as an interrupt
output (IRQN) pin when using the I2C interface (see Table 3). The IPS2200 is configured as a I2C slave, several
slaves can be connected in parallel on the I2C bus.
Table 20. I2C Interface Parameters
Symbol
CL_I2C
Parameter
I2C clock rate
Conditions
Minimum Typical
Maximum
100
Units
Kbit/s
µs
tSCL_LOW
Low level state of SCL clock
High level state of SCL clock
Rise time of SDA or SCL
Fall time of SDA or SCL
4.7
4.0
tSCL_HIGH
tR_SDA_SCL
tF_SDA_SCL
µs
Signal level change from 10 to 90%
Signal level change from 90 to 10%
1000
300
ns
ns
Jan.19.21
Page 25
IPS2200 Datasheet
Two wires, serial data (SIO_SDA, pin 16) and serial clock (SCK_SCL, pin 15), carry information between the
devices connected to the bus. Both SDA and SCL are connected to the positive supply voltage VDD via an
external pull-up resistor. When the bus is free, both lines are HIGH. The output stages of devices connected to
the bus must have an open-drain or open-collector to perform the wired-AND function.
An external master (host controller) initiates a transfer, generates clock signals, and terminates a transfer. The
implementation supports the I2C slave function, which is addressed by the master and supports the I2C bus
specification version 2.1.
13.3.1. I2C with Address Selection (Programming Option)
When the IPS2200 is programed to use the I2C interface with address selection, the CSN_IRQN pin is used to
select the I2C slave address by hardware.
VDD
4.7k ꢀ
Data In/Out
Clock
4.7k
SIO_SDA
SCK_SCL
CSN_IRQN
SDA
SCL
IPS2200
#1
MCU
VDD
SIO_SDA
SCK_SCL
CSN_IRQN
IPS2200
#2
GND
Figure 18. I2C Interface with Address Select
13.3.2. I2C Interface with Interrupt (Programming Option)
When the IPS2200 is programed to use the I2C interface with the interrupt function, it operates as a standard
I2C interface. The I2C address is programmable. In addition, the CSN_IRQN pin is used as an interrupt output
for fast signaling of a diagnostic event.
VDD
4.7k
Data In/Out
Clock
4.7k
SIO_SDA
SCK_SCL
CSN_IRQN
SDA
SCL
IRQ
MCU
IPS2200
Interrupt
Figure 19. I2C Interface Configuration with Interrupt on a Single Slave
Jan.19.21
Page 26
IPS2200 Datasheet
VDD
4.7k
Data In/Out
Clock
4.7k
SIO_SDA
SCK_SCL
CSN_IRQN
SDA
SCL
IPS2200
#1
MCU
Interrupt
IRQ1
IRQ2
SIO_SDA
SCK_SCL
CSN_IRQN
IPS2200
#2
Interrupt
Note: In this mode, several I2C slaves are connected in
parallel. Each I2C slave must have an individual I2C address.
Figure 20. I2C Interface Configuration with Multi-slave Interrupt
For a detailed description of the I2C interface, refer to the IPS2200 Programming Guide.
14. Protection and Diagnostics
14.1 I/O Protection
In order to meet the requirements for over-voltage and reverse-polarity protection on both the output and power
supply pins, the IPS2200 includes several protection and diagnosis features:
1. Protection against short circuit of the output pins SIN, SINN, COS, and COSN to GND or to VDD
2. Over-voltage and reverse-polarity protection:
a. On supply pin VDD to GND
b. On analog output pins SIN, SINN, COS, and COSN to GND
c. On digital output pins SIO_SDA, CSN_IRQN, and SCK_SCL to GND
15. Programming Options
The IPS2200 family offers a variety of programming options. The IC is programmed through the digital bi-
directional SPI or I2C interface. The main programming functions are described in Table 21.
15.1 Lock Feature (Cyber Security)
The IPS2200 contains a write lock bit option, which can be set by the user. Once the write lock bit is set, no
further writing to the chip is possible.
Note: For programming details, see the IPS2200 Programming Guide, which is available from Renesas on
request.
Table 21. Programming Options Overview
Function
Programming Options
3.3V ±10% or 5.0V ±10%, alarm levels
Supply voltage range
High speed interface
Sine/cosine differential, single-ended, A/B
Half-duplex SPI, half-duplex SPI with interrupt, I2C with address select,
I2C with interrupt
Digital diagnostic and programming interface
SPI interface
SPI modes with/without interrupt, clock polarity, clock phase
Data order: MSB first / LSB first
Jan.19.21
Page 27
IPS2200 Datasheet
Function
Programming Options
Slave address, I2C mode with address select or with interrupt
Enable/disable: Output pins are pulled low or high in diagnostic state
Register access R/W / read-only
I2C interface
Diagnostic signaling on high speed interface
Security lock function
RF front end integration cycles
Receiver overall gain
Sine, cosine channel gain
Sine, cosine offset
Number of integration cycles; adjust noise vs. speed
Overall gain coarse adjustment
Amplitude mismatch correction, fine adjustment
Pre-adjustment of input offsets
Tx oscillator
Bias current, optimization of coil performance
Measurement of Tx oscillator frequency, upper/lower frequency alarm
Enable/disable interrupt events
Time base counter
Interrupt
16. Diagnostics
The diagnostics described in Table 22 are performed on the chip level and are flagged in corresponding
registers if a fault detection occurs. Each of these diagnostic functions can be enabled or disabled to generate
an interrupt event at the CSN_IRQN output. In addition, an interrupt event can also be signaled through the high
speed interface pins (SIN, SINN, COS, COSN; see Table 2) by putting them into the diagnostic state.
Alarm types marked as “Static” will remain set while the error persists and are cleared only by power-on-reset
(POR); alarm types marked as “Temporary” will be cleared when the source of the error is removed.
Diagnostic flags marked as “Continuous” are continuously tested; diagnostic flags marked as “Start-up” are
checked at start-up only.
Table 22. Diagnostic Features
Diagnostic Flag
Type
Active
Description
VDD over-voltage
Temporary
Continuous
If the external supply voltage exceeds the maximum limit of typical +10%,
this flag is asserted. To avoid a flag toggling, a comparator hysteresis is
implemented. See Table 6 for alarm levels in 3.3V Mode and Table 7 for
alarm levels in 5V Mode.
VDD under-voltage
Temporary
Continuous
If the external supply voltage falls short of the minimum limit of typical -10%,
this flag is asserted. To avoid a flag toggling, a comparator hysteresis is
implemented. See Table 6 for alarm levels in 3.3V Mode and Table 7 for
alarm levels in 5V Mode.
Data access fail
Temporary
Temporary
Static
Continuous
Continuous
Continuous
Continuous
Chip internal failure.
Protocol integrity fail
Shadow register DED
Shadow register SED
Failure in the I2C/SPI data transfer.
Shadow register bank double-bit error detection.
Temporary
Shadow register bank single-bit error detection. Each single-bit error
detection triggers a single-bit error correction (SEC) of the register output.
Nonvolatile memory
DED
Static
Start-up
Start-up
NVM double-bit error detection. Each individual addressed word is checked
and flagged for bit error.
Nonvolatile memory
SED
Temporary
NVM single-bit error detection. Each individual addressed word is checked
and flagged for bit errors.
Each single-bit error detection triggers a single-bit error correction (SEC) of
the NVM output.
LC oscillator failure
LC oscillator stuck
Temporary
Continuous
This flag is set when the LC oscillator frequency is out of range. The
frequency range is programmable; see section 16.2 for details.
Temporary
Temporary
Continuous
Continuous
This flag is set when the LC oscillator stops running.
VDDA under-voltage or
CSN_IRQN over-voltage
or SIO_SDA over-
voltage
This flag is set when the internally regulated analog supply voltage VDDA
falls below specified limits or when an over-voltage on pins CSN_IRQN or
SIO_SDA is detected.
See Table 6 or Table 7 for VDDA alarm levels and Table 4 for IRQN_CSN
and SIO_SDA over-voltage alarm levels.
Low amplitude
Temporary
Temporary
Continuous
Continuous
In the Incremental Digital Mode, a minimum signal level must be defined
(gain factor) for a valid output function. If this flag is asserted, the gain factor
must be increased.
Internal bus failure
Chip internal failure.
Jan.19.21
Page 28
IPS2200 Datasheet
Diagnostic Flag
IRQN watchdog failure
Type
Static
Active
Continuous
Description
A cyclic interrupt request can be initiated by starting a watchdog counter.
When the timer is expired, the interrupt flag is asserted and the timer
restarts. The timer can be stopped by resetting the watchdog value to zero.
Mechanical damage
Output buffer failure
Static
Continuous
Continuous
The chip is checked for mechanical damage (cracks in the silicon)
Temporary
This flag is set when the mean value of analog outputs SIN+SINN or
COS+COSN differs from VDD/2 by more than the specified limits described
in Table 11.
Output buffer overload
R1 to R2 coil short
R2 coil failure
Temporary
Static
Continuous
Start-up
This flag is set when the output amplifier load current is above the specified
limits.
A short between the receiver coils R1 and R2 is checked after POR. The
check result is stored and flagged until the next POR.
Temporary
Temporary
Continuous
Continuous
This flag is set if there is a short between receiver coil R2 and GND, a short
between receiver coil R2 and VDD, or an open receiver coil R2.
R1 coil failure
This flag is set if there is a short between receiver coil R1 and GND, a short
between receiver coil R1 and VDD, or an open receiver coil R1.
16.1 Internal Register and Memory Errors
For all registers, volatile and nonvolatile memories, a cyclic redundancy check (CRC) is implemented, allowing
2-bit error detection and 1-bit error correction. An alarm flag is set when a CRC error occurs.
16.2 LC Oscillator Frequency Out of Range
The typical frequency range for the transmitter LC oscillator is from ~2MHz to 5MHz, which is the open
frequency band between the medium-wave radio band (0.52MHz to 1.73MHz) and the short-wave radio band
(5.8MHz to 6.3MHz). Due to the use of external components (printed inductor and discrete capacitor), the Tx
oscillation frequency will change over temperature, mainly depending on the temperature coefficient of the
discrete capacitor (see CT in the application circuit on page 1).
Recommendation: Use a capacitor with a low temperature coefficient (see the recommendation given below
Table 8).
In order to ensure that the oscillation frequency is within the boundaries of a given application, the oscillation
frequency of the Tx oscillator is internally measured and displayed as a proportional value in a register. The user
can select upper and lower limits for these register values that will create an alarm flag when the oscillation
frequency is outside of these programmable boundaries.
Jan.19.21
Page 29
IPS2200 Datasheet
17. Application Examples
Typical coil and target arrangements are shown in Figure 21 to Figure 24: As examples, rotary designs for 1
360°, 2 180°, 3 120° and 4 90° are shown. Many other combinations (essentially any n x 360/n) are
possible, where n is an integer number.
For example, in sensor designs for brushless DC rotor position feedback, n could be the number of pole pairs on
the rotor. In such cases, the output signal of the IPS2200 would be one electric period per each pole pair.
Figure 21. Coil Design and Signal Output for a 360° Rotary Sensor
Figure 22. Coil Design and Signal Output for a 2 180° Rotary Sensor
Figure 23. Coil Design and Signal Output for a 3 120° Rotary Sensor
Jan.19.21
Page 30
IPS2200 Datasheet
Figure 24. Coil Design and Signal Output for a 4 90° Rotary Sensor
18. Electromagnetic Compatibility (EMC)
Guidelines for EMC compliant circuit designs are available in a separate document “IPS2200 EMC recommendations” on request.
19. Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below.
The package information is the most current data available.
www.idt.com/document/psc/16-tssop-package-outline-drawing-44mm-body-065mm-pitch-pgg16t1
20. Marking Diagram
20.1 Marking of Production Parts
Line 1: First characters of part code (IPS); “ES” is added for engineering
samples
IPS
2200BI
Line 2: Next four characters of the part code (2200) followed by
B = Design revision
LOT
I = Operation temperature range, Industrial
YYWW
R
Line 3: “LOT” = Lot number
Line 4: “YYWW” = Manufacturing date:
YY = last two digits of manufacturing year
WW = manufacturing week
R = RoHS compliant statement
Jan.19.21
Page 31
IPS2200 Datasheet
21. Ordering Information
Orderable Part Number
IPS2200BI1W
Description and Package
16-TSSOP, 4.4 5.0 mm
16-TSSOP, 4.4 5.0 mm
MSL Rating
1
Carrier Type
7” Reel, 500 parts / reel
13” Reel, 4000 parts / reel
Temperature
-40° to +125°C
-40° to +125°C
IPS2200BI1R
1
Note: For communication and programming, the IPS2200 Application Modules listed below require an IPS-COMBOARD, which is
available separately.
IPS2200STKIT
IPS2200 Starter Kit including USB communication board, application module and connection cables
22. Revision History
Revision
1.3
Date
Description
Jan.18.21
Jul.15.20
Jul.1.20
SPI interface description updated
1.2
1.1
1.0
Pin naming aligned with other position sensor products
Formulas added for calculating the LC oscillator frequency.
Apr.15.20
Official release for product launch
3.3V and 5V supply voltage operation changed.
Circuit and block descriptions updated.
Values updated for absolute maximum ratings, operating conditions, and electrical
characteristics.
Updated formatting.
Section 9 (Output Modes) is added.
0.1
Feb.16.19
Preliminary release.
Jan.19.21
Page 32
16-TSSOP Package Outline Drawing
4.4mm Body, 0.65mm Pitch
PGG16T1, PSC-4749-01, Rev 00, Page 1
16-TSSOP Package Outline Drawing
4.4mm Body, 0.65mm Pitch
PGG16T1, PSC-4749-01, Rev 00, Page 2
Package Revision History
Description
Date Created Rev No.
Revised from PSC-4056-02 PGG16
Jan 26, 2018
Rev 00
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