ISL12032IVZ_技术文档

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NO RECOMMENDED REPLACEMENT

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DATASHEET

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Crystal Back-up

FN6618

Rev 3.00

May 5, 2011

The ISL12032 device is a low power real time clock with

50/60 AC input for timing synchronization. It also has an

Features

• 50/60 Cycle AC as a Primary Clock Input for RTC Timing

oscillator utilizing an external crystal for timing back-up,

clock/calendar registers, intelligent battery back-up

switching, battery voltage monitor, brownout indicator,

integrated trickle charger for super capacitor, single periodic

or polled alarms, POR supervisory function, and up to 4

Event Detect with time stamp. There are 128 bytes of

battery-backed user SRAM.

• Redundant Crystal Clock Input Selectable by User

- Dynamically Switch from AC Clock Input to Crystal in

Case of Power Failure

• Real Time Clock/Calendar

- Tracks Time in Hours, Minutes, Seconds and Tenths of

a Second

- Day of the Week, Day, Month, and Year

The oscillator uses a 50/60 cycle sine wave input, backed by

an external, low-cost, 32.768kHz crystal. The real time clock

tracks time with separate registers for hours, minutes, and

seconds. The calendar registers contain the date, month,

year, and day of the week. The calendar is accurate through

year 2100, with automatic leap year correction and auto

daylight savings correction.

• Auto Daylight Saving Time Correction

- Programmable Forward and Backward Dates

• Security and Event Functions

- Event Detection with Time Stamp

- Stores First and Last Three Event Time Stamps

• Separate F

OUT

- 7 Selectable Frequency Outputs

Pinout

• Dual Alarms with Hardware and Register Indicators

- Hardware Single Event or Pulse Interrupt Mode

ISL12032

(14 LD TSSOP)

TOP VIEW

• Automatic Backup to Battery or Super Capacitor

- VBAT Operation Down to 1.8V

14

13

12

X1

X2

V

DD

1

2

- 1.0µA Battery Supply Current

IRQ

• Two Battery Status Monitors with Selectable Levels

- Seven Selectable Voltages for Each Level

- 1st Level, Trip Points from 4.675V to 2.125V

- 2nd Level, Trip Points from 4.125V to 1.875V

3

4

5

VBAT

GND

AC

SCL

11

SDA

10

9

ACRDY

• V

DD

Power Brownout Monitor

6

7

LV

F

OUT

- Six Selectable Trip Levels, from 4.675V to 2.295V

8

• Time Stamp during Power-to-Battery and

Battery-to-Power Switchover

EVIN

EVDET

• Integrated Trickle Charger

- Four Selectable Charging Rates

• 128 Bytes Battery-Backed User SRAM

2

• I C Interface

- 400kHz Data Transfer Rate

• Pb-free (RoHS compliant)

Applications

• Utility Meters

• Control Applications

• Security Related Applications

• Vending Machines

• White Goods

• Consumer Electronics

FN6618 Rev 3.00

May 5, 2011

Page 1 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

TEMP RANGE

PACKAGE

(Pb-free)

PART MARKING

12032 IVZ

V

RANGE

(°C)

PKG DWG #

M14.173

DD

ISL12032IVZ

NOTE:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2.7V to 5.5V

-40 to +85

14 Ld TSSOP

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12032. For more information on MSL please see techbrief

TB363.

Block Diagram

SDA

SCL

SECONDS

MINUTES

HOURS

BUFFER

2

I C

CONTROL

LOGIC

REGISTERS

INTERFACE

SCL

BUFFER

DAY OF WEEK

DATE

X1

X2

CRYSTAL

OSCILLATOR

RTC

DIVIDER

MONTH

V

POR/LV

COMPARE

DD

YEAR

FREQUENCY

OUT

ALARM

CONTROL

REGISTERS

V

TRIP

USER

SRAM

SWITCH

INTERNAL

SUPPLY

VBAT

AC

IRQ

F

OUT

LV

AC INPUT

BUFFER

AC POWER

QUALITY

EVALUATE

ACRDY

EVDET

EVIN

GND

FN6618 Rev 3.00

May 5, 2011

Page 2 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Functional Pin Descriptions

NUMBER

SYMBOL

DESCRIPTION

1

X1

The input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal.

X1 also can be driven directly from a 32.768kHz source with no crystal connected.

2

3

X2

The output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal.

X2 should be left open when X1 is driven from an external source.

VBAT

Battery Voltage. This pin provides a backup supply voltage to the device. VBAT supplies power to the device in the

event that the V

supply fails. This pin should be tied to ground if not used.

DD

4

5

6

7

GND

AC

Ground.

AC Input. The AC input pin accepts either 50Hz of 60Hz AC 2.5V

sine wave signal.

P-P

LV

Low Voltage detection output/Brownout Alarm. Open drain active low output.

EVIN

Event Input - The EVIN is a logic input pin that is used to detect an externally monitored event. When a high signal

is present at the EVIN pin, an “event” is detected.

8

9

EVDET

Event Detect Output. Active when EVIN is triggered. Open Drain active low output.

Frequency Output. Register selectable frequency clock output. CMOS output levels.

AC Ready. Open Drain output. When High, AC input signal is qualified for timing use.

F

OUT

10

11

ACRDY

SDA

Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain

output and may be wire OR’ed with other open drain or open collector outputs.

12

13

14

SCL

IRQ

Serial Clock. The SCL input is used to clock all serial data into and out of the device.

Interrupt Output. Open Drain active low output. Interrupt output pin to indicate alarm is triggered.

Power supply.

V

DD

FN6618 Rev 3.00

May 5, 2011

Page 3 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Absolute Maximum Ratings Thermal Information

Voltage on V , VBAT, SCL, SDA, ACRDY, AC, LV, EVDET, EVIN,

DD

Thermal Resistance (Typical, Note 4)



(°C/W)

110

JA

IRQ, F

pins

OUT

14 Ld TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on X1 and X2 pins

(respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

A

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

DD

Supply Voltage (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

4.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

DC Operating Characteristics Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface

DD

A

limits apply over the operating temperature range, -40°C to +85°C.

MIN TYP

MAX

(Note 13) (Note 7) (Note 13) UNITS

SYMBOL

PARAMETER

Main Power Supply

CONDITIONS

NOTES

V

2.7

1.8

5.5

60

V

DD

VBAT

Battery Supply Voltage

Supply Current

V

I

V

= 5V, SCL, SDA = V

= 3V, SCL, SDA = V

= 5V

27

16

43

µA

6

DD1

DD

45

DD

2

I

SupplyCurrent(I CCommunications

75

5, 8

DD2

DD3

Active)

Supply Current for Timekeeping

at AC Input

V

= 5.5V at T = +25°C,

9.0

18.0

µA

5, 6

DD

A

F

disabled

OUT

IBAT

Battery Supply Current

VBAT = 5.5V at T = +25°C

A

1.0

0.8

0.7

1.8

1.2

1.0

100

5, 11

VBAT = 2.7V

VBAT = 1.8V

µA

nA

IBAT

Battery Input Leakage

V

= 5.5V, VBAT = 1.8V

LKG

DD

TRKEN = 0

I

Input Leakage Current on SCL

I/O Leakage Current on SDA

Battery Level Monitor Threshold

Brownout Level Monitor Threshold

VBAT Mode Threshold

1

µA

mV

V

LI

I

1

LO

VBAT

V

= 5.5V, VBAT = 1.8V

DD

-150

2.0

+150

2.4

M

V

PBM

V

2.2

30

TRIP

V

Hysteresis

TRIP

mV



TRIPHYS

VBAT

VBAT Hysteresis

50

HYS

RTRK

Trickle Charge Resistance

V

= 5.5V, VBAT = 3.0V,

1300

DD

TRKR01 = 0, TRKR00 = 0

V

= 5.5V, VBAT = 3.0V,

2200

3600

7800



V

DD

TRKR01 = 0, TRKR00 = 1

V

= 5.5V, VBAT = 3.0V,

DD

TRKR01 = 1, TRKR00 = 0

V

= 5.5V, VBAT = 3.0V,

DD

TRKR01 = 1, TRKR00 = 1

VTRKTERM

VBAT Charging Termination Point

VDD -

50mV

FN6618 Rev 3.00

May 5, 2011

Page 4 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

DC Operating Characteristics Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface

DD

A

limits apply over the operating temperature range, -40°C to +85°C. (Continued)

MIN TYP MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 13) (Note 7) (Note 13) UNITS

NOTES

VTRKHYS

Trickle Charge ON-OFF Hysteresis

50

mV

IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS)

Output Low Voltage

V

= 5V, I = 3mA

OL

0.4

V

OL

DD

= 2.7V, I = 1mA

OL

F

(CMOS OUTPUT)

OUT

V

Output Low Voltage

Output High Voltage

I

= 1mA

0.3 x V

DD

V

OL

OH

V

0.7 x V

OH

DD

EVIN

I

EVIN Pull-up Current

V

= 5.5V, VBAT = 3.0V

= 0V, VBAT = 1.8V

1.0

3.0

8.0

600

µA

nA

V

EVPU

DD

100

V

Input Low Voltage

0.3 x V

IL

DD

V

Input High Voltage

0.7 x V

V

IH

DD

EVIN Disabled Pull-down Current

V

= 5.5V

200

nA

EVPD

DD

Power-Down Timing Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface limits apply over

DD

A

the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 13) (Note 7) (Note 13) UNITS

NOTES

V

Negative Slew Rate

DD

10 V/ms

9

DD SR-

2

I C Interface Specifications Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface limits

DD

A

apply over the operating temperature range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 13)

(Note 7) (Note 13) UNITS NOTES

V

SDA and SCL Input Buffer LOW

Voltage

-0.3

0.3 x V

V

IL

DD

V

SDA and SCL Input Buffer HIGH

Voltage

0.7 x V

V

DD

+ 0.3

IH

DD

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x V

V

DD

V

SDA Output Buffer LOW Voltage,

Sinking 3mA

V

= 5V, I = 3mA

DD OL

0.4

V

OL

C

SDA and SCL Pin Capacitance

T

= +25°C, f = 1MHz,

10

pF

A

V

= 5V, V = 0V,

IN

DD

= 0V

OUT

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression Time at Any pulse narrower than the

IN

SDA and SCL Inputs

max spec is suppressed.

t

SCL Falling Edge to SDA Output

Data Valid

SCL falling edge crossing

30% of V , until SDA exits

DD

900

ns

AA

the 30% to 70% of V

DD

window.

t

Time the Bus Must be Free Before SDA crossing 70% of V

the Start of a New Transmission

1300

ns

BUF

DD

during a STOP condition, to

SDA crossing 70% of V

DD

during the following START

condition.

FN6618 Rev 3.00

May 5, 2011

Page 5 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

2

I C Interface Specifications Specifications apply for: V = 2.7V to 5.5V, T = -40°C to +85°C, unless otherwise stated. Boldface limits

DD

A

apply over the operating temperature range, -40°C to +85°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

Clock LOW Time

TEST CONDITIONS

(Note 13)

(Note 7) (Note 13) UNITS NOTES

t

Measured at the 30% of V

crossing.

1300

600

ns

LOW

DD

t

Clock HIGH Time

Measured at the 70% of V

crossing.

ns

HIGH

DD

t

START Condition Setup Time

SCL rising edge to SDA

600

SU:STA

falling edge. Both crossing

70% of V

.

DD

From SDA falling edge

crossing 30% of V to SCL

t

START Condition Hold Time

Input Data Setup Time

600

100

0

ns

HD:STA

DD

falling edge crossing 70% of

V

.

DD

From SDA exiting the 30% to

70% of V window, to SCL

SU:DAT

HD:DAT

SU:STO

HD:STO

DD

rising edge crossing 30% of

V

DD.

From SCL falling edge

crossing 30% of V to SDA

t

Input Data Hold Time

900

ns

DD

entering the 30% to 70% of

window.

V

DD

t

STOP Condition Setup Time

From SCL rising edge

crossing 70% of V , to SDA

DD

rising edge crossing 30% of

600

V

.

DD

t

STOP Condition Hold Time

Output Data Hold Time

From SDA rising edge to

SCL falling edge. Both

600

0

ns

crossing 70% of V

.

DD

t

From SCL falling edge

DH

crossing 30% of V , until

DD

SDA enters the 30% to 70%

of V

window.

DD

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of V

From 70% to 30% of V

20 + 0.1 x Cb

300

400

ns

10, 12

R

DD.

t

20 + 0.1 x Cb

F

Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip

10

1

pF

k

R

SDA and SCL Bus Pull-up Resistor Maximum is determined by

PU

Off-chip

t and t .

R F

For Cb = 400pF, max is about

2k.

For Cb = 40pF, max is about

15k

NOTES:

5. IRQ and F

Inactive.

OUT

6. V

> VBAT +V

DD

BATHYS

7. Specified at T =+25°C.

A

8. F

= 400kHz.

SCL

9. In order to ensure proper timekeeping, the V

10. Parameter is not 100% tested.

specification must be followed.

DD SR-

11. V

= 0V. I

increases at V

voltages between 0.5V and 1.5V.

DD

BAT

2

12. These are I C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.

13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN6618 Rev 3.00

May 5, 2011

Page 6 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

SDA vs SCL Timing

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

HD:DAT

t

SU:STA

SU:STO

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

DH

t

AA

SDA

(OUTPUT TIMING)

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

Must be steady

Will be steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes Allowed

Changing:

State Not Known

N/A

Center Line is

High Impedance

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

5.0V

= 5V

DD

FOR V = 0.4V

OL

1533

AND I

= 3mA

OL

SDA

AND

IRQ/F

OUT

100pF

FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE

DEVICE WITH V = 5.0V

DD

FN6618 Rev 3.00

May 5, 2011

Page 7 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

General Description

Pin Descriptions

The ISL12032 device is a low power real time clock with 50/60

AC input for timing synchronization. It also has an oscillator

utilizing an external crystal for timing back-up, clock/calendar

registers, intelligent battery back-up switching, battery voltage

monitor, brownout indicator, integrated trickle charger for super

capacitor, single periodic or polled alarms, POR supervisory

function, and up to 4 Event Detect with time stamp. There are

128 bytes of battery-backed user SRAM.

X1, X2

The X1 and X2 pins are the input and output, respectively, of

an inverting amplifier. An external 32.768kHz quartz crystal is

used with the device to supply a backup timebase for the real

time clock if there is no AC input. The device also can be

driven directly from a 32.768kHz source at pin X1, in which

case, pin X2 should be left unconnected. No external load

capacitors are needed for the X1 and X2 pins.

The oscillator uses a 50/60 cycle sine wave input, backed by

an external, low-cost, 32.768kHz crystal. The real time clock

tracks time with separate registers for hours, minutes, and

seconds. The calendar registers contain the date, month, year,

and day of the week. The calendar is accurate through year

2100, with automatic leap year correction and auto daylight

savings correction.

X1

X2

FIGURE 2. RECOMMENDED CRYSTAL CONNECTION

The ISL12032’s alarm can be set to any clock/calendar value

for a match. Each alarm’s status is available by checking the

Status Register. The device also can be configured to provide

a hardware interrupt via the IRQ pin. There is a repeat mode

for the alarms allowing a periodic interrupt every minute, every

hour, every day, etc.

VBAT (Battery Input)

This input provides a backup supply voltage to the device.

VBAT supplies power to the device in the event that the VDD

supply fails. This pin can be connected to a battery, a Super

Capacitor or tied to ground if not used.

The device also offers a backup power input pin. This VBAT

pin allows the device to be backed up by battery or Super

AC (AC Input)

The AC input is the main clock input for the real time clock. It

can be either 50Hz or 60Hz, sine wave. The preferred

amplitude is 2.5V , although amplitudes >0.25V

Capacitor with automatic switchover from V

to VBAT. The

DD

= 2.7V to 5.5V and the

ISL12032 devices are specified for V

DD

are

P-P

DD

clock/calendar portion of the device remains fully operational in

battery backup mode down to 1.8V (Standby Mode). The VBAT

level is monitored and warnings are reported against

preselected levels. The first report is registered when the VBAT

level falls below 85% of nominal level, the second level is set

for 75% of nominal level. Battery levels are stored in the

PWRBAT registers.

acceptable. An AC coupled (series capacitor) sine wave clock

waveform is desired as the AC clock input provides DC

biasing.

LV (Low Voltage)

This pin indicates the VDD supply is below the programmed

level. This signal notifies a host processor that the main supply

is low and requests action. It is an open drain active LOW

output.

The ISL12032 offers a “Brownout” alarm once the V

falls

DD

below a pre-selected trip level. In the ISL12032, this allows the

system microcontroller to save vital information to memory

EVIN (Event Input)

before complete power loss. There are six V

the brownout alarm.

trip levels for

DD

The EVIN pin input detects an externally monitored event.

When a HIGH signal is present at the EVIN pin, an “event” is

detected.This input may be used for various monitoring

functions, such as the opening of a detection switch on a

chassis or door. The event detection circuit can be user

enabled or disabled (see EVIN bit) and provides the option to

be operational in battery backup modes (see EVATB bit).

When the event detection is disabled, the EVIN pin is gated

OFF. See “Functional Pin Descriptions” on page 3 for more

details.

The event detection function accepts a normally low logic

input, and when triggered will store the time/date information

for the event. The first event is stored in the memory until reset;

subsequent events are stored on-chip memory and the last 3

events are retained and accessible by performing an indexed

register read.

EVDET (Event Detect Output)

The EVDET is an open drain output, which will go low when an

event is detected at the EVIN pin. If the event detection

function is enabled, the EVDET output will go LOW and stay

there until the EVT bit is cleared.

FN6618 Rev 3.00

May 5, 2011

Page 8 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

IRQ (Interrupt Output)

Battery Backup Mode (VBAT) to Normal Mode (V )

DD

This pin provides an interrupt signal output. This signal notifies

a host processor that an alarm has occurred and requests

action. It is an open drain active LOW output.

The ISL12032 device will switch from the VBAT to V

when one of the following conditions occurs:

mode

DD

Condition 1:

F

(Frequency Output)

V

> VBAT + V

BATHYS

OUT

DD

where V

This pin outputs a clock signal, which is related to the crystal

frequency. The frequency output is user selectable and

enabled via the I C bus. The options include seven different

50mV

BATHYS

Condition 2:

2

V

> V

+ V

DD

where V

TRIP TRIPHYS

frequencies or disable. It is a CMOS output.

 30mV

TRIPHYS

Serial Clock (SCL)

These power control situations are illustrated in Figures 3 and

Figure 4.

The SCL input is used to clock all serial data into and out of the

device. The input buffer on this pin is always active (not gated).

It is disabled when the backup power supply on the VBAT pin

is activated to minimize power consumption.

BATTERY BACKUP

MODE

Serial Data (SDA)

V

DD

SDA is a bi-directional pin used to transfer data into and out of

the device. It has an open drain output and may be OR’ed with

other open drain or open collector outputs. The input buffer is

always active (not gated) in normal mode.

V

TRIP

2.2V

1.8V

VBAT

VBAT + V

BATHYS

VBAT - V

BATHYS

An open drain output requires the use of a pull-up resistor. The

output circuitry controls the fall time of the output signal with

the use of a slope controlled pull-down. The circuit is designed

FIGURE 3. BATTERY SWITCHOVER WHEN VBAT < V

TRIP

2

for 400kHz I C interface speeds. It is disabled when the

backup power supply on the VBAT pin is activated.

V

, GND

DD

Chip power supply and ground pins. The device will operate

with a power supply from V = 2.7V to 5.5VDC. A 0.1µF

BATTERY BACKUP

MODE

DD

V

DD

capacitor is recommended on the V

pin to ground.

DD

VBAT

3.0V

Functional Description

V

2.2V

TRIP

Power Control Operation

V

+ V

TRIPHYS

TRIP

The power control circuit accepts a V

and a VBAT input.

DD

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and battery sizes are available that can power the

ISL12032 for up to 10 years. Another option is to use a Super

FIGURE 4. BATTERY SWITCHOVER WHEN VBAT > V

TRIP

2

The I C bus is normally deactivated in battery backup mode to

reduce power consumption, but can be enabled by setting the

Capacitor for applications where V

is interrupted for up to a

DD

2

I CBAT bit. All the other inputs and outputs of the ISL12032 are

active during battery backup mode unless disabled via the

control register.

month. See the “Application Section” on page 24 for more

information.

Normal Mode (V ) to Battery Backup Mode (VBAT)

DD

Power Failure Detection

To transition from the V

to VBAT mode, both of the following

DD

The ISL12032 provides a Real Time Clock Failure Bit (RTCF)

to detect total power failure. It allows users to determine if the

device has powered up after having lost all power to the device

conditions must be met:

Condition 1:

V

< VBAT - V

BATHYS

(both V

and VBAT very near 0.0VDC). Note that in cases

where the VBAT input is at 0.0V and the V input dips to

DD

where V

DD

 50mV

BATHYS

Condition 2:

DD

<1.8V, then recovers to normal level, the SRAM registers may

not retain their values (corrupted bits or bytes may result).

V

< V

DD

TRIP

where V

 2.2V

FN6618 Rev 3.00

May 5, 2011

Page 9 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

The pulsed interrupt mode (setting the IM bit to “1”) activates a

Brownout Detection

repetitive or recurring alarm. Hence, once the alarm is set, the

device will continue to output a pulse for each occurring match

of the alarm and present time. The Alarm pulse will occur as

often as every minute (if only the nth second is set) or as

infrequently as once a year (if at least the nth month is set).

During pulsed interrupt mode, the IRQ pin will be pulled LOW

for 250ms and the alarm status bit (ALM0 or ALM1) will be set

to “1”.

The ISL12032 monitors the V

level continuously and

DD

level drops below prescribed

provides a warning if the V

DD

levels. There are six levels that can be selected for the trip

level. These values are 85% below popular V levels. The

DD

LVDD bit in the SRDC register will be set to “1” when Brownout

2

is detected. Note that the I C serial bus remains active until the

Battery V

TRIP

level is reached.

Battery Level Monitor

The alarm function is not available during battery backup

mode.

The ISL12032 has a built in warning feature once the VBAT

battery level drops first to 85% and then to 75% of the battery’s

nominal VBAT level. When the battery voltage falls to between

85% and 75%, the LBAT85 bit is set in the SRDC register.

When the level drops below 75%, both LBAT85 and LBAT75

bits are set in the SRDC register. The trip levels for the 85%

and 75% levels are set using the PWRBAT register.

Frequency Output Mode

The ISL12032 has the option to provide a clock output signal

using the F

CMOS output pin. The frequency output mode

OUT

is set by using the FO bits to select 7 possible output frequency

values from 1.0Hz to 32.768kHz, and disable. The frequency

output can be enabled/disabled during battery backup mode by

setting the FOBATB bit to “0”. When the AC input is qualified

(within the parameters of AC qualification) then the Frequency

Output for values 50/60Hz and below are derived from the AC

The Battery Timestamp Function permits recovering the

time/date when V

power loss occurred. Once the V

is low

DD

enough to enable switchover to the battery, the RTC time/date

are written into the TSV2B section. If there are multiple power-

down cycles before reading these registers, the first values

stored in these registers will be retained and ensuing events

will be ignored. These registers will hold the original power-

down value until they are cleared by writing “00h” to each

register or setting the CLRTS bit to “1”.

input clock. Higher frequency F

values are derived from

OUT

the crystal. If the AC clock input is not qualified, then all F

values are derived from the crystal.

OUT

General Purpose User SRAM

The ISL12032 provides 128 bytes of user SRAM. The SRAM

will continue to operate in battery backup mode. However, it

The V

DD

Timestamp Function permits recovering the time/date

recovery occurred. Once the V is high enough to

2

when V

should be noted that the I C bus is disabled in battery backup

DD

2

enable switchover to V , the RTC time/date are written into

mode unless enabled by the I CBAT bit.

DD

the TSB2V register. If there are multiple power-down cycles

before reading these registers, the most recent event is

retained in these registers and the previous events will be

ignored. These registers will hold the original power-down

value until they are cleared by writing “00h” to each register.

2

I C Serial Interface

2

The ISL12032 has an I C serial bus interface that provides

access to the control and status registers and the user SRAM.

The I C serial interface is compatible with other industry I C

serial bus protocols using a bi-directional data signal (SDA)

and a clock signal (SCL).

2

Real Time Clock Operation

The Real Time Clock (RTC) maintains an accurate internal

representation of tenths of a second, second, minute, hour, day

of week, date, month, and year. The RTC also has leap-year

correction. The clock also corrects for months having fewer

than 31 days and has a bit that controls 24 hour or AM/PM

format. When the ISL12032 powers up after the loss of both

2

The I C bus normally operates down to the V

trip point set

DD

in the PWRVDD register. It can also operate in battery backup

mode by setting the I2CBAT bit to “1”, in which case operation

will be down to VBAT = 1.8V.

Register Descriptions

The battery-backed registers are accessible following an I C

V

and VBAT, the clock will not begin incrementing until at

DD

2

least one byte is written to the clock register.

slave byte of “1101 111x” and reads or writes to addresses

[00h:47h]. The defined addresses and default values are

described in the Table 1. The battery backed general purpose

SRAM has a different slave address (1010 111x), so it is not

possible to read/write that section of memory while accessing

the registers.

Alarm Operation

The alarm mode is enabled via the MSB bit. Single event or

interrupt alarm mode is selected via the IM bit. The standard

alarm allows for alarms of time, date, day of the week, month,

and year. When a time alarm occurs in single event mode, the

IRQ pin will be pulled low and the corresponding alarm status

bit (ALM0 or ALM1) will be set to “1”. The status bits can be

written with a “0” to clear, or if the ARST bit is set, a single

read of the SRDC status register will clear them.

REGISTER ACCESS

The contents of the registers can be modified by performing a

byte or a page write operation directly to any register address.

The registers are divided into 10 sections. They are:

Page 10 of 26

FN6618 Rev 3.00

May 5, 2011

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

1. Real Time Clock (8 bytes): Address 00h to 07h.

2. Status (2 bytes): Address 08h to 09h.

3. Counter (2 bytes): Address Ah to Bh.

4. Control (9 bytes): 0Ch to 14h.

5. Day Light Saving Time (8 bytes): 15h to 1Ch

6. Alarm 0/1 (12 bytes): 1Dh to 28h

7. Time Stamp for Battery Status (5 bytes): Address 29h to

2Dh.

8. Time Stamp for VDD Status (5 bytes): Address 2Eh to 32h.

9. Time Stamp for Event Status (5 bytes): 33h to 37h.

Write capability is allowable into the RTC registers (00h to 07h)

only when the WRTC bit (bit 6 of address 0Ch) is set to “1”.

Other sections do not need to have the WRTC bit set for write

access. A read or write can begin at any address within the

section. A write to sections 2 through 9 can be continuous. A

write can overlap two or more sections as well.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a

sequential read. For the RTC and Alarm registers, the read

instruction latches all clock registers into a buffer, so an update

of the clock does not change the time being read. At the end of

a read, the master supplies a stop condition to end the

operation and free the bus. After a read, the address remains

at the previous address +1 so the user can execute a current

address read and continue reading the next register.

It is only necessary to set the WRTC bit prior to writing into the

RTC registers. All other registers are completely accessible

without setting the WRTC bit.

FN6618 Rev 3.00

May 5, 2011

Page 11 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device)

BIT

REG

ADDR SECTION NAME

7

6

5

SC21

MN21

HR21

DT21

0

4

3

SC13

MN13

HR13

DT13

MO13

YR13

0

2

1

0

RANGE DEFAULT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

SC

MN

0

SC22

SC20

SC12

SC11

SC10

0 to 59

0 to 23

1 to 31

1 to 12

0 to 99

0 to 6

0 to 9

N/A

00h

01h

00h

01h

00h

01h

00h

04h

00h

01h

02h

10h

00h

01h

02h

00h

01h

00h

0

MN22

MN20

HR20

DT20

MN12

MN11

MN10

HR

MIL

0

HR12

HR11

HR10

DT

0

DT12

DT11

DT10

RTC

MO

0

MO20

YR20

MO12

YR12

MO11

MO10

YR

YR23

YR22

YR21

0

YR11

YR10

DW

0

DW2

DW1

DW0

SS

0

BMODE

X

0

SS3

SS2

SS1

SS0

SRDC

SRAC

ACCNT

EVTCNT

INT

DSTADJ

ALM1

X

ALM0

XOSCF

AXC4

EVC4

X

LVDD

X

LBAT85

X

LBAT75

ACFAIL

AXC1

RTCF

Status

X

ACRDY

AXC0

N/A

AXC7

EVC7

ARST

X

AXC6

AXXC5

EVC5

IM

AXC3

EVC3

X

AXC2

0 to 127

N/A

Counter

EVC6

EVC2

EVC1

EVC0

WRTC

X

ALE1

ALE0

FO

X

FOBATB

EVEN

X

FO2

FO1

FO0

N/A

EVIC

X

EVBATB

EVIM

X

EHYS1

X

EHYS0

0

ESMP1

EVIX1

ESMP0

EVIX0

N/A

EVIX

X

N/A

Control

TRICK

PWRVDD

PWRBAT

AC

X

TRKEN

VDDTrip2

BV75Tp2

ACFP0

XDTR2

MoFd12

DwFd12

DtFd12

HrFd12

MoRv12

DwRv12

DtRv12

HrRv12

SCA012

MNA011

HRA012

DTA012

MOA012

DWA02

TRKRO1

VDDTrip1

VB75Tp1

ACFC1

XDTR1

MoFd11

DwFd11

DtFd11

HrFd11

MoRv11

DwRv11

DtRv11

HrRv11

SCA011

MNA011

HRA011

DTA011

MOA011

DWA01

TRKRO0

VDDTrip0

VB75Tp0

ACFC0

XDTR0

MoFd10

DwFd10

DtFd10

HrFd10

MoRv10

DwRv10

DtRv10

HrRv10

SCA010

MNA010

HRA010

DTA010

MOA010

DWA00

N/A

CLRTS

X

I2CBAT

VB85Tp2

ACRP1

X

LVENB

VB85Tp1

ACRP0

ACMIN

MoFd20

WkFd11

DtFd20

HrFd20

MoRv20

WkRv11

DtRv20

HrRv20

SCA020

MNA013

HRA020

DTA020

MOA020

0

X

N/A

BHYS

VB85Tp0

ACFP1

XDTR3

MoFd13

WkFd10

DtFd13

HrFd13

MoRv13

WkRv10

DtRv13

HrRv13

SCA013

MNA012

HRA013

DTA013

MOA013

0

N/A

AC5060

X

ACENB

N/A

FTR

X

N/A

DstMoFd

DstDwFd

DstDtFd

DstHrFd

DstMoRv

DstDwRv

DstDtRv

DstHrRv

SCA0

MNA0

HRA0

DTA0

DSTE

0

1 to 12

0 to 6

1 to 31

0 to 23

1 to 12

0 to 6

1 to 31

0 to 23

0 to 59

0 to 23

1 to 31

1 to 12

0 to 6

DwFdE

WkFd12

DtFd21

HrFd21

0

HrFdMIL

0

DSTCR

0

DwRvE

WkRv12

DtRv21

HrRv21

SCA021

MNA020

HRA021

DTA021

0

HrRvMIL

ESCA0

EMNA0

EHRA0

EDTA0

EMOA0

EDWA0

0

SCA022

MNA021

0

Alarm0

MOA0

DWA0

0

FN6618 Rev 3.00

May 5, 2011

Page 12 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 1. REGISTER MEMORY MAP (X indicates writes to these bits have no effect on the device) (Continued)

BIT

REG

ADDR SECTION NAME

7

6

5

4

3

2

1

0

RANGE DEFAULT

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

SCA1

MNA1

HRA1

DTA1

MOA1

DWA1

SCVB

MNVB

HRVB

DTVB

MOVB

SCBV

MNBV

HRBV

DTBV

MOBV

SCT

ESCA1

SCA122

SCA121

MNA121

HRA121

DTA121

0

SCA120

MNA120

HRA120

DTA120

MOA120

0

SCA113

MNA113

HRA113

DTA113

MOA113

0

SCA112

MNA112

HRA112

DTA112

MOA112

DWA12

SCVB12

MNVB12

HRVB12

DTVB12

MOVB12

SCBV12

MNBV12

HRBV12

DTBV12

MOBV12

SCT12

SCA111

MNA111

HRA111

DTA111

MOA111

DWA11

SCVB11

MNVB11

HRVB11

DTVB11

MOVB11

SCBV11

MNBV11

HRBV11

DTBV11

MOBV11

SCT111

MNT11

SCA110

MNA110

HRA110

DTA110

MOA110

DWA10

SCVB10

MNVB10

HRVB10

DTVB10

MOVB10

SCBV10

MNBV10

HRBV10

DTBV10

MOBV10

SCT10

0 to 59

0 to 23

1 to 31

1 to12

0 to 6

00h

01h

00h

EMNA1

MNA122

EHRA1

0

Alarm1

EDTA1

0

EMOA1

0

EDWA1

0

X

SCBV22

SCBV21

MNVB21

HRVB21

DTVB21

X

SCBV20

MNVB20

HRVB20

DTVB20

MOVB20

SCBV20

MNBV20

HRBV20

DTBV20

MOBV20

SCT20

SCVB13

MNVB13

HRVB13

DTVB13

MOVB13

SCBV13

MNBV13

HRBV13

DTBV13

MOBV13

SCT13

0 to 59

0 to 23

1 to 31

1 to 12

0 to 59

0 to 23

1 to 31

1 to 12

0 to 59

0 to 23

1 to 31

1 to 12

X

MNVB22

TSV2B

TSB2V

TSEVT

MILVB

X

SCBV22

SCBV21

MNBV21

HRBV21

DTBV21

X

MNBV22

MILBV

X

SCT22

SCT21

MNT21

HRT21

DTT21

X

MNT

X

MNT22

MNT20

HRT20

MNT13

HRT13

MNT12

MNT10

HRT10

HRT

MILT

X

HRT12

HRT11

DTT

DTT20

DTT13

DTT12

DTT11

DTT10

MOT

X

MOT20

MOT13

MOT12

MOT11

MOT10

representing PM. The clock defaults to 12-hour format time

with HR21 = “0”.

Real Time Clock Registers

Addresses [00h to 07h]

LEAP YEARS

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW, SS)

Leap years add the day February 29 and are defined as those

years that are divisible by 4. Years divisible by 100 are not leap

years, unless they are also divisible by 400. This means that the

year 2000 is a leap year and the year 2100 is not. The ISL12032

does not correct for the leap year in the year 2100.

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR

(Hour) can be either 12-hour or 24-hour mode, DT (Date) is 1 to

31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, DW (Day of the

Week) is 0 to 6, and SS (Sub-Second) is 0 to 9. The Sub-

Second register is read-only and will clear to “0” count each time

there is a write to a register in the RTC section.

Status Registers (SR)

Addresses [08h to 09h]

The DW register provides a Day of the Week status and uses

three bits DW2 to DW0 to represent the seven days of the week.

The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2....

The assignment of a numerical value to a specific day of the

week is arbitrary and may be decided by the system software

designer. The default value is defined as “0”.

The Status Registers consist of the DC and AC status registers

(see Tables 2 and 3).

Status Register (SRDC)

The Status Register DC is located in the memory map at

address 08h. This is a volatile register that provides status of

RTC failure (RTCF), Battery Level Monitor (LBAT85, LBAT75),

24 HOUR TIME

V

level monitor (LVDD), Alarm0 or Alarm1 trigger, Daylight

DD

Saving Time adjustment, and Battery active mode.

If the MIL bit of the HR register is “1”, the RTC uses a 24-hour

format. If the MIL bit is “0”, the RTC uses a 12-hour format and

HR21 bit functions as an AM/PM indicator with a “1”

FN6618 Rev 3.00

May 5, 2011

Page 13 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Status Register (SRAC)

TABLE 2. STATUS REGISTER DC (SRDC)

TABLE 3. STATUS REGISTER AC (SRAC)

ADDR

7

6

5

4

3

2

1

0

ADDR

7

6

5

4

3

2

1

0

08h

BMODE DSTADJ ALM1 ALM0 LVDD LBAT85 LBAT75 RTCF

09h

X

XOSCF

X

ACFAIL ACRDY

BATTERY ACTIVE MODE (BMODE)

BMODE Indicates that the device is operating from the VBAT

input. A “1” indicates Battery Mode and a “0” indicates power

The Status Register AC is located in the memory map at

address 09h. This is a volatile register that provides status of

Crystal Failure (XOSCF), AC Failed (ACFAIL) and AC Ready

(ACRDY).

from V

mode. The I2CBAT bit must be set to “1” and the

DD

device must be in VBAT mode in order for a valid “1” read from

this bit.

CRYSTAL OSCILLATOR FAIL BIT (XOSCF)

DAYLIGHT SAVING TIME ADJUSTMENT BIT (DSTADJ)

Indicates Crystal Oscillator has stopped if XOSCF = 1. When

the crystal oscillator has resumed operation, the XOSCF bit is

reset to “0”.

DSTADJ is the Daylight Saving Time Adjustment Bit. It

indicates that daylight saving time adjustment has happened.

The bit will be set to “1” when the Forward DST event has

occurred. The bit will stay set until the Reverse DST event has

happened. The bit will also reset to “0” when the DSTE bit is

set to “0” (DST function disabled). The bit can be forced to “1”

with by writing “F0h” to the Status Register. The default value

for DSTADJ is “0”.

AC FAIL (ACFAIL)

This bit announces the status of the AC input. If ACFAIL = 1,

then the AC input frequency and amplitude qualification check

has failed. ACFAIL is reset to “0” when the AC input meets the

preset requirements (see “AC (AC Input)” on page 8).

ALARM BITS (ALM0 AND ALM1)

AC READY (ACRDY)

These bits announce if an alarm matches the real time clock. If

there is a match, the respective bit is set to “1”. This bit can be

manually reset to “0” by the user or automatically reset by

enabling the auto-reset bit (see ARST bit). A write to this bit in

the SR can only set it to “0”, not “1”. An alarm bit that is set by an

alarm occurring during an SR read operation will remain set after

the read operation is complete.

This bit announces the status of the AC input. If ACRDY = 1,

then the AC input has passed the qualification parameter

check (as set by ACFC and ACFP bits) for the time prescribed

by ACRP and is used for the RTC clock. When ACRDY = 0 the

AC input failed the qualification requirements and the crystal

oscillator clock is used for the RTC clock (see “AC (AC Input)”

on page 8).

LOW V

INDICATOR BIT (LVDD)

Indicates V dropped below the pre-selected trip level.

When ACFAIL transitions from “1” to “0” (from failed to pass),

then the timer set by ACRP will determine the delay until

ACRDY transitions from “0” to “1”. ACRDY will be set to “0”

immediately after ACRDY is set to “0” (failed AC input),

indicating the crystal oscillator is the RTC clock.

DD

(Brownout Mode). The Trip points for Brownout levels are

selected by three bits VDDTrip2, VDDTrip1 and VDDTrip0 in

the PWRVDD registers.

LOW BATTERY INDICATOR 85% BIT (LBAT85)

Counter Registers

Indicates battery level dropped below the pre-selected trip

level (85% of battery voltage). The trip point is set by three bits:

VB85Tp2, VB85Tp1 and VB85Tp0 in the PWRBAT register.

Addresses [0Ah to 0Bh]

These registers will count the number of times AC failure

occurs and the number of times an event occurs. These

registers are 8-bits each and will count up to 255.

LOW BATTERY INDICATOR 75% BIT (LBAT75)

Indicates battery level dropped below the pre-selected trip

level (75% of battery voltage). The trip point is set by three bits:

VB75Tp2, VB75Tp1 and VB75Tp0 in the PWRBAT register.

AC COUNT (ACCNT)

TABLE 4. AC COUNTER REGISTER (ACCNT)

ADDR

7

6

5

4

3

2

1

0

REAL TIME CLOCK FAIL BIT (RTCF)

0Ah

AXC7 AXC6 AXC5 AXC4 AXC3 AXC2 AXC1 AXC0

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (internally) when the device

The ACCNT register increments automatically each time the

AC input switches to the crystal backup. The register is set to

00h on initial power-up. The maximum count is 255, and will

powers up after having lost all power (defined as V

= 0V and

or VBAT

DD

VBAT = 0V). The bit is set regardless of whether V

DD

is applied first. The loss of only one of the supplies does not

set the RTCF bit to “1”. The first valid write to the RTC section

after a complete power failure resets the RTCF bit to “0”

(writing one byte is sufficient).

2

stay at that value until set to zero via an I C write.

FN6618 Rev 3.00

May 5, 2011

Page 14 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

be set LOW until both the ALM0/ALM1 status bits are cleared

Event Count (EVTCNT)

to “0”.

TABLE 5. EVENT COUNTER REGISTER (EVTCNT)

ALARM 1 (ALE 1)

ADDR

7

6

5

4

3

2

1

0

This bit enables the Alarm1 function. When ALE1 = “1”, a

match of the RTC section with the Alarm1 section will result is

setting the ALM1 status bit to “1” and the IRQ output LOW.

When set to “0”, the Alarm1 function is disabled.

0Bh EVC7 EVC6 EVC5 EVC4 EVC3 EVC2 EVC1 EVC0

The EVTCNT register increments automatically each time an

event occurs. The register is set to 00h on initial power-up. The

maximum count is 255, and will stay at that value until set to

ALARM 0 (ALE 0)

2

zero via an I C write.

This bit enables the Alarm0 function. When ALE0 = 1, a match

of the RTC section with the Alarm1 section will result is setting

the ALM0 status bit to “1” and the IRQ output LOW. When set

to “0”, the Alarm0 function is disabled.

Performing a write of 00h to this register will clear the contents

of this register and all levels of the TSEVT section. A clear to

this register should be done with care. Write event index

register zero only selects first event time stamp. Write event

count EVNTCNT zero will both clear event counter and all time

stamps.

Frequency Out Register (FO)

TABLE 7. FREQUENCY OUT REGISTER (FO)

ADDR

7

6

5

4

3

2

1

0

Control Registers

0Dh

X

FOBATB

X

FO2 FO1 FO0

Addresses [0Ch to 14h]

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables F during battery backup mode (i.e.

The control registers (INT, FO, EVIC, EVIX, TRICK, PWRVDD,

PWRBAT, AC, and FTR) contain all the bits necessary to

control the parametric functions on the ISL12032.

OUT

VBAT power source active). When the FOBATB is set to “1” the

pin is disabled during battery backup mode. When the

F

OUT

Interrupt Control Register (INT)

FOBATB is cleared to “0”, the F

pin is enabled during battery

is a CMOS output and

OUT

TABLE 6. INTERRUPT CONTROL REGISTER (INT)

backup mode (default). Note that F

OUT

needs no pull-up resistor. Note also that battery current drain will

be higher with F enabled in battery backup mode.

ADDR

7

6

5

4

3

2

1

0

OUT

0Ch

ARST WRTC IM

X

ALE1 ALE0

FREQUENCY OUT CONTROL BITS (FO <2:0>)

AUTOMATIC RESET BIT (ARST)

These bits enable/disable the frequency output function and

This bit enables/disables the automatic reset of the ALM0,

ALM1, LVDD, LBAT85, and LBAT75 status bits only. When

ARST bit is set to “1”, these status bits are reset to “0” after a

valid read of the SRDC Register (with a valid STOP condition).

When the ARST is cleared to “0”, the user must manually reset

the ALM0, ALM1, LVDD, LBAT85, and LBAT75 bits.

select the output frequency at the F

pin. See Table 8 for

OUT

frequency selection. Note that frequencies from 4096Hz to

32768Hz are derived from the Crystal Oscillator, and the 1.0, 10,

and 50/60Hz frequencies are derived from the AC clock input.

The exception to this is when the AC input qualification has

failed, and the crystal oscillator is used for the 1.0Hz F

.

OUT

WRITE RTC ENABLE BIT (WRTC)

TABLE 8. FREQUENCY SELECTION OF F

OUT

The WRTC bit enables or disables write capability into the RTC

Register section. The factory default setting of this bit is “0”.

Upon initialization or power-up, the WRTC must be set to “1” to

enable the RTC. Upon the completion of a valid write (STOP),

the RTC starts counting. The RTC internal 1Hz signal is

synchronized to the STOP condition during a valid write cycle.

This bit will remain set until reset to “0” or a complete power-

FREQUENCY,

F

UNITS

Hz

FO2

0

FO1

FO0

0

OUT

32768

0

1

0

1

16372

8192

4096

50/60

1

Hz

0

1

Hz

0

Hz

0

1

down occurs (V

= VBAT = 0.0V)

DD

Hz

1

0

ALARM INTERRUPT MODE BIT (IM)

Hz

1

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarms will operate in

the interrupt mode, where an active low pulse width of 250ms

will appear at the IRQ pin when the RTC is triggered by either

alarm as defined by the Alarm0 section (1Dh to 22h) or the

Alarm1 section (23h to 28h). When the IM bit is cleared to “0”,

the alarm will operate in standard mode, where the IRQ pin will

Low

Hz

1

0

High

Hz

1

FN6618 Rev 3.00

May 5, 2011

Page 15 of 26

ISL12032

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 11. EVENT INPUT SAMPLING RATE

Event Detection Register (EVIC)

ESMP1

ESMP2

SAMPLING RATE

TABLE 9. EVENT DETECTION REGISTER (EVIC)

1

0

1

1 Hz

ADDR

7

6

5

4

3

2

1

0

1/4 Hz

0Eh

X

EVBATB EVIM EVEN EHYS1 EHYS0 ESMP1 ESMP0

Event Index Register (EVIX)

EVENT OUTPUT IN BATTERY MODE ENABLE BIT

(EVBATB)

TABLE 12. EVENT INDEX REGISTER (EVIX)

This bit enables/disables the EVDET pin during battery backup

mode (i.e. VBAT pin supply ON). When the EVBATB is set to

“1”, the Event Detect Output is disabled in battery backup

mode. When the EVBATB is cleared to “0”, the Event Detect

output is enabled in battery backup mode. This feature can be

used to save power during battery mode.

ADDR

7

6

5

4

3

2

1

0

0Fh

X

EVIX1 EVIX0

The Event Index Register provides the index for locating an

individual event that has been stored. The Event recording

function allows recalling up to 4 events, although the Event

counting register will count up to 255 events. The 0th location

corresponds to the first event, and the 1st through 3rd

locations correspond to the most recent events, with the 3rd

location (11b) representing the latest event. Therefore, setting

EVIX to 03h location and reading the TSEVT section will

access the timestamp information for the most recent (latest)

event. Setting this register to another value will allow reading

the corresponding event from the TSEVT section.

EVENT OUTPUT PULSE MODE (EVIM)

This bit controls the EVDET pin output mode. With EVIM = 0,

the output is in normal mode and when an event is triggered,

the output will be set LOW until reset. With EVIM = 1, the

output is in pulse mode and when an event is triggered, the

device will generate a 200ms to 300ms pulse at the EVDET

output.

EVENT DETECT ENABLE (EVEN)

EVENT BIT (EVIX <1:0>)

This bit enables/disables the Event Detect function of the

ISL12032. When this bit is set to “1”, the Event Detect is active.

When this bit is cleared to “0”, the Event Detect is disabled.

These bits are the Event Counter Register index bits. EVIX1 is

the MSB and EVIX0 is the LSB.

EVENT TIME-BASED HYSTERESIS (EHYS1, EHYS0)

Trickle Charge Register (TRICK)

These bits set the amount of time-based hysteresis that is

present at the EVIN pin for deglitching the input signal. The

settings vary from 0ms (hysteresis OFF) to 31.25ms (delay of

31.25ms to check for change of state at the EVIN pin). The

Hysteresis function and the Event Input Sampling function

work independently.

TABLE 13. TRICKLE CHARGE REGISTER (TRICK)

ADDR

7

6

5

4

3

2

1

0

10h

X

TRKEN TRKRO1 TRKRO0

The trickle charge function allows charging current to flow from

the V supply to the VBAT pin through a selectable current

DD

limiting resistor. Disabling the trickle charge function removes

this connection and isolates the battery from the V supply in

TABLE 10. EVENT TIME-BASED HYSTERESIS

EHSYS1

EHSYS0

TIME (ms)

0

DD

the case charging is not necessary or harmful (as in the case

with a lithium coin cell battery). Note that there is no charging

diode in series with the trickle charge resistor, but a switch

network that adds a small series resistance to the charging

resistance.

0

1

0

1

0

1

3.9

16.625

31.25

TRICKLE CHARGE BIT (TRKEN)

EVENT INPUT SAMPLING RATE (ESMP)

This bit enables/disables the trickle charge capability for the

backup battery supply. Setting this bit to “1” will enable the

trickle charge. Resetting this bit to “0” will disable the trickle

These bits set the frequency of sampling of the Event Input

(EVIN). The settings include from 1/4Hz (one sample per 4s) to

2Hz (twice a second), 1Hz, or continuous sampling (Always

ON). The less frequent the sampling, the lower the current

drain, which can affect battery current drain and battery life.

charge function and isolate the battery from the V

supply.

DD

TRICKLE CHARGE RESISTOR (TRKRO<1:0>)

.

These bits allow the user to change the trickle charge resistor

settings according to the maximum current desired for the

battery or super capacitor charging.

TABLE 11. EVENT INPUT SAMPLING RATE

ESMP1

ESMP2

SAMPLING RATE

Always ON

2 Hz

V

– V

0

1

DD

BAT

--------------------------------

(EQ. 1)

I

=

MAX

R

OUT

FN6618 Rev 3.00

May 5, 2011

Page 16 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Where the R is the selected resistor between V and

TABLE 16. VDD TRIP LEVELS

OUT

DD

VBAT. Table 14 gives the typical resistor values for V

= 5V

DD

and VBAT = 3.0V. Note that the resistor value changes with

input voltage and VBAT voltage, as well as with

TRIP

VOLTAGE

(V)

V

Trip2

V

Trip1

V

Trip0

DD

V

DD

temperature.

1

0

1

4.675

TABLE 14. RESISTOR SELECTION REGISTER

Battery Voltage Warning Register (PWRVBAT)

TRKRO1

TRKRO0

Rtrk

1300

2200

3600

7800

UNITS

This register controls the trip points for the two VBAT warnings,

with levels set to approximately 85% and 75% of the nominal

battery level.

0

1

0

1

0

1



TABLE 17. BATTERY VOLTAGE WARNING REGISTER

(PWRVBAT)

ADDR

7

6

5

4

3

2

1

0

12h

X

BHYS VB85T VB85T VB85T VB75T VB75T VB75T

p2 p1 p0 p2 p1 p0

Power Supply Control Register (PWRVDD)

TABLE 15. POWER SUPPLY CONTROL REGISTER (PWRVDD)

VBAT HYSTERESIS (BHYS)

ADDR

7

6

5

4

3

2

1

0

This bit enables/disables the hysteresis voltage for the V /VBAT

DD

switchover. When set to “1”, hysteresis is enabled and switching

11h

CLRTS

X

I2CBAT LVENB

X

VDD VDD VDD

Trip2 Trip1 Trip0

to VBAT occurs at approximately 50mV below the V

(set by VDDTrip<2:0>). Switching from VBAT to V

DD

Trip point

power will

DD

CLEAR TIME STAMP BIT (CLRTS)

occur at approximately 50mV above the V

trip point.

DD

This bit clears both the Time Stamp V

and Time Stamp Battery to V

setting is “0” which allows normal operation. Setting CLRTS =

1 performs the clear timestamp register function at the

conclusion of a successful write operation.

to Battery (TSV2B)

DD

When set to “0”, there is no hysteresis and switchover will

occur at exactly the VDD trip point. Note that for slow moving

(TSB2V) sections. The default

DD

V

power-down and power-up signals there can be some

DD

extra switching cycles without hysteresis.

2

BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)

I C IN BATTERY MODE (I2CBAT)

2

Three bits selects the first alarm (85% of Nominal VBAT) level for

the battery voltage monitor. There are total of 7 levels that could

be selected for the first warning. Any of the levels could be

selected as the first warning with no reference as to nominal

VBAT voltage level. See Table 18 for typical values.

This bit allows I C operation in battery backup mode (VBAT

2

powered) when set to “1”. When reset to “0”, the I C operation

is disabled in battery mode, which results in the lowest I

current.

DD

2

Note that when the I C operation is desired in VBAT mode, the

SCL and SDA pull-ups must go to the VBAT source for proper

communications. This will result in additional VBAT current

drain (on top of the increased device VBAT current) during

serial communications.

V

BROWNOUT TRIP VOLTAGE (VDDTRIP <2:0>)

DD

These bits set the 6 trip levels for the V

alarm and VBAT

DD

switchover. The LVDD bit in the SRDC is set to “1” when V

drops below this preset level. See Table 16.

DD

TABLE 16. VDD TRIP LEVELS

TRIP

VOLTAGE

V

Trip2

V

Trip1

V Trip0

DD

(V)

DD

0

1

0

1

0

1

0

1

0

2.295

2.550

2.805

3.060

4.250

FN6618 Rev 3.00

May 5, 2011

Page 17 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 18. VB85T VBAT WARNING LEVELS

BATTERY

AC RECOVERY PERIOD (ACRP<1:0>)

This bit sets the AC clock input validation recovery period. After

the AC input fails validation (ACFAIL = 1), a predefined period

is used to test the frequency and voltage of the AC clock input.

The range is from 2s to 16s.

ALARM TRIP

LEVEL (V)

VB85Tp2

VB85Tp1

VB85Tp0

0

1

0

1

0

1

0

1

0

1

0

1

0

2.125

2.295

2.550

2.805

3.060

4.250

4.675

TABLE 21. AC RECOVERY PERIOD

ACRP1

ACRP0

RECOVERY TIME

0

1

0

1

0

1

2s

4s

8s

16s

AC FAILURE CYCLES (ACFP<1:0>)

These two bits determine how many AC cycles are used for the

AC clock qualification, or to disable the AC clock qualification.

The range is from 1 AC cycle to 12 AC cycles or disable, and is

also dependent on the AC5060 bit setting (see Table 22). The

qualification logic will count the number of crystal cycles in the

chosen AC period, and if the count is outside the window set

by ACFC bits then the ACFAIL signal is set to “1”.

BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)

Three bits selects the second warning (75% of Nominal VBAT)

level for the battery voltage monitor. There are total of 7 levels that

could be selected for the second monitor. Any of the levels could

be selected as the second alarm with no reference as to nominal

VBAT voltage level. See Table 19 for typical values.

TABLE 19. VB75T VBAT WARNING LEVELS

For example, if 10 cycles are chosen for 50Hz input, then

during those 10 cycles there would need to be exactly 6554

crystal cycles. That number is subtracted from the actual count

during the 10 AC cycles and the absolute value is compared to

the error value set by ACFC. If the error were 10 crystal cycles

and ACFC were set to 11b, then the allowable error would be

20 crystal cycles and the ACFAIL would be “0”, or qualification

has passed. If the actual error count were 22 cycles then the

ACFAIL would be set to “1”, qualification has failed.

BATTERY

ALARM TRIP

LEVEL (V)

VB75Tp2

VB75Tp1

VB75Tp0

0

1

0

1

0

1

0

1

0

1

0

1

0

1.875

2.025

2.250

2.475

2.700

.

TABLE 22. AC FAILURE CYCLES

3.750

CYCLE USED for COUNT

4.125

AC5060 = 0

AC5060=1

ACFP1

ACFP0

(Disabled)

0

1

0

1

0

1

AC Register (AC)

1

6

1

5

This register sets the performance screening for the AC input.

12

10

TABLE 20. AC REGISTER

ADDR

7

6

5

4

3

2

1

0

AC/CRYSTAL FREQUENCY FAILURE CRITERION

(ACFC<1:0>)

13h

AC5060 ACENB ACRP1 ACRP0 ACFP1 ACFP0 ACFC1 ACFC0

These two bits determine the number of crystal cycles used for

the error budget for the AC qualification (see Table 24). Two of

the choices are for a fixed ppm criterion of 1 or 2 crystal cycles

in just one AC cycle (independent of the ACFP setting). The

other choices are for 1 or 2 crystal cycles per AC cycle, but

includes the total number of cycles set by the ACFP.

AC 50/60HZ INPUT SELECT (AC5060)

This bit selects either 50Hz or 60Hz powerline AC clock input

frequency. Setting this bit to “0” selects a 60Hz input (default).

Setting this bit to “1” selects a 50Hz input.

AC ENABLE (ACENB)

Using the example given for the ACFP bits previously

mentioned:

This bit will enable/disable the AC clock input. Setting this bit to

“0” will enable the AC clock input (default). Setting this bit to “1”

will disable the AC clock input. When the AC input is disabled,

the crystal oscillator becomes the sole source for RTC and

AC5060 = 1 (50Hz)

ACFC = 11b (2 crystal cycles/AC cycle)

ACFP = 11b (10 total AC cycles)

So the resulting crystal cycle count must be within:

F

clocking.

OUT

FN6618 Rev 3.00

May 5, 2011

Page 18 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 25. XDTR FREQUENCY COMPENSATION

FREQUENCY

±(10 AC cycles x 2 crystal cycles/AC cycle) or

± 20 total crystal cycles (error budget) as shown in Table 23.

COMPENSATION

(ppm)

XDTR3

XDTR2

XDTR1

XDTR0

TABLE 23. AC/CRYSTAL FREQUENCY FAILURE CRITERION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TOTAL XTAL

CYCLE ERROR

10

20

30

40

50

60

0

ACFC1 ACFC0

CRITERION

BUDGET

ACFP x 1

ACFP x 2

1

0

1

0

1

0

1 crystal cycle per AC cycle

2 crystal cycle per AC cycle

1 crystal cycle in all AC

cycles

1

2 crystal cycles in all AC

cycles

2

0

-10

-20

-30

-40

-50

-60

0

Fine Trim Compensation Register (FTR)

This register (Table 24) provides control of the crystal oscillator

clock compensation and the AC clock input minimum level

detect.

TABLE 24. FINE TRIM COMPENSATION REGISTER

ADDR

7

6

5

4

3

2

1

0

14h

X

ACMIN XDTR3 XDTR2 XDTR1 XDTR0

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the Daylight

Savings Time (DST) functions. DST beginning (set Forward)

time is controlled by the registers DstMoFd, DstDwFd,

DstDtFd, and DstHrFd. DST ending time (set Backward or

Reverse) is controlled by DstMoRv, DstDwRv, DstDtRv and

DstHrRv.

AC MINIMUM (ACMIN)

This bit determines the minimum peak-to-peak voltage level for

the AC clock input as a percentage of the existing V supply.

DD

ACMIN = 0 sets the minimum level to 5% x V . ACMIN = 1

DD

sets the minimum level to 10% x V

DD

.

DIGITAL TRIM REGISTER (XDTR<3:0>)

Tables 26 and 27 describe the structure and functions of the

DSTCR.

The digital trim register bits control the amount of trim used to

adjust for the crystal clock error. This trim is accomplished by

adding or subtracting the 32kHz clock in the clock counter

chain to adjust the RTC clock. Calibration can be done by

DST FORWARD REGISTERS (15H TO 18H)

DSTE is the DST Enabling Bit located in bit 7 of register 15h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.

Upon powering up for the first time (including battery), the

DSTE bit defaults to “0”.

monitoring the F

pin with a frequency counter with the

OUT

frequency output set to 1.0Hz, with no AC input.

DST forward is controlled by the following DST Registers:

DstMoFd sets the Month that DST starts. The default value for

the DST begin month is April (04h).

DstDwFd sets the Day of the Week that DST starts. DstDwFdE

sets the priority of the Day of the Week over the Date. For

DstDwFdE = 1, Day of the week is the priority. Note that Day of

the week counts from 0 to 6, like the RTC registers. The default

for the DST Forward Day of the Week is Sunday (00h).

DstDtfd controls which Date DST begins. The default value for

DST forward date is on the first date of the month (01h).

DstDtFd is only effective if DstDwFdE = 0.

FN6618 Rev 3.00

May 5, 2011

Page 19 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

TABLE 26. DST FORWARD REGISTERS

ADDRESS

15h

FUNCTION

Month Forward

Day Forward

Date Forward

Hour Forward

7

DSTE

0

6

5

4

3

2

1

0

MoFd20

WkFd11

DtFd20

HrFd20

MoFd13

WkFd10

DtFd13

HrFd13

MoFd12

DwFd12

DtFd12

HrFd12

MoFd11

DwFd11

DtFd11

HrFd11

MoFd10

DwFd10

DtFd10

HrFd10

16h

DwFdE

WkFd12

DtFd21

HrFd21

17h

0

18h

HrFdMIL

TABLE 27. DST REVERSE REGISTERS

ADDRESS

19h

NAME

7

6

5

4

3

2

1

0

Month Reverse

Day Reverse

Date Reverse

Hour Reverse

0

MoRv20

WkRv11

DtRv20

HrRv20

MoRv13

WkRv10

DtRv13

HrRv13

MoRv12

DwRv12

DtRv12

HrRv12

MoRv11

DwRv11

DtRv11

HrRv11

MoRv10

DwRv10

DtRv10

HrRv10

1Ah

0

DwRvE

WkRv12

DtRv21

HrRv21

1Bh

0

1Ch

HrRvMIL

DstHrFd controls the hour that DST begins. It includes the MIL

bit, which is in the corresponding RTC register. The RTC hour

and DstHrFd registers need to match formats (Military or

AM/PM) in order for the DST function to work. The default

value for DST hour is 2:00AM (02h). The time is advanced

from 2:00:00AM to 3:00:00AM for this setting.

registers and the RTC registers. Any one alarm register,

multiple registers, or all registers can be enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

Single Event Mode is enabled by setting either ALE0 or ALE1

to 1, then setting bit 7 on any of the Alarm registers (ESCA...

EDWA) to “1”, and setting the IM bit to “0”. This mode permits a

one-time match between the Alarm registers and the RTC

registers. Once this match occurs, the ALM bit is set to “1” and

the IRQ output will be pulled LOW and will remain LOW until

the ALM bit is reset. This can be done manually or by using the

auto-reset feature. Since the IRQ output is shared by both

alarms, they both need to be reset in order for the IRQ output

to go HIGH.

DST REVERSE REGISTERS (19H TO 1CH)

DST end (reverse) is controlled by the following DST

Registers.

DstMoRv sets the Month that DST ends. The default value for

the DST end month is October (10h).

DstDwRv controls the Day of the Week that DST should end.

The DwRvE bit sets the priority of the Day of the Week over the

Date. For DwRvE = 1, Day of the week is the priority. Note that

Day of the week counts from 0 to 6, like the RTC registers. The

default for DST DwRv end is Sunday (00h).

Interrupt Mode is enabled by setting either ALE0 or ALE1 to

1, then setting bit 7 on any of the Alarm registers (ESCA...

EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit to

1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ

output will now be pulsed each time an alarm occurs (either

AL0 or AL1). This means that once the interrupt mode alarm is

set, it will continue to alarm until it is reset.

DstDtRv controls which Date DST ends. The default value for

DST Date Reverse is on the first date of the month. The

DstDtRv is only effective if the DwRvE = 0.

DstHrRv controls the hour that DST ends. It includes the MIL

bit, which is in the corresponding RTC register. The RTC hour

and DstHrRv registers need to match formats (Military or

AM/PM) in order for the DST function to work. The default

value sets the DST end at 2:00AM. The time is set back from

2:00:00AM to 1:00:00AM for this setting.

To clear a single event alarm, the corresponding ALM0 or

ALM1 bit in the SRDC register must be set to “0” with a write.

Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the

ALM0 and ALM1 bits will automatically be cleared when the

status register is read.

ALARM Registers (1Dh to 28h)

The IRQ output will be set by an alarm match for either ALM0

or ALM1.

The alarm register bytes are set up identical to the RTC

register bytes, except that the MSB of each byte functions as

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make the

comparison. Note that there is no alarm byte for year.

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

The alarm function works as a comparison between the alarm

registers and the RTC registers. As the RTC advances, the

alarm will be triggered once a match occurs between the alarm

FN6618 Rev 3.00

May 5, 2011

Page 20 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Example 1

Note that the status register ALM0 bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

• Alarm set with single interrupt (IM = ”0”)

Time Stamp V to Battery Registers (TSV2B)

• A single alarm will occur on January 1 at 11:30am.

• Set Alarm registers as follows:

DD

The TSV2B section bytes are identical to the RTC register

section, except they do not extend beyond the Month. The Time

Stamp captures the FIRST V to Battery Voltage transition time,

BIT

DD

ALARM

REGISTER 7

and will not update upon subsequent events, until cleared (only

the first event is captured before clearing). Set CLRTS = 1 to clear

this register (Addr 11h, PWRVDD register).

6

0

5

0

1

4

0

1

3

0

2

0

1

0

HEX

DESCRIPTION

SCA0

MNA0

0

1

00h Seconds disabled

B0h Minutes set to 30,

enabled

Time Stamp Battery to V

Registers (TSB2V)

DD

The Time Stamp Battery to V

the RTC section bytes, except they do not extend beyond

Month. The Time Stamp captures the LAST transition of VBAT

section bytes are identical to

DD

HRA0

DTA0

MOA0

DWA0

1

0

1

0

1

0

91h Hours set to 11,

enabled

81h Date set to 1,

enabled

to V

(only the last power up event of a series of power

DD

up/down events is retained). Set CLRTS = 1 to clear this

register (Addr 11h, PWRVDD register).

81h Month set to 1,

enabled

Time Stamp Event Registers (TSEVT)

00h Day of week

disabled

The TSEVT section bytes are identical to the RTC section bytes,

except they do not extend beyond the Month. The Time Stamp

captures the first event and the most recent three events. The first

event Time Stamp will not update until cleared. All 4 Time Stamps

are all cleared to “0” when writing the event counter (0Bh) is set to

“0”.

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30 a.m. on January 1 (after

seconds changes from 59 to 00) by setting the ALM0 bit in the

status register to “1” and also bringing the IRQ output LOW.

Note: The time stamp registers are cleared to all “0”, including

the month and day, which is different from the RTC and alarm

registers (those registers default to 01h). This is the indicator

that no time stamping has occurred since the last clear or initial

power-up. Once a time stamp occurs, there will be a non-zero

time stamp.

Example 2

• Pulsed interrupt once per minute (IM = ”1”)

• Interrupts at one minute intervals when the seconds register

is at 30 seconds.

• Set Alarm registers as follows:

BIT

User Memory Registers (accessed by using

Slave Address 1010111x)

ALARM

REGISTER 7

6

5

4

3

2

1

0 HEX

DESCRIPTION

SCA0

1

0

1

0

B0h Seconds set to 30,

enabled

Addresses [00h to 7Fh]

These registers are 128 bytes of battery-backed user SRAM.

Writes to this section do not need to be proceeded by setting

the WRTC bit.

MNA0

HRA0

DTA0

MOA0

DWA0

0

00h Minutes disabled

00h Hours disabled

00h Date disabled

2

I C Serial Interface

00h Month disabled

00h Day of week disabled

The ISL12032 supports a bi-directional bus oriented protocol.

The protocol defines any device that sends data onto the bus

as a transmitter and the receiving device as the receiver. The

device controlling the transfer is the master and the device

being controlled is the slave. The master always initiates data

transfers and provides the clock for both transmit and receive

operations. Therefore, the ISL12032 operates as a slave

device in all applications.

Once the registers are set, the following waveform will be seen

at IRQ:

RTC AND ALARM REGISTERS ARE BOTH “30s”

2

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

60s

FIGURE 5. IRQ WAVEFORM

FN6618 Rev 3.00

May 5, 2011

Page 21 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

operation or at the end of a write operation to memory only

Protocol Conventions

places the device in its standby mode.

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 6). On

power-up of the ISL12032, the SDA pin is in the input mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after transmitting

eight bits. During the ninth clock cycle, the receiver pulls the

SDA line LOW to acknowledge the reception of the eight bits of

data (see Figure 7).

2

All I C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while SCL

is HIGH. The ISL12032 continuously monitors the SDA and

SCL lines for the START condition and does not respond to

any command until this condition is met (see Figure 6). A

START condition is ignored during the power-up sequence.

The ISL12032 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL12032 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

2

All I C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL

is HIGH (see Figure 6). A STOP condition at the end of a read

SCL

SDA

DATA

STABLE

DATA

CHANGE STABLE

DATA

START

STOP

FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

SIGNALS FROM

THE MASTER

S

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 1 0 1 1 1 1 0

0 0 0 0

SIGNALS FROM

THE ISL12032

A

C

K

A

C

K

A

C

K

FIGURE 8. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

FN6618 Rev 3.00

May 5, 2011

Page 22 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Device Addressing

Write Operation

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifier. These bits

are “1101111b” for the RTC registers and “1010111b” for the User

SRAM.

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte, and

a STOP condition. After each of the three bytes, the ISL12032

2

responds with an ACK. At this time, the I C interface enters a

standby state.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, then a

read operation is selected. A “0” selects a write operation (refer

to Figure 9).

A multiple byte operation within a page is permitted. The

Address Byte must have the start address, and the data bytes

are sent in sequence after the address byte, with the ISL12032

sending an ACK after each byte. The page write is terminated

with a STOP condition from the master. The pages within the

ISL12032 do not support wrapping around for page read or

write operations.

After loading the entire Slave Address Byte from the SDA bus, the

ISL12032 compares the device identifier and device select bits

with “1101111b” or “1010111b”. Upon a correct compare, the

device outputs an acknowledge on the SDA line.

Read Operation

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained from

an internal counter. On power up the internal address counter is

set to address 00h, so a current address read starts at address

00h. When required, as part of a random read, the master must

supply the 1 Word Address Byte as shown in Figure 9.

A Read operation consists of a three byte instruction followed

by one or more Data Bytes (see Figure 10). The master

initiates the operation issuing the following sequence: a

START, the Identification byte with the RW bit set to “0”, an

Address Byte, a second START, and a second Identification

byte with the RW bit set to “1”. After each of the three bytes,

the ISL12032 responds with an ACK. Then the ISL12032

transmits Data Bytes as long as the master responds with an

ACK during the SCL cycle following the eighth bit of each byte.

The master terminates the read operation (issuing a STOP

condition) following the last bit of the last Data Byte (see Figure

10).

In a random read operation, the slave byte in the “dummy write”

portion must match the slave byte in the “read” section. For a

random read of the Control/Status Registers, the slave byte must

be “1101111x” in both places.

SLAVE

ADDRESS BYTE

1

R/W

1

0

1

The Data Bytes are from the memory location indicated by an

internal pointer. This pointers initial value is determined by the

Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the last memory location in a section or page,

the master should issue a STOP. Bytes that are read at

addresses higher than the last address in a section may be

erroneous.

WORD ADDRESS

A7

D7

A6

D6

A5

D5

A4

D4

A3

D3

A2

D2

A1

D1

A0

D0

DATA BYTE

FIGURE 9. SLAVE ADDRESS, WORD ADDRESS, AND DATA

BYTES

S

T

A

R

T

SIGNALS

FROM THE

MASTER

T

A

R

T

S

IDENTIFICATION

BYTE WITH

R/W=0

IDENTIFICATION

BYTE WITH

R/W = 1

A

C

K

A

C

K

T

O

P

ADDRESS

BYTE

SIGNAL AT

SDA

1 1 0 1 1 1 1 0

1 1 0 1 1 1 1

1

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 10. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)

FN6618 Rev 3.00

May 5, 2011

Page 23 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

AC Input Circuits

The AC input ideally will have a 2.5V

so this is the target for any signal conditioning circuitry for the

50/60Hz waveform. Note that the peak-to-peak amplitude can

Application Section

sine wave at the input,

P-P

Oscillator Crystal Requirements

The ISL12032 uses a standard 32.768kHz crystal. Either

through hole or surface mount crystals can be used. Table 28

lists some recommended surface mount crystals and the

parameters of each. This list is not exhaustive and other

surface mount devices can be used with the ISL12032 if their

specifications are very similar to the devices listed. The

crystal should have a required parallel load capacitance of

12.5pF and an equivalent series resistance of less than 50k.

The crystal’s temperature range specification should match the

application. Many crystals are rated for -10°C to +60°C

(especially through hole and tuning fork types), so an

appropriate crystal should be selected if extended temperature

range is required.

range from 1V

up to V , although it is best to keep the

P-P

DD

max signal level just below V . The AC input provides DC

DD

offset so AC coupling with a series capacitor is advised.

If the AC power supply has a transformer, the secondary

output can be used for clocking with a resistor divider and

series AC coupling capacitor. A sample circuit is shown in

Figure 12. Values for R /R are chosen depending on the

1

2

peak-to-peak range on the secondary voltage in order to match

the input of the ISL12032. C can be sized to pass up to

IN

300Hz or so, and in most cases, 0.47µF should be the selected

value for a ±20% tolerance device.

The AC input to the IS12032 can be damaged if subjected to a

TABLE 28. SUGGESTED SURFACE MOUNT CRYSTALS

normal AC waveform when V

is powered down. this can

DD

MANUFACTURER

Citizen

PART NUMBER

CM200S

happen in circuits where there is a local LDO or power switch

for placing circuitry in standby, while the AC main is still

switched ON. Figure 11 shows a modified version of the Figure

12 circuit, which uses an emitter follower to essentially turn off

Epson

MC-405, MC-406

RSM-200S

Raltron

the AC input waveform if the V

supply goes down.

DD

SaRonix

Ecliptek

ECS

32S12

Using the ISL12032 with No AC Input

ECPSM29T-32.768K

ECX-306

Some applications may need all the features of the ISL12032

but do not have access to the power line AC clock, or do not

need the accuracy provided by that clock. In these cases there

is no problem using the crystal oscillator as the primary clock

source for the device.

Fox

FSM-327

Layout Considerations

The crystal input at X1 has a very high impedance, and

oscillator circuits operating at low frequencies (such as

32.768kHz) are known to pick up noise very easily if layout

precautions are not followed. Most instances of erratic clocking

or large accuracy errors can be traced to the susceptibility of

the oscillator circuit to interference from adjacent high speed

clock or data lines. Careful layout of the RTC circuit will avoid

noise pickup and ensure accurate clocking.

The user must simply set the ACENB bit in register 13h to “1”,

which disables the AC input pin and forces the device to use

the crystal oscillator exclusively for the RTC and F

clock

OUT

source. Setting this bit to “1” also will cause the ACRDY bit in

the SRAC register to be set to “1”, indicating that there can be

no fault with the AC input clock since it is not used.

Two main precautions for crystal PC board layout should be

followed:

1. Do not run the serial bus lines or any high speed logic lines

in the vicinity of the crystal. These logic level lines can

induce noise in the oscillator circuit to cause misclocking.

2. Add a ground trace around the crystal with one end

terminated at the chip ground. This will provide termination

for emitted noise in the vicinity of the RTC device.

In addition, it is a good idea to avoid a ground plane under the

X1 and X2 pins and the crystal, as this will affect the load

capacitance and therefore the oscillator accuracy of the circuit.

If the F

pin is used as a clock, it should be routed away

OUT

from the RTC device as well. The traces for the VBAT

and V pins can be treated as a ground, and should be

DD

routed around the crystal.

FN6618 Rev 3.00

May 5, 2011

Page 24 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

VIN (AC) = 1.5V

TO VDD (MAX)

P-P

CIN

R1

120VAC

ISL12032

R2

50/60Hz

FIGURE 11. AC INPUT USING A TRANSFORMER SECONDARY

VIN (AC) = 1.5V

TO VDD (MAX)

P-P

VDD

C1

R1

CIN

120VAC

50/60Hz

ISL12032

R2

FIGURE 12. USING THE V

SUPPLY TO GATE THE AC INPUT

DD

.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6618 Rev 3.00

May 5, 2011

Page 25 of 26

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Package Outline Drawing

M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09

A

1

3

5.00 ±0.10

SEE

DETAIL "X"

14

8

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

1

7

0.20 C B A

B

0.65

0.09-0.20

TOP VIEW

END VIEW

1.00 REF

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

SEATING

PLANE

GAUGE

PLANE

0.25

5

0.25 +0.05/-0.06

0.10 CBA

0°-8°

0.60 ±0.15

0.05 MIN

0.15 MAX

0.10 C

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

(5.65)

3. Dimensions are measured at datum plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.80mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead is 0.07mm.

6. Dimension in ( ) are for reference only.

(0.65 TYP)

(0.35 TYP)

7. Conforms to JEDEC MO-153, variation AB-1.

TYPICAL RECOMMENDED LAND PATTERN

FN6618 Rev 3.00

May 5, 2011

Page 26 of 26


型号：	ISL12032IVZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up; TSSOP14; Temp Range: -40° to 85°C 时钟电池静态存储器光电二极管外围集成电路
文件：	总26页 (文件大小：973K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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