ISL22346UFRT20Z [RENESAS]
Quad Digitally Controlled Potentiometers (XDCPâ¢) Low Noise, Low Power I2C⢠Bus, 128 Taps;
| 型号： | ISL22346UFRT20Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Quad Digitally Controlled Potentiometers (XDCPâ¢) Low Noise, Low Power I2C⢠Bus, 128 Taps 转换器 电阻器 |
| 文件： | 总16页 (文件大小：954K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL22346
FN6177
Rev 2.00
September 3, 2009
2
Quad Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power I C™
Bus, 128 Taps
The ISL22346 integrates four digitally controlled potentiometers
(DCP) and non-volatile memory on a monolithic CMOS
Features
• Four potentiometers in one package
• 128 resistor taps
integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2
• I C serial interface
- Three address pins, up to eight devices/bus
2
I C bus interface. Each potentiometer has an associated
• Non-volatile storage of wiper position
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
• Wiper resistance: 70 typical @ V
• Shutdown mode
= 3.3V
CC
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10k total resistance
• High reliability
The DCPs can be used as a three-terminal potentiometers
or as a two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 20 Ld TSSOP or 20 Ld TQFN package
• Pb-free (RoHS compliant)
Pinouts
ISL22346
(20 LD TSSOP)
TOP VIEW
ISL22346
(20 LD TQFN)
TOP VIEW
RH3
RL3
RW3
A2
1
20
19
18
17
16
15
14
13
12
11
RW0
RL0
RH0
SHDN
VCC
A1
2
O
20 19 18 17 16
3
RH1
RL1
15
14
1
RL0
RW0
RH3
RL3
4
2
3
4
SCL
SDA
GND
RW2
RL2
RH2
5
13 RW1
6
RH2
12
7
A0
RW3
RL2
11
5
8
RH1
RL1
RW1
9
6
7
8
9
10
10
FN6177 Rev 2.00
September 3, 2009
Page 1 of 16
ISL22346
Ordering Information
PART NUMBER
(Note)
PART
MARKING
RESISTANCE OPTION
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
(k)
ISL22346UFV20Z*
ISL22346UFRT20Z*
ISL22346WFV20Z*
ISL22346WFRT20Z*
22346 UFVZ
223 46UFZ
50
50
10
10
-40 to +125
-40 to +125
-40 to +125
-40 to +125
20 Ld TSSOP
20 Ld 4x4 TQFN
20 Ld TSSOP
20 Ld 4x4 TQFN
M20.173
L20.4x4A
M20.173
L20.4x4A
22346 WFVZ
223 46WFZ
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
V
CC
RH3
WR3
WR2
RW3
SCL
SDA
A0
POWER-UP
RL3
RH2
INTERFACE,
CONTROL
AND STATUS
LOGIC
2
I C
INTERFACE
A1
RW2
RL2
RH1
A2
WR1
WR0
RW1
NON-
VOLATILE
REGISTERS
RL1
RH0
SHDN
RW0
RL0
GND
Pin Descriptions
TSSOP PIN
NUMBER
TQFN PIN
NUMBER
PIN NAME
RH3
RL3
DESCRIPTION
1
2
3
4
“High” terminal of DCP3
“Low” terminal of DCP3
“Wiper” terminal of DCP3
3
5
RW3
A2
2
4
6
Device address input for the I C interface
2
5
7
SCL
SDA
GND
RW2
RL2
Open drain I C interface clock input
2
6
8
Open drain Serial data I/O for the I C interface
7
9
Device ground pin
8
10
11
12
13
14
15
16
“Wiper” terminal of DCP2
“Low” terminal of DCP2
“High” terminal of DCP2
“Wiper” terminal of DCP1
“Low” terminal of DCP1
“High” terminal of DCP1
9
10
11
12
13
14
RH2
RW1
RL1
RH1
A0
2
Device address input for the I C interface
FN6177 Rev 2.00
September 3, 2009
Page 2 of 16
ISL22346
Pin Descriptions (Continued)
TSSOP PIN
NUMBER
TQFN PIN
NUMBER
PIN NAME
A1
DESCRIPTION
2
15
16
17
18
19
20
17
18
Device address input for the I C interface
VCC
Power supply pin
19
SHDN
RH0
Shutdown active low input
“High” terminal of DCP0
20
1
RL0
“Low” terminal of DCP0
2
RW0
“Wiper” terminal of DCP0
Exposed Die Pad internally connected to GND
EPAD*
*Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
FN6177 Rev 2.00
September 3, 2009
Page 3 of 16
ISL22346
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
JA
20 Lead TSSOP (Note 1). . . . . . . . . . .
20 Lead TQFN (Notes 2, 3) . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
95
40
N/A
3.0
with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V
+ 0.3
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
V
CC
Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V
CC
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C
ESD Ratings
Recommended Operating Conditions
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CC
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.
Analog Specifications Over recommended operating conditions, unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
to R Resistance
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
k
R
R
R
W option
U option
10
50
TOTAL
H
L
k
to R Resistance Tolerance
W and U option
W option
-20
+20
%
H
L
End-to-End Temperature Coefficient
±50
±80
ppm/°C
(Note 18)
U option
ppm/°C
(Note 18)
V
, V
RH RL
V
and V Terminal Voltages
RL
V
V
and V to GND
RL
0
V
CC
V
RH
RH
CC
R
Wiper Resistance
= 3.3V, wiper current = V /R
CC TOTAL
70
200
W
C /C /C
W
Potentiometer Capacitance
10/10/25
pF
H
L
(Note 20)
I
Leakage on DCP Pins
Voltage at pin from GND to V
0.1
1
µA
LkgDCP
CC
VOLTAGE DIVIDER MODE (0V @ R i; V
@ R i; measured at R i, unloaded; i = 0, 1, 2, or 3)
L
CC
H
W
INL
(Note 10)
Integral Non-linearity
Differential Non-linearity
Zero-scale Error
Monotonic over all tap positions
-1
1
LSB
(Note 6)
DNL
(Note 9)
Monotonic over all tap positions
-0.5
0.5
LSB
(Note 6)
ZSerror
(Note 7)
W option
0
0
1
0.5
-1
5
2
0
0
2
LSB
(Note 6)
U option
FSerror
(Note 8)
Full-scale error
W option
-5
-2
-2
LSB
(Note 6)
U option
-1
V
DCP to DCP Matching
Any two DCPs at same tap position, same
LSB
(Note 6)
MATCH
(Note 11)
voltage at all R terminals, and same voltage
H
at all R terminals
L
FN6177 Rev 2.00
September 3, 2009
Page 4 of 16
ISL22346
Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued)
MIN
TYP
MAX
SYMBOL
TC
PARAMETER
TEST CONDITIONS
DCP register set to 40 hex
(Note 21) (Note 5) (Note 21)
UNIT
Ratiometric Temperature Coefficient
±4
ppm/°C
V
(Note 12)
RESISTOR MODE (Measurements between R i and R i with R i not connected, or between R i and R i with R i not connected. i = 0, 1, 2 or 3)
W
L
H
W
H
L
RINL
(Note 16)
Integral Non-linearity
DCP register set between 10h and 7Fh;
monotonic over all tap positions
-1
1
MI
(Note 13)
RDNL
(Note 15)
Differential Non-linearity
DCP register set between 10h and 7Fh;
monotonic over all tap positions, W option
-1
-0.5
0
1
MI
(Note 13)
DCP register set between 10h and 7Fh;
monotonic over all tap positions, U option
0.5
5
MI
(Note 13)
Roffset
Offset
W option
1
MI
(Note 14)
(Note 13)
U option
0
0.5
2
MI
(Note 13)
R
DCP to DCP Matching
Any two DCPs at the same tap position with
the same terminal voltages
-2
2
MI
(Note 13)
MATCH
(Note 17)
Operating Specifications Over the recommended operating conditions, unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
= 400kHz; SDA = Open; (for I C,
(Note 21) (Note 5) (Note 21)
UNIT
2
I
V
Supply Current (Volatile
Write/Read)
f
0.5
mA
CC1
CC
SCL
active, read and write states)
2
I
V
Supply Current (Non-volatile
f
= 400kHz; SDA = Open; (for I C,
SCL
3
5
7
3
5
3
5
2
4
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC2
CC
Write/Read)
active, read and write states)
2
I
V
CC
Current (Standby)
V
= +5.5V @ +85°C, I C interface in
CC
SB
standby state
2
V
= +5.5V @ +125°C, I C interface in
CC
standby state
2
V
= +3.6V @ +85°C, I C interface in
CC
standby state
2
V
= +3.6V @ +125°C, I C interface in
CC
standby state
2
I
V
CC
Current (Shutdown)
V
= +5.5V @ +85°C, I C interface in
SD
CC
standby state
2
V
= +5.5V @ +125°C, I C interface in
CC
standby state
2
V
= +3.6V @ +85°C, I C interface in
CC
standby state
2
V
= +3.6V @ +125°C, I C interface in
CC
standby state
I
Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to V
SHDN, SDA and SCL
-1
1
LkgDig
CC
t
DCP Wiper Response Time
SCL falling edge of last bit of DCP data byte
to wiper new position
1.5
1.5
1.5
WRT
(Note 20)
t
DCP Recall Time from Shutdown
From rising edge of SHDN signal to wiper
stored position and RH connection
µs
ShdnRec
(Note 20) Mode
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
µs
Vpor
Power-on Recall Voltage
Minimum V
occurs
at which memory recall
2.0
2.6
V
CC
FN6177 Rev 2.00
September 3, 2009
Page 5 of 16
ISL22346
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
Ramp
PARAMETER
Ramp Rate
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
V/ms
ms
V
V
0.2
CC
CC
t
Power-up Delay
V
above Vpor, to DCP Initial Value
2
3
D
CC
Register recall completed, and I C Interface
in standby state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T < +55°C
t
Non-volatile Write Cycle Time
12
20
WC
(Note 19)
SERIAL INTERFACE SPECIFICATIONS
V
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*V
V
V
IL
CC
V
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*V
V
+ 0.3
CC
IH
CC
Hysteresis SDA and SCL Input Buffer Hysteresis
0.05*V
0
V
V
CC
V
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.4
OL
Cpin
A2, A1, A0, SHDN, SDA, and SCL Pin
10
pF
(Note 20) Capacitance
f
SCL Frequency
400
50
kHz
ns
SCL
t
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
sp
t
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V , until
CC
900
ns
ns
AA
Valid
SDA exits the 30% to 70% of V
window
CC
during a STOP
CC
t
Time the Bus Must be Free Before the SDA crossing 70% of V
1300
BUF
CC
condition, to SDA crossing 70% of V
Start of a New Transmission
during the following START condition
t
Clock LOW Time
Measured at the 30% of V
Measured at the 70% of V
crossing
crossing
1300
600
ns
ns
ns
LOW
CC
CC
t
Clock HIGH Time
HIGH
t
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of V
600
SU:STA
HD:STA
SU:DAT
CC
From SDA falling edge crossing 30% of V
t
t
START Condition Hold Time
Input Data Setup Time
600
100
ns
ns
CC
CC
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
t
Input Data Hold Time
From SCL rising edge crossing 70% of V
0
ns
HD:DAT
CC
to SDA entering the 30% to 70% of V
window
CC
t
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
,
600
1300
0
ns
ns
ns
SU:STO
CC
to SDA rising edge crossing 30% of V
CC
t
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
HD:STO
or Volatile Only Write
Output Data Hold Time
both crossing 70% of V
CC
t
From SCL falling edge crossing 30% of V
,
DH
CC
CC
until SDA enters the 30% to 70% of V
window
t
SDA and SCL Rise Time
From 30% to 70% of V
20 +
250
ns
R
CC
0.1*Cb
FN6177 Rev 2.00
September 3, 2009
Page 6 of 16
ISL22346
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
t
SDA and SCL Fall Time
From 70% to 30% of V
20 +
0.1*Cb
250
400
ns
F
CC
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
1
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t and t
For Cb = 400pF, max is about 2k~2.5k
k
R
F
For Cb = 40pF, max is about 15k~20k
t
A2, A1 and A0 Setup Time
A2, A1 and A0 Hold Time
Before START condition
After STOP condition
600
600
ns
ns
SU:A
t
HD:A
NOTES:
5. Typical values are for T = +25°C and 3.3V supply voltage.
A
6. LSB: [V(R
)
– V(R ) ]/127. V(R
)
and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
W 0
W 127
W 0 W 127
W
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW) /LSB.
0
8. FS error = [V(RW)
127
– V ]/LSB.
CC
9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.
i-1
i
10. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 127.
i
0
11. V
= [V(RWx) – V(RWy) ]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
i i
MATCH
MaxVRW – MinVRW
6
10
i
i
--------------------------------------------------------------------------------------------- --------------------
12. TC
=
for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
V
MaxVRW + MinVRW 2 +165°C
i
i
13. MI = |RW
– RW |/127. RW
0
and RW are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
127 0
127
14. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
127
15. RDNL = (RW – RW )/MI - 1, for i = 16 to 127.
i
i-1
16. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 127.
i
0
17. R
= (RW – RW )/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
i,x i,y
MATCH
6
MaxRi – MinRi
MaxRi + MinRi 2
10
+165°C
--------------------------------------------------------------- --------------------
18.
for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
TC
=
R
the minimum value of the resistance over the temperature range.
2
19. t
is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-volatile
WC
write cycle.
20. Limits should be considered typical and are not production tested.
21. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6177 Rev 2.00
September 3, 2009
Page 7 of 16
ISL22346
SDA vs SCL Timing
t
sp
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
AA
DH
BUF
SDA
(OUTPUT TIMING)
A0, A1, and A2 Pin Timing
STOP
START
SCL
CLK 1
SDA
t
t
HD:A
SU:A
A0, A1, OR A2
Typical Performance Curves
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
V
CC
= 3.3V, T = +125°C
90
80
70
60
50
40
30
20
10
0
T = +125°C
T = +25°C
V
= 3.3V, T = -40°C
V
CC
= 3.3V, T = +20°C
CC
2.7
3.2
3.7
4.2
(V)
4.7
5.2
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
V
CC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10k (W)
FIGURE 2. STANDBY I
vs V
CC CC
CC TOTAL
FN6177 Rev 2.00
September 3, 2009
Page 8 of 16
ISL22346
Typical Performance Curves (Continued)
0.2
0.2
0.1
0
T = +25°C
T = +25°C
V
= 2.7V
CC
0.1
0
V
= 2.7V
CC
-0.1
-0.2
-0.1
-0.2
V
= 5.5V
40
V
= 5.5V
CC
CC
0
20
40
60
80
100
120
0
20
60
80
100
120
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
MODE FOR 10k (W)
1.3
10k
1.1
0.0
-0.3
V
= 2.7V
CC
0.9
0.7
V
= 5.5V
CC
50k
-0.6
-0.9
-1.2
-1.5
V
= 2.7V
CC
0.5
0.3
V
= 5.5V
CC
10k
40
0.1
50k
-0.1
-0.3
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (ºC)
FIGURE 5. ZS
vs TEMPERATURE
FIGURE 6. FS
vs TEMPERATURE
ERROR
ERROR
0.4
0.2
0
0.4
0.2
0
T = +25°C
T = +25°C
V
= 5.5V
V
= 5.5V
CC
CC
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
V
= 2.7V
CC
V
= 2.7V
CC
16
36
56
76
96
116
16
36
56
76
96
116
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
10k (W)
FN6177 Rev 2.00
September 3, 2009
Page 9 of 16
ISL22346
Typical Performance Curves (Continued)
1.0
105
90
75
60
45
30
15
0
0.5
V
= 2.7V
CC
50k
0.0
-0.5
-1.0
V
= 5.5V
CC
10k
50k
10k
-40
-20
0
20
40
60
80
100
120
16
36
56
76
96
TEMPERATURE (ºC)
TAP POSITION (DECIMAL)
FIGURE 9. END TO END R
% CHANGE vs
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
TOTAL
TEMPERATURE
OUTPUT
INPUT
300
250
200
150
100
50
50k
10k
WIPER AT MID POINT (POSITION 40h)
R
= 9.5k
TOTAL
0
16
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
SCL
SIGNAL AT WIPER
(WIPER UNLOADED)
SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)
WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FIGURE 14. LARGE SIGNAL SETTLING TIME
FN6177 Rev 2.00
September 3, 2009
Page 10 of 16
ISL22346
pins in order to initiate communication with the ISL22346. A
maximum of 8 ISL22346 devices may occupy the I C serial
bus.
Pin Descriptions
2
Potentiometers Pins
RHI AND RLI (i = 0, 1, 2 OR 3)
Principles of Operation
The high (RHi) and low (RLi) terminals of the ISL22346 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest to
RLi.
The ISL22346 is an integrated circuit incorporating four DCPs
2
with their associated registers, non-volatile memory and an I C
serial interface providing direct communication between a host
and the potentiometers and memory. The resistor arrays are
comprised of individual resistors connected in series. At either
end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
RWI (i = 0, 1, 2 OR 3)
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
When the device is powered down, the last value stored in IVRi
will be maintained in the non-volatile memory. When power is
restored, the contents of the IVRi are recalled and loaded into
the corresponding WRi to set the wipers to the initial value.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RHi and shorts RWi to RLi. When SHDN is
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0]= 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
2
logically ANDed with SHDN bit in ACR register. I C interface is
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.
RH
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
2
The SDA is a bidirectional serial data input/output pin for I C
While the ISL22346 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
interface. It receives device address, operation code, wiper
address and data from an I C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
2
SDA requires an external pull-up resistor, since it is an open
drain input/output.
2
The WRs can be read or written to directly using the I C serial
SERIAL CLOCK (SCL)
2
interface as described in the following sections. The I C
2
This is the serial clock input of the I C serial interface. SCL
interface Address Byte has to be set to 00h, 01h, 02h or 03h to
access the WR of DCP0, DCP1, DCP2 or DCP3 respectively.
requires an external pull-up resistor, since it is an open drain
input.
Memory Description
DEVICE ADDRESS (A2 - A0)
The ISL22346 contains seven non-volatile and five volatile 8-
bit registers. The memory map of ISL22346 is on Table 1. The
four non-volatile registers (IVRi) at address 0, 1, 2 and 3
contain initial wiper value and volatile registers (WRi) contain
The address inputs are used to set the least significant 3 bits of
2
the 7-bit I C interface slave address. A match in the slave
address serial data stream must match with the Address input
FN6177 Rev 2.00
September 3, 2009
Page 11 of 16
ISL22346
current wiper position. In addition, three non-volatile General
Purpose registers from address 4 to address 6 are available.
initiates data transfers and provides the clock for both transmit
and receive operations. Therefore, the ISL22346 operates as a
slave device in all applications.
TABLE 1. MEMORY MAP
2
All communication over the I C interface is conducted by
ADDRESS
NON-VOLATILE
VOLATILE
sending the MSB of each byte of data first.
8
7
—
ACR
Protocol Conventions
Reserved
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22346, the SDA pin is in the
input mode.
6
5
4
General Purpose
General Purpose
General Purpose
Not Available
Not Available
Not Available
3
2
1
0
IVR3
IVR2
IVR1
IVR0
WR3
WR2
WR1
WR0
2
All I C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The ISL22346 continuously monitors the SDA and
SCL lines for the START condition and does not respond to
any command until this condition is met (see Figure 16). A
START condition is ignored during the power-up of the device.
The non-volatile IVRi and volatile WRi registers are accessible
with the same address.
The Access Control Register (ACR) contains information and
control bits described in Table 2. The VOL bit at access control
register (ACR[7]) determines whether the access is to wiper
registers WRi or initial value registers IVRi.
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (see Figure 16). A STOP condition at the end of a read
operation, or at the end of a write operation places the device
in its standby mode.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN
WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVRi registers are accessible. If
VOL bit is 1, only the volatile WRi are accessible. Note, value
is written to IVRi register also is written to the corresponding
WRi. The default value of this bit is 0.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits of
data (see Figure 17).
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
This bit is logically ANDed with SHDN pin. When this bit is 0, all
DCPs are in Shutdown mode. Default value of SHDN bit is 1.
The ISL22346 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22346 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
The WIP bit (ACR[5]) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register to
0. The truth table for Shutdown mode is in Table 3.
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits matching the logic values present at
pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation (see
Table 4).
TABLE 3.
SHDN pin
High
SHDN bit
Mode
Normal operation
Shutdown
TABLE 4. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
1
1
0
0
Low
High
Shutdown
1
0
1
0
A2
A1
A0
R/W
Low
Shutdown
(MSB)
(LSB)
2
I C Serial Interface
2
The ISL22346 supports an I C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and the
device being controlled is the slave. The master always
FN6177 Rev 2.00
September 3, 2009
Page 12 of 16
ISL22346
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE
CHANGE STABLE
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
SIGNALS FROM
THE MASTER
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT SDA
1 0 1 0
A2A1A0 0
0 0 0 0
SIGNALS FROM
THE SLAVE
A
C
K
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
ADDRESS
BYTE
SIGNAL AT SDA
1 0 1 0 A2A1A0 0
0 0 0 0
1 0 1 0 A2A1A0 1
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
FN6177 Rev 2.00
September 3, 2009
Page 13 of 16
ISL22346
Write Operation
Read Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte, and
a STOP condition. After each of the three bytes, the ISL22346
responds with an ACK. At this time, the device enters its
standby state (see Figure 18). Device can receive more than
one byte of data by auto incrementing the address after each
received byte. Note after reaching the address 08h, the internal
pointer “rolls over” to address 00h. The non-volatile write cycle
starts after STOP condition is determined and it requires up to
20ms delay for the next non-volatile write. Thus, non-volatile
registers must be written individually.
A Read operation consist of a three byte instruction followed by
one or more Data Bytes (See Figure 19). The master initiates
the operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte,
a second START, and a second Identification byte with the R/W
bit set to “1”. After each of the three bytes, the ISL22346
responds with an ACK. Then the ISL22346 transmits Data
Bytes as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The master
terminates the read operation (issuing a ACK and a STOP
condition) following the last bit of the last Data Byte (see Figure
19).
The Data Bytes are from the registers indicated by an internal
pointer. This pointer initial value is determined by the Address
Byte in the Read operation instruction, and increments by one
during transmission of each Data Byte. After reaching the
memory location 08h, the pointer “rolls over” to 00h, and the
device continues to output data for each ACK received.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit is
0. If the WIP bit (ACR[5]) is not 0, the host should repeat its
reading sequence again.
FN6177 Rev 2.00
September 3, 2009
Page 14 of 16
ISL22346
Thin Micro Lead FramePlastic Package
(TMLFP)
L20.4x4A
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
0.80
0.05
0.80
NOTES
A
A1
A2
A3
b
0.70
0.75
-
-
-
0.02
-
0.55
9
0.20 REF
9
0.18
1.95
1.95
0.25
0.30
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.50 BSC
-
k
0.20
0.35
-
0.60
20
5
-
-
L
0.75
8
N
2
Nd
Ne
P
3
5
3
-
-
-
0.60
12
9
-
9
Rev. 0 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
FN6177 Rev 2.00
September 3, 2009
Page 15 of 16
ISL22346
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M20.173
INDEX
AREA
0.25(0.010)
M
B M
E
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.260
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
6.60
4.50
NOTES
1
2
3
A
A1
A2
b
-
-
L
0.002
0.031
0.0075
0.0035
0.252
0.169
0.05
0.80
0.19
0.09
6.40
4.30
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
D
9
c
-
-C-
D
3
A2
e
A1
E1
e
4
c
b
0.10(0.004)
0.026 BSC
0.65 BSC
-
0.10(0.004) M
C
A M B S
E
0.246
0.256
6.25
0.45
6.50
0.75
-
L
0.0177
0.0295
6
NOTES:
N
20
20
7
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
o
o
o
o
0
8
0
8
-
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 2006-2009. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6177 Rev 2.00
September 3, 2009
Page 16 of 16
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