ISL28117FUZ [RENESAS]
40V Precision Low Power Operational Amplifiers;
| 型号： | ISL28117FUZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 40V Precision Low Power Operational Amplifiers 放大器 光电二极管 |
| 文件： | 总39页 (文件大小：2296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL28117, ISL28217, ISL28417, ISL28417SEH
40V Precision Low Power Operational Amplifiers
FN6632
Rev 12.00
March 30, 2016
The ISL28117, ISL28217, ISL28417 and ISL28417SEH are a
Features
family of very high precision amplifiers featuring low noise vs
power consumption, low offset voltage, low bias current and low
temperature drift making them the ideal choice for applications
requiring both high DC accuracy and AC performance. The
combination of precision, low noise and small footprint provides
the user with outstanding value and flexibility relative to similar
competitive parts.
• Low input offset voltage . . . . . . . . . . . . . . . ±50µV, maximum
ISL28417SEH ±110µV, maximum
• Superb offset voltage TC. . . . . . . . . . . . 0.6µV/°C, maximum
ISL28417SEH 1µV/°C, maximum
• Input bias current. . . . . . . . . . . . . . . . . . . . . . ±1nA, maximum
ISL28417SEH ±5nA, maximum
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls and industrial controls.
• Input bias current TC . . . . . . . . . . . . . . . . ±5pA/°C, maximum
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . . 440µA
• Voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V
The ISL28117 single and ISL28217 dual are offered in
8 Ld SOIC, MSOP and TDFN packages. The ISL28417 is offered
in 14 Ld SOIC, 14 Ld TSSOP packages. All devices are offered
in standard pin configurations and operate over the extended
temperature range from -40°C to +125°C.
• Operating temperature range. . . . . . . . . . . .-40°C to +125°C
ISL28417SEH -55°C to +125°C
• Small package offerings in single, dual and quad
• Pb-free (RoHS compliant)
The ISL28417SEH is offered in a 14 Ld Hermetic Ceramic
Flatpack package. The device is offered in an industry
standard pin configuration and operates over the extended
temperature range from -55°C to +125°C.
• No phase reversal
Applications
• Precision instruments
• Medical instrumentation
• Power supply control
Related Literature
• AN1508 “ISL281X7SOICEVAL1Z Evaluation Board User’s
Guide”
• AN1509 “ISL282X7SOICEVAL2Z Evaluation Board User’s
Guide”
• Active filter blocks
• Thermocouples and RTD reference buffers
• Data acquisition
18
C
1
V
= ± 15V
S
16
14
12
10
8
8.2nF
V
+
-
OUTPUT
R
R
2
1
6
V
IN
+
4
1.84k
4.93k
3.3nF
2
C
2
V
-
0
-0.45
-0.30
-0.15
0
0.15
0.30
0.45
V
TC (µV/°C)
OS
SALLEN-KEY LOW PASS FILTER (10kHz)
FIGURE 2. V TEMPERATURE COEFFICIENT (V TC)
FIGURE 1. TYPICAL APPLICATION
OS
OS
FN6632 Rev 12.00
March 30, 2016
Page 1 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications ISL28117, ISL28217, ISL28417(V ± 15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
S
Electrical Specifications ISL28117, ISL28217, ISL28417 (V ± 5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
S
Electrical Specifications ISL28417SEH (V ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
S
Electrical Specifications ISL28417SEH (V ±5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
S
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ISL28117, ISL28217, ISL28417, ISL28417SEH SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
License Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Metallization Mask Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
L8.3x3K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MDP0027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
M14.173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
K14.A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN6632 Rev 12.00
March 30, 2016
Page 2 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
.
Ordering Information
PART
MARKING
V
(MAX)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
OS
(µV)
PART NUMBER
ISL28117FBBZ (Notes 1, 4, 6)
ISL28117FBZ (Notes 1, 4, 6)
ISL28117FUBZ (Notes 3, 4, 6)
ISL28117FUZ (Notes 3, 4, 6)
ISL28117FRTBZ (Notes 2, 4, 6)
ISL28117FRTZ (Notes 1, 4, 6)
ISL28217FBBZ (Notes 1, 4, 6)
ISL28217FBZ (Notes 1, 4, 6)
ISL28217FUZ (Notes 1, 4, 6)
ISL28217FRTBZ (Notes 1, 4, 6)
ISL28217FRTZ (Notes 1, 4, 6)
ISL28417FBBZ (Notes 1, 4, 6)
ISL28417FBZ (Notes 1, 4, 6)
ISL28417FVBZ (Notes 1, 4, 6)
ISL28417FVZ (Notes 1, 4, 6)
ISL28417SEHMF (Note 5)
ISL28417SEHF/PROTO (Note 5)
ISL28417SEHMX (Note 5)
ISL28417SEHX/SAMPLE (Note 5)
ISL28117SOICEVAL1Z
28117 FBZ
50 (B Grade)
8 Ld SOIC
M8.15E
M8.15E
28117 FBZ -C
8117Z
100 (C Grade)
70 (B Grade)
150 (C Grade)
75 (B Grade)
150 (C Grade)
50 (B Grade)
100 (C Grade)
150 (C Grade)
70 (B Grade)
150 (C Grade)
120 (B Grade)
200 (C Grade)
120 (B Grade)
200 (C Grade)
110 (B Grade)
110 (B Grade)
110 (B Grade)
110 (B Grade)
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
8 Ld TDFN
8 Ld TDFN
8 Ld SOIC
8 Ld SOIC
8 Ld MSOP
8 Ld TDFN
8 Ld TDFN
14 Ld SOIC
14 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP
14 Ld Flatpack
14 Ld Flatpack
DIE
M8.118B
M8.118B
L8.3x3K
L8.3x3K
M8.15E
M8.15E
M8.118B
L8.3x3K
L8.3x3K
MDP0027
MDP0027
M14.173
M14.173
K14.A
8117Z -C
8117
-C 8117
28217 FBZ
28217 FBZ -C
8217Z -C
8217
-C 8217
28417 FBZ
28417 FBZ -C
28417 FVZ
28417 FVZ-C
ISL28417SEHMF
ISL28417SEHF/PROTO
K14.A
DIE
Evaluation Board
Evaluation Board
ISL28217SOICEVAL2Z
NOTES:
1. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. Add “-T13” suffix for 6k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
3. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1.5k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
6. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217, ISL28417. For more information on MSL please see
techbrief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL28117
NUMBER OF DEVICES
PACKAGE
8 Ld SOIC
OPERATING TEMPERATURE RANGE
-40°C to +125°C
1
2
4
4
ISL28217
8 Ld SOIC
-40°C to +125°C
ISL28417
14 Ld SOIC
14 Ld Flatpack
-40°C to +125°C
ISL28417SEH
-55°C to +125°C
FN6632 Rev 12.00
March 30, 2016
Page 3 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Pin Configurations
ISL28117
(8 LD SOIC, MSOP)
TOP VIEW
ISL28117
(8 LD TDFN)
TOP VIEW
NC
-IN
+IN
V -
1
2
3
4
8
7
6
5
NC
V+
NC
NC
1
2
3
4
8
7
6
5
+
-
-IN
+IN
V-
V+
V
- +
V
OUT
OUT
NC
NC
ISL28217
(8 LD SOIC, MSOP)
TOP VIEW
ISL28217
(8 LD TDFN)
TOP VIEW
V
_A
1
2
3
4
8
7
6
5
V+
V
OUT
V
_A
V+
8
1
OUT
-IN_A
+IN_A
V -
_B
-
+
OUT
-IN_A
+IN_A
V-
V
_B
OUT
2
3
4
7
6
- +
-IN_B
+IN_B
-IN_B
+ -
+
-
5 +IN_B
ISL28417
ISL28417SEH
(14 LD SOIC, TSSOP)
TOP VIEW
(14 LD FLATPACK)
TOP VIEW
V
_A
14 V
_D
1
2
V
OUT
_A
V
_D
OUT
14
13
OUT
OUT
1
2
3
4
5
6
7
A
D
-IN_A
13
12
-IN_D
A
D
-IN_A
+IN_A
V+
-IN_D
-
-
+
+
-
-
-
-
+
+
-
-
3
4
5
6
7
+IN_A
V +
+IN_D
12
11
10
9
+IN_D
V-
11 V -
+IN_C
10
9
+IN_B
-IN_B
+IN_B
-IN_B
+IN_C
-IN_C
+
B
+
C
+
B
+
C
-IN_C
8
V
_C
OUT
V
_B
8
V
_B
V
_C
OUT
OUT
OUT
FN6632 Rev 12.00
March 30, 2016
Page 4 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Pin Descriptions
ISL28117
(8 Ld SOIC,
MSOP, TDFN)
ISL28217
(8 Ld SOIC,
MSOP, TDFN)
ISL28417/SEH
(14 Ld SOIC, TSSOP)
(14 Ld FLATPACK)
PIN NAME
+IN
EQUIVALENT CIRCUIT
Circuit 1
DESCRIPTION
3
-
3
5
-
-
3
Amplifier noninverting input
-
+IN_A
+IN_B
+IN_C
+IN_D
V-
-
5
-
10
12
11
-
-
-
4
4
-
Circuit 3
Circuit 1
Negative power supply
Amplifier inverting input
2
-IN
-
2
6
-
2
-IN_A
-IN_B
-IN_C
-IN_D
V+
-
6
-
9
-
-
13
4
7
8
-
Circuit 3
Circuit 2
Positive power supply
Amplifier output
6
-
V
OUT
-
1
7
-
1
V
V
_A
_B
_C
_D
OUT
-
7
OUT
-
-
8
V
OUT
-
14
-
V
OUT
1, 5, 8
PD
-
NC
PD
-
-
No internal connection
PD
-
Thermal Pad - TDFN package only.
Connect thermal pad to ground or most
negative potential.
V+
V+
V+
500Ω
500Ω
CAPACITIVELY
COUPLED
ESD CLAMP
IN-
IN+
OUT
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN6632 Rev 12.00
March 30, 2016
Page 5 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage ISL28417SEH (Note 13) . . . . . . . . . . . . . . . . 40V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Voltage (ISL28417SEH) . . . . . . . . . . . . . . 20V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . Indefinite
ESD Rating
Thermal Resistance (Typical)
(°C/W)
120
105
155
160
48
43
73
90
105
(°C/W)
60
50
50
55
7
JA
JC
8 Ld SOIC ISL28117 (Notes 7, 10) . . . . . . .
8 Ld SOIC ISL28217 (Notes 7, 10) . . . . . . .
8 Ld MSOP ISL28117 (Notes 7, 10). . . . . .
8 Ld MSOP ISL28217 (Notes 7, 10). . . . . .
8 Ld TDFN ISL28117 (Notes 8, 9). . . . . . . .
8 Ld TDFN ISL28217 (Notes 8, 9). . . . . . . .
14 Ld SOIC (Notes 8, 10). . . . . . . . . . . . . . .
14 Ld TSSOP (Notes 7, 10) . . . . . . . . . . . . .
14 Ld Flatpack (Notes 11, 12) . . . . . . . . . .
2
45
32
15
Human Body Model
ISL28117, ISL28417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
ISL28217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5kV
ISL28217 MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5kV
ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model
ISL28117, ISL28217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV
ISL28217 (MSOP), ISL28417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model
Maximum Storage Temperature Range . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (T ) . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile (Non-Hermetic Packages Only) . . . . . see TB493
JMAX
Recommended Operating Conditions
Ambient Temperature Range (T )
A
ISL28117, ISL28217, ISL28417. . . . . . . . . . . . . . . . . . .-40°C to +125°C
ISL28417SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
ISL28117, ISL28217 (MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
ISL28217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
ISL28417, ISL28417SEH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
7. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
10. For JC, the “case temp” location is taken at the package top center.
11. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
12. For JC, the "case temp" location is the center of the ceramic on the package underside.
2
13. No destructive single-event effects at effective LET of 73.9MeV•cm /mg up to a supply of ±20V. Reference manufacturers SEE report.
FN6632 Rev 12.00
March 30, 2016
Page 6 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28117, ISL28217, ISL28417(V ± 15V) V = 0, V = 0V, T = +25°C, unless
CM
O
A
S
otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
ISL28x17 B Grade
(Note 14)
-50
TYP
8
(Note 14)
UNIT
µV
V
Input Offset Voltage, SOIC, TSSOP
Package
50
110
100
190
70
OS
-110
-100
-190
-70
µV
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
4
µV
µV
10
10
µV
-120
-110
-160
-200
-70
120
110
160
200
70
µV
µV
T
= -40°C to +85°C
= -40°C to +125°C
µV
A
T
µV
A
Input Offset Voltage, MSOP Package
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-10
4
µV
-150
-150
-250
-150
-250
-75
150
150
250
150
250
75
µV
µV
µV
10
-10
10
10
µV
µV
Input Offset Voltage, TDFN Package
µV
-160
-70
160
70
µV
µV
-140
-150
-250
-0.6
-0.9
-0.75
-0.9
-0.8
-1
140
150
250
0.6
0.9
0.75
0.9
0.8
1
µV
µV
µV
TCV
OS
Input Offset Voltage Temperature
Coefficient; SOIC, TSSOP Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
0.14
0.14
0.20
0.3
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
nA
Input Offset Voltage Temperature
Coefficient; MSOP Package
0.1
0.14
0.14
0.1
-1
1
Input Offset Voltage Temperature
Coefficient; TDFN Package
-0.9
-0.7
-1
0.9
0.7
1
0.1
0.1
I
Input Bias Current
-1
0.08
1
B
-1.5
-5
1.5
5
nA
TCI
Input Bias Current Temperature
Coefficient
1
pA/°C
B
I
Input Offset Current
-1.50
-1.85
-3
0.08
1.50
1.85
3
nA
nA
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
0.45
pA/°C
pA/°C
V
OS
ISL28417 SOIC, TSSOP B and C Grade
Guaranteed by CMRR test
-4.00
-13
4.00
13
V
Input Voltage Range
CM
CMRR
Common-Mode Rejection Ratio
V
= -13V to +13V
120
120
120
120
145
145
dB
CM
dB
PSRR
Power Supply Rejection Ratio
V
= ±2.25V to ±20V
dB
S
dB
FN6632 Rev 12.00
March 30, 2016
Page 7 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28117, ISL28217, ISL28417(V ± 15V) V = 0, V = 0V, T = +25°C, unless
CM
O
A
S
otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
Open-Loop Gain
TEST CONDITIONS
V = -13V to +13V, R = 10kΩ to ground
O
(Note 14)
TYP
143
13.7
(Note 14)
UNIT
dB
V
A
130
VOL
L
V
Output Voltage High
Output Voltage Low
R = 10kΩ to ground
13.5
OH
L
13.2
V
R = 2kΩ to ground
13.30
13.1
13.55
-13.7
-13.55
0.44
43
V
L
V
V
R = 10kΩ to ground
-13.5
-13.2
-13.30
-13.1
0.53
V
OL
L
V
R = 2kΩ to ground
V
L
V
I
Supply Current/Amplifier
mA
mA
mA
V
S
0.68
I
Short-Circuit
SC
V
Supply Voltage Range
Guaranteed by PSRR
±2.25
±20
SUPPLY
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
Voltage Noise V
A = 1k, R = 2kΩ
1.5
0.25
10
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
nVp-p
P-P
e
Voltage Noise Density
nV/Hz
nV/Hz
nV/Hz
nV/Hz
pA/Hz
%
n
f = 100Hz
f = 1kHz
8.2
8
f = 10kHz
f = 1kHz
8
in
THD + N
Current Noise Density
0.1
Total Harmonic Distortion
1kHz, G = 1, V = 3.5V
, R = 2kΩ
0.0009
0.0005
O
RMS
L
1kHz, G = 1, V = 3.5V
, R = 10kΩ
%
O
RMS
L
TRANSIENT RESPONSE
SR Slew Rate, V
20% to 80%
A = 11, R = 2kΩV = 4V
0.5
V/µs
ns
OUT
t , t ,
V
L
O
P-P
Rise Time
A = 1, V
= 50mV ,
P-P
130
r
f
V
OUT
Small Signal
10% to 90% of V
R = 10kΩ to V
OUT
L
CM
Fall Time
90% to 10% of V
A
= 1,
V
= 50mV , RL = 10kΩto V
130
21
ns
µs
µs
µs
µs
V
OUT P-P CM
OUT
t
Settling Time to 0.1%
10V Step; 10% to V
A
= -1,
= -1,
= -1,
= -1,
V
= 10V , RL = 5kΩto V
P-P CM
s
V
OUT
OUT
OUT
OUT
OUT
Settling Time to 0.01%
10V Step; 10% to V
A
V
= 10V , RL = 5kΩto V
P-P CM
24
V
OUT
Settling Time to 0.1%
4V Step; 10% to V
A
V
V
= 4V , RL = 5kΩto V
P-P CM
13
18
V
OUT
Settling Time to 0.01%
4V Step; 10% to V
A
= 4V , RL = 5kΩto V
P-P CM
V
OUT
t
Output Positive Overload Recovery Time A = -100, V = 0.2V , R = 2kΩ to V
IN P-P
5.6
µs
µs
OL
V
L
CM
Output Negative Overload Recovery Time A = -100, V = 0.2V , R = 2kΩ to V
IN P-P
10.6
V
L
CM
FN6632 Rev 12.00
March 30, 2016
Page 8 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28117, ISL28217, ISL28417 (V ± 5V)
S
V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C.
O A
CM
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
ISL28x17 B Grade
(Note 14)
TYP
8
(Note 14)
UNIT
µV
V
Input Offset Voltage, SOIC, TSSOP
Package
-50
-110
-100
-190
-70
50
110
100
190
70
OS
µV
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
4
µV
µV
10
10
µV
-120
-110
-160
-200
-70
120
110
160
200
70
µV
µV
T
= -40°C to +85°C
= -40°C to +125°C
µV
A
T
µV
A
Input Offset Voltage, MSOP Package
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
-10
4
µV
-150
-150
-250
-150
-250
-75
150
150
250
150
250
75
µV
µV
µV
10
-10
10
10
µV
µV
Input Offset Voltage, TDFN Package
µV
-160
-70
160
70
µV
µV
-140
-150
-250
-0.60
-0.90
-0.75
-0.9
-0.8
-1
140
150
250
0.60
0.90
0.75
0.9
0.8
1
µV
µV
µV
TCV
OS
Input Offset Voltage Temperature
Coefficient; SOIC, TSSOP Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28417 B Grade
ISL28417 C Grade
ISL28117 B Grade
ISL28117 C Grade
ISL28217 C Grade
ISL28117 B Grade
ISL28217 B Grade
ISL28x17 C Grade
0.14
0.14
0.20
0.3
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
µV/°C
nA
Input Offset Voltage Temperature
Coefficient; MSOP Package
0.1
0.14
0.14
0.1
-1
1
Input Offset Voltage Temperature
Coefficient; TDFN Package
-0.9
-0.7
-1
0.9
0.7
1
0.1
0.1
I
Input Bias Current
-1
0.18
1
B
-1.5
-5
1.5
5
nA
TCI
Input Bias Current Temperature
Coefficient
1
pA/°C
B
I
Input Offset Current
-1.5
-1.85
-3
0.3
1.5
1.85
3
nA
nA
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
0.45
pA/°C
pA/°C
V
OS
ISL28417 SOIC, TSSOP B and C Grade
-4.00
-3
4.00
3
V
Input Voltage Range
CM
CMRR
Common-Mode Rejection Ratio
V
= -3V to +3V
120
120
145
dB
CM
dB
FN6632 Rev 12.00
March 30, 2016
Page 9 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28117, ISL28217, ISL28417 (V ± 5V)
S
V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
O A
CM
MIN
MAX
PARAMETER
PSRR
DESCRIPTION
TEST CONDITIONS
= ±2.25V to ±5V
(Note 14)
TYP
145
(Note 14)
UNIT
dB
dB
dB
V
Power Supply Rejection Ratio
V
V
120
120
130
3.5
S
A
Open-Loop Gain
= -3.0V to +3.0V, R = 10kΩ to ground
143
3.7
VOL
O
L
V
Output Voltage High
R = 10kΩ to ground
L
OH
3.2
V
R = 2kΩ to ground
3.30
3.1
3.55
-3.7
V
L
V
V
Output Voltage Low
R = 10kΩ to ground
-3.5
-3.2
V
OL
L
V
R = 2kΩ to ground
-3.55
0.44
43
-3.30
-3.1
V
L
V
I
Supply Current/Amplifier
Short-Circuit
0.53
0.68
mA
mA
mA
S
I
SC
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
Voltage Noise
A = 1k, RL = 2kΩ
1.5
0.25
12
8.6
8
MHz
V
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
np-p
e
Voltage Noise Density
nV/Hz
nV/Hz
nV/Hz
nV/Hz
pA/Hz
n
f = 100Hz
f = 1kHz
f = 10kHz
f = 1kHz
8
in
Current Noise Density
0.1
TRANSIENT RESPONSE
SR Slew Rate, V
t , t , Small Signal Rise Time
20% to 80%
A =11, R = 2kΩV = 4V
0.5
V/µs
ns
OUT
V
L
O
P-P
A = 1, V
= 50mV ,
P-P
130
r
f
V
OUT
10% to 90% of V
R
L = 10kΩ to V
OUT
CM
Fall Time
90% to 10% of V
A
R
= 1,
V
= 50mV ,
P-P
130
12
19
7
ns
µs
µs
µs
µs
V
OUT
L = 10kΩ to V
OUT
CM
t
Settling Time to 0.1%
4V Step; 10% to V
A
= -1,
L = 5kΩ to V
V
= 4V
,
P-P
s
V
OUT
R
OUT
Settling Time to 0.01%
4V Step; 10% to V
CM
AV = -1, V
OUT
R
= 4V
CM
,
P-P
L = 5kΩ to V
OUT
t
Output Positive Overload Recovery Time
A
= -100, V = 0.2V
L = 2kΩ to V
CM
OL
V IN P-P
R
Output Negative Overload Recovery Time
A
= -100, V = 0.2V
5.8
V
IN
P-P
R
= 2kΩ to V
L
CM
FN6632 Rev 12.00
March 30, 2016
Page 10 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28417SEH (V ±15V)
S
V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
CM O A
60
apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance.
MIN
MAX
PARAMETER
DESCRIPTION
Input Offset Voltage
CONDITIONS
(Note 14)
TYP
10
(Note 14)
UNIT
µV
V
85
110
1
OS
µV
TCV
OS
Offset Voltage Drift
Input Bias Current
0.1
µV/°C
nA
I
-2.5
-5
0.08
2.5
5
IB
T
= -55°C, +125°C
nA
A
T
= +25°C, post radiation
-15
-5
15
5
nA
A
TCI
IB
Input Bias Current Temperature
Coefficient
1
pA/°C
I
Input Offset Current
-2.50
-3
0.08
2.50
nA
nA
OS
T
= -55°C, +125°C
3
6
3
A
T
= +25°C, post radiation
-6
nA
A
TCI
Input Offset Current Temperature
Coefficient
-3
0.42
pA/°C
OS
V
Input Voltage Range
Guaranteed by CMRR test
-13
120
13
V
dB
dB
dB
dB
V/mV
V
CM
CMRR
Common-Mode Rejection Ratio
V
V
V
= -13V to +13V
145
145
CM
120
PSRR
Power Supply Rejection Ratio
= ±2.25V to ±20V
120
S
120
A
Open-Loop Gain
= -13V to +13V, R = 10kΩ to ground
3,000
13.5
13.2
13.30
13.0
14,000
13.7
VOL
O
L
V
Output Voltage High
R = 10kΩ to ground
L
OH
V
R = 2kΩ to ground
13.55
-13.7
-13.55
0.44
43
V
L
V
V
Output Voltage Low
R = 10kΩ to ground
-13.5
-13.2
-13.30
-13.0
0.53
V
OL
L
V
R = 2kΩ to ground
V
L
V
I
Supply Current/Amplifier
mA
mA
mA
V
S
0.68
I
Short-Circuit Current
Supply Voltage Range
SC
V
Guaranteed by PSRR
±2.25
±20
SUPPLY
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
Voltage Noise V
A = 1k, R = 2kΩ
1.5
0.25
10
8.2
8
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
nVp-p
P-P
Voltage Noise Density
e
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
n
f = 100Hz
f = 1kHz
f = 10kHz
8
FN6632 Rev 12.00
March 30, 2016
Page 11 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28417SEH (V ±15V)
S
V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
CM O A
60
apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued)
MIN
MAX
PARAMETER
in
DESCRIPTION
Current Noise Density
Total Harmonic Distortion
CONDITIONS
(Note 14)
TYP
0.1
(Note 14)
UNIT
pA/√Hz
%
f = 1kHz
1kHz, G = 1, V = 3.5VRMS, R = 2kΩ
THD + N
0.0009
0.0005
O
L
1kHz, G = 1, V = 3.5VRMS, R = 10kΩ
%
O
L
TRANSIENT RESPONSE
SR Slew Rate, V
20% to 80%
OUT
A = 11, R = 2kΩ, V = 4V
0.3
0.5
130
130
V/µs
V/µs
ns
OUT
V
L
O
P-P
0.2
t , t ,
Rise Time
A = 1, V
= 50mV ,
P-P
450
625
600
700
r
f
V
OUT
Small Signal
10% to 90% of V
R = 10kΩ to V
L
CM
ns
Fall Time
A = 1, V
OUT
= 50mV , R = 10kΩ to
P-P
ns
V
L
90% to 10% of VOUT
Settling Time to 0.1%
V
CM
ns
t
AV = -1, V
OUT
= 10V , R = 5kΩ to V
P-P CM
21
24
13
18
µs
s
L
10V Step; 10% to V
OUT
Settling Time to 0.01%
10V Step; 10% to V
A
= -1,
V
= 10V , RL = 5kΩto V
µs
µs
µs
V
OUT P-P CM
OUT
Settling Time to 0.1%
4V Step; 10% to V
A = -1, V
= 4V , R = 5kΩ to V
P-P CM
V
OUT
L
OUT
Settling Time to 0.01%
4V Step; 10% to V
A = -1, V
= 4V , R = 5kΩ to V
P-P CM
V
OUT
L
OUT
t
Output Positive Overload Recovery Time A = -100, V = 0.2V , R = 2kΩ to V
5.6
10.6
15
µs
µs
%
OL
V
IN P-P
L
CM
Output Negative Overload Recovery Time A = -100, V = 0.2V , R = 2kΩ to V
IN P-P
V
L
CM
OS+
OS-
Positive Overshoot
Negative Overshoot
A = 1, V
OUT
= 10V , R = 0Ω
P-P
CM
V
f
R = 2kΩ to V
L
33
33
%
A = 1, V
OUT
= 10V , R = 0Ω
P-P
15
%
V
f
R = 2kΩ to V
L
CM
%
Electrical Specifications ISL28417SEH (V ±5V) V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
CM
O
A
S
60
apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance.
MIN
MAX
PARAMETER
DESCRIPTION
Input Offset Voltage
TEST CONDITIONS
(Note 14)
TYP
10
(Note 14)
UNIT
µV
V
150
250
1
OS
µV
TCV
OS
Offset Voltage Drift
Input Bias Current
0.1
µV/°C
nA
I
-2.50
-5
0.18
2.50
5
IB
T
= -55°C, +125°C
nA
A
T
= +25°C, post radiation
-15
-5
15
5
nA
A
TCI
IB
Input Bias Current Temperature Coefficient
Input Offset Current
1
pA/°C
nA
I
-2.5
-3
0.3
2.5
3
OS
T
= -55°C, +125°C
nA
A
T
= +25°C, post radiation
6
0.42
6
nA
A
FN6632 Rev 12.00
March 30, 2016
Page 12 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28417SEH (V ±5V) V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
CM
O
A
S
60
apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued)
MIN
MAX
PARAMETER
TCI
DESCRIPTION
Input Offset Current Temperature Coefficient
Input Voltage Range
TEST CONDITIONS
(Note 14)
TYP
(Note 14)
UNIT
pA/°C
V
-3
-3
0.42
3
3
OS
V
CM
CMRR
PSRR
Common-Mode Rejection Ratio
V
V
V
= -3V to +3V
120
120
120
120
3,000
145
145
dB
CM
dB
Power Supply Rejection Ratio
= ±2.25V to ±5V
= -3.0V to +3.0V
dB
S
dB
A
Open-Loop Gain
14,000
3.7
V/mV
VOL
O
R = 10kΩ to ground
L
V
Output Voltage High
R = 10kΩ to ground
3.5
3.2
V
V
OH
L
R = 2kΩ to ground
3.300
3.0
3.550
-3.7
V
L
V
V
Output Voltage Low
R = 10kΩ to ground
-3.5
-3.2
V
OL
L
V
R = 2kΩ to ground
-3.55
0.44
43
-3.30
-3.0
V
L
V
I
Supply Current/Amplifier
Short-Circuit Current
0.53
0.68
mA
mA
mA
S
I
SC
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
Voltage Noise
A = 1k, R = 2kΩ
1.5
0.25
12
8.6
8
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
np-p
e
Voltage Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
n
f = 100Hz
f = 1kHz
f = 10kHz
f = 1kHz
8
in
Current Noise Density
0.1
TRANSIENT RESPONSE
SR Slew Rate, V
20% to 80%
A = 11, R = 2kΩ, VO = 4V
0.5
V/µs
ns
OUT
t , t ,
V
L
P-P
Rise Time
AV = 1, V
= 50mV ,
P-P
130
r
f
OUT
Small Signal
10% to 90% of V
R = 10kΩ to V
OUT
L
CM
Fall Time
90% to 10% of V
A = 1, V
OUT
= 50mV
,
P-P
130
12
ns
µs
µs
V
R = 10kΩ to V
OUT
L
CM
t
Settling Time to 0.1%
4V Step; 10% to V
A = -1, V
OUT
= 4V
CM
,
P-P
s
V
R = 5kΩ to V
OUT
Settling Time to 0.01%
4V Step; 10% to V
L
A = -1, V
OUT
= 4V
CM
,
P-P
19
V
R = 5kΩ to V
OUT
L
FN6632 Rev 12.00
March 30, 2016
Page 13 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Electrical Specifications ISL28417SEH (V ±5V) V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits
CM
O
A
S
60
apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 14)
TYP
7
(Note 14)
UNIT
µs
t
Output Positive Overload Recovery Time
A = -100, V = 0.2V
IN
OL
V
P-P
R = 2kΩ to V
L
CM
Output Negative Overload Recovery Time
Positive Overshoot
A = -100, V = 0.2V
IN
5.8
15
15
µs
%
V
P-P
R = 2kΩ to V
L
CM
OS+
OS-
A = 1, V
OUT
= 10V , R = 0Ω
P-P
V
f
R = 2kΩ to V
L
CM
Negative Overshoot
A = 1, V
OUT
= 10V , R = 0Ω
P-P
%
V
f
R = 2kΩ to V
L
CM
NOTE:
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified.
S
CM
L
140
120
100
80
140
V
= ±15V
S
V
= ±5V
S
ISL28217FBBZ
ISL28217FBBZ
120
100
80
60
40
20
0
60
40
20
0
-50
-30
-10
10
(µV)
30
50
-50
-30
-10
10
(µV)
30
50
V
V
OS
OS
FIGURE 4. V DISTRIBUTION FOR GRADE B
OS
FIGURE 3. V DISTRIBUTION FOR GRADE B
OS
300
250
200
150
100
50
300
250
200
150
100
50
V
= ± 5V
S
V
= ± 15V
S
ISL28217FBZ
ISL28217FBZ
0
0
-100
-60
-20
20
60
100
-100
-60
-20
20
60
100
V
(µV)
V
(µV)
OS
OS
FIGURE 5. V DISTRIBUTION FOR GRADE C
OS
FIGURE 6. V DISTRIBUTION FOR GRADE C
OS
FN6632 Rev 12.00
March 30, 2016
Page 14 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
100
18
V
= ± 15V
V
= ± 15V
S
S
16
14
12
10
8
50
0
6
-50
4
2
-100
0
-50
0
50
100
150
150
150
-0.45
-0.30
-0.15
0
0.15
0.30
0.45
TEMPERATURE (°C)
V TC (µV/°C)
OS
FIGURE 7. V RANGE vs TEMPERATURE
OS
FIGURE 8. TCV vs NUMBER OF AMPLIFIERS
OS
100
50
16
14
12
10
8
V
= ± 5V
V
= ±5V
S
S
0
6
-50
-100
4
2
0
-50
0
50
100
-0.45
-0.30
-0.15
0
0.15
0.30
0.45
TEMPERATURE (°C)
V
TC (µV/°C)
OS
FIGURE 9. V RANGE vs TEMPERATURE
OS
FIGURE 10. TCV vs NUMBER OF AMPLIFIERS
OS
500
70
60
50
40
30
20
10
0
V
= ± 15V
V
= ±15V
S
S
400
300
200
100
0
-100
-200
-300
-400
-500
-50
0
50
100
-3.5
-2.5
-1.5
-0.5
I
0.5
1.5
2.5
3.5 MORE
+TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 11. I + RANGE vs TEMPERATURE
FIGURE 12. TCI + vs NUMBER OF AMPLIFIERS
B
B
FN6632 Rev 12.00
March 30, 2016
Page 15 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
70
500
400
300
200
100
0
V
= ± 15V
S
V
= ±15V
S
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50
0
50
100
150
I -TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 14. TCI - vs NUMBER OF AMPLIFIERS
B
FIGURE 13. I - RANGE vs TEMPERATURE
B
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
V
= ± 5V
S
V
S
= ±5V
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
TEMPERATURE (°C)
I +TC (pA/°C)
B
FIGURE 15. I + RANGE vs TEMPERATURE
FIGURE 16. TCI + vs NUMBER OF AMPLIFIERS
B
B
90
80
70
60
50
40
30
20
10
0
500
400
300
200
100
0
V
= ± 5V
V
S
= ±5V
S
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-50
0
50
100
150
I -TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 17. I - RANGE vs TEMPERATURE
FIGURE 18. TCI - vs NUMBER OF AMPLIFIERS
B
B
FN6632 Rev 12.00
March 30, 2016
Page 16 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
90
500
400
300
200
100
0
V
= ± 15V
V
= ±15V
S
S
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
TCI
0.5
1.5
2.5
3.5
-50
0
50
100
150
(pA/°C)
TEMPERATURE (°C)
OS
FIGURE 19. I RANGE vs TEMPERATURE
OS
FIGURE 20. I TC vs NUMBER OF AMPLIFIERS
OS
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
V
= ± 5V
V
S
= ±5V
S
-100
-200
-300
-400
-500
-3.5
-2.5
-1.5
-0.5
TCI
0.5
1.5
2.5
3.5
-50
0
50
100
150
(pA/°C)
TEMPERATURE (°C)
OS
FIGURE 21. I RANGE vs TEMPERATURE
OS
FIGURE 22. I TC vs NUMBER OF AMPLIFIERS
OS
0.7
0.6
0.5
0.4
0.3
20000
15000
10000
V
= ±13V
O
±15V
±2.25V
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. SUPPLY CURRENT PER AMPLIFIERS vs TEMPERATURE
FIGURE 24. A vs TEMPERATURE
VOL
FN6632 Rev 12.00
March 30, 2016
Page 17 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
-140
-145
-150
-155
-130
-135
-140
-145
-150
-155
-160
V
= ±13V
V
= ±2.25V TO ±20V
CM
S
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 25. PSRR vs TEMPERATURE
FIGURE 26. CMRR vs TEMPERATURE
60
55
50
45
40
35
30
25
60
I
- AT ±15V
I
+ AT ±15V
SC
SC
55
50
45
40
35
30
25
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. POSITIVE SHORT-CIRCUIT CURRENT vs TEMPERATURE
FIGURE 28. NEGATIVE SHORT-CIRCUIT CURRENT vs TEMPERATURE
100
100
V
= ±5V
S
80
60
40
20
0
V
= ±15V
80
60
40
20
0
S
+125°C
+125°C
+25°C
-40°C
+25°C
-40°C
-20
-40
-60
-20
-40
-60
-15
-10
-5
0
5
10
15
-5
-3
-1
1
3
5
V
(V)
VCM (V)
CM
FIGURE 29. INPUT V vs INPUT COMMON-MODE VOLTAGE,
OS
FIGURE 30. INPUT V vs INPUT COMMON-MODE VOLTAGE,
OS
V
= ±15
V = ±5V
S
S
FN6632 Rev 12.00
March 30, 2016
Page 18 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
14.4
14.2
14.0
13.8
13.6
13.4
13.2
-13.2
V
= ±15V
S
V
= ±15V
= 10kΩ
S
R
= 10kΩ
L
R
L
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. V vs TEMPERATURE
OH
FIGURE 32. V vs TEMPERATURE,
OL
14.4
14.2
14.0
13.8
13.6
13.4
13.2
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
V
= ±15V
= 2kΩ
S
V
= ±15V
= 2kΩ
S
R
L
R
L
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 33. V vs TEMPERATURE
OH
FIGURE 34. V vs TEMPERATURE
OL
250
200
150
100
50
100
V
= ±18.2V
S
A
= 1
V
10
0
-50
-100
-150
-200
-250
V+ = 36.4V
= 10, R = 100k
R
g
f
AV = 10,000
1
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
TIME (s)
FIGURE 35. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
FIGURE 36. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FN6632 Rev 12.00
March 30, 2016
Page 19 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
1
200
180
160
140
120
100
80
V
= ±18.2V
= 1
S
A
V
PHASE
60
40
20
0
GAIN
-20
-40
-60
-80
-100
R
C
= 10k
L
= 10pF
L
SIMULATION
0.1
1
10
100
1k
10k
100k
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. INPUT NOISE CURRENT SPECTRAL DENSITY
FIGURE 38. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ
L
C = 10pF
L
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
40
20
V
= ±2.5V
S
V
= ±5V
S
PHASE
V
= ±15V
S
GAIN
0
60
-20
-40
-60
R
C
= 10k
L
R
C
= INF
L
L
40
= 100pF
L
= 10pF
SIMULATION
20
-80
SIMULATION
-100
0
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 39. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ
FIGURE 40. CMRR vs FREQUENCY, V = ±2.25, ±5V, ±15V
S
L
C = 100pF
L
120
110
100
90
80
70
60
50
40
30
20
10
0
70
R
= 100, R = 100k
f
g
A
= 1000
= 100
= 10
V
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
PSRR+ AND PSRR- V = ±2.25V
g
S
V
C
R
= ±20V
= 4pF
= 10k
S
L
A
V
L
R
C
= INF
= 4pF
L
L
V
= 50mV
P-P
OUT
A
V
AV = +1
= 1V
V
CM
P-P
R
= 10k, R = 100k
f
g
A
= 1
V
PSRR+ AND PSRR- V = ±15V
S
R
= OPEN, R = 0
f
g
-10
-10
10M
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 41. PSRR vs FREQUENCY, V = ±5V, ±15V
FIGURE 42. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
S
FN6632 Rev 12.00
March 30, 2016
Page 20 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
4
2
R
= 10k
L
2
R = R = 100k
1
f
g
0
0
-2
R = R = 10k
-1
-2
-3
-4
-5
-6
-7
-8
f
g
R
= 4.99k
L
-4
R = R = 1k
f
g
-6
R
= 1k
L
R = R = 100
f
g
-8
V
= ±20V
= 10k
S
V
= ±20V
= 4pF
= +1
R
R
= 499
S
L
L
L
-10
-12
-14
-16
C
= 4pF
C
L
AV = +2
A
V
R
= 100
L
V
= 50mV
V
= 50mV
OUT
P-P
OUT
P-P
10k
10
100
1k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 43. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
R /R
FIGURE 44. GAIN vs FREQUENCY vs R
L
f
g
2
1
12
10
8
V
= ±2.25V
S
V
= ±2.5V
= 10k
= +1
S
V
= ±5V
R
S
L
0
A
V
V
= 50mV
P-P
OUT
-1
-2
-3
-4
-5
-6
-7
-8
6
V
= ±15V
S
4
2
C = 0.01µF
L
V
= ±20V
C
= 47pF
S
L
0
C
R
= 4pF
-2
-4
-6
-8
L
L
C
= 100pF
L
= 10k
= +1
C
= 4pF
C
= 270pF
L
L
A
V
C
= 470pF
L
V
= 50mV
OUT
P-P
C
= 1000pF
10k
L
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
10
100
1k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 45. GAIN vs FREQUENCY vs C
FIGURE 46. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
L
180
160
140
120
100
80
2.4
2.0
1.6
1.2
0.8
0.4
0
V
S
= ±15V, R = 2k, 10k
L
S
V
= ±15V
S
R -DRIVER CH. = OPEN
V
= ±5V, R = 2k, 10k
L
L
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
R -RECEIVING CH. = 10k
L
60
C
A
= 4pF
= +1
L
C
A
= 4pF
= +1
L
40
V
V
V
= 1V
V
= 4V
SOURCE
P-P
1k
OUT
P-P
20
0
10
100
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90 100
FREQUENCY (Hz)
TIME (µs)
FIGURE 47. CROSSTALK, V = ±15V
FIGURE 48. LARGE SIGNAL TRANSIENT RESPONSE vs R V = ±5V,
L S
S
±15V
FN6632 Rev 12.00
March 30, 2016
Page 21 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise specified. (Continued)
S
CM
L
60
50
40
30
20
10
0
14
12
10
8
0.04
INPUT
0
-0.04
-0.08
-0.12
-0.16
-0.20
-0.24
-0.28
OUTPUT AT V = ±15V
S
V
= ±15V
S
R
C
A
= 10k
= 4pF
= +1
R
C
A
= 2k
L
L
L
L
6
= 4pF
= -100
V
V
4
R = 100k, R = 1k
f
g
V
= 50mV
P-P
OUT
V
= 200mV
P-P
IN
2
0
OUTPUT AT V = ±5V
S
-10
-2
0
5
10
15
20
TIME (µs)
25
30
35
40
0
10
20
30
40
50
60
70
80
90 100
TIME (µs)
FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V
FIGURE 49. SMALL SIGNAL TRANSIENT RESPONSE, V = ±5V, ±15V
S
V
S
80
70
60
50
40
30
20
10
0
0.24
0.20
0.16
0.12
0.08
0.04
0
4
V
R
= ±15V
= 10k
S
L
2
OUTPUT AT V = ±5V
S
A
= 1
V
0
V
= 50mV
P-P
OUT
R
C
A
= 2k
-2
-4
-6
-8
-10
-12
L
L
= 4pF
= -100
V
R = 100k, R = 1k
f
g
V
= 200mV
P-P
IN
INPUT
80
OUTPUT AT V = ±15V
S
-0.04
-0.08
1
10
100
1k
10k
100k
0
10
20
30
40
50
60
70
90 100
CAPACITANCE (pF)
TIME (µs)
FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V
FIGURE 52. % OVERSHOOT vs LOAD CAPACITANCE, V = ±15V
S
V
S
100M
10M
1M
100k
10k
1k
100
10
1
0.01 0.1
1
10
100
1k
10k 100k 1M
10M
FREQUENCY (Hz)
FIGURE 53. COMMON-MODE INPUT IMPEDANCE
FN6632 Rev 12.00
March 30, 2016
Page 22 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Applications Information
V+
Functional Description
The ISL28117, ISL28217, ISL28417 and ISL28417SEH are
single, dual and quad, low noise precision op amps. Both devices
are fabricated in a new precision 40V complementary bipolar DI
process. A super-beta NPN input stage with input bias current
cancellation provides low input bias current (180pA typical), low
input offset voltage (13µV typical), low input noise voltage
(8nV/Hz) and low 1/f noise corner frequency (~8Hz). These
amplifiers also feature high open loop gain (18kV/mV) for
excellent CMRR (145dB) and THD+N performance (0.0005% at
500Ω
V
OUT
500Ω
V
R
IN
L
V-
FIGURE 54. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dv/dt exceeds the
0.5V/µs slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output resulting in severe distortion and possible diode
failure. Figure 48 provides an example of distortion free large signal
3.5V
, 1kHz into 2kΩ). A complimentary bipolar output stage
RMS
enables high capacitive load drive without external
compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). The Power Supply Rejection Ratio typically exceeds
140dB over the full operating voltage range and 120dB
minimum over the -40°C to +125°C temperature range. The
worst case common-mode input voltage range over-temperature
is 2V to each rail. With ±15V supplies, CMRR performance is
typically >130dB over-temperature. The minimum CMRR
performance over the -40°C to +125°C temperature range is
>120dB for power supply voltages from ±5V (10V) to ±15V (30V).
response using a 4V input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be equal
to the maximum power supply voltage (40V) without damage.
P-P
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to
20mA maximum.
Output Current Limiting
Input Performance
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short-circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability. Figures 27 and 28 show the current limit variation with
temperature.
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <1nA and excellent temperature stabilization.
Figures 11 through 18 show the high degree of bias current
stability at ±5V and ±15V supplies that is maintained across the
-40°C to +125°C temperature range. The low bias current TC
also produces very low input offset current TC, which reduces DC
input offset errors in precision, high impedance amplifiers.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28117, ISL28217, ISL28417 and ISL28417SEH
are immune to output phase reversal, even when the input
voltage is 1V beyond the supplies.
The +25°C maximum input offset voltage (V ) for the “B” grade
OS
is 50µV and 100µV for the “C” grade. Input offset voltage
temperature coefficients (V TC) are a maximum of ±0.6µV/°C
for the “B” and ±0.9µV/°C for the “C” grade. Figures 3 through 6
show the typical gaussian-like distribution over the ±5V to ±15V
OS
Unused Channels
The user must configure unused channel(s) to prevent them from
oscillating. The unused channel(s) oscillates if the input and
output pins are floating. This results in higher than expected
supply currents and possible noise injection into the other
channel(s) being used. The proper way to prevent this oscillation
is to short the output to the inverting input and ground the
positive input, as shown in Figure 55.
supply range and over the full temperature range. The V
temperature behavior is smooth (Figures 7 through 10)
maintaining constant TC across the entire temperature range.
OS
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500Ω current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 54).
-
+
FIGURE 55. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
FN6632 Rev 12.00
March 30, 2016
Page 23 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Power Dissipation
License Statement
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
temperature (T
) for all applications to determine if power
JMAX
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
(EQ. 1)
T
= T
+ xPD
MAX JA MAXTOTAL
JMAX
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications and the
Licensee may make copies of this macro-model for use within
their company only.
Where:
• PD
is the sum of the maximum power dissipation of
MAXTOTAL
each amplifier in the package (PD
)
MAX
• PD
for each amplifier can be calculated using Equation 2:
MAX
V
OUTMAX
R
L
----------------------------
PD
= V I
+ V - V
OUTMAX
This macro-model is provided “AS IS, WHERE IS AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
(EQ. 2)
MAX
S
qMAX
S
Where:
• T
= Maximum ambient temperature
MAX
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
• = Thermal resistance of the package
JA
• PD
= Maximum power dissipation of 1 amplifier
MAX
• V = Total supply voltage
S
• I
qMAX
= Maximum quiescent supply current of 1 amplifier
= Maximum output voltage swing of the application
• V
OUTMAX
ISL28117, ISL28217, ISL28417, ISL28417SEH
SPICE Model
Figure 56 shows the SPICE model schematic and Figure 57
shows the net list for the ISL28117, ISL28217, ISL28417 and
ISL28417SEH SPICE model for a Grade “B” part. The model is a
simplified version of the actual device and simulates important
AC and DC parameters. AC parameters incorporated into the
model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and
Phase. The DC parameters are VOS, IOS, total supply current and
output voltage swing. The model uses typical parameters given in
the “Electrical Specifications” table beginning on page 7. The
AVOL is adjusted for 155dB with the dominant pole at 0.02Hz.
The CMRR is set (210dB, f = 10Hz). The input stage models
cm
the actual device to present an accurate AC representation. The
model is configured for ambient temperature of +25°C.
Figures 58 through 68 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Closed Loop Gain vs RL, Large Signal Step Response, Open Loop
Gain Phase and Simulated CMRR vs Frequency.
FN6632 Rev 12.00
March 30, 2016
Page 24 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
.
V++
V++
R
R
4
IEE1
3
4
5
96E-6
4.45k
4.45k
4
5
CASCODE
CASCODE
Q4
6
7
Q5
3
D1
DX
C4
2
2pF
SUPERB
SUPERB
V
-
IN
V
-
Q1 Q2
IN
C
2pF
5
V5
R
1
8
5E11
24
25
EOS
C
1
6
I
OS
MIRROR
V
C
1.2pF
D12
DN
0.1V
V
+
-
CM
+
V
Q3
-
mid
0.3nA
R
17
9
+
-
IEE
200E-6
R
2
290
In+
V
5E11
OS
e
n
13E-6
V
+
IN
V--
VCM
Voltage Noise
Input Stage
V++
V++
D2
DX
D4
DX
G1
G3
G5
L
1
13
10
4
15.9159E-3
+
+
+
-
+
-
+
-
R
R
7
C
R
9
2.1E3
5
2
V1
V3
1.86V
17
1
400pF
R
11
1
1.86V
1.99e10
-
-
5
11
Vc
V
g
Vmid
Vg
VC
R
L
12
1
R
R
8
R
C
6
3
10
Vmid
V--
G4
G6
G2
1
2.1E3
1.99e10
400pF
18
+
-
+
-
-
+
-
+
-
+
V4
V2
2
1.86V
1.86V
12
14
V
15.9159E-3
V--
CM
D5
DX
D3
DX
V
ST
nd
CM
Mid Supply Ref
Common-Mode Gain Stage
1
Gain Stage
2
Gain Stage
V++
D8
DX
D9
DX
G7
V+
V+
+
-
+
E2
R
15
90
-
-
+
22
23
V5
DX
DX
D6
20
21
ISY
0.44mA
V
OUT
VOUT
1.12V
V
g
V6
D7
1.12V
G8
R
16
V-
90
-
+
+
-
+
-
-
+
D10
DY
D11
DY
-
E3
V-
+
V--
G9
G10
Supply Isolation Stage
Output Stage
FIGURE 56. SPICE SCHEMATIC
FN6632 Rev 12.00
March 30, 2016
Page 25 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
*ISL28117 Macromodel - covers
following
*Loading effects on closed loop
frequency
R_R17
D_D12
V_V7
*
25 0 290
24 25 DN
24 0 0.1
*products
*response
*Input Stage
*ISL28117
*Input noise terms including 1/f effects
*Slew rate
I_IOS
C_C6
R_R1
R_R2
Q_Q1
Q_Q2
Q_Q3
Q_Q4
Q_Q5
R_R3
R_R4
IN+ VIN- DC 0.08E-9
*ISL28217
IN+ VIN- 1.2E-12
VCM VIN- 5e11
IN+ VCM 5e11
2 VIN- 1 SuperB
3 8 1 SuperB
*ISL28417 and ISL28417SEH
**Revision History:
*Input and Output Headroom limits to
I/O
*voltage swing
*Revision C, LaFontaine January 31,
2012
V-- 1 7 Mirror
*Supply current at nominal specified
supply
4 6 2 Cascode
5 6 3 Cascode
4 V++ 4.45e3
5 V++ 4.45e3
*Model for Noise, quiescent supply
currents,
*voltages
*CMRR 210dB, fcm=10Hz, AVOL 155dB
**
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
*f=0.02Hz, SR = 0.5V/us, output voltage
*clamp and short ckt current limit.
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Post Radiation effects
*Disable operation (if any)
D_D1
I_IEE
I_IEE1
V_VOS
E_EOS
*
6 7 DX
1 V-- DC 200e-6
V++ 6 DC 96e-6
9 IN+ 8e-6
*
*Copyright 2012 by Intersil Corporation
Refer *to data sheet "LICENSE
STATEMENT", Use *of this model
indicates your acceptance with *the
terms and provisions in the License
*Statement.
8 9 VC VMID 1
*1st Gain Stage
G_G1
G_G2
R_R5
R_R6
D_D2
D_D3
V_V1
V_V2
*
V++ 11 4 5 8.129384e-2
*Thermal effects and/or over
temperature
V-- 11 4 5 8.129384e-2
11 V++ 1
*parameter variation
V-- 11 1
*Intended use:
10 V++ DX
V-- 12 DX
*Limited performance variation vs.
supply
*This Pspice Macromodel is intended to
give
10 11 1.86
11 12 1.86
*voltage is modeled
*typical DC and AC performance
*Part to part performance variation due
to
*2nd Gain Stage
*characteristics under a wide range of
*external circuit configurations using
G_G3
G_G4
R_R7
R_R8
C_C2
C_C3
D_D4
D_D5
V_V3
V_V4
*
V++ VG 11 VMID 2.83e-3
V-- VG 11 VMID 2.83e-3
VG V++ 1.99e10
V-- VG 1.99e10
VG V++ 4e-10
V-- VG 4e-10
13 V++ DX
*normal process parameter spread
*compatible simulation platforms - such
as
*Any performance difference arising
from
*iSim PE.
**
*different packaging
* source
V-- 14 DX
13 VG 1.86
*Device performance features
supported by
:
VG 14 1.86
*+input
*this model
*Mid supply Ref
R_R9
VMID V++ 2.1E3
V-- VMID 2.1E3
*|-input
*Typical, room temp., nominal power
supply
R_R10
* | | +Vsupply
* | | |-Vsupply
* | | | |output
* | | | | |
I_ISY V+ V- DC 0.44E-3
E_E2
E_E3
*
V++ 0 V+ 0 1
V-- 0 V- 0 1
*voltages used to produce the following
*characteristics:
*Common Mode Gain Stage with Zero
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
G_G5
G_G6
R_R11
R_R12
L_L1
V++ VC VCM VMID 3.162277
V-- VC VCM VMID 3.162277
VC 17 1
.subckt ISL28117 Vin+ Vin- V+ V- VOUT
* source ISL28107subckt
18 VC 1
*
17 V++ 15.9159E-3
18 V-- 15.9159E-3
*Voltage Noise
L_L2
E_En
IN+ VIN+ 25 0 1
FIGURE 57. SPICE NET LIST
FN6632 Rev 12.00
March 30, 2016
Page 26 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Characterization vs Simulation Results
100
100
10
1
V
= ±18.2V
= 1
S
A
V
10
1.0
1.0
10
100
1.0k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 58. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 59. SIMULATED INPUT NOISE VOLTAGE
70
60
70
R
= 100, R = 100k
f
R
= 100, R = 100k
f
A
= 1000
= 100
= 10
g
g
V
A
= 1000
V
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
R
= 1k, R = 100k
f
g
V
C
R
V
= ±20V
= 4pF
= 10k
V
= ±15V
S
S
L
A
V
A
= 100
= 10
V
40
20
C
= 4pF
L
R
V
= 10k
L
L
= 50mV
= 50mV
OUT
P-P
OUT
P-P
A
V
A
V
R
= 10k, R = 100k
f
R
= 10k, R = 100k
f
g
g
A
= 1
A
= 1
V
V
0
R
= OPEN, R = 0
f
g
R
= OPEN, R = 0
f
g
-10
10
-10
10k
10
100
1k
100k
1M
10M
100
1.0k
10k
100k
1.0M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 60. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 61. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
2
1
R
= 10k
R = 10k
L
L
1
0
0
-2
-4
-6
-8
R
= 4.99k
L
-1
-2
-3
-4
-5
-6
-7
-8
R
= 1k
R
= 4.99k
L
L
R
= 1k
L
V
= ±15V
= 4pF
= +1
V
= ±20V
= 4pF
= +1
S
R
= 499
S
L
R
= 499
L
C
A
C
A
L
L
V
V
R
=100
100k
L
R
= 100
V
= 50mV
L
V
= 50mV
OUT
P-P
OUT
P-P
10
100
1k
10k
100k
1M
10M
10
100
1.0k
10k
1.0M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 62. CHARACTERIZED CLOSED LOOP GAIN vs R
FIGURE 63. SIMULATED CLOSED LOOP GAIN vs R
L
L
FN6632 Rev 12.00
March 30, 2016
Page 27 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Characterization vs Simulation Results(Continued)
3
2.4
2.0
1.6
1.2
0.8
0.4
0
2
INPUT
V
= ±15V, RL =10k
S
OUTPUT
1
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-1
-2
-3
CL = 4pF
= +1
C
A
= 4pF
= +1
= 4V
L
A
V
V
V
= 4V
OUT
P-P
V
OUT
P-P
0
20
40
60
80
100
0
10
20
30
40
50
TIME (µs)
60
70
80
90 100
TIME (µs)
FIGURE 65. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
FIGURE 64. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs R
V
= ±15V
L
S
200
160
200
180
160
140
120
100
80
PHASE
PHASE
120
60
80
40
20
0
GAIN
40
GAIN
-20
-40
-60
-80
-100
R
C
= 10k
L
0
= 10pF
L
SIMULATION
-40
1.0m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 66. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 67. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
250
200
150
100
50
1m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 68. SIMULATED CMRR vs FREQUENCY
FN6632 Rev 12.00
March 30, 2016
Page 28 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Metallization Mask Layout
-IN_A
-IN_D
V
_A
OUT
V
_D
OUT
+IN_A
+IN_D
V+
V-
+IN_B
+IN_C
-IN_B
-IN_C
V
_C
OUT
V
_B
OUT
TABLE 2. DIE LAYOUT X-Y COORDINATES
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
PAD NAME
_A
PAD NUMBER
V
3
4
-256
-661
1152
1152
948.5
0
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUT
-IN_A
+IN_A
V+
5
-867.5
-880.5
-867.5
-661
9
+IN_B
-IN_B
13
14
15
16
17
18
22
26
1
-948.5
-1152
-1152
-1152
-1152
-948.5
0
V
_B
-256
OUT
V
_C
256
OUT
-IN_C
+IN_C
V-
661
867.5
880.5
867.5
661
+IN_D
-IN_D
948.5
1152
1152
V
_D
2
256
OUT
NOTE: Origin of coordinates is the center of die.
FN6632 Rev 12.00
March 30, 2016
Page 29 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
March 30, 2016
FN6632.12
Removed Note that references SMD for the ISL28417SEH from ordering information table on page 3 and
removed ISL28417SEH from MSL note due to not applicable.
March 16, 2016
FN6632.11
-Added the ISL28417SEH throughout the datasheet.
-Updated POD L8.3x3k to most recent revision with change as follows:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
-Added about Intersil verbiage
-Electrical Specifications Table Title on page 7: Added ISL28117, ISL28217, ISL28417 (VS ± 15V).
-Electrical Specifications Table Title on page 9: Added ISL28117, ISL28217, ISL28417 (VS ± 5V).
September 11, 2012
February 23, 2012
FN6632.10
FN6632.9
Feature on page 1: Added No phase reversal.
Removed from ordering information QFN parts ISL28417FRZ (not release part) on Page 3.
Removed all instances of QFN through document (front page, table of contents, thermal information, pin
description and POD.
Added to the typical performance curves table figure 53 on page 22: Common-mode input impedance.
“Ordering Information” on page 2:
Removed “Coming soon” from ISL28417FVZ and changed Part Marking column from "28417 FVZ" to
28417 FVZ-C". Changed "-40 to +125" to "200 C-grade”
Added new Part Number ISL28417 FVBZ
Electrical Spec changes:
VOS Description Section: page 7 & page 9: Changed “Input Offset Voltage; SOIC Package” to Input Offset
Voltage; SOIC, TSSOP Package”
TCVOS Description section: page 7 & page 9: Changed;Input Offset Voltage Temperature Coefficient; SOIC
Package to Input Offset Voltage Temperature Coefficient; SOIC, TSSOP Package
TCIOS Conditions section: page 7 & page 9: Changed "ISL28417 SOIC B and C Grade” to "ISL28417 SOIC, TSSOP
B and C Grade”.
“Ordering Information” on page 3:
Updated Pkg. Dwg. # for ISL28117FUBZ, ISL28117FUZ, ISL28217FUBZ & ISL28217FUZ from M8.118 to
M8.118B
Updated Pkg. Dwg. # for ISL28117FRTBZ, ISL28117FRTZ, ISL28217FRTBZ & ISL28217FRTZ from L8.3x3A to
L8.3x3K
Updated Pkg. Dwg. # for ISL28417FRZ from L16.4x4 to L16.4x4E
“Thermal Information” on page 6:
Added and for 16 Ld QFN and 14 Ld TSSOP
JA JC
Figure 52, “% OVERSHOOT vs LOAD CAPACITANCE, V = ±15V” on page 22:
S
X-Axis (Capacitance pF) values 1k and 10k were shifted 1 decade to the right. Shifted 1 decade to the left and
added new label "100k" at the extreme right (where the "10k" value was located).
Added dual and quad to the “SPICE NET LIST” on page 26.
“Package Outline Drawing” on page 35:
Changed from M8.118 to M8.118B
Top View:
Package width & height changed from 3.0±0.05 to 3.0±0.1
Package height from lead to lead changed from 4.9±0.15 to 4.9±0.2
Side View 2:
Lead thickness changed from 0.09-0.20 to 0.15±0.05mm
Side View 1:
Package height changed from 0.85±0.10 to 0.86±0.05
Changed lead width from 0.25-0.036 to 0.23-0.36
Detail X:
Foot of lead length changed from 0.55±0.15 to 0.53±0.10
“Package Outline Drawing” on page 36:
Changed from L8.3x3A to L8.3x3K
Bottom View:
Changed lead height from 0.3±0.1 to 0.4±0.05
Changed lead width from 0.30±0.05 to 0.25±0.05
Land Pattern:
Changed lead width from 0.30 to 0.25
FN6632 Rev 12.00
March 30, 2016
Page 30 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev. (Continued)
DATE
REVISION
FN6632.8
CHANGE
Figure 27 added “Positive” to Short-Circuit Current title
October 11, 2011
Figure 28 added “Negative” to Short-Circuit Current title
Figure 36 y axis label units changed from (nV/√Hz) to (nV/√Hz)
Figure 37 y axis label units changed from pA/√hz to pA/√Hz
Figure 31, 33 changed from VOUT vs Temperature to VOH vs Temperature
Figure 32, 34 changed from VOUT vs Temperature to VOL vs Temperature
Table of Contents on page 5 updated to list all package outline drawings
Changed POD M14.15 to MDP0027
Changed TCIos for ISL28417 SOIC grade B and C on pages 7 and 9 from ±3.5pA/C to ±4.0pA/C
1. Pg 2 Ordering Information:
a.Added ordering information rows for ISL28417FBBZ (B grade) and ISL28417FBZ (C grade).
b. Add Table of Contents
2. Pg 5 Abs Max and Thermal Information Tables:
a. Added HBM, MM and CDM ESD levels for the ‘417
b. Added and values for the 14 Ld SOIC
JA JC
3. Pg 6 ±15V electrical Specs
a. Added ISL28417 B & C grade VOS and limits
b. Added ISL28417 B & C grade TCVOS and limits
c. Added ISL28417 B & C grade TCIOS and limits
4. Pg 7
a. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV typ to 130dB and 143dB respectively
5. Pg 8 ±5V electrical Specs
a. Added ISL28417 B & C grade VOS and limits
6. Pg 9
a. Added ISL28417 B & C grade TCVOS and limits
b. Added ISL28417 B & C grade TCIOS and limits
c. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV Typ to 130dB and 143dB respectively
7. Pg 17 Applications Information
a. Added Unused Channels paragraph and Figure 54.
July 12, 2011
FN6632.7
1. Releasing ISL28217FUZ MSOP Grade C package. Remove 'Coming Soon' from Order Information Table
2. Page 5, added: Machine Model (ISL28217 MSOP only). . . . . 300V
3. Under Electrical Spec ±15V and ±5V tables, changed Typical Rise Time and Fall Time from: Rise Time 100ns,
Fall Time 120ns, to: Rise Time 130ns, Fall Time 130ns.
4. Under Electrical Spec ±15V and ±5V table for Vos and TCVos, added in row for ISL28217 MSOP Grade C
package. Added Vos and TCVos limits for 25C and Full Temp.
5. For Typical performance curves for Vos Histograms, added note that histogram is based on ISL28217FBBZ for
Grade B figures and ISL28217FBZ for Grade C figures. (Figures 3-6, added part number label to graph below Vs)
6. Under Electrical Spec ±15V and ±5V tables, changed TYP for Open Loop Gain from 18,000V/mV to
14,000V/mV
December 2, 2010
FN6632.6
1. Updated “Ordering Information” table on page 3. Removed Coming Soon for ISL28117FRTBZ and
ISL28117FUBZ parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively).
2. Corrected part marking in “Ordering Information” table on page 3 for ISL28117FRTZ from 8117 -C to -C 8117
3. Corrected part marking in “Ordering Information” table on page 3 for ISL28217FRTZ from 8217 -C to -C 8217
4. Updated Tape & Reel note in “Ordering Information” table on page 3 from “Add "-T7", "-T7A" or "-T13" suffix
for tape and reel." to new standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel
options
5. Updated “Electrical Specifications” Table for “V ” on page 7 and “TCV ” on page 7
OS
OS
a. Added data row for Offset Voltage; MSOP Grade B Package; ISL28117
b. Added data row for Offset Voltage; TDFN Grade B Package; ISL28117
c. Added data row for Input Offset Voltage Temperature Coefficient; MSOP Grade B Package; ISL28117
d. Added data row for Input Offset Voltage Temperature Coefficient; TDFN Grade B Package; ISL28117
6. Removed "Temperature data established by characterization" from common conditions of spec table.
Removed note "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested." from Min Max columns of
spec table. Replaced with new standard note in Min Max columns, “Compliance to datasheet limits is assured
by one or more methods: production test, characterization and/or design.”
FN6632 Rev 12.00
March 30, 2016
Page 31 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev. (Continued)
DATE
REVISION
FN6632.5
CHANGE
August 31, 2010
1. General changes:
a. Added in Quad devices to the datasheet for SOIC, TSSOP and QFN packages.
b. Added in TDFN packages for single and dual devices.
c. Added in new VOS and TCVOS limits for TDFN packages
d. Added Tja and Tjc Notes for TDFN Package which are “direct attach (Tja) ” and “bottom (Tjc)”
2. Specific changes:
a. Added in ISL28417 to title and front page info on page 1
b. Added in ISL28117FRTZ, ISL28117FRTBZ, ISL28217FRTZ, ISL28217FRTBZ, ISL28417FBZ, ISL28417FVZ
and ISL28417FRZ packages to Ordering information on page 3 and page 3. Added in -T7 and -T7A tape and reel
extensions where applicable.
c. Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations on page 4 and page 3.
d. Updated Pin Descriptions tables with new added in packages on page 5.
e. Abs Max Table added in thermal packaging info for TDFN packages on page 6.
f. Electrical Specifications Table - Added two new line items for VOS spec. TDFN package ISL28217 Grade B
limits ±70uV 25C and ±140uV full temp. TDFN package ISL28x17 Grade C limits ±150uV 25C and ±250uV full
temp on page 7 and page 9.
g. Electrical Specifications Table - Added two new line items for TCVOS spec. TDFN package ISL28217 Grade B
limits ±0.7uV/C full temp. TDFN package ISL28x17 Grade C limits ±1uV/C on page 7 and page 9.
h. Added in PODs for L8.3x3A, M14.15, M14.173 and L16.4x4
March 18, 2010
FN6632.4
1. Updated “Ordering Information” on page 3 by adding two rows for MSOP packages ISL28117FUBZ and
ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout accordingly.
2. Added POD for MSOP M8.118 to the end of datasheet
3. In “Ordering Information” on page 3, Separated each part number with it's own specific -T7 and -T13 suffix
and removed “Add “-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs for MSOP Grade C
package.
B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS specs for MSOP Grade C
package.
5. Added “Thermal Information” on page 6 for ISL28117 MSOP package.
Added page1.
Added Evaluation Boards to “Ordering Information” on page 3.
Added Theta JC values to “Thermal Information” on page 6. Added applicable Theta JC Note 7.
Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W.
Part marking in “Ordering Information” on page 3 changed as follows:
ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ"
ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C"
ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ"
ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C"
On page 14: Changed label in Figure 3 from “V = +5V” to “V = ±5V”
S
S
On page 14: Changed label in Figure 4 from “V = +15V” to “V = ±15V”
S
S
Changed Typical VOS spec from “13” to “8” (B Grade), “19” to “4” (C Grade), IB from “0.18” to “0.08, IOS from
“0.3” to “0.08”. Edited Spice Schematic - L1 from “95.4957” to “15.9159E”, R1 from “6k” to 1, R9 from “1” to
“2.1E3”, R10 from “1” to “2.1E3, R12 from “6k” to “1”, L2 from “95.4957” to “15.9159E”. Edited Spice Net List
- Changed Revision from “A” to “B”, Date change from “October 29th 2009” to “November 20th 2009”, added
after AOL “SR = 0.5V/µsec, Input Stage changed in I_IOS from “0.3E-9” to 0.08E-9”, V_VOS “13e-6” to
“8e-6”, Mid supply Ref R_R9 and R_R10 changed “1” to “2.1E3”, Common-Mode Gain Stage with Zero change
in G_G5 and G_G6 “5.27046e-15” to “3.162277”, R_R11 and R_R12 “6.3” to “1”, L_L1 and L_L2 “95.4957” to
“15.9159E-3”
November 12, 2009
FN6632.3
Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model and license
statement. Replaced typical application schematic.
FN6632 Rev 12.00
March 30, 2016
Page 32 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev. (Continued)
DATE
REVISION
FN6632.2
CHANGE
October 16, 2009
On page 3 “Ordering Information”, changed the following:
a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B". Corrected part marking
for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B"
B) Updated package outline drawing to most recent revision (no changes were made to package dimensions;
land pattern was added and dimensions were moved from table onto drawing)
c) Added "Add “-T7” or “-T13” suffix for tape and reel." to the tape and reel Note 1.
d) added Note 3 callout to all parts (Note 3 reads: “For Moisture Sensitivity Level (MSL), please see device
information page for ISL28117, ISL28217. For more information on MSL please see techbrief TB363.")
e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices
October 8, 2009
FN6632.1
1. Removed “very” from “...low noise..” 1st sentence, page 1.
2. Removed “Low” from 6th bullet under features, page 1.
3. Modified typical characteristics curves to show conservative performance. Specific channel designations
removed. On temperature curves, changed formatting to indicate range from typical value. Changes include:
a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34, 37 & 38 (all
Channel A curves)
b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures 9 thru 20 (all
“conservative channels”)
c. Added Figures 30, 31, 32
4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same graphic)
5. Added temp labels to Figures 28 & 29
September 3, 2009
FN6632.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2009-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6632 Rev 12.00
March 30, 2016
Page 33 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6632 Rev 12.00
March 30, 2016
Page 34 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
M8.118B
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 3/12
5
3.0±0.10mm
A
D
8
4.9±0.20mm
DETAIL "X"
3.0±0.10mm
5
1.10 MAX
0.15±0.05mm
PIN# 1 ID
SIDE VIEW 2
1
2
B
0.65mm BSC
TOP VIEW
0.95 REF
0.86±0.05mm
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.10 ± 0.05mm
0.23 - 0.36mm
3°±3°
0.10 C
0.08
C A-B D
M
0.53 ± 0.10mm
DETAIL "X"
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN6632 Rev 12.00
March 30, 2016
Page 35 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
L8.3x3K
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 5/15
2X 1.95
3.00
A
6X 0.65
B
1
PIN #1
INDEX AREA
6
6
1.50 ±0.10
PIN 1
INDEX AREA
(4X)
0.15
8
4
TOP VIEW
8X 0.25 ±0.05
0.10 M C A
0.40 ± 0.05
B
2.30 ±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
5
C
0 . 203 REF
C
0.75 ±0.05
0 . 02 NOM.
0 . 05 MAX.
0.08 C
SIDE VIEW
DETAIL "X"
( 2.30)
( 1.95)
NOTES:
( 8X 0.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
(1.50)
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
( 2.90 )
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
PIN 1
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5.
6.
(6x 0.65)
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
( 8 X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN6632 Rev 12.00
March 30, 2016
Page 36 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16 (0.300”) SO20 (SOL- SO24 (SOL- SO28 (SOL-
SO16
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(0.150”)
(SOL-16)
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
20)
24)
28)
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
-
-
-
-
L
0.009
Basic
L1
h
Reference
Reference
N
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6632 Rev 12.00
March 30, 2016
Page 37 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN6632 Rev 12.00
March 30, 2016
Page 38 of 39
ISL28117, ISL28217, ISL28417, ISL28417SEH
Package Outline Drawing
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
INCHES
MIN
MILLIMETERS
A
e
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
NOTES
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
D
-A-
-B-
S1
b1
c
-
-
c1
D
-
b
3
-
E1
E
0.235
-
5.97
-
0.004
Q
H
A - B
D
S
0.036
M
H
A - B
S
C
D
S
M
S
E1
E2
E3
e
3
-
E
0.125
0.030
3.18
0.76
-D-
A
-
-
7
-
-H-
-C-
0.050 BSC
1.27 BSC
L
E2
L
E3
E3
k
0.008
0.270
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.86
0.66
0.13
-
0.38
9.40
1.14
-
2
-
SEATING AND
BASE PLANE
c1
LEAD FINISH
L
Q
S1
M
N
8
6
-
BASE
METAL
(c)
0.0015
0.04
b1
14
14
-
M
M
(b)
Rev. 0 5/18/94
SECTION A-A
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN6632 Rev 12.00
March 30, 2016
Page 39 of 39
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