ISL55291IUZ-T13 [RENESAS]
DUAL OP-AMP, 800uV OFFSET-MAX, 800MHz BAND WIDTH, PDSO10, ROHS COMPLIANT, MSOP-10;
| 型号： | ISL55291IUZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL OP-AMP, 800uV OFFSET-MAX, 800MHz BAND WIDTH, PDSO10, ROHS COMPLIANT, MSOP-10 放大器 信息通信管理 光电二极管 |
| 文件： | 总18页 (文件大小：1162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL55191, ISL55291
Single and Dual Ultra-Low Noise, Ultra-Low Distortion, Rail-to-Rail, Low Power Op
Amp
FN6263
Rev 1.00
March 30, 2007
The ISL55191 and ISL55291 are single and dual high speed
operational amplifiers featuring low noise, low distortion, and
rail-to-rail output drive capability. They are designed to
Features
• 1.3nV/Hz input voltage noise, f = 1kHz
O
operate with single and dual supplies from +5VDC
(±2.5VDC) down to +3VDC (±1.5VDC). These amplifiers
draw 6.1mA of quiescent supply current per amplifier. For
power conservation, this family offers a low-power shutdown
mode that reduces supply current to 21µA and places the
amplifiers' output into a high impedance state. The ISL55191
ENABLE logic places the device in the shutdown mode with
EN = 0 and the ISL55291 is placed in the shutdown mode
with EN = 1.
• Harmonic Distortion -94dBc, -104dBc, f = 1MHz
O
• Stable at gains as low as 10
• 800MHz gain bandwidth product (A = 10)
V
• 260V/µs slew rate
• 6.1mA supply current (21µA in disable mode)
• 800µV maximum offset voltage
• 12µA input bias current
These amplifiers have excellent input and output overload
recovery times and outputs that swing rail-to-rail. Their input
common mode voltage range includes ground. The
ISL55191 and ISL55291 are stable at gains as low as 10
with an input referred noise voltage of 1.3nV/Hz and
harmonic distortion products -94dBc (2nd) and -104dBc
• 3V to 5.5V single supply voltage range
• Rail-to-rail output
• Pb-free plus anneal available (RoHS compliant)
Applications
(3rd) below a 1MHz 2V
P-P
signal.
• High speed pulse applications
• Low noise signal processing
• ADC buffers
The ISL55191 is available in space-saving 8 Ld DFN and 8 Ld
SOIC packages. The ISL55291 is available in a 10 Ld MSOP
package.
• DAC output amplifiers
• Radio systems
Ordering Information
PART
NUMBER
(Note)
TAPE
AND
REEL
PKG.
DWG.
#
PART
MARKING
PACKAGE
(Pb-Free)
• Portable equipment
TABLE 1. ENABLE LOGIC
ISL55191IBZ
55191 IBZ
-
8 Ld SOIC
MDP0027
MDP0027
ENABLE
EN = 1
EN = 0
DISABLE
ISL55191IBZ-T13 55191 IBZ
13”
8 Ld SOIC
ISL55191
ISL55291
EN = 0
EN = 1
(2,500 pcs) Tape and Reel
ISL55191IRZ
191Z
-
8 Ld DFN
L8.3x3D
L8.3x3D
ISL55191IRZ-T13 191Z
13”
8 Ld DFN
(2,500 pcs) Tape and Reel
ISL55291IUZ
5291Z
-
10 Ld MSOP MDP0043
10 Ld MSOP MDP0043
ISL55291IUZ-T13 5291Z
13”
(2,500 pcs) Tape and Reel
Coming Soon
ISL55191EVAL1Z
Evaluation Board
Coming Soon
ISL55291EVAL1Z
Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6263 Rev 1.00
March 30, 2007
Page 1 of 18
ISL55191, ISL55291
Pinouts
ISL55191
(8 LD SOIC)
TOP VIEW
ISL55191
(8 LD DFN)
TOP VIEW
FEEDBACK
1
2
3
4
8
7
6
5
EN
EN
V +
1
2
3
4
8
7
6
5
IN-
IN+
V-
V+
FEEDBACK
OUT
NC
V-
-
+
-
+
IN-
OUT
NC
IN+
ISL55291
(10 LD MSOP)
TOP VIEW
OUT_A
IN-_A
IN+_A
V-
1
2
3
4
5
10 V+
9
8
7
6
OUT_B
IN-_B
-
+
-
+
IN+_B
EN_B
EN_A
FN6263 Rev 1.00
March 30, 2007
Page 2 of 18
ISL55191, ISL55291
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV
ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V
ESD Rating
Thermal Resistance
(°C/W)
JA
8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
TBD
110
115
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .300V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V = 5V, V- = GND, R = 1k R = 30R = 270unless otherwise specified. Parameters are per amplifier.
+
L
G
F
All values are at V+ = 5V, T = +25°C.
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
V
Input Offset Voltage
170
2.2
800
µV
OS
V
Input Offset Drift vs Temperature
-40°C to +85°C
µV/°C
OS
T
---------------
I
I
Input Offset Current
0.3
-12
0.7
-19
3.8
µA
µA
V
OS
B
Input Bias Current
V
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Maximum Output Voltage Swing
0
CM
CMRR
PSRR
V
= 0V to 3.8V
85
70
85
100
77
dB
dB
dB
mV
V
CM
V+ = 3V to 5V
= 0.5V to 4V, R = 1k
A
V
97
VOL
O
L
V
Output low, R = 1kconnected to V+/2
23
40
OUT
S,ON
S,OFF
L
Output high, R = 1kconnected to V+/2
4.96
4.98
6.1
12
L
I
I
Supply Current, Enabled
ISL55191
ISL55291
9
mA
mA
µA
mA
mA
V
18
40
Supply Current, Disabled
Short-Circuit Output Current
Short-Circuit Output Current
Supply Operating Range
ENABLE High Level
21
I +
R
R
= 10connected to V+/2
= 10connected to V+/2
110
110
3
132
132
O
L
L
I -
O
V
V
V
V+ to V-
5
SUPPLY
INH
2
V
ENABLE Low Level
0.8
80
V
INL
I
ENABLE Input High Current
ISL55191 (EN)
ISL55291 (EN)
ISL55191 (EN)
ISL55291 (EN)
20
0.8
5
nA
µA
µA
nA
ENH
V
= V+
EN
1.5
6.2
80
I
ENABLE Input Low Current
= V-
ENL
V
EN
20
FN6263 Rev 1.00
March 30, 2007
Page 3 of 18
ISL55191, ISL55291
Electrical Specifications V = 5V, V- = GND, R = 1k R = 30R = 270unless otherwise specified. Parameters are per amplifier.
+
L
G
F
All values are at V+ = 5V, T = +25°C.
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
2nd Harmonic Distortion
3rd Harmonic Distortion
A
= +10; V
= +10; V
= 100mVP-P; R /R = 909100
800
-94
MHz
dBc
dBc
dB
V
OUT
OUT
f
g
HD
(4MHz)
A
= 2VP-P; R /R = 909100
f g
V
-104
-65
ISO
Off-state Isolation; EN = 1 ISL55291;
EN = 0 ISL55191
f
= 10MHz; A = +10; V = 640mVP-P
;
O
V
IN
R /R = 909100C = 1.2pF
f
g
L
X-TALK
Channel to Channel Crosstalk
f
= 10MHz; A = +10; V (Driven Channel) =
OUT
-75
dB
O
V
ISL55291
640mVP-P; R /R = 909100C = 1.2pF
f
g
L
V
Input Referred Voltage Noise
Input Referred Current Noise
f
f
= 1kHz
1.2
3.8
nV/Hz
pA/Hz
N
O
O
IN
= 10kHz
TRANSIENT RESPONSE
SR Slew Rate
t , t Large Rise Time, t 10% to 90%
150
260
6.6
5.7
5
V/uS
ns
A
= +10; V
= 3.5VP-P; R /R = 909/100
f g
r
f
r
V
OUT
OUT
OUT
OUT
Signal
C = 1.2pF
L
Fall Time, t 10% to 90%
ns
f
Rise Time, t 10% to 90%
A
= +10; V
= 1VP-P; R /R = 909100
ns
r
V
f
g
C = 1.2pF
L
Fall Time, t 10% to 90%
4
ns
f
t , t , Small
Rise Time, t 10% to 90%
A
= +10; V
= 100mVP-P; R /R = 909100
3
ns
r
f
r
V
f
g
Signal
C = 1.2pF
L
Fall Time, t 10% to 90%
f
3
ns
t
t
Propagation Delay
A
= +10; V
= 100mVP-P; R /R = 909100
1.6
ns
pd
V
f
g
10% V to 10% V
C = 1.2pF
IN
OUT
L
Positive Input Overload Recovery
Time, t ; 10% V to 10% V
V
= ±2.5V; A = +10; V = +V +0.5V;
IN CM
50
30
ns
ns
ns
ns
ns
ns
ns
ns
IOL
S
V
R /R = 909100C = 1.2pF
IOL+ IN
OUT
f
g
L
Negative Input Overload Recovery
Time, t ; 10% V to 10% V
V
= ±2.5V; A = +10; V = -V -0.5V;
IN
S
V
R /R = 909100C = 1.2pF
IOL-
IN
Positive Output Overload Recovery
Time, t ; 10% V to 10% V
OUT
f
g
L
t
t
V
= ±2.5V; A = +10; V = 2.3VP-P
;
;
40
OOL
EN
S
V
IN
R /R = 909100C = 1.2pF
OOL+ IN OUT
f
g
L
Negative Output Overload Recovery
Time, t ; 10% V to 10% V
V
= ±2.5V; A = +10; V = 2.3VP-P
IN
30
S
V
R /R = 909100C = 1.2pF
OOL-
IN
ENABLE to Output Turn-on Delay
Time; 10% EN to 10% V
OUT
f
g
L
A
= +10; V = 500mVP-P; R /R = 909100
IN
540
390
330
50
V
f
g
ISL55191
C = 1.2pF
OUT
ENABLE to Output Turn-off Delay
Time; 10% EN to 10% V
L
A
= +10; V = 500mVP-P; R /R = 909100
IN
V
f
g
C = 1.2pF
OUT
ENABLE to Output Turn-on Delay
Time; 10% EN to 10% V
L
t
A
= +10; V = 500mVP-P; R /R = 909100
IN
EN
ISL55291
V
f
g
C = 1.2pF
OUT
ENABLE to Output Turn-off Delay
Time;10% EN to 10% V
L
A
= +10; V = 500mVP-P; R /R = 909100
IN
V
f
g
C = 1.2pF
OUT
L
FN6263 Rev 1.00
March 30, 2007
Page 4 of 18
ISL55191, ISL55291
Typical Performance Curves
1
0
1
0
V
= 100mV
OUT
R = 133, R = 14.7
f
g
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
R = 249, R = 27.4
f
g
R = 274, R = 30.1
f
g
V
= 200mV
R = 316, R = 34.8
OUT
f
g
A
R
C
= 10
= 1k
= 1.3pF
V
L
L
f
g
R = 365, R = 40.2
f
g
V
= 1V
OUT
A
= 10
= 1k
= 100mV
V
R = 2.74k, R = 301
R = 909
R
f
g
R
V
L
= 100
R = 909, R = 100
f
g
OUT
P-P
0.1
1.0
10
FREQUENCY (MHz)
100
1k
.01
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS R vs R
f
FIGURE 2. GAIN vs FREQUENCY vs V
OUT
g
1
0
65
60
55
50
45
40
35
30
25
20
15
10
5
A
= 1000 R /R = 100k/100
V
f
i
-1
-2
-3
A
= 10 R /R = 909/100
f i
V
R
= 1k
L
-4
-5
-6
-7
-8
-9
A
= 100 R /R = 10k/100
f i
V
R
= 500
= 250
= 100
L
R
L
A
C
= 10
= 1.3pF
V
L
R
R
C
V
= 1k
= 2.2pF
L
L
L
OUT
V
= 100mV
= 100mV
OUT
P-P
P-P
0
0.1
.01
0.1
1.0
10
100
1k
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS R
FIGURE 4. CLOSED LOOP GAIN vs FREQUENCY
LOAD
2
4
C
= 23.2pF
= 13.2pF
L
V
= 1.2V
S
1
0
3
2
C
L
L
C
= 8.0pF
-1
-2
-3
-4
-5
-6
-7
-8
1
0
C
= 1.2pF
L
-1
-2
-3
-4
-5
-6
C = 2.2pF
L
V
S
= 2.5V
C
= 0.5pF
g
f
g
L
C = 4.5pF
L
A
= 10
= 5V
= 1k
V
R = 909
R
R
V
R
+
= 100
= 1k
= 100mV
L
V
= 100mV
OUT
P-P
V
OUT
P-P
.01
0.1
1.0
10
100
1k
0.1
10
FREQUENCY (MHz)
100
1k
0.1
FREQUENCY (MHz)
FIGURE 5. GAIN vs FREQUENCY vs V
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS C
LOAD
S
FN6263 Rev 1.00
March 30, 2007
Page 5 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
5
5
4
C
C
= 8.7pF
= 7.3pF
= 5.2pF
C
= 12.8pF
= 10.8pF
= 9.0pF
g
g
4
3
C
g
g
g
3
C
C
g
2
2
C
= 3.8pF
g
C
= 7.6pF
g
1
1
C
= 2.7pF
g
C
= 5.5pF
g
0
0
C
= 1.6pF
C
C
= 3.0pF
g
g
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R = 909
R = 909
f
f
= 0.8pF
C = 0.5pF
g
g
R
A
R
= 100
= 10
= 1k
R
A
R
V
V
= 100
= 10
= 1k
g
V
L
g
V
L
V
V
= 100mV
= 5V
= 100mV
= 5V
OUT
S
P-P
OUT
S
P-P
.01
0.1
1.0
10
100
1k
.01
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 7. ISL55191 GAIN vs FREQUENCY FOR
FIGURE 8. ISL55291 GAIN vs FREQUENCY FOR
VARIOUS C
VARIOUS C
g
g
1M
100k
10k
1k
1M
100k
10k
1k
C
C
A
= 1.6pF
= 1.2pF
= 10
C
C
A
= 1.6pF
= 1.2pF
= 10
g
L
V
g
L
V
100
10
100
10
R = 909
R = 100
g
R = 909
R = 100
g
f
f
V
R
= 500mV
V
R
= 500mV
SOURCE
P-P
SOURCE
P-P
1.0
= 1k
= 1k
L
L
1
1
.01
0.1
10
100
1k
.01
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 9. DISABLED INPUT IMPEDANCE vs FREQUENCY
FIGURE 10. ENABLED INPUT IMPEDANCE vs FREQUENCY
100
10k
C
= 0.5pF
g
f
g
R = 909
R
= 100
= 10
A
V
10
1
V
= 1V
P-P
SOURCE
1k
100
C
= 0.5pF
g
f
g
0.1
R = 909
R
= 100
= 10
A
V
V
= 1V
P-P
SOURCE
0.01
.01
10
.01
0.1
1.0
10
100
1k
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 11. DISABLED OUTPUT IMPEDANCE vs
FREQUENCY
FIGURE 12. ENABLED OUTPUT IMPEDANCE vs FREQUENCY
FN6263 Rev 1.00
March 30, 2007
Page 6 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
A
= 10
= 0.8pF
= 1k
V
A
= 10
= 0.8pF
= 1k
V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
C
R
R
g
L
g
C
R
R
g
L
g
PSRR-
= 100
= 100
Rf = 909
= 1V
Rf = 909
= 1V
V
P-P
V
P-P
PSRR+
.01
0.1
1.0
10
100
1k
.01
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 13. CMRR vs FREQUENCY
FIGURE 14. PSRR vs FREQUENCY
0
-20
0
C
= 1.6pF
= 1.2pF
= 10
C
C
A
= 1.6pF
= 1.2pF
= 10
g
L
g
L
V
C
A
-20
V
R = 909
R = 909
f
f
-40
R = 100
i
R = 100
i
-40
-60
V
R
= 640mV
V
(DRIVEN CHANNEL) = 640mV
IN
= 1k
P-P
OUT
R = 1k
L
P-P
-60
L
-80
-80
-100
-120
-140
-100
-120
.01
0.1
1.0
10
100
1k
.01
0.1
1.0
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. OFF ISOLATION vs FREQUENCY
FIGURE 16. ISL55291 CHANNEL TO CHANNEL CROSSTALK
vs FREQUENCY
100
10
1
1000
100
10
A
= 100
V
f
g
i
R = 303
R
R = 1k
= 3.3
A
= 100
V
f
g
L
R = 303
R
R
= 3.3
= 1k
1
0.1
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. INPUT VOLTAGE NOISE vs FREQUENCY
FIGURE 18. INPUT CURRENT NOISE vs FREQUENCY
FN6263 Rev 1.00
March 30, 2007
Page 7 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
0.6
0.06
0.04
0.02
0
V
A
R
R
= +2.5V
= 10
= 1k
S
V
L
V
A
R
= +2.5V
= 10
= 1k
S
V
L
0.4
0.2
0
= 100
g
R
= 100
g
R = 909
f
R = 909
f
-0.02
-0.04
-0.06
-0.2
-0.4
-0.6
0
20
40
60
80
100
0
20
40
60
80
100
TIME (ns)
TIME (ns)
FIGURE 19. LARGE SIGNAL STEP RESPONSE
FIGURE 20. SMALL SIGNAL STEP RESPONSE
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
50
V
A
R
R
= +2.5V
= 10
= 1k
S
V
L
45
40
35
30
25
20
15
10
5
V
= 0.1V
OUT
= 100
g
R = 909
f
V
= 0.5V
OUT
INPUT
V
= 1V
OUT
OUTPUT
A
= 10
= 10k
V
R
L
V
= ±2.5V
= 100
S
V
= 3.5V
OUT
R
g
R = 909
f
V
= VCM +0.5V
IN
0
0
20
40
60
80 100 120 140 160 180 200
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
CL (pF)
FIGURE 21. PERCENT OVERSHOOT FOR VARIOUS C
FIGURE 22. ISL55291 POSITIVE INPUT RECOVERY TIME
LOAD
0.6
0.4
0.2
0
3
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
-2.8
-2.9
-3.0
-3.1
1.5
1.0
0.5
0
2
INPUT
1
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
INPUT
OUTPUT
0
OUTPUT
A
R
= 10
= 10k
= +2.5V
= 100
V
L
A
R
= 10
= 10k
V
L
-0.2
-0.4
-0.6
-1
-2
-3
V
S
V
R
= ±2.5V
= 100
S
R
g
g
R = 909
f
R = 909
f
V
= 0.7V
P-P
IN
V
= -V-0.5V
IN
0
20
40
60
80 100 120 140 160 180 200
TIME (ns
0
20
40
60
80 100 120 140 160 180 200
TIME (ns)
)
FIGURE 23. ISL55291 NEGATIVE INPUT RECOVERY
RECOVERY
FIGURE 24. OUTPUT OVERLOAD RECOVERY
FN6263 Rev 1.00
March 30, 2007
Page 8 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
280
270
260
250
240
230
220
3.0
6.0
5.0
4.0
3.0
2.0
1.0
0
A
= 10
V
f
L
i
R = 909
R
R = 100
2.5
OUTPUT
= 10k
2.0
A
= 10
1.5
1.0
0.5
0
V
f
g
L
R = 909
R = 100
R
= 10k
= 280mV
V
IN
ENABLE
-0.5
-1.0
3.0
3.5
4.0
4.5
5.0
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
TIME (µs)
V
(V)
S
FIGURE 25. ENABLE TO OUTPUT DELAY
FIGURE 26. ISL55291 POSITIVE SLEW RATE vs V
S
-260
-270
-280
-290
-300
-310
-320
3.0
3.5
4.0
4.5
5.0
5.5
S
V
(V)
S
FIGURE 27. ISL55291 NEGATIVE SLEW RATE vs V
19
18
17
16
15
14
13
12
11
10
9
n = 2000
n = 2000
34
MAX
MAX
30
26
22
MEDIAN
MEDIAN
18
MIN
MIN
14
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 28. SUPPLY CURRENT ENABLED vs TEMPERATURE
= ±2.5V
FIGURE 29. SUPPLY CURRENT DISABLED vs
TEMPERATURE V = ±2.5V
V
S
S
FN6263 Rev 1.00
March 30, 2007
Page 9 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
16
20
18
16
14
12
10
8
n = 2000
15
14
13
12
11
10
9
MAX
MAX
MEDIAN
MEDIAN
n = 2000
MIN
60
6
MIN
8
4
-40
-20
0
20
40
60
80
-40
-20
0
20
40
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 30. SUPPLY CURRENT ENABLED vs TEMPERATURE
= ±1.5V
FIGURE 31. SUPPLY CURRENT DISABLED vs TEMPERATURE
= ±1.5V
V
V
S
S
500
300
800
600
400
200
0
n = 2000
n = 2000
MAX
MAX
100
MEDIAN
MEDIAN
-100
-300
-500
-700
-200
MIN
-20
MIN
-20
-400
-40
0
20
40
60
80
-40
0
20
TEMPERATURE (°C)
FIGURE 33. VIO vs TEMPERATURE V = ±1.5V
40
60
80
TEMPERATURE (°C)
FIGURE 32. VIO vs TEMPERATURE V = ±2.5V
S
S
-10
-10
n = 2000
n = 2000
-10.5
-11
-10.5
-11
MAX
MEDIAN
MAX
-11.5
-12
-11.5
-12
MEDIAN
-12.5
-13
-12.5
-13
-13.5
-14
-13.5
-14
MIN
-14.5
-15
MIN
20
-14.5
-15
-40
-20
0
20
40
60
80
-40
-20
0
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 34. I
vs TEMPERATURE V = ±2.5V
FIGURE 35. I
BIAS-
vs TEMPERATURE V = ±2.5V
BIAS+
S
S
FN6263 Rev 1.00
March 30, 2007
Page 10 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
-10.0
-9
-10
-11
-12
-13
-14
-15
n = 2000
-10.5
n = 2000
MAX
-11.0
MAX
-11.5
MEDIAN
-12.0
-12.5
-13.0
-13.5
MEDIAN
MIN
-14.0
-14.5
-15.0
MIN
40
-40
-20
0
20
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 36. I
vs TEMPERATURE V = ±1.5V
FIGURE 37. I
vs TEMPERATURE V = ±1.5V
S
BIAS+
S
BIAS-
105
81
n = 2000
n = 2000
103
101
99
80
79
78
77
76
75
74
73
MAX
V+ = 5V
MEDIAN
97
95
V+ = 3V
93
MIN
91
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 38. CMRR vs TEMPERATURE V+ = ±2.5V, ±1.5V
FIGURE 39. PSRR vs TEMPERATURE ±1.5V TO ±2.5V
38
4.986
n = 2000
n = 2000
36
4.984
MAX
MAX
34
4.982
32
30
MEDIAN
4.98
28
MEDIAN
4.978
26
24
22
MIN
4.976
4.974
4.972
MIN
20
18
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 40. V
R
HIGH vs TEMPERATURE V = ±2.5V,
= 1K
FIGURE 41. V
LOW vs TEMPERATURE V = ±2.5V, R = 1k
OUT S L
OUT
S
L
FN6263 Rev 1.00
March 30, 2007
Page 11 of 18
ISL55191, ISL55291
Typical Performance Curves (Continued)
2.990
41
38
35
32
29
26
23
n = 2000
n = 2000
2.988
2.986
2.984
2.982
2.980
2.978
2.976
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
80
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 42. V
HIGH vs TEMPERATURE V = ±1.5V, R = 1k
FIGURE 43. V
LOW vs TEMPERATURE V = ±1.5V, R = 1k
OUT S L
OUT
S
L
FN6263 Rev 1.00
March 30, 2007
Page 12 of 18
ISL55191, ISL55291
Pin Descriptions
ISL55191
ISL55191
ISL55291
(8 LD SOIC) (8 LD DFN) (10 LD MSOP) PIN NAME
FUNCTION
Not connected
EQUIVALENT CIRCUIT
5
2
6
3
NC
IN-
2 (A)
8 (B)
Inverting input
V+
IN+
V-
IN-
Circuit 1
3
4
3 (A)
7 (B)
IN+
Non-inverting input
(See circuit 1)
4
6
5
7
4
V-
Negative supply
Output
1 (A)
9 (B)
OUT
V+
OUT
V-
Circuit 2
7
8
10
V+
Positive supply
5 (A)
6 (B)
EN
Enable pin with internal pull-
down referenced to the -V pin;
Logic “1” selects the disabled
state; Logic “0” selects the
enabled state.
V+
EN
V-
Circuit 3a
8
1
EN
Enable pin with internal pull-
down referenced to the -V pin;
Logic “0” (-V) selects the
disabled state; Logic “1” (+V)
selects the enabled state.
V+
EN
V-
Circuit 3b
1
2
FEEDBACK Feedback pin to reduce IN-
capacitance
V+
FEEDBACK
OUT
V-
Circuit 4
FN6263 Rev 1.00
March 30, 2007
Page 13 of 18
ISL55191, ISL55291
where:
Applications Information
• P
is the sum of the maximum power dissipation
DMAXTOTAL
of each amplifier in the package (PD
Product Description
)
MAX
The ISL55191 and ISL55291 are voltage feedback operational
amplifiers designed for communication and imaging
• PD
for each amplifier can be calculated as follows:
MAX
applications requiring very low voltage and current noise. Both
parts features low distortion while drawing moderately low
supply current. The ISL55191 and ISL55291 use a classical
voltage-feedback topology which allows them to be used in a
variety of applications where current-feedback amplifiers are
not appropriate because of restrictions placed upon the
feedback element used with the amplifier.
V
OUTMAX
R
L
----------------------------
PD
= 2*V I
+ V - V
OUTMAX
MAX
S
SMAX
S
(EQ. 2)
where:
• T
= Maximum ambient temperature
MAX
• = Thermal resistance of the package
JA
Enable/Power-Down
• PD
= Maximum power dissipation of 1 amplifier
MAX
Both devices can be operated from a single supply with a
voltage range of +3V to +5V, or from split ±1.5V to ±2.5V. The
logic level input to the ENABLE pins are TTL compatible and
are referenced to the -V terminal in both single and split supply
applications. The following discussion assumes single supply
operation.
• V = Supply voltage
S
• I
= Maximum supply current of 1 amplifier
MAX
• V
= Maximum output voltage swing of the
OUTMAX
application
• R = Load resistance
L
The ISL55191 uses a logic “0” (<0.8V) to disable the amplifier
and the ISL55291 uses a logic “1” (>2V) to disable its
amplifiers. In this condition, the output(s) will be in a high
impedance state and the amplifier(s) current will be reduced to
21µA. The ISL55191 has an internal pull-up on the EN pin and
is enabled by either floating or tying the EN pin to a voltage
>2V. The ISL55291 has internal pull-downs on the EN pins and
are enabled by either floating or tying the EN pins to a voltage
<0.8V. The enable pins should be tied directly to their
Power Supply Bypassing and Printed Circuit Board
Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Low impedance
ground plane construction is essential. Surface mount
components are recommended, but if leaded components are
used, lead lengths should be as short as possible. The power
supply pins must be well bypassed to reduce the risk of
oscillation. The combination of a 4.7µF tantalum capacitor in
parallel with a 0.01µF capacitor has been shown to work well
when placed at each supply pin.
respective supply pins when not being used (EN tied to -V for
the ISL55291 and EN tied to +V for the ISL55191).
Current Limiting
The ISL55191 and ISL55291 have no internal current-limiting
circuitry. If the output is shorted, it is possible to exceed the
Absolute Maximum Rating for output current or power
dissipation, potentially resulting in the destruction of the
device.
For good AC performance, parasitic capacitance should be
kept to a minimum, especially at the inverting input. When
ground plane construction is used, it should be removed from
the area near the inverting input to minimize any stray
capacitance at that node. Carbon or Metal-Film resistors are
acceptable with the Metal-Film resistors giving slightly less
peaking and bandwidth because of additional series
inductance. Use of sockets (particularly for the SOIC package)
should be avoided if possible. Sockets add parasitic
inductance and capacitance which will result in additional
peaking and overshoot.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply conditions.
It is therefore important to calculate the maximum junction
temperature (T
) for all applications to determine if power
JMAX
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These
parameters are related as follows:
For inverting gains, this parasitic capacitance has little effect
because the inverting input is a virtual ground, but for non-
inverting gains, this capacitance (in conjunction with the
feedback and gain resistors) creates a pole in the feedback
path of the amplifier. This pole, if low enough in frequency, has
the same destabilizing effect as a zero in the forward open-
loop response. The use of large-value feedback and gain
resistors exacerbates the problem by further lowering the pole
frequency (increasing the possibility of oscillation.).
T
= T
+ xPD
MAXTOTAL
JMAX
MAX
JA
(EQ. 1)
FN6263 Rev 1.00
March 30, 2007
Page 14 of 18
ISL55191, ISL55291
CURRENT
INPUT
+5VDC
R
F
10k
R
G-
100
ISL55191
R
T
V+
IN-
PARASITIC
L TO R
FEEDBACK
R
SENSE
0.01
VOUT
OUT
IN+
V-
R
G+
100
R
L
R
REF
10k
V
REF
+2.5V
CURRENT
INPUT
FIGURE 44. GROUND SIDE CURRENT SENSE AMPLIFIER
Current Sense Application Circuit
The schematic in Figure 44 provides an example of utilizing
the ISL55191 high speed performance with the ground
sensing input capability to implement a single-supply, G = 10
differential low side current sense amplifier. The reference
voltage applied to V
(+2.5V) defines the amplifier output
REF
0A current sense reference voltage at one half the supply
voltage level (V = +5VDC), and R sets the current
S
SENSE
sense gain and full scale values. In this example the current
gain is 10A/V over a maximum current range of slightly less
than ±25A with R
SENSE
= 0.01. The amplifier V error
IO
(800µV max) and input bias offset current I error (0.7µA)
IO
together contribute less than 10mV (100mA) at the output for
better than 0.2% full scale accuracy.
The amplifier’s high slew rate and fast pulse response make
this circuit suitable for low-side current sensing in PMWM
and motor control applications. The excellent input overload
recovery response enables the circuit to maintain
performance in the presence of parasitic inductance that
cause fast rise and falling edge spikes that can momentarily
overload the input stage of the amplifier.
FN6263 Rev 1.00
March 30, 2007
Page 15 of 18
ISL55191, ISL55291
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6263 Rev 1.00
March 30, 2007
Page 16 of 18
ISL55191, ISL55291
Package Outline Drawing
L8.3x3D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN)
Rev 0, 9/06
PIN 1 INDEX AREA
3.00
A
1.45
PIN 1 INDEX AREA
B
0.075 C
4X
6X 0.50 BSC
1.50
REF
3.00
1.75
8X 0.25
0.10 M C A B
8X 0.40
2.20
TOP VIEW
BOTTOM VIEW
SEE DETAIL X''
0.10 C
(8X 0.60)
(1.75)
(8X 0.25)
0.85
C
SEATING PLANE
0.08 C
(6X 0.50 BSC)
SIDE VIEW
(1.45)
(2.20)
5
TYPICAL RECOMMENDED LAND PATTERN
0.20 REF
c
0~0.05
DETAIL “X”
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to JEDEC STD MO220-D.
4. The configuration of the pin #1 identifier is optional, but must be located
within the zone indicated. The pin #1 identifier may be either a mold or
mark feature.
5. Tiebar shown (if present) is a non-functional feature.
FN6263 Rev 1.00
March 30, 2007
Page 17 of 18
ISL55191, ISL55291
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
© Copyright Intersil Americas LLC 2006-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6263 Rev 1.00
March 30, 2007
Page 18 of 18
相关型号：
ISL5585AIMZ
3.3 Volt Ringing SLIC Family for Voice Over Broadband (VOB); PLCC28, QFN32; Temp Range: See Datasheet
RENESAS
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