ISL6124LIB-T [RENESAS]
ISL6124LIB-T;
| 型号： | ISL6124LIB-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ISL6124LIB-T |
| 文件： | 总9页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6123, ISL6124
TM
Data Sheet
February 2001
File Number 9005
ADVANCE INFORMATION
USB Port Power Supply Controllers
Features
The ISL6123 and ISL6124 are USB port power controllers.
The ISL6123 is a triple port controller, whereas the
ISL6124 is a quad port controller. Both of these products
have fully independent channels offering overcurrent (OC)
fault protection. Operational over the +2.5V to +5V range,
these devices feature internal current monitoring, accurate
current limiting, integrated power switches and current
limited delay to latch-off for system protection.
• 80mΩ Integrated Power N-channel MOSFET Switches
• Accurate Current Sensing and 1A Current Limiting
• 12ms Fault Delay to Latch-Off, No Thermal Dependency
• Operating Range 2.5V to 5.5V
• Disabled Output Internally Pulled Low
• Undervoltage Lockout
The ISL6123/24 current sense and limiting circuitry sets
the current limit to a nominal 1A, making this device well
suited for t USB port power management. The ISL6123/24
provide OC fault notification, accurate current limiting and a
consistent timed latch-off, thus isolating and protecting the
voltage bus in the presence of an OC event or short circuit.
The 12ms time to latch-off is independent of the adjoining
switches electrical or thermal condition and the OC
• Controlled Turn-on Ramp Time
• Channel Independent Fault Output Signals
• Compatible with 3.3V and 5V Logic Families
• Channel Independent Logic Level Enable High Inputs
(ISL6123H, ISL6124H) or Enable Low Inputs (ISL6123L,
ISL6124L)
response time is inversely related to the OC magnitude.
Applications
Each ISL6123/24 incorporates in a 16 lead SOIC package
80mΩ N-channel MOSFET power switches for power
control. Each switch is driven by a constant current source
giving a controlled ramp up of the output voltage. This
provides a soft start turn-on eliminating bus voltage
drooping caused by inrush current while charging heavy
load capacitances. Independent enabling inputs and fault
reporting outputs for each channel are compatible with 3V
and 5V logic to allow external control and monitoring.
• USB Port Power Management
• Electronic Circuit Limiting and Breaker
Ordering Information
TEMP. RANGE
o
PART NUMBER
ISL6123LIB
( C)
PACKAGE
PKG. NO.
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
16 Ld SOIC
M16.15
ISL6123LIB-T
ISL6123HIB
16 Ld SOIC Tape and Reel
16 Ld SOIC M16.15
16 Ld SOIC Tape and Reel
16 Ld SOIC M16.15
16 Ld SOIC Tape and Reel
16 Ld SOIC M16.15
16 Ld SOIC Tape and Reel
The ISL6123/24 undervoltage lockout feature prevents
turn-on of the outputs unless the correct ENABLE state and
VIN > 2.5V are present. During initial turn-on the
ISL6123HIB-T
ISL6124LIB
ISL6123/24 prevents fault reporting by blanking the fault
signal. Rising and falling outputs are current limited voltage
ramps so that both the inrush current and voltage slew rate
are limited, independent of load. This reduces supply droop
due to surge and eliminates the need for external EMI
filters. During operation, once an OC condition is detected
the appropriate output is current limited for 12ms to allow
transient conditions to pass. If still in current limit after the
current limit period has elapsed, the output is then latched
off and the fault is reported by pulling the corresponding
FAULT low. The FAULT signal is latched low until reset by
the ENABLE signal being de-asserted at which time the
FAULT signal will clear.
ISL6124LIB-T
ISL6124HIB
ISL6124HIB-T
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1
ISL6123, ISL6124
Pinout
ISL6123
ISL6124
TOP VIEW
TOP VIEW
GND
VIN
1
2
3
4
5
6
7
8
16 FLT1
15 OUT1
14 OUT2
13 FLT2
12 FLT3
11 OUT3
10 NC
GND
VIN
1
2
3
4
5
6
7
8
16 FLT1
15 OUT1
14 OUT2
13 FLT2
12 FLT3
11 OUT3
10 OUT4
EN1
EN2
GND
VIN
EN1
EN2
GND
VIN
EN3
NC
EN3
EN4
9
NC
9
FLT4
Typical Application
V+
OUT_1
ENABLE_1
USB
PORT_1
FAULT_1
ENABLE_2
FAULT_2
USB
OUT_2
V+
USB
PORT_2
+5V
VIN
CONTROLLER
ISL6123
ISL6124
V+
OUT_3
USB
PORT_3
ENABLE_3
FAULT_3
V+
OUT_4
ENABLE_4
FAULT_4
USB
PORT_4
GND
ISL6124 ONLY
2
ISL6123, ISL6124
Simplified Block Diagram Each Channel
VIN
Q-PUMP
POR
OUT
CURRENT AND TEMP.
MONITORING, GATE AND
OUTPUT CONTROL
LOGIC
EN
FAULT
GND
Pin Descriptions
PIN NO.
DESIGNATOR
FUNCTION
IC Reference
DESCRIPTION
1, 5
GND
VIN
2, 6
Chip Bias, Controlled
Supply Input,
VIN provides chip bias voltage. At VIN < 2.5V chip functionality is disabled,
FAULT_X latch is cleared and floating and VOUT_X is held low.
Undervoltage Lock-Out
3, 4, 7, 8
ENABLE 1, 2, 3,4 Channel Enable Inputs Enables / Disables Switch.
16, 13, 12, 9
FAULT _1, 2, 3, 4 Channel 2, 1 Over
Channel overcurrent fault indicator. FAULT floats and is disabled until VIN >2.5V.
Current Fault Indicator This output is pulled low after the OC time-out period has expired and stays latched
until ENABLE is deasserted.
15, 14, 11, 10
VOUT1, 2, 3, 4
Channel 2, 1
Controlled Supply
Output
Channel voltage output, connect to load to protect. Upon an OC condition I
current limited to 1A. Current limit response time is within 200µS. This output will
remain in current limit for a nominal 12ms before being latched off.
is
OUT
3
ISL6123, ISL6124
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage (VIN to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V
EN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 6V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to VIN + 0.3V
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
16 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . .
70
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . 3KV
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
o
Electrical Specifications Supply Voltages = 5V, T = T = -40 to 85 C, Unless Otherwise Specified
A
J
PARAMETER
POWER SWITCH
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
o
ISL6123, ISL6124 On Resistance
ISL6123, ISL6124 On Resistance
ISL6123, ISL6124 On Resistance
r
r
r
VIN = 2.7V, IOUT = 0.7A, T = T = 25 C
-
-
-
-
-
-
-
-
-
-
90
115
80
105
130
100
130
95
130
450
-
mΩ
mΩ
DS(ON)_27
DS(ON)_33
DS(ON)_50
A
J
o
T
= T = 85 C
J
A
o
VIN = 3.3V, IOUT = 0.7A, T = T = 25 C
mΩ
A
J
o
T
= T = 85 C
115
80
mΩ
A
J
o
VIN = 5V, IOUT = 0.7A, T = T = 25 C
mΩ
A
J
o
T
= T = 85 C
115
300
10
mΩ
A
J
Disabled Output Voltage
VOUT Rising Rate
V
VIN = 5V, Switch Disabled, 50µA Load
mV
OUT_DIS
t_vout_rt
t_svout_offt R = 10Ω, C = 0.1µF, 90% - 10%
R = 10Ω, C = 0.1µF, 10% - 90%
V/ms
V/ms
V/µs
L
L
Slow VOUT Turn-off Rate
Fast VOUT Turn-off Rate
CURRENT CONTROL
Current Limit, VIN = 3.3V - 5V
OC Regulation Settling Time
Severe OC Regulation Settling Time
Over Current Latch-off Time
I/O PARAMETERS
10
-
L
L
t_fvout_offt R = 1Ω, C = 0.1µF, 90%-10%
4
-
L
L
Ilim
tsett
VOUT = 0.8V
R = 5Ω, C = 0.1µF to Within 10% of CR
0.75
1
2
1.25
A
-
-
-
-
-
-
ms
µs
Ilim
L
L
tsett
R < 1Ω, C = 0.1µF to Within 10% of CR
100
10
Ilim_sev
OC_loff
L
L
o
t
ISL6123, ISL6124X, T = 25 C
J
ms
Fault Output Voltage
Vfault_hi
Ven_vih
Ven_vil
Ien_i
Fault IOUT = 10mA
VIN = 5.5V
-
2.0
-
-
-
-
-
0.4
-
V
V
ENABLE High Threshold
ENABLE Low Threshold
ENABLE Input Current
BIAS PARAMETERS
VIN = 2.7V
0.6
0.5
V
o
ENABLE = 0V to 5V, VIN = 5V, T >25 C
-0.5
µA
J
o
Enabled VIN Current
I
I
Switches Closed, OUTPUT = OPEN, T >0 C
J
-
-
120
-
200
µA
µA
V
VDD
VDD
Disabled VIN Current
Switches Open, OUTPUT = OPEN
VIN Rising, Switch Enabled
5
2.5
-
Undervoltage Lockout Threshold
UV Hysteresis
V
1.7
50
-
2.25
100
150
UVLO
UV
mV
HYS
Temp_dis
o
Over Temperature Disable
-
C
4
ISL6123, ISL6124
Latch-Off Time Delay
Introduction
The primary function of any OC protection device is to
quickly isolate the voltage bus from a faulty load. Many other
IC products sense the IC thermal condition (the monitored
IC junction temperature depends on a number of factors the
most important of which are power dissipation of the faulted
and adjacent switches and package temp) to isolate a faulty
load. The ISL6123/24 uses an internal 12ms timer that starts
upon OC detection. Once an OC condition is detected the
appropriate output is current limited for 12ms to allow
transient conditions to pass before latch-off. The time to
latch-off is independent of device thermal or adjacent switch
condition. See Figure 16 for waveforms illustrating
independent latch-off.
The ISL6123 and ISL6124 are fully independent triple and
quad channel overcurrent (OC) fault protection ICs respectively
for the +2.5V to +5V environment. Each ISL6123/24
incorporates in a 16 lead SOIC package, 80mΩ N-channel
MOSFET power switches for power control. See Figure 1 for
switch resistance performance curves. Independent enabling
inputs and fault reporting outputs compatible with 3V and 5V
logic allows for external control and monitoring. This device
features internal current monitoring, accurate current limiting,
integrated power switches and current limited timed delay to
latch-off for system protection. See Figure 7 for operational
waveforms.
Key Feature Description and Operation
If, after the ISL6123/24 has latched off, and the fault has
asserted and, the enable is not deasserted but the OC
condition still exists, the ISL6123/24 unlike other IC devices
does not send to the controller a continuous string of fault
pulses. The ISL6123/24’s single fault signal is sent at the
time of latch-off unlike other devices, see Figure 10.
UV Lockout
The ISL6123/24 undervoltage lockout feature prevents
functionality of the device unless the correct ENABLE state
and VIN > 2.5V are present.
Soft Start
Slow and Fast Shutdown
A constant 500nA current source ramps up the switch’s gate
causing a voltage follower effect on the output voltage. This
provides a soft start turn-on eliminating bus voltage drooping
caused by in-rush current charging heavy load capacitances.
Rising and falling outputs are current limited voltage ramps
so that both the inrush current and voltage slew rate are
limited, independent of load. This reduces supply droop due
to surge and also eliminates the need for EMI filters
necessary on other IC products. See Figure 2 for turn on
waveforms.
The ISL6123/24 has two shutdown modes. When disabled
with a load current less than the Current Regulation (CR)
level the ISL6123/24 shuts down in a controlled manner
using a 500nA constant current source controlled ramp.
When latched off due to CR and the timer has expired the
ISL6123/24 quickly pulls down the output thereby quickly
removing the faulted load from the voltage bus. See Figures
8 and 9 for waveforms of each mode.
Temperature Shutdown
Although the ISL6123/24 has a thermal shutdown feature,
because of the 12ms timed shutdown this will only be
invoked in extremely high ambient temperatures.
Fault Blanking On Start-up
During initial turn-on the ISL6123/24 prevent nuisance faults
being reported to the system controller by blanking the fault
signal for 12ms. This blanking eliminates the need for
external RC filters necessary for other vendor products that
assert a fault signal upon initial turn-on into a temporary high
current condition. See Figures 10 through 12 for waveform
examples.
Active Output Pulldown
Another unique ISL6123/24 feature is the active pull down
on the outputs to 300mV above GND when the device is
disabled. Competitors’ parts’ switch leakage causes the
output voltage to drift up to VIN voltage even when the part
is supposed to be disabled.
Current Regulation
The ISL6123/24 have integrated current sensing on the
power MOSFET that allows for rapid control of OC events.
Once an OC is detected the ISL6123/24 goes into its
Current Regulation (CR) control mode. The ISL6123/24 CR
level is set to a nominal 1A for each channel. This current
regulation is ±25% over the full operating temperature and
voltage bias range. See Figures 3 and 4 for illustrative
curves.
Instantaneous Protection Compared to PPTC
Devices
The ISL6123/24 provide a more consistent level of protection
versus the PPTC alternative. PPTC, or poly fuses which are
thermal sensing devices, increasing in resistance as their
internal temperature increases to a level where current flow
is slowly restricted. See Figure 13 for a comparison of the
ISL6123/24 voltage loss (efficiency) to a PPTC device. The
ISL6123 and ISL6124 with their independent of temperature
12ms time to latch off is contrasted to a suitably sized PPTC
device for time to shutdown in an OC condition for both in
Figures 14 and 15.
The speed of this control is inversely related to the
magnitude of the OC fault. Thus a hard over current is more
quickly controlled than a marginal OC condition. See Figure
5 for waveforms illustrating this and Figure 6 for an
accompanying graph.
5
ISL6123, ISL6124
Typical Performance Curves
120
110
ENABLE
100
VIN = 2.7V
90
80
CL = 0.1µF, 10µF
VIN = 5V
70
60
50
40
VIN = 3.3V
C = 100µF
L
VOUT
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
o
VOUT VOLTAGE (1V/DIV.)
TIME (400µs /DIV.)
TEMPERATURE ( C)
FIGURE 1. SWITCH ON RESISTANCE AT 0.7A
FIGURE 2. VOUT SOFT START vs C
LOAD
1200
1200
o
-40 C
o
-40 C
1100
1000
1000
1000
o
25 C
o
25 C
o
85 C
900
800
900
800
o
85 C
1.25 1.5
1.75 2.0
2.25 2.5
2.75 3.0
3.1
1.3 1.5
2.0
2.5
3.0
3.5
4.0
4.5 4.8
VOUT (V)
VOUT (V)
FIGURE 3. CURRENT REGULATION vs VOUT (VIN = 3.3V)
FIGURE 4. CURRENT REGULATION vs VOUT (VIN = 5.0V)
1.6
1.4
1.2
1.0
0.8
0.6
CURRENT REGULATED
LEVEL
0.4
0.2
NOMINAL CURRENT
0
1
2
3
4
5
6
7
8
9
10
TIME (200µs /DIV.)
FAULT CURRENT (A)
FIGURE 5. OC TO CR SETTLING TIME WAVEFORMS
FIGURE 6. CR SETTLING TIME vs FAULT CURRENT
6
ISL6123, ISL6124
Typical Performance Curves (Continued)
ENABLE
ON
OFF
ENABLE
FAULT
RESET BY
ENABLE
LATCH-OFF SET
CURRENT
REGULATION
SETTLING
C = 10µF
L
VOUT
TIME (1.4ms)
C =100µF
L
OVER CURRENT
1A CURRENT
LIMIT
C = 0.1µF
L
VOUT
IOUT
TIME (400µs /DIV.)
VOUT VOLTAGE (1V/DIV.)
12ms CURRENT REGULATION PERIOD
FIGURE 7. OPERATIONAL WAVEFORMS
FIGURE 8. SLOW TURN-OFF vs C
LOAD
ENABLE
FAULT
C = 10µF
L
C = 100µF
L
VOUT
C = 0.1µF
L
VOUT
VOUT VOLTAGE (1V/DIV.)
TIME (400µs /DIV.)
VOUT (1V/DIV.)
TIME (2ms /DIV.)
FIGURE 9. FAST TURN-OFF vs C
FIGURE 10. ISL6123, ISL6124 TURN-ON INTO 1.5A OC
LOAD
ENABLE
ENABLE
FAULT
FAULT
VOUT
VOUT
VOUT (1V/DIV.)
TIME (2ms /DIV.)
VOUT (1V/DIV.)
TIME (2ms /DIV.)
FIGURE 11. ISL6123, ISL6124 TURN-ON INTO 1.5A
MOMENTARY OC
FIGURE 12. VENDOR IC TURN-ON INTO MOMENTARY OC
7
ISL6123, ISL6124
Typical Performance Curves (Continued)
VDD = 5.08V
PPTC
ISL6123, ISL6124 = 5.04 VOUT
ISL6123, ISL6124
0.012s
PPTC = 4.98 VOUT
VOUT (1V/DIV.)
TIME (10ms /DIV.)
VOUT (100mV/DIV.)
FIGURE 14. ISL6123, ISL6124 vs PPTC PLUGGED ONTO 1.5A
LOAD
FIGURE 13. ISL6123, ISL6124 vs PPTC INTO 500mA LOAD
ENABLE
PPTC
ISL6123, ISL6124
COMP IC
8s
ISL6123, ISL6124
VOUT (1V/DIV.)
TIME (100µs/DIV.)
VOUT (1V/DIV.)
TIME (1s /DIV.)
FIGURE 15. ISL6123, ISL6124 vs PPTC WITH EXTENDED 1.5A
LOAD
FIGURE 16. SWITCH FAULT INDEPENDENCE
8
ISL6123, ISL6124
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/quality/iso.asp.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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9
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RENESAS
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