ISL6256AHRZ [RENESAS]

Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers; QFN28, QSOP28; Temp Range: -10° to 100°C;
ISL6256AHRZ
型号: ISL6256AHRZ
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers; QFN28, QSOP28; Temp Range: -10° to 100°C

电池
文件: 总26页 (文件大小:1413K)
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DATASHEET  
ISL6256, ISL6256A  
Highly Integrated Battery Charger with Automatic Power Source Selector for  
Notebook Computers  
FN6499  
Rev 3.00  
September 14, 2010  
The ISL6256, ISL6256A is a highly integrated battery charger  
controller for Li-ion/Li-ion polymer batteries. High Efficiency is  
Features  
• ±0.5% Charge Voltage Accuracy (-10°C to +100°C)  
• ±3% Accurate Input Current Limit  
achieved by a synchronous buck topology and the use of a  
MOSFET, instead of a diode, for selecting power from the  
adapter or battery. The low side MOSFET emulates a diode at  
light loads to improve the light load efficiency and prevent  
system bus boosting.  
• ±3% Accurate Battery Charge Current Limit  
• ±25% Accurate Battery Trickle Charge Current Limit  
• Programmable Charge Current Limit, Adapter Current  
Limit and Charge Voltage  
The constant output voltage can be selected for 2, 3 and 4  
series Li-ion cells with 0.5% accuracy over-temperature. It can  
also be programmed between 4.2V + 5%/cell and  
• Fixed 300kHz PWM Synchronous Buck Controller with  
Diode Emulation at Light Load  
4.2V - 5%/cell to optimize battery capacity. When supplying  
the load and battery charger simultaneously, the input current  
limit for the AC adapter is programmable to within 3%  
accuracy to avoid overloading the AC adapter, and to allow  
the system to make efficient use of available adapter power  
for charging. It also has a wide range of programmable  
charging current. The ISL6256, ISL6256A provides outputs  
that are used to monitor the current drawn from the AC  
adapter, and monitor for the presence of an AC adapter. The  
ISL6256, ISL6256A automatically transitions from regulating  
current mode to regulating voltage mode.  
• Overvoltage Protection  
• Output for Current Drawn from AC Adapter  
• AC Adapter Present Indicator  
• Fast Input Current Limit Response  
• Input Voltage Range 7V to 25V  
• Support 2-, 3- and 4-Cells Battery Pack  
• Up to 17.64V Battery-Voltage Set Point  
• Control Adapter Power Source Select MOSFET  
• Thermal Shutdown  
ISL6256, ISL6256A has a feature for automatic power source  
selection by switching to the battery when the AC adapter is  
removed or switching to the AC adapter when the AC adapter is  
available. It also provides a DC adapter monitor to support  
aircraft power applications with the option of no battery charging.  
• Aircraft Power Capable  
• DC Adapter Present Indicator  
• Battery Discharge MOSFET Control  
• Less than 10µA Battery Leakage Current  
• Supports Pulse Charging  
Ordering Information  
PART  
NUMBER  
(Notes 1, 2)  
TEMP  
RANGE  
(°C)  
PART  
MARKING  
PACKAGE  
(Pb-free)  
PKG.  
DWG. #  
ISL6256HRZ  
ISL6256HAZ  
ISL 6256HRZ  
ISL 6256HAZ  
-10 to +100 28 Ld 5x5 QFN L28.5x5  
-10 to +100 28 Ld QSOP M28.15  
• Pb-free (RoHS Compliant)  
Applications  
ISL6256AHRZ ISL6256 AHRZ -10 to +100 28 Ld 5x5 QFN L28.5x5  
ISL6256AHAZ ISL6256 AHAZ -10 to +100 28 Ld QSOP M28.15  
• Notebook, Desknote and Sub-notebook Computers  
• Personal Digital Assistant  
NOTES:  
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on  
reel specifications.  
2. These Intersil Pb-free plastic packaged products employ special Pb-  
free material sets, molding compounds/die attach materials, and  
100% matte tin plate plus anneal (e3 termination finish, which is  
RoHS compliant and compatible with both SnPb and Pb-free  
soldering operations). Intersil Pb-free products are MSL classified at  
Pb-free peak reflow temperatures that meet or exceed the Pb-free  
requirements of IPC/JEDEC J STD-020.  
3. For Moisture Sensitivity Level (MSL), please see device information  
page for ISL6256, ISL6256A. For more information on MSL please  
see techbrief TB363.  
FN6499 Rev 3.00  
Page 1 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Pinouts  
ISL6256, ISL6256A  
(28 LD QFN)  
ISL6256, ISL6256A  
(28 LD QSOP)  
TOP VIEW  
TOP VIEW  
1
2
3
4
5
28  
27  
26  
25  
24  
DCPRN  
ACPRN  
CSON  
CSOP  
CSIN  
DCIN  
VDD  
28 27 26 25 24 23 22  
ACSET  
DCSET  
EN  
1
2
3
4
5
6
7
21  
20 CSIN  
EN  
CSOP  
CELLS  
6
23  
22  
21  
20  
19  
18  
17  
16  
15  
CSIP  
CELLS  
ICOMP  
VCOMP  
ICM  
CSIP  
19  
18  
17  
ICOMP  
7
SGATE  
BGATE  
PHASE  
UGATE  
BOOT  
VDDP  
VCOMP  
SGATE  
BGATE  
8
9
ICM  
VREF  
10  
11  
12  
13  
14  
VREF  
CHLIM  
ACLIM  
VADJ  
16 PHASE  
UGATE  
15  
CHLIM  
8
9
10  
11 12 13 14  
LGATE  
PGND  
GND  
FN6499 Rev 3.00  
September 14, 2010  
Page 2 of 26  
ISL6256, ISL6256A  
SGATE  
ICM  
CSIP CSIN  
DCSET  
DCPRN  
-
+
ACSET  
ACPRN  
X19.9  
CA1  
+
-
+
-
1.26V  
1.26V  
VREF  
152k  
-
CSON  
-
BGATE  
gm3  
ADAPTER  
CURRENT  
LIMIT SET  
+
ACLIM  
ICOMP  
+
152k  
DCIN  
VDD  
LDO  
REGULATOR  
MIN  
CURRENT  
BUFFER  
BOOT  
300kHz  
RAMP  
-
UGATE  
PHASE  
PWM  
MIN  
VOLTAGE  
BUFFER  
+
VCOMP  
VADJ  
VDDP  
VREF  
-0.25  
LGATE  
PGND  
514k  
514k  
gm1  
2.1V  
288k  
-
gm2  
-
32k  
16k  
1.065V  
-
VOLTAGE  
SELECTOR  
+
EN  
CELLS  
VREF  
CA2  
X19.9  
48k  
VDD  
-
+
REFERENCE  
GND  
FB  
CSON CSOP  
CHLIM  
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM  
FN6499 Rev 3.00  
Page 3 of 26  
September 14, 2010  
ISL6256, ISL6256A  
AC ADAPTER  
Q3  
Q5  
VDD  
C8  
R8  
130k  
1%  
C8  
0.1µF  
R9  
10.2k  
1%  
DCIN
SGATE  
CSIP  
2.2  
22  
R21  
ACSET
R2  
20m  
C2  
0.1µF  
ISL6256  
C7  
ISL6256A  
SYSTEM LOAD  
1µF  
CSIN  
BGATE  
BOOT  
VDDP
R22  
R10  
4.7  
3.3V  
VDDP  
D2  
VDD  
VDD
Q4  
C1:10µF  
C9  
1µF  
R5  
100k  
TO HOST  
CONTROLLER  
UGATE  
PHASE  
LGATE  
PGND  
ACPRN
ICOMP
VCOMP
VADJ
Q1  
C4  
0.1µF  
R23  
10k  
C6  
R6  
6.8nF  
C5  
D3  
1N914  
10nF  
D1  
OPTIONAL  
L
Q2  
R11  
4.7µH  
4.7k  
FLOATING  
4.2V/CELL  
22  
CSON  
CHARGE  
ENABLE  
CSOP  
EN
R1  
20m  
C3  
0.047µF  
ACLIM
VREF
BAT+  
CSON  
R12  
VDD  
4 CELLS  
22  
BATTERY  
PACK  
C10  
22µF  
CELLS  
R12  
20k 1%  
2.6A CHARGE LIMIT  
253mA TRICKLE CHARGE  
VREF  
BAT-  
ICM  
CHLIM
C11  
3300pF  
R7: 100  
R13  
1.87k  
1%  
R11  
130k  
1%  
GND  
TRICKLE  
CHARGE  
Q6  
FIGURE 2. ISL6256, ISL6256A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS  
FN6499 Rev 3.00  
September 14, 2010  
Page 4 of 26  
ISL6256, ISL6256A  
ADAPTER  
Q5  
Q3  
VDD  
R8  
130k  
1%  
C8  
0.1µ  
R14  
100k  
1%  
R9  
10.2k  
1%  
DCIN
SGATE  
R21  
2.2  
22  
CSIP  
ACSET
C2  
0.1µF  
R2  
20m  
DCSET
R15  
11.5k  
1%  
SYSTEM LOAD  
CSIN  
ISL6256  
C7  
1µF  
ISL6256A  
R22  
Q4  
BGATE  
BOOT  
VDDP
R10  
4.7  
VDDP  
C1:10µF  
Q1  
C9  
1µF  
VDD  
VCC  
D2  
VDD
R16  
100k  
R5  
100k  
UGATE  
PHASE  
LGATE  
PGND  
C4  
0.1µF  
DIGITAL  
INPUT  
R23  
10k  
ACPRN
DCPRN
DIGITAL  
INPUT  
D1  
OPTIONAL  
D3  
1N914  
L
Q2  
4.7µH  
D/A OUTPUT  
OUTPUT  
CHLIM
R11  
22  
CSON  
EN
CSOP  
R7: 100  
R1  
20m  
C3  
A/D INPUT  
ICM
0.047µF  
C11  
3300pF  
VREF  
5.15A INPUT  
CSON  
CELLS  
VADJ  
BAT+  
ACLIM
VREF
HOST  
C10  
22µF  
R12  
22  
GND  
CURRENT LIMIT  
3 CELLS  
C6  
6.8nF  
FLOATING  
4.2V/CELL  
R11, R12  
R13: 10k  
BATTERY  
PACK  
ICOMP
AVDD/VREF  
GND  
VCOMP
R6  
4.7k  
C5  
10nF  
SCL  
SDL  
SCL  
SDL  
A/D INPUT  
GND  
TEMP  
BAT-  
FIGURE 3. ISL6256, ISL6256A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL AND AIRCRAFT POWER SUPPORT  
FN6499 Rev 3.00  
September 14, 2010  
Page 5 of 26  
ISL6256, ISL6256A  
Absolute Maximum Ratings  
Thermal Information  
DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . .-0.3V to +28V  
CSIP-CSIN, CSOP-CSON. . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V  
CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V  
PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V  
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +35V  
BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V  
ACLIM, ACPRN, CHLIM, DCPRN, VDD to GND. . . . . . . -0.3V to 7V  
BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . .-0.3V to 7V  
ACSET and DCSET to GND (Note 4) . . . . . . . -0.3V to VDD +0.3V  
ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD +0.3V  
VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V  
EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V  
UGATE. . . . . . . . . . . . . . . . . . . . . . . . PHASE -0.3V to BOOT +0.3V  
LGATE . . . . . . . . . . . . . . . . . . . . . . . . . PGND -0.3V to VDDP +0.3V  
Thermal Resistance  
(°C/W)  
(°C/W)  
JA  
JC  
QFN Package (Notes 5, 6). . . . . . . . . .  
QSOP Package (Note 5) . . . . . . . . . . .  
39  
80  
9.5  
N/A  
Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +150°C  
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and  
result in failures not covered by warranty.  
NOTES:  
4. ACSET may be operated 1V below GND if the current through ACSET is limited to less than 1mA.  
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech  
Brief TB379.  
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.  
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,  
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C  
= 1µF, I = 0mA,  
VDD  
VDD  
= -10°C to +100°C, T +125°C, Unless Otherwise Noted. Boldface limits apply over the  
T
A
J
operating temperature range, -10°C to +100°C.  
MIN  
MAX  
PARAMETER  
TEST CONDITIONS  
(Note 8)  
TYP  
(Note 8)  
UNITS  
SUPPLY AND BIAS REGULATOR  
DCIN Input Voltage Range  
7
25  
3
V
mA  
µA  
V
DCIN Quiescent Current  
EN = VDD or GND, 7V DCIN 25V  
1.4  
3
Battery Leakage Current (Note 7)  
VDD Output Voltage/Regulation  
VDD Undervoltage Lockout Trip Point  
DCIN = 0, no load  
10  
7V DCIN 25V, 0 I  
VDD Rising  
30mA  
4.925  
4.0  
5.075  
4.4  
5.225  
4.6  
VDD  
V
Hysteresis  
200  
250  
2.39  
400  
2.415  
0.5  
mV  
V
Reference Output Voltage VREF  
Battery Charge Voltage Accuracy  
0 I  
300µA  
2.365  
-0.5  
-0.5  
-0.5  
-0.5  
VREF  
CSON = 16.8V, CELLS = VDD, VADJ = Float  
CSON = 12.6V, CELLS = GND, VADJ = Float  
CSON = 8.4V, CELLS = Float, VADJ = Float  
%
0.5  
%
0.5  
%
CSON = 17.64V, CELLS = VDD,  
VADJ = VREF  
0.5  
%
CSON = 13.23V, CELLS = GND,  
VADJ = VREF  
-0.5  
0.5  
%
CSON = 8.82V, CELLS = Float, VADJ = VREF  
CSON = 15.96V, CELLS = VDD, VADJ = GND  
CSON = 11.97V, CELLS = GND, VADJ = GND  
CSON = 7.98V, CELLS = Float, VADJ = GND  
-0.5  
-0.5  
-0.5  
-0.5  
0.5  
0.5  
0.5  
0.5  
%
%
%
%
TRIP POINTS  
ACSET Threshold  
1.24  
2.4  
1.26  
3.4  
1.28  
4.4  
V
ACSET Input Bias Current Hysteresis  
µA  
FN6499 Rev 3.00  
Page 6 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,  
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C  
= 1µF, I = 0mA,  
VDD  
VDD  
= -10°C to +100°C, T +125°C, Unless Otherwise Noted. Boldface limits apply over the  
T
A
J
operating temperature range, -10°C to +100°C. (Continued)  
MIN  
MAX  
PARAMETER  
ACSET Input Bias Current  
ACSET Input Bias Current  
DCSET Threshold  
TEST CONDITIONS  
ACSET 1.26V  
(Note 8)  
TYP  
3.4  
0
(Note 8)  
UNITS  
µA  
2.4  
4.4  
1
ACSET < 1.26V  
-1  
µA  
1.24  
2.4  
1.26  
3.4  
3.4  
0
1.28  
4.4  
4.4  
1
V
DCSET Input Bias Current Hysteresis  
DCSET Input Bias Current  
DCSET Input Bias Current  
OSCILLATOR  
µA  
DCSET 1.26V  
2.4  
µA  
DCSET < 1.26V  
-1  
µA  
Frequency  
245  
97  
300  
1.6  
1
355  
kHz  
V
PWM Ramp Voltage (peak-to-peak)  
CSIP = 18V  
CSIP = 11V  
V
SYNCHRONOUS BUCK REGULATOR  
Maximum Duty Cycle  
99  
99.6  
3.0  
%
A
UGATE Pull-up Resistance  
UGATE Source Current  
UGATE Pull-down Resistance  
UGATE Sink Current  
BOOT-PHASE = 5V, 500mA source current  
BOOT-PHASE = 5V, BOOT-UGATE = 2.5V  
BOOT-PHASE = 5V, 500mA sink current  
BOOT-PHASE = 5V, UGATE-PHASE = 2.5V  
VDDP-PGND = 5V, 500mA source current  
VDDP-PGND = 5V, VDDP-LGATE = 2.5V  
VDDP-PGND = 5V, 500mA sink current  
VDDP-PGND = 5V, LGATE = 2.5V  
1.8  
1.0  
1.0  
1.8  
1.8  
1.0  
1.0  
1.8  
1.8  
3.0  
1.8  
30  
A
LGATE Pull-up Resistance  
LGATE Source Current  
LGATE Pull-down Resistance  
LGATE Sink Current  
A
A
Dead Time  
Falling UGATE to rising LGATE or  
falling LGATE to rising UGATE  
10  
0
ns  
CHARGING CURRENT SENSING AMPLIFIER  
Input Common-Mode Range  
18  
2
V
Input Bias Current at CSOP  
Input Bias Current at CSON  
CHLIM Input Voltage Range  
5 < CSOP < 18V  
0.25  
75  
µA  
µA  
V
5 < CSON < 18V  
100  
3.6  
0
160  
95  
ISL6256  
ISL6256: CHLIM = 3.3V  
ISL6256: CHLIM = 2.0V  
ISL6256: CHLIM = 0.2V  
ISL6256A: CHLIM = 3.3V  
ISL6256A: CHLIM = 2.0V  
ISL6256A: CHLIM = 0.2V  
165  
100  
10  
170  
105  
15.0  
168.3  
103  
12.5  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
CSOP to CSON Full-Scale Current Sense  
Voltage  
5.0  
161.7  
97  
ISL6256A  
165  
100  
10  
CSOP to CSON Full-Scale Current Sense  
Voltage  
7.5  
ISL6256 CSOP to CSON Full-Scale  
Current Sense Voltage Formula  
Charge current limit mode  
0.2V < CHLIM < 3.3V  
CHLIM*50  
- 5  
CHLIM*50  
+ 5  
ISL6256A CSOP to CSON Full-Scale  
Current Sense Voltage Formula  
Charge current limit mode  
0.2V < CHLIM < 3.3V  
CHLIM*49.72  
-2.4  
CHLIM*50.28  
+2.4  
mV  
µA  
CHLIM Input Bias Current  
CHLIM = GND or 3.3V, DCIN = 0V  
-1  
1
FN6499 Rev 3.00  
Page 7 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,  
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C  
= 1µF, I = 0mA,  
VDD  
VDD  
= -10°C to +100°C, T +125°C, Unless Otherwise Noted. Boldface limits apply over the  
T
A
J
operating temperature range, -10°C to +100°C. (Continued)  
MIN  
MAX  
PARAMETER  
TEST CONDITIONS  
CHLIM rising  
(Note 8)  
TYP  
(Note 8)  
UNITS  
CHLIM Power-down Mode Threshold  
Voltage  
80  
88  
95  
mV  
CHLIM Power-down Mode Hysteresis  
Voltage  
15  
7
25  
40  
mV  
ADAPTER CURRENT SENSING AMPLIFIER  
Input Common-Mode Range  
25  
V
Input Bias Current at CSIP and CSIN  
Combined  
CSIP = CSIN = 25V  
100  
130  
µA  
Input Bias Current at CSIN  
0 < CSIN < DCIN  
0.10  
µA  
ADAPTER CURRENT LIMIT THRESHOLD  
CSIP to CSIN Full-Scale Current Sense  
Voltage  
ACLIM = VREF  
ACLIM = Float  
ACLIM = GND  
ACLIM = VREF  
ACLIM = GND  
97  
72  
47  
10  
-20  
100  
75  
103  
78  
mV  
mV  
mV  
µA  
50  
53  
ACLIM Input Bias Current  
16  
20  
-16  
-10  
µA  
VOLTAGE REGULATION ERROR AMPLIFIER  
Error Amplifier Transconductance from  
CSON to VCOMP  
CELLS = VDD  
30  
µA/V  
CURRENT REGULATION ERROR AMPLIFIER  
Charging Current Error Amplifier  
Transconductance  
50  
50  
µA/V  
µA/V  
Adapter Current Error Amplifier  
Transconductance  
BATTERY CELL SELECTOR  
CELLS Input Voltage for 4-Cell Select  
CELLS Input Voltage for 3-Cell Select  
CELLS Input Voltage for 2-Cell Select  
MOSFET DRIVER  
4.3  
2.1  
V
V
V
2
4.2  
BGATE Pull-up Current  
CSIP-BGATE = 3V  
CSIP-BGATE = 5V  
10  
2.7  
8
30  
4.0  
9.6  
0
45  
5.0  
11  
mA  
mA  
V
BGATE Pull-down Current  
CSIP-BGATE Voltage High  
CSIP-BGATE Voltage Low  
-50  
-100  
50  
mV  
mV  
DCIN-CSON Threshold for CSIP-BGATE DCIN = 12V, CSON Rising  
Going High  
0
100  
DCIN-CSON Threshold Hysteresis  
250  
7
300  
12  
160  
9
400  
15  
mV  
mA  
µA  
V
SGATE Pull-up Current  
CSIP-SGATE = 3V  
CSIP-SGATE = 5V  
SGATE Pull-down Current  
CSIP-SGATE Voltage High  
CSIP-SGATE Voltage Low  
50  
8
370  
11  
-50  
2.5  
0
50  
mV  
mV  
CSIP-CSIN Threshold for CSIP-SGATE  
Going High  
8
13  
FN6499 Rev 3.00  
Page 8 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, ACLIM = VREF,  
VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, C  
= 1µF, I = 0mA,  
VDD  
VDD  
= -10°C to +100°C, T +125°C, Unless Otherwise Noted. Boldface limits apply over the  
T
A
J
operating temperature range, -10°C to +100°C. (Continued)  
MIN  
MAX  
PARAMETER  
CSIP-CSIN Threshold Hysteresis  
LOGIC INTERFACE  
TEST CONDITIONS  
(Note 8)  
TYP  
(Note 8)  
UNITS  
2
5
8
mV  
EN Input Voltage Range  
EN Threshold Voltage  
0
1.030  
0.985  
30  
VDD  
1.100  
1.025  
90  
V
V
Rising  
1.06  
1.000  
60  
Falling  
V
Hysteresis  
EN = 2.5V  
mV  
µA  
mA  
µA  
mA  
µA  
%
EN Input Bias Current  
ACPRN Sink Current  
ACPRN Leakage Current  
DCPRN Sink Current  
DCPRN Leakage Current  
ICM Output Accuracy  
1.8  
3
2.0  
2.2  
11  
ACPRN = 0.4V  
8
ACPRN = 5V  
-0.5  
3
0.5  
11  
DCPRN = 0.4V  
8
DCPRN = 5V  
-0.5  
-3  
0.5  
+3  
CSIP-CSIN = 100mV  
CSIP-CSIN = 75mV  
CSIP-CSIN = 50mV  
0
0
(V  
= 19.9 x (V  
-V ))  
CSIP CSIN  
ICM  
-4  
+4  
%
-5  
0
+5  
%
Thermal Shutdown Temperature  
150  
25  
°C  
°C  
Thermal Shutdown Temperature  
Hysteresis  
NOTE:  
7. This is the sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET,  
VADJ, CELLS, ACLIM, CHLIM.  
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are  
established by characterization and are not production tested.  
FN6499 Rev 3.00  
Page 9 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Typical Operating Performance  
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted.  
A
0.6  
0.10  
0.08  
0.06  
0.04  
0.02  
0.3  
0.0  
-0.3  
-0.6  
0.00  
0
5
10  
15  
20  
40  
0
100  
200  
300  
400  
LOAD CURRENT (mA)  
LOAD CURRENT (µA)  
FIGURE 4. VDD LOAD REGULATION  
FIGURE 5. VREF LOAD REGULATION  
10  
9
8
7
6
5
4
3
2
1
0
100  
96  
92  
88  
84  
80  
76  
VCSON = 8.4V  
2 CELLS  
VCSON = 12.6V  
3 CELLS  
VCSON = 16.8V  
4 CELLS  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
CSIP-CSIN (mV)  
LOAD CURRENT (A)  
FIGURE 6. ACCURACY vs AC ADAPTER CURRENT  
FIGURE 7. SYSTEM EFFICIENCY vs CHARGE CURRENT  
LOAD  
CURRENT  
5A/div  
DCIN  
10V/div  
ADAPTER  
CURRENT  
5A/div  
ACSET  
1V/div  
CHARGE  
CURRENT  
2A/div  
DCSET  
1V/div  
LOAD STEP: 0A TO 4A  
CHARGE CURRENT: 3A  
AC ADAPTER CURRENT LIMIT: 5.15A  
BATTERY  
VOLTAGE  
2V/div  
DCPRN  
5V/div  
ACPRN  
5V/div  
FIGURE 8. AC AND DC ADAPTER DETECTION  
FIGURE 9. LOAD TRANSIENT RESPONSE  
FN6499 Rev 3.00  
September 14, 2010  
Page 10 of 26  
ISL6256, ISL6256A  
Typical Operating Performance  
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted. (Continued)  
A
CSON  
5V/div  
INDUCTOR  
CURRENT  
2A/div  
EN  
5V/div  
BATTERY  
REMOVAL  
I
INSERTION  
BATTERY  
CSON  
10V/div  
INDUCTOR  
CURRENT  
2A/div  
VCOMP  
2V/div  
VCOMP  
CHARGE  
CURRENT  
2A/div  
ICOMP  
ICOMP  
2V/div  
FIGURE 10. CHARGE ENABLE AND SHUTDOWN  
FIGURE 11. BATTERY INSERTION AND REMOVAL  
CHLIM = 0.2V  
CSON = 8V  
PHASE  
10V/div  
PHASE  
10V/div  
INDUCTOR  
CURRENT  
1A/div  
UGATE  
2V/div  
UGATE  
5V/div  
LGATE  
2V/div  
FIGURE 12. SWITCHING WAVEFORMS AT DIODE EMULATION  
FIGURE 13. SWITCHING WAVEFORMS IN CC MODE  
BGATE-CSIP  
2V/div  
SGATE-CSIP  
2V/div  
ADAPTER REMOVAL  
SYSTEM BUS  
VOLTAGE  
10V/div  
SYSTEM BUS  
VOLTAGE  
10V/div  
SGATE-CSIP  
2V/div  
BGATE-CSIP  
2V/div  
INDUCTOR  
CURRENT  
2A/div  
INDUCTOR  
CURRENT  
2A/div  
ADAPTER INSERTION  
AD
FIGURE 14. AC ADAPTER REMOVAL  
FIGURE 15. AC ADAPTER INSERTION  
FN6499 Rev 3.00  
September 14, 2010  
Page 11 of 26  
ISL6256, ISL6256A  
Typical Operating Performance  
DCIN = 20V, 4S2P Li-Battery, T = +25°C, Unless Otherwise Noted. (Continued)  
A
CHARGE  
CURRENT  
1A/div  
CHLIM  
1V/div  
FIGURE 16. TRICKLE TO FULL-SCALE CHARGING  
GND  
Functional Pin Descriptions  
GND is an analog ground.  
BOOT  
DCIN  
Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin  
and connect to the cathode of the bootstrap Schottky diode.  
The DCIN pin is the input of the internal 5V LDO. Connect it to  
the AC adapter output. Connect a 0.1µF ceramic capacitor  
from DCIN to CSON.  
UGATE  
UGATE is the high side MOSFET gate drive output.  
ACSET  
SGATE  
ACSET is an AC adapter detection input. Connect to a resistor  
divider from the AC adapter output.  
SGATE is the AC adapter power source select output. The  
SGATE pin drives an external P-MOSFET used to switch to AC  
adapter as the system power source.  
ACPRN  
Open-drain output signals AC adapter is present. ACPRN pulls  
low when ACSET is higher than 1.26V; and pulled high when  
ACSET is lower than 1.26V.  
BGATE  
Battery power source select output. This pin drives an external  
P-Channel MOSFET used to switch the battery as the system  
power source. When the voltage at CSON pin is higher than  
the AC adapter output voltage at DCIN, BGATE is driven to low  
and selects the battery as the power source.  
DCSET  
DCSET is a lower voltage adapter detection input (like aircraft  
power 15V). Allows the adapter to power the system where  
battery charging has been disabled.  
LGATE  
DCPRN  
LGATE is the low side MOSFET gate drive output; swing  
between 0V and VDDP.  
Open-drain output signals DC adapter is present. DCPRN pulls  
low when DCSET is higher than 1.26V; and pulled high when  
DCSET is lower than 1.26V.  
PHASE  
The Phase connection pin connects to the high side MOSFET  
source, output inductor, and low side MOSFET drain.  
EN  
EN is the Charge Enable input. Connecting EN to high enables  
the charge control function, connecting EN to low disables  
charging functions. Use with a thermistor to detect a hot  
battery and suspend charging.  
CSOP/CSON  
CSOP/CSON is the battery charging current sensing  
positive/negative input. The differential voltage across CSOP  
and CSON is used to sense the battery charging current, and  
is compared with the charging current limit threshold to  
regulate the charging current. The CSON pin is also used as  
the battery feedback voltage to perform voltage regulation.  
ICM  
ICM is the adapter current output. The output of this pin  
produces a voltage proportional to the adapter current.  
CSIP/CSIN  
PGND  
CSIP/CSIN is the AC adapter current sensing positive/negative  
input. The differential voltage across CSIP and CSIN is used to  
sense the AC adapter current, and is compared with the AC  
adapter current limit to regulate the AC adapter current.  
PGND is the power ground. Connect PGND to the source of  
the low side MOSFET.  
FN6499 Rev 3.00  
Page 12 of 26  
September 14, 2010  
ISL6256, ISL6256A  
begins to operate at a constant voltage charge mode. The  
charger also drives an adapter isolation P-Channel MOSFET to  
efficiently switch in the adapter supply.  
VDD  
VDD is an internal LDO output to supply IC analog circuit.  
Connect a 1µF ceramic capacitor to ground.  
ISL6256 is a complete power source selection controller for  
single battery systems and also aircraft power applications. It  
drives a battery selector P-Channel MOSFET to efficiently  
select between a single battery and the adapter. It controls the  
battery discharging MOSFET and switches to the battery when  
the AC adapter is removed, or, switches to the AC adapter  
when the AC adapter is inserted for single battery system.  
VDDP  
VDDP is the supply voltage for the low-side MOSFET gate  
driver. Connect a 4.7resistor to VDD and a 1µF ceramic  
capacitor to power ground.  
ICOMP  
ICOMP is a current loop error amplifier output.  
The EN input allows shutdown of the charger through a  
command from a micro-controller. It also uses EN to safely  
shutdown the charger when the battery is in extremely hot  
conditions. The amount of adapter current is reported on the  
ICM output. Figure 1 shows the IC functional block diagram.  
VCOMP  
VCOMP is a voltage loop amplifier output.  
CELLS  
This pin is used to select the battery voltage. CELLS = VDD for  
a 4S battery pack, CELLS = GND for a 3S battery pack,  
CELLS = Float for a 2S battery pack.  
The synchronous buck converter uses external N-Channel  
MOSFETs to convert the input voltage to the required charging  
current and charging voltage. Figure 2 shows the ISL6256  
typical application circuit with charging current and charging  
voltage fixed at specific values. The typical application circuit  
shown in Figure 3 shows the ISL6256 typical application circuit  
which uses a micro-controller to adjust the charging current set  
by CHLIM input for aircraft power applications. The voltage at  
VADJ  
VADJ adjusts battery regulation voltage. VADJ = VREF for  
4.2V + 5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for  
4.2V - 5%/cell. Connect to a resistor divider to program the  
desired battery cell voltage between 4.2V - 5% and 4.2V + 5%.  
CHLIM and the value of R sets the charging current. The  
CHLIM  
1
DC/DC converter generates the control signals to drive two  
external N-Channel MOSFETs to regulate the voltage and  
current set by the ACLIM, CHLIM, VADJ and CELLS inputs.  
CHLIM is the battery charge current limit set pin. CHLIM input  
voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set  
point for CSOP-CSON is 165mV. The charger shuts down if  
CHLIM is forced below 88mV.  
The ISL6256 features a voltage regulation loop (VCOMP) and  
two current regulation loops (ICOMP). The VCOMP voltage  
regulation loop monitors CSON to ensure that its voltage never  
exceeds the voltage and regulates the battery charge voltage  
set by VADJ. The ICOMP current regulation loops regulate the  
battery charging current delivered to the battery to ensure that  
it never exceeds the charging current limit set by CHLIM; and  
the ICOMP current regulation loops also regulate the input  
current drawn from the AC adapter to ensure that it never  
exceeds the input current limit set by ACLIM, and to prevent a  
system crash and AC adapter overload.  
ACLIM  
ACLIM is the adapter current limit set pin. ACLIM = VREF for  
100mV, ACLIM = Floating for 75mV, and ACLIM = GND for  
50mV. Connect a resistor divider to program the adapter  
current limit threshold between 50mV and 100mV.  
VREF  
VREF is a 2.39V reference output pin. It is internally  
compensated. Do not connect a decoupling capacitor.  
Theory of Operation  
PWM Control  
Introduction  
The ISL6256 employs a fixed frequency PWM current mode  
control architecture with a feed-forward function. The  
feed-forward function maintains a constant modulator gain of  
11 to achieve fast line regulation as the buck input voltage  
changes. When the battery charge voltage approaches the  
input voltage, the DC/DC converter operates in dropout mode,  
where there is a timer to prevent the frequency from dropping  
into the audible frequency range. It can achieve duty cycle of  
up to 99.6%.  
Note: Unless otherwise noted, all descriptions that refer to the  
ISL6256 also refer to the ISL6256A.  
The ISL6256 includes all of the functions necessary to charge  
2 to 4 cell Li-ion and Li-polymer batteries. A high efficiency  
synchronous buck converter is used to control the charging  
voltage and charging current up to 10A. The ISL6256 has input  
current limiting and analog inputs for setting the charge current  
and charge voltage; CHLIM inputs are used to control charge  
current and VADJ inputs are used to control charge voltage.  
To prevent boosting of the system bus voltage, the battery  
charger operates in standard-buck mode when CSOP-CSON  
drops below 4.25mV. Once in standard-buck mode, hysteresis  
does not allow synchronous operation of the DC/DC converter  
until CSOP-CSON rises above 12.5mV.  
The ISL6256 charges the battery with constant charge current,  
set by CHLIM input, until the battery voltage rises up to a  
programmed charge voltage set by VADJ input; then the charger  
FN6499 Rev 3.00  
Page 13 of 26  
September 14, 2010  
ISL6256, ISL6256A  
An adaptive gate drive scheme is used to control the dead time  
between two switches. The dead time control circuit monitors  
the LGATE output and prevents the upper side MOSFET from  
turning on until LGATE is fully off, preventing cross-conduction  
and shoot-through. In order for the dead time circuit to work  
properly, there must be a low resistance, low inductance path  
from the LGATE driver to MOSFET gate, and from the source  
of MOSFET to PGND. The external Schottky diode is between  
the VDDP pin and BOOT pin to keep the bootstrap capacitor  
charged.  
compensation of the voltage regulation and current-regulation  
loops allows for optimal compensation.  
TABLE 1. CELL NUMBER PROGRAMMING  
CELLS  
VDD  
CELL NUMBER  
4
3
2
GND  
Float  
Setting the Battery Charge Current Limit  
Setting the Battery Regulation Voltage  
The CHLIM input sets the maximum charging current. The  
current set by the current sense-resistor connects between  
CSOP and CSON. The full-scale differential voltage between  
CSOP and CSON is 165mV for CHLIM = 3.3V, so the  
maximum charging current is 4.125A for a 40msensing  
resistor. Other battery charge current-sense threshold values  
can be set by connecting a resistor divider from VREF or 3.3V  
to ground, or by connecting a low impedance voltage source  
like a D/A converter in the micro-controller. Unlike VADJ and  
ACLIM, CHLIM does not have an internal resistor divider  
network. The charge current limit threshold is given by  
Equation 3:  
The ISL6256 uses a high-accuracy trimmed band-gap voltage  
reference to regulate the battery charging voltage. The VADJ  
input adjusts the charger output voltage, and the VADJ control  
voltage can vary from 0 to VREF, providing a 10% adjustment  
range (from 4.2V - 5% to 4.2V + 5%) on CSON regulation  
voltage. An overall voltage accuracy of better than 0.5% is  
achieved.  
The per-cell battery termination voltage is a function of the  
battery chemistry (consult the battery manufacturers to  
determine this voltage)  
• Float VADJ to set the battery voltage V  
number of the cells  
= 4.2V   
CSON  
V
165mV  
CHLIM  
3.3V  
   
------------------- ---------------------  
I
=
(EQ. 3)  
CHG  
   
R
1
• Connect VADJ to VREF to set 4.41V number of cells  
• Connect VADJ to ground to set 3.99V number of the cells  
To set the trickle charge current for the dumb charger, an A/D  
output controlled by the micro-controller is connected to  
CHLIM pin. The trickle charge current is determined by  
Equation 4:  
so, the maximum battery voltage of 17.6V can be achieved. Note  
that other battery charge voltages can be set by connecting a  
resistor divider from VREF to ground. The resistor divider should  
be sized to draw no more than 100µA from VREF; or connect a  
low impedance voltage source like the D/A converter in the micro-  
controller. The programmed battery voltage per cell can be  
determined by Equation 1:  
V
165mV  
   
CHLIM,trickle  
(EQ. 4)  
------------------- ---------------------------------------  
I
=
CHG  
   
R
3.3V  
1
When the CHLIM voltage is below 88mV (typical), it will disable  
the battery charge. When choosing the current sensing  
resistor, note that the voltage drop across the sensing resistor  
causes further power dissipation, reducing efficiency. However,  
adjusting CHLIM voltage to reduce the voltage across the  
(EQ. 1)  
V
= 0.175 V  
+ 3.99V  
VADJ  
CELL  
An external resistor divider from VREF sets the voltage at  
VADJ according to Equation 2:  
current sense resistor R will degrade accuracy due to the  
1
smaller signal to the input of the current sense amplifier. There  
is a trade-off between accuracy and power dissipation. A low  
pass filter is recommended to eliminate switching noise.  
Connect the resistor to the CSOP pin instead of the CSON pin,  
as the CSOP pin has lower bias current and less influence on  
current-sense accuracy and voltage regulation accuracy.  
  
R
514k  
bot_VADJ  
----------------------------------------------------------------------------------------------------------------  
top_VADJ  
V
= VREF   
VADJ  
  
  
514k  
R
514k+ R  
bot_VADJ  
(EQ. 2)  
To minimize accuracy loss due to interaction with VADJ's  
internal resistor divider, ensure the AC resistance looking back  
into the external resistor divider is less than 25k.  
Charge Current Limit Accuracy  
The “Electrical Specifications” table on page 7 gives minimum  
and maximum values for the CSOP-CSON voltage resulting  
from IC variations at 3 different CHLIM voltages (see “CSOP to  
CSON Full-Scale Current Sense Voltage” on page 7). It also  
gives formulae for calculating the minimum and maximum  
CSOP-CSON voltage at any CHLIM voltage. Equation 5 shows  
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells.  
When charging other cell chemistries, use CELLS to select an  
output voltage range for the charger. The internal error amplifier  
gm1 maintains voltage regulation. The voltage error amplifier is  
compensated at VCOMP. The component values shown in Figure  
3 provide suitable performance for most applications. Individual  
FN6499 Rev 3.00  
Page 14 of 26  
September 14, 2010  
ISL6256, ISL6256A  
the formula for the max full scale CSOP-CSON voltage (in mV)  
for the ISL6256A:  
ISL6256A  
An internal amplifier gm3 compares the voltage between CSIP  
and CSIN to the input current limit threshold voltage set by  
ACLIM. Connect ACLIM to REF, Float and GND for the full-  
scale input current limit threshold voltage of 100mV, 75mV and  
50mV, respectively, or use a resistor divider from VREF to  
ground to set the input current limit as Equation 10:  
(EQ. 5)  
CSOP CSON  
= CHLIM 50.28 + 2.4  
= CHLIM 49.72 2.4  
MAX  
CSOP CSON  
MIN  
Equation 5 shows the formula for the max full scale CSOP-  
CSON voltage (in mV) for the ISL6256:  
ISL6256  
1
0.05  
VREF  
------ ----------------  
I
=
V  
+ 0.05  
ACLIM  
(EQ. 10)  
INPUT  
R
2
An external resistor divider from VREF sets the voltage at  
ACLIM according to Equation 11:  
(EQ. 6)  
MAXCSOP CSON= CHLIM 50 + 5  
MINCSOP CSON= CHLIM 50 5  
  
R
152k  
With CHLIM = 1.5V, the maximum CSOP-CSON voltage is  
78mV and the minimum CSOP-CSON voltage is 72mV.  
botACLIM  
-----------------------------------------------------------------------------------------------------------------------  
V
= VREF   
ACLIM  
  
  
152k  
R
152k+ R  
topACLIM  
botACLIM  
When ISL6256A is in charge current limiting mode, the  
maximum charge current is the maximum CSOP-CSON  
voltage divided by the minimum sense resistor. This can be  
calculated for ISL6256A with Equation 7:  
(EQ. 11)  
where R  
ACLIM.  
and R  
are external resistors at  
bot_ACLIM  
top_ACLIM  
ISL6256A  
To minimize accuracy loss due to interaction with ACLIM's  
internal resistor divider, ensure the AC resistance looking back  
into the resistor divider is less than 25k.  
I
I
= CHLIM 50.28 + 2.4  R  
= CHLIM 49.72 2.4  R  
CHGMAX  
1min  
(EQ. 7)  
CHGMIN  
1max  
When choosing the current sense resistor, note that the  
voltage drop across this resistor causes further power  
Maximum charge current can be calculated for ISL6256 with  
Equation 8:  
ISL6256  
dissipation, reducing efficiency. The AC adapter current sense  
accuracy is very important. Use a 1% tolerance current-sense  
resistor. The highest accuracy of ±3% is achieved with 100mV  
current-sense threshold voltage for ACLIM = VREF, but it has  
the highest power dissipation. For example, it has 400mW  
power dissipation for rated 4A AC adapter and 1sensing  
resistor may have to be used. ±4% and ±6% accuracy can be  
achieved with 75mV and 50mV current-sense threshold  
voltage for ACLIM = Floating and ACLIM = GND, respectively.  
I
= CHLIM 50 + 5  R  
= CHLIM 50 5  R  
(EQ. 8)  
CHGMAX  
CHGMIN  
1min  
I
1max  
With CHLIM = 0.7V and R = 0.02, 1%:  
1
ISL6256A  
I
= 1.5V 50.28 + 2.4  0.0198 = 3930mA  
= 1.5V 49.72 2.4  0.0202 = 3573mA  
CHGMAX  
(EQ. 9)  
I
CHGMIN  
A low pass filter is suggested to eliminate the switching noise.  
Connect the resistor to CSIN pin instead of CSIP pin because  
CSIN pin has lower bias current and less influence on the  
current-sense accuracy.  
Setting the Input Current Limit  
The total input current from an AC adapter, or other DC source,  
is a function of the system supply current and the battery-  
charging current. The input current regulator limits the input  
current by reducing the charging current, when the input  
current exceeds the input current limit set point. System  
current normally fluctuates as portions of the system are  
powered up or down. Without input current regulation, the  
source must be able to supply the maximum system current  
and the maximum charger input current simultaneously. By  
using the input current limiter, the current capability of the AC  
adapter can be lowered, reducing system cost.  
AC Adapter Detection  
Connect the AC adapter voltage through a resistor divider to  
ACSET to detect when AC power is available, as shown in  
Figure 2. ACPRN is an open-drain output and is high when  
ACSET is less than V  
, and active low when ACSET is  
and V are given by Equation 12 and  
th,rise  
above V  
. V  
th,fall th,rise  
th,fall  
Equation 13:  
R
8
(EQ. 12)  
------  
V
V
=
+ 1 V  
thrise  
thfall  
ACSET  
R
9
The ISL6256 limits the battery charge current when the input  
current-limit threshold is exceeded, ensuring the battery  
charger does not load down the AC adapter voltage. This  
constant input current regulation allows the adapter to fully  
power the system and prevent the AC adapter from  
overloading and crashing the system bus.  
R
8
------  
(EQ. 13)  
=
+ 1 V  
I  
R  
hys 8  
ACSET  
R
9
FN6499 Rev 3.00  
Page 15 of 26  
September 14, 2010  
ISL6256, ISL6256A  
where:  
The threshold voltage of EN is 1.0V with 60mV hysteresis. The  
thermistor can be selected to have a resistance vs temperature  
characteristic that abruptly decreases above a critical  
temperature. This arrangement automatically shuts down the  
ISL6256 when the battery pack is above a critical temperature.  
• I  
hys  
is the ACSET input bias current hysteresis, and  
= 1.24V (min), 1.26V (typ) and 1.28V (max).  
• V  
ACSET  
The hysteresis is I R , where I  
hys  
= 2.2µA (min), 3.4µA (typ)  
hys  
8
and 4.4µA (max).  
Another method for inhibiting charging is to force CHLIM below  
85mV (typ).  
DC Adapter Detection  
Supply Isolation  
Connect the DC adapter voltage like aircraft power through a  
resistor divider to DCSET to detect when DC power is  
available, as shown in Figure 3. DCPRN is an open-drain  
If the voltage across the adapter sense resistor R is typically  
2
greater than 8mV, the P-Channel MOSFET controlled by  
output and is high when DCSET is less than V  
, and  
and V  
SGATE is turned on reducing the power dissipation. If the  
voltage across the adapter sense resistor R is less than 3mV,  
2
SGATE turns off the P-Channel MOSFET isolating the adapter  
from the system bus.  
th,rise  
active low when DCSET is above V  
are given by Equations 14 and 15:  
. V  
th,fall th,rise  
th,fall  
R
14  
---------  
V
=
+ 1 V  
(EQ. 14)  
thrise  
DCSET  
R
15  
Battery Power Source Selection and Aircraft Power  
Application  
R
14  
The battery voltage is monitored by CSON. If the battery voltage  
measured on CSON is less than the adapter voltage measured  
on DCIN, then the P-Channel MOSFET controlled by BGATE  
turns off and the P-Channel MOSFET controlled by SGATE is  
allowed to turn on when the adapter current is high enough. If it is  
greater, then the P-Channel MOSFET controlled by SGATE turns  
off and BGATE turns on the battery discharge P-Channel  
MOSFET to minimize the power loss. Also, the charging function  
is disabled. If designing for airplane power, DCSET is tied to a  
resistor divider sensing the adapter voltage. When a user is  
plugged into the 15V airplane supply and the battery voltage is  
lower than 15V, the MOSFET driven by BGATE (see Figure 3) is  
turned off which keeps the battery from supplying the system bus.  
The comparator looking at CSON and DCIN has 300mV of  
hysteresis to avoid chattering. Only 2S and 3S are supported for  
DC aircraft power applications. For 4S battery packs, set  
DCSET = 0.  
---------  
V
=
+ 1 V  
I  
R
hys 14  
(EQ. 15)  
thfall  
DCSET  
R
15  
Where I  
is the DCSET input bias current hysteresis and  
= 1.24V (min), 1.26V (typ) and 1.28V (max). The  
hys  
V
DCSET  
hysteresis is I  
R
, where I = 2.2µA (min), 3.4µA (typ)  
hys 14 hys  
and 4.4µA (max).  
Current Measurement  
Use ICM to monitor the input current being sensed across  
CSIP and CSIN. The output voltage range is 0V to 2.5V. The  
voltage of ICM is proportional to the voltage drop across CSIP  
and CSIN, and is given by Equation 16:  
(EQ. 16)  
ICM = 19.9 I  
R  
2
INPUT  
where I  
is the DC current drawn from the AC adapter.  
INPUT  
ICM has ±3% accuracy. It is recommended to have an RC filter  
at the ICM output for minimizing the switching noise.  
Short Circuit Protection and 0V Battery Charging  
LDO Regulator  
Since the battery charger will regulate the charge current to the  
limit set by CHLIM, it automatically has short circuit protection  
and is able to provide the charge current to wake up an  
extremely discharged battery.  
VDD provides a 5.0V supply voltage from the internal LDO  
regulator from DCIN and can deliver up to 30mA of current.  
The MOSFET drivers are powered by VDDP, which must be  
connected to VDDP as shown in Figure 2. VDDP connects to  
VDD through an external low pass filter. Bypass VDDP and  
VDD with a 1µF capacitor.  
Over-Temperature Protection  
If the die temp exceeds +150°C, it stops charging. Once the  
die temp drops below +125°C, charging will start-up again.  
Shutdown  
Overvoltage Protection  
The ISL6256 features a low-power shutdown mode. Driving  
EN low shuts down the ISL6256. In shutdown, the DC/DC  
converter is disabled, and VCOMP and ICOMP are pulled to  
ground. The ICM, ACPRN and DCPRN outputs continue to  
function.  
ISL6256 has an Overvoltage Protection circuit that limits the  
output voltage when the battery is removed or disconnected by  
a pulse charging circuit. If CSON exceeds the output voltage  
set point by more than V  
an internal comparator pulls  
OVP  
VCOMP down and turns off both upper and lower FETs of the  
buck as in Figure 17. The trip point for Overvoltage Protection  
EN can be driven by a thermistor to allow automatic shutdown  
of the ISL6256 when the battery pack is hot. Often a NTC  
thermistor is included inside the battery pack to measure its  
temperature. When connected to the charger, the thermistor  
forms a voltage divider with a resistive pull-up to the VREF.  
FN6499 Rev 3.00  
Page 16 of 26  
September 14, 2010  
ISL6256, ISL6256A  
is always above the nominal output voltage and can be  
Inductor Selection  
calculated from Equation 17:  
V
The inductor selection has trade-offs between cost, size,  
crossover frequency and efficiency. For example, the lower the  
inductance, the smaller the size, but ripple current is higher.  
This also results in higher AC losses in the magnetic core and  
the windings, which decrease the system efficiency. On the  
other hand, the higher inductance results in lower ripple current  
and smaller output filter capacitors, but it has higher DCR (DC  
resistance of the inductor) loss, lower saturation current and  
has slower transient response. So, the practical inductor  
design is based on the inductor ripple current being ±15% to  
±20% of the maximum operating DC current at maximum input  
voltage. Maximum ripple is at 50% duty cycle or  
ADJ  
---------------  
V
= V  
+ N  
42.2mV 22.2mV   
OVP  
OUTNOM  
CELLS  
2.39V  
(EQ. 17)  
For example, if the CELLS pin is connected to ground  
(N  
= 3) and V  
is floating (V = 1.195V) then  
CELLS  
ADJ  
ADJ  
V
V
= 12.6V and VOVP = 12.693V or  
+ 93mV.  
OUT,NOM  
OUT,NOM  
There is a delay of approximately 400ns between V  
OUT  
exceeding the OVP trip point and pulling VCOMP, LGATE and  
UGATE low.  
V
= V /2. The required inductance can be calculated  
BAT  
IN,MAX  
from Equation 18:  
V
VCOMP  
ICOMP  
OUT  
V
INMAX  
I  
(EQ. 18)  
---------------------------------------------  
L =  
4 f  
SW RIPPLE  
WHEN V  
OUT  
THE OVP THRESHOLD  
EXCEEDS  
Where V  
and f  
are the maximum input voltage, and  
SW  
IN,MAX  
VCOMP IS PULLED LOW  
AND FETS TURN OFF  
switching frequency, respectively.  
The inductor ripple current I is found from Equation 19:  
(EQ. 19)  
I
= 0.3 I  
LMAX  
RIPPLE  
BATTERY  
REMOVAL  
CURRENT FLOWS IN THE  
LOWER FET BODY DIODE  
where the maximum peak-to-peak ripple current is 30% of the  
maximum charge current is used.  
UNTIL INDUCTOR CURRENT  
REACHES ZERO  
For V  
= 19V, V  
BAT  
= 16.8V, I = 2.6A, and  
BAT,MAX  
IN,MAX  
PHASE  
f = 300kHz, the calculated inductance is 8.3µH. Choosing the  
s
closest standard value gives L = 10µH. Ferrite cores are often  
the best choice since they are optimized at 300kHz to 600kHz  
operation with low core loss. The core must be large enough  
not to saturate at the peak inductor current IPeak in  
Equation 20:  
FIGURE 17. OVERVOLTAGE PROTECTION IN ISL6256  
1
2
--  
I
= I  
+
I  
RIPPLE  
(EQ. 20)  
PEAK  
LMAX  
During normal operation with cells installed, the CSON pin  
voltage will be the cell stack voltage. When EN is low and the  
cells are removed, this voltage may drop below 100mV. Due to  
non-linearities in the OVP comparator at this low input level,  
the VCOMP pin may be held low even after EN is commanded  
high. If regulation is required in the absence of cells then a  
series resistor and diode need to be installed which inject  
current into the CSON pin from the VDD pin. See R23 and D3  
in Figure 3. This will maintain the CSON pin voltage well within  
its linear range in the absence of cells, and will be effectively  
out of the circuit when the diode is reversed biased by the cell  
stack. Resistor values from 10k to 100k have been found to be  
effective.  
Inductor saturation can lead to cascade failures due to very  
high currents. Conservative design limits the peak and RMS  
current in the inductor to less than 90% of the rated saturation  
current.  
Crossover frequency is heavily dependent on the inductor  
value. f  
should be less than 20% of the switching frequency  
CO  
and a conservative design has f  
less than 10% of the  
CO  
switching frequency. The highest f  
is in voltage control  
CO  
mode with the battery removed and may be calculated  
(approximately) from Equation 21:  
5 11 R  
SENSE  
(EQ. 21)  
------------------------------------------  
=
f
CO  
2  L  
Application Information  
Output Capacitor Selection  
The following battery charger design refers to the typical  
application circuit in Figure 2, where typical battery  
configuration of 4S2P is used. This section describes how to  
select the external components including the inductor, input  
and output capacitors, switching MOSFETs, and current  
sensing resistors.  
The output capacitor in parallel with the battery is used to  
absorb the high frequency switching ripple current and smooth  
FN6499 Rev 3.00  
Page 17 of 26  
September 14, 2010  
ISL6256, ISL6256A  
the output voltage. The RMS value of the output ripple current  
exhibit cross conduction (or shoot through) due to current  
I
is given by Equation 22:  
injected into the drain-to-source parasitic capacitor (C ) by  
RMS  
gd  
the high dV/dt rising edge at the phase node when the  
high-side MOSFET turns on. Although LGATE sink current  
(1.8A typical) is more than enough to switch the FET off  
quickly, voltage drops across parasitic impedances between  
LGATE and the MOSFET can allow the gate to rise during the  
fast rising edge of voltage on the drain. MOSFETs with low  
V
(EQ. 22)  
INMAX  
---------------------------------  
I
=
D  1 D  
RMS  
12 L f  
SW  
where the duty cycle D is the ratio of the output voltage (battery  
voltage) over the input voltage for continuous conduction  
mode, which is typical operation for the battery charger. During  
the battery charge period, the output voltage varies from its  
initial battery voltage to the rated battery voltage. So, the duty  
cycle change can be in the range of between 0.53 and 0.88 for  
the minimum battery voltage of 10V (2.5V/Cell) and the  
maximum battery voltage of 16.8V. The maximum RMS value  
of the output ripple current occurs at the duty cycle of 0.5 and  
is expressed as Equation 23:  
threshold voltage (<1.5V) and low ratio of C /C (<5) and  
gs gd  
high gate resistance (>4) may be turned on for a few ns by  
the high dV/dt (rising edge) on their drain. This can be avoided  
with higher threshold voltage and C /C ratio. Another way  
gs gd  
to avoid cross conduction is slowing the turn-on speed of the  
high-side MOSFET by connecting a resistor between the  
BOOT pin and the boot strap capacitor.  
V
For the high-side MOSFET, the worst-case conduction losses  
INMAX  
-------------------------------------------  
I
=
(EQ. 23)  
RMS  
occur at the minimum input voltage as shown in Equation 24:  
V
4 12 L F  
SW  
2
OUT  
(EQ. 24)  
---------------  
P
=
I  
r  
BAT DSON  
Q1conduction  
For V  
= 19V, VBAT = 16.8V, L = 10µH, and f = 300kHz,  
V
IN,MAX  
s
IN  
the maximum RMS current is 0.19A. A typical 10F ceramic  
capacitor is a good choice to absorb this current and also has  
very small size. Organic polymer capacitors have high  
capacitance with small size and have a significant equivalent  
series resistance (ESR). Although ESR adds to ripple voltage,  
it also creates a high frequency zero that helps the closed loop  
operation of the buck regulator.  
The optimum efficiency occurs when the switching losses  
equal the conduction losses. However, it is difficult to calculate  
the switching losses in the high-side MOSFET since it must  
allow for difficult-to-quantify factors that influence the turn-on  
and turn-off times. These factors include the MOSFET internal  
gate resistance, gate charge, threshold voltage, stray  
inductance, pull-up and pull-down resistance of the gate driver.  
EMI considerations usually make it desirable to minimize ripple  
current in the battery leads. Beads may be added in series with  
the battery pack to increase the battery impedance at 300kHz  
switching frequency. Switching ripple current splits between  
the battery and the output capacitor depending on the ESR of  
the output capacitor and battery impedance. If the ESR of the  
output capacitor is 10mand battery impedance is raised to  
2with a bead, then only 0.5% of the ripple current will flow in  
the battery.  
The following switching loss calculation (Equation 25) provides  
a rough estimate.  
P
=
Q1Switching  
(EQ. 25)  
Q
Q
gd  
1
2
1
2
gd  
--  
------------------------  
--  
-----------------  
V
I
f
+
V
I
f
+ Q V f  
rr IN sw  
IN LV sw  
IN LP sw  
I
I
gsource  
gsink  
where the following are the peak gate-drive source/sink current  
of Q , respectively:  
1
MOSFET Selection  
• Q : drain-to-gate charge,  
gd  
The Notebook battery charger synchronous buck converter  
has the input voltage from the AC adapter output. The  
maximum AC adapter output voltage does not exceed 25V.  
Therefore, 30V logic MOSFET should be used.  
• Q : total reverse recovery charge of the body-diode in  
rr  
low-side MOSFET,  
• I : inductor valley current,  
LV  
• I : Inductor peak current,  
LP  
The high side MOSFET must be able to dissipate the  
conduction losses plus the switching losses. For the battery  
charger application, the input voltage of the synchronous buck  
converter is equal to the AC adapter output voltage, which is  
relatively constant. The maximum efficiency is achieved by  
selecting a high side MOSFET that has the conduction losses  
equal to the switching losses. Switching losses in the low-side  
FET are very small. The choice of low-side FET is a trade-off  
• I  
g,sink  
• I ,  
g source  
Low switching loss requires low drain-to-gate charge Q  
.
gd  
Generally, the lower the drain-to-gate charge, the higher the  
ON-resistance. Therefore, there is a trade-off between the ON-  
resistance and drain-to-gate charge. Good MOSFET selection  
is based on the figure of Merit (FOM), which is a product of the  
total gate charge and ON-resistance. Usually, the smaller the  
value of FOM, the higher the efficiency for the same  
application.  
between conduction losses (r  
) and cost. A good rule of  
DS(ON)  
of the low-side FET is 2x the r  
thumb for the r  
of  
DS(ON)  
DS(ON)  
the high-side FET.  
The LGATE gate driver can drive sufficient gate current to  
switch most MOSFETs efficiently. However, some FETs may  
FN6499 Rev 3.00  
Page 18 of 26  
September 14, 2010  
ISL6256, ISL6256A  
For the low-side MOSFET, the worst-case power dissipation  
occurs at minimum battery voltage and maximum input voltage  
(Equation 26):  
CSNUB and RSNUB can be calculated from Equations 28 and  
29:  
2
------------------------------------  
C
=
SNUB  
(EQ. 28)  
2
2F  
  L  
V
2
ring  
OUT  
(EQ. 26)  
---------------  
IN  
P
=
1 –  
I  
r  
BAT DSON  
Q2  
V
2 L  
Choose a low-side MOSFET that has the lowest possible ON-  
resistance with a moderate-sized package like the SO-8 and is  
reasonably priced. The switching losses are not an issue for  
the low-side MOSFET because it operates at zero-voltage-  
switching.  
R
=
-------------------  
(EQ. 29)  
SNUB  
C
SNUB  
Input Capacitor Selection  
The input capacitor absorbs the ripple current from the  
synchronous buck converter, which is given by Equation 30:  
Choose a Schottky diode in parallel with low-side MOSFET Q  
2
with a forward voltage drop low enough to prevent the low-side  
V
 V V  
OUT  
OUT  
IN  
(EQ. 30)  
-------------------------------------------------------------  
I
= I  
BAT  
RMS  
MOSFET Q body-diode from turning on during the dead time.  
V
2
IN  
This also reduces the power loss in the high-side MOSFET  
associated with the reverse recovery of the low-side MOSFET  
Q body diode.  
2
This RMS ripple current must be smaller than the rated RMS  
current in the capacitor datasheet. Non-tantalum chemistries  
(ceramic, aluminum, or OSCON) are preferred due to their  
resistance to power-up surge currents when the AC adapter is  
plugged into the battery charger. For Notebook battery charger  
applications, it is recommended that ceramic capacitors or  
polymer capacitors from Sanyo be used due to their small size  
and reasonable cost.  
As a general rule, select a diode with DC current rating equal  
to one-third of the load current. One option is to choose a  
combined MOSFET with the Schottky diode in a single  
package. The integrated packages may work better in practice  
because there is less stray inductance due to a short  
connection. This Schottky diode is optional and may be  
removed if efficiency loss can be tolerated. In addition, ensure  
that the required total gate drive current for the selected  
MOSFETs should be less than 24mA. So, the total gate charge  
for the high-side and low-side MOSFETs is limited by Equation  
27:  
Table 2 shows the component lists for the typical application  
circuit in Figure 2.  
TABLE 2. COMPONENT LIST  
PARTS  
PART NUMBERS AND MANUFACTURER  
1
C , C  
10µF/25V ceramic capacitor, Taiyo Yuden  
TMK325 MJ106MY X5R (3.2mmx2.5mmx1.9mm)  
GATE  
1
10  
(EQ. 27)  
------------------  
Q
GATE  
f
sw  
C , C , C  
0.1µF/50V ceramic capacitor  
2
4
8
9
Where I  
is the total gate drive current and should be less  
than 24mA. Substituting I = 24mA and f = 300kHz into  
GATE  
C , C , C  
1µF/10V ceramic capacitor, Taiyo Yuden  
LMK212BJ105MG  
GATE  
s
3
7
Equation 27 yields that the total gate charge should be less  
than 80nC. Therefore, the ISL6256 easily drives the battery  
charge current up to 10A.  
C
C
10nF ceramic capacitor  
5
6.8nF ceramic capacitor  
6
Snubber Design  
C
3300pF ceramic capacitor  
11  
ISL6256's buck regulator operates in discontinuous current  
mode (DCM) when the load current is less than half the  
peak-to-peak current in the inductor. After the low-side FET  
turns off, the phase voltage rings due to the high impedance  
with both FETs off. This can be seen in Figure 9. Adding a  
snubber (resistor in series with a capacitor) from the phase  
node to ground can greatly reduce the ringing. In some  
situations a snubber can improve output ripple and regulation.  
D
30V/3A Schottky diode, EC31QS03L (optional)  
100mA/30V Schottky Diode, Central Semiconductor  
10µH/3.8A/26m, Sumida, CDRH104R-100  
30V/35m, FDS6912A, Fairchild  
-30V/30m, SI4835BDY, Siliconix  
Signal P-Channel MOSFET, NDS352AP  
Signal N-Channel MOSFET, 2N7002  
40m, ±1%, LRC-LR2512-01-R040-F, IRC  
20m, ±1%, LRC-LR2010-01-R020-F, IRC  
18, ±5%, (0805)  
1
D
2
L
Q , Q  
1
2
4
Q , Q  
3
Q
5
6
1
2
3
4
5
6
Q
The snubber capacitor should be approximately twice the  
parasitic capacitance on the phase node. This can be  
estimated by operating at very low load current (100mA) and  
measuring the ringing frequency.  
R
R
R
R
R
R
2.2, ±5%, (0805)  
100k, ±5%, (0805)  
4.7k, ±5%, (0805)  
FN6499 Rev 3.00  
Page 19 of 26  
September 14, 2010  
ISL6256, ISL6256A  
TABLE 2. COMPONENT LIST (Continued)  
The output capacitor creates a pole at a very high frequency  
due to the small resistance in parallel with it. The frequency of  
this pole is calculated in Equation 32:  
1
PARTS  
PART NUMBERS AND MANUFACTURER  
100, ±5%, (0805)  
R
7
--------------------------------------  
=
f
POLE2  
(EQ. 32)  
2  C R  
R , R  
11  
130k, ±1%, (0805)  
o
BAT  
8
R
10.2k, ±1%, (0805)  
9
R
R
R
4.7, ±5%, (0805)  
10  
12  
13  
VDD  
20k, ±1%, (0805)  
RAMP GEN  
1.87k, ±1%, (0805)  
V
= VDD/11  
RAMP  
L
LOOP COMPENSATION DESIGN  
-
ISL6256 has three closed loop control modes. One controls  
the output voltage when the battery is fully charged or absent.  
A second controls the current into the battery when charging  
and the third limits current drawn from the adapter. The charge  
current and input current control loops are compensated by a  
single capacitor on the ICOMP pin. The voltage control loop is  
compensated by a network on the VCOMP pin. Descriptions of  
these control loops and guidelines for selecting compensation  
components will be given in the following sections. Which loop  
controls the output is determined by the minimum current  
buffer and the minimum voltage buffer shown in Figure 1 on  
page 3. These three loops will be described separately.  
+
CO  
PWM  
INPUT  
PWM  
GAIN = 11  
L
R
SENSE  
11  
R
R
FET_r  
DS(ON)  
L_DCR  
CO  
R
BAT  
PWM  
TRANSCONDUCTANCE AMPLIFIERS GM1, GM2 AND GM3  
INPUT  
R
ESR  
The ISL6256 uses several transconductance amplifiers (also  
known as gm amps). Most commercially available op amps are  
voltage controlled voltage sources with gain expressed as  
FIGURE 18. SMALL SIGNAL AC MODEL  
A = V  
/V . Transconductance amps are voltage controlled  
/V  
Charge Current Control Loop  
OUT IN  
current sources with gain expressed as gm = I  
Transconductance gain (gm) will appear in some of the  
equations for poles and zeros in the compensation.  
.
OUT IN  
When the battery voltage is less than the fully charged voltage,  
the voltage error amplifier goes to it’s maximum output (limited  
to 1.2V above ICOMP) and the ICOMP voltage controls the  
loop through the minimum voltage buffer. Figure 19 shows the  
charge current control loop.  
PWM GAIN F  
M
The Pulse Width Modulator in the ISL6256 converts voltage at  
VCOMP to a duty cycle by comparing VCOMP to a triangle  
L
PHASE  
wave (duty = VCOMP/V  
). The low-pass filter formed  
P-P RAMP  
by L and C convert the duty cycle to a DC output voltage  
11  
O
R
R
FET_r  
DS(ON)  
L_DCR  
R
(Vo = V  
*duty). In ISL6256, the triangle wave amplitude is  
DCIN  
proportional to V  
. Making the ramp amplitude proportional  
DCIN  
to DCIN makes the gain from VCOMP to the PHASE output a  
constant 11 and is independent of DCIN. For small signal AC  
analysis, the battery is modeled by it’s internal resistance. The  
total output resistance is the sum of the sense resistor and the  
internal resistance of the MOSFETs, inductor and capacitor.  
Figure 18 shows the small signal model of the pulse width  
modulator (PWM), power stage, output filter and battery.  
+
0.25  
CSOP  
CSON  
F2  
+
-
-
20  
CA2  
C
R
F2  
S2  
ICOMP  
-
gm2  
R
BAT  
C
+
O
C
CHLIM  
+
-
ICOMP  
R
ESR  
In most cases the Battery resistance is very small (<200m)  
resulting in a very low Q in the output filter. This results in a  
frequency response from the input of the PWM to the inductor  
current with a single pole at the frequency calculated in  
Equation 31:  
FIGURE 19. CHARGE CURRENT LIMIT LOOP  
The compensation capacitor (C  
) gives the error amplifier  
(GMI) a pole at a very low frequency (<<1Hz) and a a zero at fZ1.  
ICOMP  
R  
+ r  
+ R  
+ R  
BAT  
(EQ. 31)  
SENSE  
DSON  
DCR  
------------------------------------------------------------------------------------------------------  
=
f
POLE1  
2  L  
FN6499 Rev 3.00  
Page 20 of 26  
September 14, 2010  
ISL6256, ISL6256A  
fZ1 is created by the 0.25*CA2 output added to ICOMP. The  
frequency of can be calculated from Equation 33.  
4 gm2  
Adapter Current Limit Control Loop  
If the combined battery charge current and system load current  
draws current that equals the adapter current limit set by the  
ACLIM pin, ISL6256 will reduce the current to the battery  
and/or reduce the output voltage to hold the adapter current at  
the limit. Above the adapter current limit, the minimum current  
buffer equals the output of gm3 and ICOMP controls the  
charger output. Figure 21 shows the adapter current limit  
control loop.  
---------------------------------------  
gm2 = 50A V  
f
=
(EQ. 33)  
ZERO  
2  C  
ICOMP  
Placing this zero at a frequency equal to the pole calculated in  
Equation 31 will result in maximum gain at low frequencies and  
phase margin near 90°. If the zero is at a higher frequency  
(smaller C  
), the DC gain will be higher but the phase  
ICOMP  
margin will be lower. Use a capacitor on ICOMP that is equal to  
or greater than the value calculated in Equation 34:  
.
DCIN  
4  50A V  
-----------------------------------------------------------------------------------------  
=
C
(EQ. 34)  
ICOMP  
R + r  
+ R  
+ R  
BAT  
S2  
DSON  
DCR  
L
PHASE  
R
S1  
11  
A filter should be added between RS2 and CSOP and CSON to  
reduce switching noise. The filter roll off frequency should be  
between the crossover frequency and the switching frequency  
(~100kHz). RF2 should be small (<10 to minimize offsets due  
to leakage current into CSOP. The filter cut off frequency is  
calculated using Equation 35:  
R
R
FET_r  
DS(ON)  
L_DCR  
R
R
F1  
C
F1  
CSOP  
+
F2  
0.25  
+
-
20  
C
F2  
R
-
CSIN  
CSIP  
CA2  
CSON  
-
1
20  
(EQ. 35)  
------------------------------------------  
f
=
FILTER  
C
2  C R  
F2  
O
+
F2  
CA1  
R
ESR  
-
The crossover frequency is determined by the DC gain of the  
modulator and output filter and the pole in Equation 31. The  
DC gain is calculated in Equation 36 and the crossover  
frequency is calculated with Equation 37.  
gm3  
+
ICOMP  
ICOMP  
ACLIM  
+
C
-
FIGURE 21. ADAPTER CURRENT LIMIT LOOP  
11 R  
S2  
(EQ. 36)  
---------------------------------------------------------------------------------------------------------  
=
A
DC  
The loop response equations, bode plots and the selection of  
ICOMP are the same as the charge current control loop with  
loop gain reduced by the duty cycle and the ratio of R /R  
R + r  
+ R  
+ R  
BATTERY  
S2  
DSON  
DCR  
C
.
S1 S2  
11 R  
S2  
(EQ. 37)  
In other words, if R = R and the duty cycle D = 50%, the  
---------------------  
f
= A  
f  
DC POLE1  
=
S1 S2  
CO  
2  L  
loop gain will be 6dB lower than the loop gain in Figure 21.  
This gives lower crossover frequency and higher phase margin  
The Bode plot of the loop gain, the compensator gain and the  
power stage gain is shown in Figure 20.  
in this mode. If R /R = 2 and the duty cycle is 50% then the  
S1 S2  
:
adapter current loop gain will be identical to the gain in Figure  
21.  
60  
COMPENSATOR  
f
ZERO  
MODULATOR  
LOOP  
A filter should be added between RS1 and CSIP and CSIN to  
reduce switching noise. The filter roll off frequency should be  
between the crossover frequency and the switching frequency  
(~100kHz).  
40  
20  
Voltage Control Loop  
0
When the battery is charged to the voltage set by CELLS and  
VADJ the voltage error amplifier (gm1) takes control of the  
output (assuming that the adapter current is below the limit set  
by ACLIM). The voltage error amplifier (gm1) discharges the cap  
on VCOMP to limit the output voltage. The current to the battery  
decreases as the cells charge to the fixed voltage and the  
voltage across the internal battery resistance decreases. As  
battery current decreases the 2 current error amplifiers (gm2  
and gm3) output their maximum current and charge the  
capacitor on ICOMP to its maximum voltage (limited to 1.2V  
above VCOMP). With high voltage on ICOMP, the minimum  
voltage buffer output equals the voltage on VCOMP.  
-20  
-40  
-60  
f
POLE1  
f
FILTER  
f
POLE2  
0.01k  
0.1k  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
FIGURE 20. CHARGE CURRENT LOOP BODE PLOTS  
FN6499 Rev 3.00  
September 14, 2010  
Page 21 of 26  
ISL6256, ISL6256A  
The voltage control loop is shown in Figure 22.  
The compensation network consists of the voltage error  
amplifier gm1 and the compensation network R  
,
VCOMP  
which give the loop very high DC gain, a very low  
C
VCOMP  
L
PHASE  
frequency pole and a zero at f  
. Inductor current  
ZERO1  
information is added to the feedback to create a second zero  
. The low pass filter R , C between R and  
11  
R
R
FET_r  
DS(ON)  
L_DCR  
R
f
ZERO2 F2 F2 SENSE  
ISL6256 add a pole at f . R and R are internal divider  
FILTER  
3
4
resistors that set the DC output voltage. For a 3-cell battery,  
CA2  
20  
+
CSOP  
F2  
R = 320kand R = 64k. Equations 39, 40, 41, 42, 43 and  
0.25  
+
3
4
-
44 relate the compensation network’s poles, zeros and gain to  
the components in Figure 22. Figure 2424 shows an asymptotic  
bode plot of the DC/DC converter’s gain vs frequency. It is  
C
R
F2  
S2  
-
CSON  
R3  
VCOMP  
R
BAT  
-
C
strongly recommended that f  
is approximately 30% of f  
O
ZERO1  
LC  
gm1  
and f  
is approximately 70% of f  
+
R4  
ZERO2  
LC.  
R
ESR  
C
R
VCOMP  
.
+
-
2.1V  
COMPENSATOR  
MODULATOR  
VCOMP  
f
LC  
f
POLE1  
40  
20  
0
LOOP  
FIGURE 22. VOLTAGE CONTROL LOOP  
Output LC Filter Transfer Functions  
The gain from the phase node to the system output and battery  
depend entirely on external components. Typical output LC  
filter response is shown in Figure 23. Transfer function ALC(s)  
is shown in Equation 38:  
f
FILTER  
-20  
-40  
s
---------------  
1 –  
ESR  
----------------------------------------------------------  
A
=
(EQ. 38)  
LC  
f
2
ZERO1  
s
s
f
ZERO2  
----------- ------------------------  
+
+ 1  
  Q  
DP  
LC  
f
ESR  
-60  
0.1k  
1k  
10k  
FREQUENCY (Hz)  
100k  
1M  
1
1
L
C
o
--------------------------------  
-----------------------  
=
=
LC  
Q = R  
------  
ESR  
o
R  
C   
o
L C   
ESR  
o
FIGURE 24. ASYMPTOTIC BODE PLOT OF THE VOLTAGE  
CONTROL LOOP GAIN  
20  
10  
0
-10  
-20  
-30  
-40  
-50  
-60  
COMPENSATION BREAK FREQUENCY EQUATIONS  
1
NO BATTERY  
----------------------------------------------------------------------  
f
=
ZERO1  
2  C  
R  
1COMP  
(EQ. 39)  
VCOMP  
R
= 200m  
BATTERY  
R
= 50m  
BATTERY  
R
R
gm1  
5
VCOMP  
4
-------------------------------------------------------  
--------------------  
------------  
f
f
=
ZERO2  
2  R  
C  
R
+ R  
3
SENSE  
4
-20  
-40  
-60  
OUT  
(EQ. 40)  
(EQ. 41)  
-80  
1
-------------------------------  
2L C   
=
LC  
-100  
-120  
-140  
-160  
o
1
------------------------------------------  
=
f
(EQ. 42)  
(EQ. 43)  
FILTER  
100 200 500 1k 2k  
5k 10k 20k 50k 100k200k 500k  
FREQUENCY  
2  R C  
F2  
F2  
FIGURE 23. FREQUENCY RESPONSE OF THE LC OUTPUT  
FILTER  
1
---------------------------------------------------  
f
=
POLE1  
2  R  
C   
o
SENSE  
The resistance RO is a combination of MOSFET r  
DCR, R  
SENSE  
, inductor  
and the internal resistance of the battery (normally  
DS(ON)  
1
--------------------------------------------  
f
=
(EQ. 44)  
ESR  
2  C R  
ESR  
between 50mand 200m). The worst case for voltage mode  
control is when the battery is absent. This results in the highest Q  
of the LC filter and the lowest phase margin.  
o
FN6499 Rev 3.00  
Page 22 of 26  
September 14, 2010  
ISL6256, ISL6256A  
LGATE Pin  
TABLE 3.  
This is the gate drive signal for the bottom MOSFET of the  
buck converter. The signal going through this trace has both  
high dv/dt and high di/dt, and the peak charging and  
discharging current is very high. These two traces should be  
short, wide, and away from other traces. There should be no  
other traces in parallel with these traces on any layer.  
CELLS  
R
R
4
3
2
3
4
288k  
320k  
336k  
48k  
64k  
96k  
Choose R  
VCOMP  
equal or lower than the value calculated from  
Equation 45.  
PGND Pin  
R
+ R  
4
R
4
5
gm1  
3
PGND pin should be laid out to the negative side of the  
relevant output cap with separate traces.The negative side of  
the output capacitor must be close to the source node of the  
bottom MOSFET. This trace is the return path of LGATE.  
-----------  
--------------------  
R
= 0.7 F   2  C R    
SENSE  
VCOMP  
LC  
o
(EQ. 45)  
Next, choose C  
equal or higher than the value  
VCOMP  
calculated from Equation 46.  
PHASE Pin  
1
--------------------------------------------------------------------------  
=
C
(EQ. 46)  
This trace should be short, and positioned away from other weak  
signal traces. This node has a very high dv/dt with a voltage swing  
from the input voltage to ground. No trace should be in parallel  
with it. This trace is also the return path for UGATE. Connect this  
pin to the high-side MOSFET source.  
VCOMP  
0.3 F   2  R  
VCOMP  
LC  
PCB Layout Considerations  
Power and Signal Layers Placement on the PCB  
As a general rule, power layers should be close together, either  
on the top or bottom of the board, with signal layers on the  
opposite side of the board. As an example, layer arrangement  
on a 4-layer board is shown below:  
UGATE Pin  
This pin has a square shape waveform with high dv/dt. It  
provides the gate drive current to charge and discharge the top  
MOSFET with high di/dt. This trace should be wide, short, and  
away from other traces similar to the LGATE.  
1. Top Layer: signal lines, or half board for signal lines and the  
other half board for power lines  
2. Signal Ground  
BOOT Pin  
3. Power Layers: Power Ground  
This pin’s di/dt is as high as the UGATE; therefore, this trace  
should be as short as possible.  
4. Bottom Layer: Power MOSFET, Inductors and other Power  
traces  
CSOP, CSON Pins  
Separate the power voltage and current flowing path from the  
control and logic level signal path. The controller IC will stay on  
the signal layer, which is isolated by the signal ground to the  
power signal traces.  
Accurate charge current and adapter current sensing is critical  
for good performance. The current sense resistor connects to  
the CSON and the CSOP pins through a low pass filter with the  
filter cap very near the IC (see Figure 2). Traces from the  
sense resistor should start at the pads of the sense resistor  
and should be routed close together, throughout the low pass  
filter and to the CSON and CSON pins (see Figure 25). The  
CSON pin is also used as the battery voltage feedback. The  
traces should be routed away from the high dv/dt and di/dt pins  
like PHASE, BOOT pins. In general, the current sense resistor  
should be close to the IC. These guidelines should also be  
followed for the adapter current sense resistor and CSIP and  
CSIN. Other layout arrangements should be adjusted  
accordingly.  
Component Placement  
The power MOSFET should be close to the IC so that the gate  
drive signal, the LGATE, UGATE, PHASE, and BOOT, traces  
can be short.  
Place the components in such a way that the area under the IC  
has less noise traces with high dv/dt and di/dt, such as gate  
signals and phase node signals.  
Signal Ground and Power Ground Connection  
At minimum, a reasonably large area of copper, which will  
shield other noise couplings through the IC, should be used as  
signal ground beneath the IC. The best tie-point between the  
signal ground and the power ground is at the negative side of  
the output capacitor on each side, where there is little noise; a  
noisy trace beneath the IC is not recommended.  
SENSE  
RESISTOR  
RESISTER  
HIGH  
CURRENT  
TRACE  
HIGH  
CURRENT  
TRACE  
GND and VDD Pin  
KELVIN CONNECTION TRACES  
TO THE LOW PASS FILTER  
AND  
At least one high quality ceramic decoupling cap should be  
used to cross these two pins. The decoupling cap can be put  
close to the IC.  
CSOP AND CSON  
FIGURE 25. CURRENT SENSE RESISTOR LAYOUT  
FN6499 Rev 3.00  
Page 23 of 26  
September 14, 2010  
ISL6256, ISL6256A  
EN Pin  
This pin stays high at enable mode and low at idle mode and is  
relatively robust. Enable signals should refer to the signal  
ground.  
DCIN Pin  
This pin connects to AC adapter output voltage, and should be  
less noise sensitive.  
Copper Size for the Phase Node  
The capacitance of PHASE should be kept very low to  
minimize ringing. It would be best to limit the size of the  
PHASE node copper in strict accordance with the current and  
thermal management of the application.  
Identify the Power and Signal Ground  
The input and output capacitors of the converters, the source  
terminal of the bottom switching MOSFET PGND should  
connect to the power ground. The other components should  
connect to signal ground. Signal and power ground are tied  
together at one point.  
Clamping Capacitor for Switching MOSFET  
It is recommended that ceramic caps be used closely  
connected to the drain of the high-side MOSFET, and the  
source of the low-side MOSFET. This capacitor reduces the  
noise and the power loss of the MOSFET.  
FN6499 Rev 3.00  
Page 24 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Package Outline Drawing  
L28.5x5  
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
Rev 2, 10/07  
4X  
3.0  
5.00  
0.50  
24X  
A
6
B
PIN #1 INDEX AREA  
28  
22  
6
PIN 1  
INDEX AREA  
1
21  
3 .10 ± 0 . 15  
15  
7
(4X)  
0.15  
8
14  
0.10 M C A B  
- 0.07  
TOP VIEW  
28X 0.55 ± 0.10  
BOTTOM VIEW  
4
28X 0.25  
+ 0.05  
SEE DETAIL "X"  
C
0.10  
0 . 90 ± 0.1  
C
BASE PLANE  
SEATING PLANE  
0.08  
C
( 4. 65 TYP )  
(
( 24X 0 . 50)  
SIDE VIEW  
3. 10)  
(28X 0 . 25 )  
( 28X 0 . 75)  
5
C
0 . 2 REF  
0 . 00 MIN.  
0 . 05 MAX.  
TYPICAL RECOMMENDED LAND PATTERN  
DETAIL "X"  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
FN6499 Rev 3.00  
Page 25 of 26  
September 14, 2010  
ISL6256, ISL6256A  
Shrink Small Outline Plastic Packages (SSOP)  
Quarter Size Outline Plastic Packages (QSOP)  
M28.15  
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE  
(0.150” WIDE BODY)  
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
E
GAUGE  
PLANE  
INCHES  
MIN  
MILLIMETERS  
-B-  
SYMBOL  
MAX  
0.069  
0.010  
0.061  
0.012  
0.010  
0.394  
0.157  
MIN  
1.35  
0.10  
-
MAX  
1.75  
0.25  
1.54  
0.30  
0.25  
10.00  
3.98  
NOTES  
A
A1  
A2  
B
0.053  
0.004  
-
-
1
2
3
-
L
0.25  
0.010  
SEATING PLANE  
A
-
-A-  
0.008  
0.007  
0.386  
0.150  
0.20  
0.18  
9.81  
3.81  
9
D
h x 45°  
C
D
E
-
-C-  
3
4
A2  
e
A1  
C
e
0.025 BSC  
0.635 BSC  
-
B
0.10(0.004)  
H
h
0.228  
0.0099  
0.016  
0.244  
0.0196  
0.050  
5.80  
0.26  
0.41  
6.19  
0.49  
1.27  
-
0.17(0.007) M  
C
A M B S  
5
L
6
NOTES:  
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2  
of Publication Number 95.  
N
28  
28  
7
0°  
8°  
0°  
8°  
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
Rev. 1 6/04  
3. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusion and gate burrs shall not exceed  
0.15mm (0.006 inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. Inter-  
lead flash and protrusions shall not exceed 0.25mm (0.010 inch)  
per side.  
5. The chamfer on the body is optional. If it is not present, a visual in-  
dex feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. Dimension “B” does not include dambar protrusion. Allowable dam-  
bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”  
dimension at maximum material condition.  
10. Controlling dimension: INCHES. Converted millimeter dimensions  
are not necessarily exact.  
© Copyright Intersil Americas LLC 2007-2010. All Rights Reserved.  
All trademarks and registered trademarks are the property of their respective owners.  
For additional products, see www.intersil.com/en/products.html  
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted  
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html  
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such  
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are  
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its  
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6499 Rev 3.00  
Page 26 of 26  
September 14, 2010  

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