ISL6324AIRZ [RENESAS]
DUAL SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, QFN-48;![ISL6324AIRZ](http://pdffile.icpdf.com/pdf2/p00302/img/icpdf/ISL6324AIRZ-_1821956_icpdf.jpg)
型号: | ISL6324AIRZ |
厂家: | ![]() |
描述: | DUAL SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, QFN-48 开关 |
文件: | 总39页 (文件大小:1673K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DATASHEET
2
ISL6324A Hybrid SVI/PVI with I C
FN6880
Rev 1.00
May 14, 2010
Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI
The ISL6324A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
Features
Processor Core Voltage Regulator Features
• Configuration Flexibility
converters. The ISL6324A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6324A features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
- 1- or 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Parallel VID (6-bit) Interface Inputs for PVI Mode
• PSI_L Support via Phase Shedding
• Differential Remote Voltage Sensing
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
A precision uniplane core voltage regulation system is provided
by a 2-to-4-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers, adding flexibility in
layout, reduce the number of external components in the multi-
phase section. A single phase PWM controller with integrated
driver provides a second precision voltage regulation system
for the North Bridge portion of the processor. This monolithic,
dual controller with integrated driver solution provides a cost
and space saving power management solution.
- Active Pulse Positioning Modulation
Processor Core Voltage Regulator and North Bridge
Voltage Regulator Shared Features
• Precision Voltage Regulation: ±0.5% System Accuracy
Over-Temperature
• Two Wire, AMD Compliant Serial VID Interface Inputs for
SVI Mode
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6324A features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient response
to load application and removal. One of these features is
highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
2
• I C Interface
- Voltage Margining, OVP and PGOOD Trip Levels
- Enhanced PSI_L State Control
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing for Core
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
The ISL6324A supports Power Savings Mode by dropping
phases when the PSI_L bit is set. The number of phases
that the ISL6324A will drop to is programmable through an
2
I C interface. The number of PWM cycles between both
dropping phases when entering Power Savings Mode and
adding phases when exiting Power Savings Mode is also
Ordering Information
2
programmable through the I C interface.
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
2
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
The ISL6324A I C interface also allows independent
programmable output voltage offset for both the Core and
2
ISL6324ACRZ* ISL6324A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6324AIRZ* ISL6324A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
North Bridge regulators. The I C interface can also be used
to set the PGOOD and OVP trip levels for both regulators as
well.
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6880 Rev 1.00
May 14, 2010
Page 1 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Pinout
ISL6324A HYBRID SVI AND PVI
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
FB_NB
ISEN_NB+
SDA
PWM4
PWM3
3
PWROK
PHASE1
4
VID0/VFIXEN
VID1/SEL
VID2/SVD
5
32 UGATE1
49
GND
6
31
30
29
BOOT1
7
VID3/SVC
VID4
LGATE1
PVCCI_2
8
VID5
9
28 LGATE2
BOOT2
VCC
10
27
26 UGATE2
FS 11
RGND
PHASE2
25
12
13 14 15 16 17 18 19 20 21 22 23 24
Integrated Driver Block Diagram
PVCC
BOOT
UGATE
PHASE
PWM
20k
SHOOT-
THROUGH
PROTECTION
SOFT-START
AND
GATE
CONTROL
LOGIC
FAULT LOGIC
10k
LGATE
FN6880 Rev 1.00
May 14, 2010
Page 2 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Controller Block Diagram
FB_NB
COMP_NB
NB_OVP
SCL
SDA
CORE_OVP
DAC_OFS
2
I C
LGATE_NB
BOOT_NB
E/A
MOSFET
DRIVER
ISEN_NB+
ISEN_NB-
UV
LOGIC
OV
LOGIC
CURRENT
SENSE
NB_REF
UGATE_NB
PHASE_NB
RAMP
VDDPWRGD
APA
EN_12V
PVCC_NB
EN
APA
NB
FAULT
LOGIC
ENABLE
LOGIC
COMP
VCC
POWER-ON
RESET
VDDPWRGD_MOD
PVCC1_2
SOFT-START
AND
FB
FAULT LOGIC
E/A
DVC
2X
BOOT1
RGND
DROOP
UGATE1
CONTROL
MOSFET
DRIVER
LOAD APPLY
TRANSIENT
ENHANCEMENT
PHASE1
LGATE1
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
SVI
SLAVE
BUS
AND
PVI
CLOCK AND
TRIANGLE WAVE
GENERATOR
DAC_OFS
FS
DAC
VID5
PWM1
NB_REF
BOOT2
OV
LOGIC
PWM2
PWM3
PWM4
CORE_OVP
UGATE2
MOSFET
DRIVER
VSEN
RSET
PHASE2
LGATE2
UV
LOGIC
OC
RESISTOR
MATCHING
PH3/PH4
POR
CH1
I_TRIP I_AVG
ISEN1+
ISEN1-
EN_12V
CURRENT
SENSE
CHANNEL
DETECT
ISEN3-
ISEN4-
CH2
CURRENT
SENSE
ISEN2+
ISEN2-
CHANNEL
CURRENT
BALANCE
I_AVG
1
N
PWM3
SIGNAL
LOGIC
ISEN3+
ISEN3-
CH3
CURRENT
SENSE
PWM3
PWM4
ISEN3-
ISEN4+
ISEN4-
CH4
CURRENT
SENSE
PWM4
SIGNAL
LOGIC
ISEN4-
GND
FN6880 Rev 1.00
May 14, 2010
Page 3 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Typical Application - SVI Mode
+12V
+12V
FB
VSEN
COMP
ISEN3+
ISEN3-
PWM3
BOOT1
BOOT1
UGATE1
PHASE1
UGATE1
PHASE1
LGATE1
LGATE1
PGND
PWM1
APA
DVC
ISEN1-
ISEN1+
+5V
+12V
ISL6614
+12V
VDD
+12V
PVCC1_2
VCC
PVCC
VCC
BOOT2
BOOT2
UGATE2
GND
UGATE2
PHASE2
FS
CPU
LOAD
PHASE2
LGATE2
PWM2
LGATE2
RSET
VFIXEN
SEL
SVD
ISEN2-
ISEN2+
SVC
VID4
RGND
NC
NC
VID5
PWROK
ISEN4+
ISEN4-
VDDPWRGD
GND
SCL
SDA
PWM4
+12V
ISL6324A
+12V
PVCC_NB
EN
OFF
ON
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
VDDNB
NB
LOAD
ISEN_NB-
ISEN_NB+
COMP_NB
FB_NB
FN6880 Rev 1.00
May 14, 2010
Page 4 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Typical Application - PVI Mode
+12V
+12V
FB
VSEN
COMP
ISEN3+
ISEN3-
PWM3
BOOT1
UGATE1
PHASE1
BOOT1
UGATE1
PHASE1
LGATE1
LGATE1
PWM1
APA
DVC
PGND
ISEN1-
ISEN1+
+5V
+12V
ISL6614
+12V
VDD
+12V
PVCC1_2
VCC
PVCC
BOOT2
VCC
BOOT2
GND
UGATE2
UGATE2
PHASE2
FS
CPU
LOAD
PHASE2
LGATE2
PWM2
LGATE2
RSET
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC
PWROK
ISEN4+
ISEN4-
VDDPWRGD
GND
SCL
SDA
PWM4
ISL6324A
+12V
+12V
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
PVCC_NB
EN
OFF
ON
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
VDDNB
NB
LOAD
ISEN_NB-
ISEN_NB+
COMP_NB
FB_NB
FN6880 Rev 1.00
May 14, 2010
Page 5 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.2V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V
Thermal Resistance
(°C/W)
27
(°C/W)
2
JA
JC
QFN Package (Notes 1, 2) . . . . . . . . . .
Absolute Boot Voltage (V
Phase Voltage (V
). . . . . . . .GND - 0.3V to GND + 36V
). . . . . . . . GND - 0.3V to 15V (PVCC = 12)
PHASE
BOOT
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
GND - 8V (<400ns, 20µJ) to 24V (<200ns, V
= 12V)
+ 0.3V
+ 0.3V
BOOT-PHASE
Upper Gate Voltage (V
). . . . V
UGATE
- 0.3V to V
PHASE
BOOT
V
- 3.5V (<100ns Pulse Width, 2µJ) to V
PHASE
Lower Gate Voltage (V
BOOT
) . . . . . . . GND - 0.3V to PVCC + 0.3V
LGATE
Recommended Operating Conditions
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%
Ambient Temperature
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
ISL6324ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6324AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 4)
TYP
(Note 4) UNITS
BIAS SUPPLIES
Input Bias Supply Current
I
I
I
; EN = high
15
1
22
25
3
mA
mA
mA
V
VCC
Gate Drive Bias Current - PVCC1_2 Pin
Gate Drive Bias Current - PVCC_NB Pin
VCC POR (Power-On Reset) Threshold
; EN = high
1.8
PVCC1_2
; EN = high
0.3
0.9
2
PVCC_NB
VCC Rising
VCC Falling
PVCC Rising
PVCC Falling
4.20
3.70
4.20
3.70
4.35
3.85
4.35
3.85
4.50
4.05
4.50
4.05
V
PVCC POR (Power-On Reset) Threshold
V
V
PWM MODULATOR
Oscillator Frequency Accuracy, f
SW
R
= 100k (±0.1%) to Ground, (All Temps)
225
245
240
0.08
250
275
275
265
310
310
1.0
kHz
kHz
kHz
MHz
T
(Droop Enabled)
R
= 100k (±0.1%) to VCC, T = 0°C to +70°C
T
A
(Droop Disabled)
R = 100k (±0.1%) to VCC, T = -40°C to +85°C
T
A
(Droop Disabled)
Typical Adjustment Range of Switching
Frequency
(Note 3)
Oscillator Ramp Amplitude, V
Maximum Duty Cycle
CONTROL THRESHOLDS
EN Rising Threshold
EN Hysteresis
(Note 3)
(Note 3)
1.50
99.5
V
P-P
%
0.80
70
0.88
130
1.1
0.92
190
V
mV
V
PWROK Input HIGH Threshold
PWROK Input LOW Threshold
VDDPWRGD Sink Current
0.95
V
Open drain, V_VDDPWRGD = 400mV
, V
4
mA
V
PWM Channel Disable Threshold
REFERENCE AND DAC
V
V
4.4
ISEN3- ISEN4-, ISEN2-
System Accuracy (VDAC > 1.000V)
-0.6
0.6
%
FN6880 Rev 1.00
May 14, 2010
Page 6 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.
MIN
MAX
PARAMETER
System Accuracy (0.600V < VDAC < 1.000V)
System Accuracy (VDAC < 0.600V)
DVC Voltage Gain
TEST CONDITIONS
(Note 4)
TYP
(Note 4) UNITS
-1.0
1.0
2.0
%
%
V
-2.0
VDAC = 1V
= 1V
2.0
APA Current Tolerance
V
90
100
108
µA
APA
ERROR AMPLIFIER
DC Gain
R = 10k to ground, (Note 3)
96
20
dB
MHz
V/µs
V
L
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
C = 100pF, R = 10k to ground, (Note 3)
L L
C = 100pF, Load = ±400µA, (Note 3)
L
8
Maximum Output Voltage
Minimum Output Voltage
Load = 1mA
Load = -1mA
3.80
2.2
4.20
1.3
1.6
4.0
0.5
V
SOFT-START RAMP
Soft-Start Ramp Rate
3.0
mV/µs
PWM OUTPUTS
PWM Output Voltage LOW Threshold
PWM Output Voltage HIGH Threshold
CURRENT SENSING - CORE CONTROLLER
Sensed Current Tolerance
I
I
= ±500µA
= ±500µA
V
V
LOAD
LOAD
4.5
68
V
- V
= 23.2mV, R
= 37.6k,
88
89
µA
µA
µA
ISENn-
ISENn+
SET
4 Phases, T = +25°C
A
CURRENT SENSING - NB CONTROLLER
Sensed Current Tolerance
V
R
- V
= 23.2mV,
ISEN_NB+
68
68
87
ISEN_NB-
= 37.6k, 4 Phases, T = +25°C
SET
A
DROOP CURRENT
Tolerance
V
- V
= 23.2mV, R
ISENn+ SET
= 37.6k,
88
ISENn-
4 Phases, T = +25°C
A
OVERCURRENT PROTECTION
Overcurrent Trip Level - Average Channel
Normal Operation, R
= 28.2k
100
130
142
190
120
µA
µA
µA
µA
SET
Dynamic VID Change (Note 3)
Normal Operation, R = 28.2k
Overcurrent Limiting- Individual Channel
SET
Dynamic VID Change (Note 3)
POWER-GOOD
Core Overvoltage Threshold
VSEN Rising
Bit 6 of I C data = 0
VDAC +
225mV
VDAC + VDAC +
V
2
250mV
275mV
Undervoltage Threshold
VSEN Falling (Core)
Bit 6 of I C data = 0
VDAC -
325mV
VDAC -
300mV
VDAC -
270mV
mV
mV
mV
2
ISEN_NB+ Falling (North Bridge)
VDAC -
310mV
VDAC -
275mV
VDAC -
235mV
2
Bit 6 of I C data = 0
Power Good Hysteresis
50
OVERVOLTAGE PROTECTION
OVP Trip Level
2
Bit 7 of I C data = 0, VDAC 1.55V
1.73
350
1.80
400
1.84
V
OVP Lower Gate Release Threshold
mV
SWITCHING TIME (Note 3) [See “Timing Diagram” on page 8]
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
t
t
V
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
26
18
18
12
ns
ns
ns
ns
RUGATE; PVCC
V
RLGATE; PVCC
t
V
FUGATE; PVCC
t
V
FLGATE; PVCC
FN6880 Rev 1.00
May 14, 2010
Page 7 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.
MIN
MAX
PARAMETER
UGATE Turn-On Non-overlap
LGATE Turn-On Non-overlap
GATE DRIVE RESISTANCE (Note 3)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
MODE SELECTION
TEST CONDITIONS
(Note 4)
TYP
10
(Note 4) UNITS
t
; V
PDHUGATE PVCC
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
ns
ns
t
; V
PDHLGATE PVCC
10
V
V
V
V
= 12V, 15mA Source Current
2.0
PVCC
PVCC
PVCC
PVCC
= 12V, 15mA Sink Current
= 12V, 15mA Source Current
= 12V, 15mA Sink Current
1.65
1.25
0.80
VID1/SEL Input Low
EN taken from HI to LO, VDDIO = 1.5V
EN taken from LO to HI, VDDIO = 1.5V
0.6
V
V
VID1/SEL Input High
1.00
1.00
PVI INTERFACE
VIDx Pull-down
VDDIO = 1.5V
VDDIO = 1.5V
VDDIO = 1.5V
30
40
µA
V
VIDx Input Low
0.6
VIDx Input High
V
SVI INTERFACE
SVC, SVD Input LOW (VIL)
SVC, SVD Input HIGH (VIH)
Schmitt Trigger Input Hysteresis
SVD Low Level Output Voltage
Maximum SVC, SVD Leakage (Note 3)
0.4
V
V
0.95
0.14
0.35
±5
0.45
V
3mA Sink Current
0.285
V
µA
2
I C INTERFACE
SCL, SDA Input LOW (VIL)
SCL, SDA Input HIGH (VIH)
Schmitt Trigger Input Hysteresis
SDA Low Level Output Voltage
Maximum SCL, SDA Leakage (Note 3)
NOTES:
1.10
V
V
1.75
0.18
0.35
±5
0.50
0.2
V
3mA Sink Current
V
µA
3. Limits should be considered typical and are not production tested.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
t
PDHUGATE
t
t
RUGATE
FUGATE
UGATE
LGATE
t
t
FLGATE
RLGATE
t
PDHLGATE
FN6880 Rev 1.00
May 14, 2010
Page 8 of 39
2
ISL6324A Hybrid SVI/PVI with I C
depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0µF ceramic capacitor.
Functional Pin Description
VID1/SEL
PVCC_NB
This pin selects SVI or PVI mode operation based on the state
of the pin prior to enabling the ISL6324A. If the pin is LO prior
to enable, the ISL6324A is in SVI mode and the dual purpose
pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI
mode related functions. If the pin held HI prior to enable, the
ISL6324A is in PVI mode and dual purpose pins use their
VIDx related functions to decode the correct DAC code.
The power supply pin for the internal MOSFET driver for the
Northbridge controller. Connect this pin to any voltage from
+5V to +12V depending on the desired MOSFET gate-drive
level. Decouple this pin with a quality 1.0µF ceramic capacitor.
GND
GND is the bias and reference ground for the IC. The GND
connection for the ISL6324A is through the thermal pad on
the bottom of the package.
VID0/VFIXEN
If VID1 is LO prior to enable [SVI Mode], the pin is functions
as the VFIXEN selection input from the AMD processor for
determining SVI mode versus VFIX mode of operation.
If VID1 is HI prior to enable [PVI Mode], the pin is used as
DAC input VID0. This pin has an internal 30µA pull-down
current applied to it at all times.
EN
This pin is a threshold-sensitive (approximately 0.85V) system
enable input for the controller. Held low, this pin disables both
CORE and NB controller operation. Pulled high, the pin
enables both controllers for operation.
VID2/SVD
When the EN pin is pulled high, the ISL6324A will be placed
in either SVI or PVI mode. The mode is determined by the
latched value of VID1 on the rising edge of the EN signal.
If VID1 is LO prior to enable [SVI Mode], this pin is the serial
VID data bi-directional signal to and from the master device on
AMD processor. If VID1 is HI prior to enable [PVI Mode], this
pin is used to decode the programmed DAC code for the
processor. In PVI mode, this pin has an internal 30µA pull-down
current applied to it. There is no pull-down current in SVI mode.
A third function of this pin is to provide driver bias monitor for
external drivers. A resistor divider with the center tap
connected to this pin from the drive bias supply prevents
enabling the controller before insufficient bias is provided to
external driver. The resistors should be selected such that
when the POR-trip point of the external driver is reached, the
voltage at this pin meets the above mentioned threshold level.
VID3/SVC
If VID1 is LO prior to enable [SVI Mode], this pin is the serial
VID clock input from the AMD processor. If VID1 is HI prior to
enable [PVI Mode], the ISL6324A is in PVI mode and this pin
is used to decode the programmed DAC code for the
processor. In PVI mode, this pin has an internal 30µA
pull-down current applied to it. There is no pull-down current in
SVI mode.
FS
A resistor, placed from FS to Ground or from FS to VCC,
sets the switching frequency of both controllers. Refer to
Equation 1 for proper resistor calculation.
10.61 – 1.035logf
s
VID4
(EQ. 1)
R
= 10
T
This pin is active only when the ISL6324A is in PVI mode.
When VID1 is HI prior to enable, the ISL6324A decodes the
programmed DAC voltage required by the AMD processor.
This pin has an internal 30µA pull-down current applied to it at
all times.
With the resistor tied from FS to Ground, Droop is enabled.
With the resistor tied from FS to VCC, Droop is disabled.
VSEN and RGND
VSEN and RGND are inputs to the core voltage regulator
(VR) controller precision differential remote-sense amplifier
and should be connected to the sense pins of the remote
processor core(s), VDDFB[H,L].
VID5
This pin is active only when the ISL6324A is in PVI mode.
When VID1 is HI prior to enable, the ISL6324A decodes the
programmed DAC voltage required by the AMD processor.
This pin has an internal 30µA pull-down current applied to it at
all times.
FB and COMP
These pins are the internal error amplifier inverting input and
output respectively of the core VR controller. FB, VSEN and
COMP are tied together through external R-C networks to
compensate the regulator.
VCC
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1µF ceramic capacitor.
APA
Adaptive Phase Alignment (APA) pin for setting trip level and
adjusting time constant. A 100µA current flows into the APA
pin and by tying a resistor from this pin to COMP the trip
level for the Adaptive Phase Alignment circuitry can be set.
PVCC1_2
The power supply pin for the multi-phase internal MOSFET
drivers. Connect this pin to any voltage from +5V to +12V
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4-, and ISEN4+
DVC
The DVC pin is a buffered version of the reference to the error
amplifier. A series resistor and capacitor between the DVC pin
and FB pin smooth the voltage transition during VID-on-the-fly
operations.
These pins are used for differentially sensing the corresponding
channel output currents. The sensed currents are used for
channel balancing, protection, and core load line regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
between the RC sense elements surrounding the inductor of
their respective channel. Tie the ISEN+ pins to the VCORE
side of their corresponding channel’s sense capacitor.
FB_NB and COMP_NB
These pins are the internal error amplifier inverting input and
output respectively of the NB VR controller. FB_NB,
VDIFF_NB, and COMP_NB are tied together through
external R-C networks to compensate the regulator.
UGATE1 and UGATE2
Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
ISEN_NB-, ISEN_NB+
These pins are used for differentially sensing the North
Bridge output current. The sensed current is used for
protection and load line regulation if droop is enabled.
BOOT1 and BOOT2
Connect ISEN_NB- to the node between the RC sense
element surrounding the inductor. Tie the ISEN_NB+ pin to
the VNB side of the sense capacitor.
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to appropriately
chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC1_2 pin provide the
necessary bootstrap charge.
UGATE_NB
Connect this pin to the corresponding upper MOSFET gate.
This pin provides the PWM-controlled gate drive for the
upper MOSFET and is monitored for shoot-through
prevention purposes.
PHASE1 and PHASE2
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
BOOT_NB
This pin provides the bias voltage for the corresponding
upper MOSFET drive. Connect this pin to appropriately
chosen external bootstrap capacitor. The internal bootstrap
diode connected to the PVCC_NB pin provides the
necessary bootstrap charge.
LGATE1 and LGATE2
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
PWM3 and PWM4
PHASE_NB
Pulse-width modulation outputs. Connect these pins to the
PWM input pins of an Intersil driver IC if 3- or 4-phase
operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core
VR controller for 2-phase or 3-phase operation.
Connect this pin to the source of the corresponding upper
MOSFET. This pin is the return path for the upper MOSFET
drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
LGATE_NB
PWROK
Connect this pin to the corresponding MOSFET’s gate. This
pin provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
System wide Power Good signal. If this pin is low, the two
SVI bits are decoded to determine the “metal VID”. When the
pin is high, the SVI is actively running its protocol.
RSET
Connect this pin to the VCC pin through a resistor (R
set the effective value of the internal R
ISEN
) to
current sense
SET
SCL
2
Connect this pin to the clock signal for the I C bus, which is
resistors. The values of the R
than 20k and no more than 80k. A 0.1µF capacitor
should be placed in parallel to the R
resistor should be no less
SET
a logic level input signal. The clock signal tells the controller
2
when data is available on the I C bus.
resistor.
SET
SDA
VDDPWRGD
2
Connect this pin to the bidirectional data line of the I C bus,
which is a logic level input/output signal. All I C data is sent
over this line, including the address of the device the bus is
trying to communicate with, and what functions the device
should perform.
During normal operation this pin indicates whether both output
voltages are within specified overvoltage and undervoltage
limits. If either output voltage exceeds these limits or a reset
event occurs (such as an overcurrent event), the pin is pulled
low. This pin is always low prior to the end of soft-start.
2
FN6880 Rev 1.00
May 14, 2010
Page 10 of 39
2
ISL6324A Hybrid SVI/PVI with I C
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 2 to the expression
for the peak-to-peak current after the summation of N
symmetrically phase-shifted inductor currents in Equation 3.
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output voltage ripple is
a function of capacitance, capacitor equivalent series
resistance (ESR), and inductor ripple current. Reducing the
inductor ripple current allows the designer to use fewer or less
costly output capacitors.
Operation
The ISL6324A utilizes a multi-phase architecture to provide a
low cost, space saving power conversion solution for the
processor core voltage. The controller also implements a
simple single phase architecture to provide the Northbridge
voltage on the same chip.
Multi-phase Power Conversion
Microprocessor load current profiles have changed to the point
that the advantages of multi-phase power conversion are
impossible to ignore. The technical challenges associated with
producing a single-phase converter that is both cost-effective
and thermally viable have forced a change to the cost-saving
approach of multi-phase. The ISL6324A controller helps
simplify implementation by integrating vital functions and
requiring minimal external components. The “Controller Block
Diagram” on page 3 provides a top level view of the multi-
phase power conversion using the ISL6324A controller.
V – N V
V
OUT
IN
OUT
(EQ. 3)
I
= -----------------------------------------------------------
CP – P
Lf
V
S
IN
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multi-phase topologies can improve overall
system cost and size by lowering input ripple current and
allowing the designer to reduce the cost of input capacitance.
The example in Figure 2 illustrates input currents from a three-
phase converter combining to reduce the total input ripple
current.
Interleaving
The switching of each channel in a multi-phase converter is timed
to be symmetrically out-of-phase with each of the other channels.
In a 3-phase converter, each channel switches 1/3 cycle after the
previous channel and 1/3 cycle before the following channel. As a
result, the three-phase converter has a combined ripple frequency
three times greater than the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined inductor
currents is reduced in proportion to the number of phases
(Equations 2 and 3). Increased ripple frequency and lower ripple
amplitude mean that the designer can use less per-channel
inductance and lower total output capacitance for any
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS
input capacitor current. The single-phase converter must use an
input capacitor bank with twice the RMS current capacity as the
equivalent three-phase converter.
performance specification.
Figures 26, 27 and 28 in the section entitled “Input Capacitor
Selection” on page 35 can be used to determine the input
capacitor RMS current based on load current, duty cycle, and
the number of channels. They are provided as aids in
determining the optimal input capacitor solution.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3)
combine to form the AC ripple current and the DC load current.
The ripple component has three times the ripple frequency of
each individual channel current. Each PWM pulse is terminated
1/3 of a cycle after the PWM pulse of the previous phase. The
peak-to-peak current for each phase is about 7A, and the DC
components of the inductor currents combine to feed the load.
IL1 + IL2 + IL3, 7A/DIV
IL3, 7A/DIV
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 2, which represents an
individual channel peak-to-peak inductor current.
PWM3, 5V/DIV
IL2, 7A/DIV
V – V
V
OUT
IN
OUT
(EQ. 2)
I
= -----------------------------------------------------
P – P
Lf
V
S
PWM2, 5V/DIV
IN
In Equation 2, V and V
IN
are the input and output voltages
OUT
IL1, 7A/DIV
respectively, L is the single-channel inductor value, and f is
S
the switching frequency.
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
FN6880 Rev 1.00
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2
ISL6324A Hybrid SVI/PVI with I C
To further improve the transient response, ISL6324A also
implements Intersil’s proprietary Adaptive Phase Alignment (APA)
technique, which turns on all phases together under transient
events with large step current. With both APP and APA control,
ISL6324A can achieve excellent transient performance and
reduce the demand on the output capacitors.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
Adaptive Phase Alignment (APA)
To further improve the transient response, the ISL6324A also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all of the channels together at
the same time during large current step transient events. As
Figure 3 shows, the APA circuitry works by monitoring the
voltage on the APA pin and comparing it to a filtered copy of
the voltage on the COMP pin. The voltage on the APA pin is a
copy of the COMP pin voltage that has been negatively offset.
If the APA pin exceeds the filtered COMP pin voltage an APA
event occurs and all of the channels are forced on.
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1s/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
Active Pulse Positioning Modulated PWM Operation
ISL6324A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
APA
The ISL6324A uses a proprietary Active Pulse Positioning (APP)
modulation scheme to control the internal PWM signals that
command each channel’s driver to turn their upper and lower
MOSFETs on and off. The time interval in which a PWM signal
can occur is generated by an internal clock, whose cycle time is
the inverse of the switching frequency set by the resistor between
the FS pin and ground. The advantage of Intersil’s proprietary
Active Pulse Positioning (APP) modulator is that the PWM signal
has the ability to turn on at any point during this PWM time
interval, and turn off immediately after the PWM signal has
transitioned high. This is important because it allows the controller
to quickly respond to output voltage drops associated with current
load spikes, while avoiding the ring back affects associated with
other modulation schemes.
-
+
APA
100µA
C
R
APA
APA
V
APA,TRIP
-
TO APA
CIRCUITRY
LOW
PASS
FILTER
COMP
ERROR
AMPLIFIER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion that
the APA and COMP pins must have during a transient event to
activate the Adaptive Phase Alignment circuitry. This APA trip
The PWM output state is driven by the position of the error
amplifier output signal, V
, minus the current correction
COMP
signal relative to the proprietary modulator ramp waveform as
illustrated in Figure 3. At the beginning of each PWM time
level is set through a resistor, R
, that connects from the
APA
interval, this modified V
modulator waveform. As long as the modified V
COMP
signal is compared to the internal
voltage is
COMP
APA pin to the COMP pin. A 100µA current flows across R
into the APA pin to set the APA trip level as described in
APA
lower then the modulator waveform voltage, the PWM signal is
commanded low. The internal MOSFET driver detects the low
state of the PWM signal and turns off the upper MOSFET and
turns on the lower synchronous MOSFET. When the modified
Equation 4. An APA trip level of 500mV is recommended for
most applications. A 0.1µF capacitor, C , should also be
APA
placed across the R
resistor to help with noise immunity.
APA
–6
(EQ. 4)
V
= R
100 10
APA
V
voltage crosses the modulator ramp, the PWM output
APA TRIP
COMP
transitions high, turning off the synchronous MOSFET and
turning on the upper MOSFET. The PWM signal will remain high
PWM Operation
until the modified V
again. When this occurs the PWM signal will transition low
again.
voltage crosses the modulator ramp
The timing of each core channel is set by the number of active
channels. Channel detection on the ISEN2-, ISEN3- and
ISEN4- pins selects 1-Channel to 4-Channel operation for the
ISL6323A. The switching cycle is defined as the time between
PWM pulse termination signals of each channel. The cycle
time of the pulse signal is the inverse of the switching
COMP
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM time
interval. This prevents the occurrence of double PWM pulses
occurring during a single period.
frequency set by the resistor between the FS pin and ground.
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
The PWM signals command the MOSFET driver to turn on/off
the channel MOSFETs.
A simple R-C network across the inductor (R , R and C)
1 2
extracts the DCR voltage, as shown in Figure 6. The voltage
across the sense capacitor, V , can be shown to be
C
For 4-channel operation, the channel firing order is 1-2-3-4:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and PWM1
delays another 1/4 of a cycle after PWM2. For 3-channel
operation, the channel firing order is 1-2-3.
proportional to the channel current I , shown in Equation 6.
Ln
s L
-------------
+ 1
(EQ. 6)
(EQ. 7)
DCR
-------------------------------------------------------
V
s =
K DCR I
C
L
n
R R
1
2
-----------------------
s
C + 1
Connecting ISEN4- to VCC selects three channel operation
and the pulse times are spaced in 1/3 cycle increments. If
ISEN3- is also connected to VCC, 2-Channel operation is
selected and the PWM2 pulse happens 1/2 of a cycle after
PWM1 pulse. If ISEN2- is also connected to VCC, 1-Channel
operation is selected.
R
+ R
2
1
Where:
R
2
--------------------
K =
R
+ R
1
2
I
V
IN
L
Continuous Current Sampling
n
UGATE(n)
LGATE(n)
In order to realize proper current-balance, the currents in each
channel are sampled continuously every switching cycle.
During this time, the current-sense amplifier uses the ISEN
inputs to reproduce a signal proportional to the inductor
L
DCR
V
OUT
MOSFET
DRIVER
INDUCTOR
-
C
OUT
V (s)
L
current, I . This sensed current, I
version of the inductor current.
, is simply a scaled
-
L
SEN
V
(s)
C
C
R
1
R
2
ISL6323 INTERNAL CIRCUIT
I
n
PWM
SWITCHING PERIOD
SAMPLE
I
L
+
-
ISENn-
-
V
(s)
C
ISENn+
VCC
R
ISEN
I
I
SEN
SEN
RSET
R
SET
TIME
C
SET
FIGURE 4. CONTINUOUS CURRENT SAMPLING
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
The ISL6324A supports Inductor DCR current sensing to
continuously sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 6 represents
Channel N of an N-Channel converter. This circuitry is repeated
for each channel in the converter, but may not be active
depending on how many channels are operating.
If the R-C network components are selected such that the RC
time constant matches the inductor L/DCR time constant (see
Equation 8), then V is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
C
R
R
2
L
1
-------------
--------------------
C
Inductor windings have a characteristic distributed resistance
or DCR (Direct Current Resistance). For simplicity, the inductor
DCR is considered as a separate lumped quantity, as shown in
=
(EQ. 8)
DCR
R + R
1 2
The capacitor voltage V , is then replicated across the effective
internal sense resistor, R
C
Figure 6. The channel current I , flowing through the inductor,
Ln
. This develops a current through
ISEN
passes through the DCR. Equation 5 shows the S-domain
equivalent voltage, V , across the inductor.
L
R
which is proportional to the inductor current. This
, is continuously sensed and is then used by the
SEN
ISEN
current, I
(EQ. 5)
V s = I s L + DCR
controller for load-line regulation, channel-current balancing,
and overcurrent detection and limiting. Equation 9 shows that
L
L
n
the proportion between the channel current, I , and the sensed
L
FN6880 Rev 1.00
May 14, 2010
Page 13 of 39
2
ISL6324A Hybrid SVI/PVI with I C
.
current, I
resistance, R
, is driven by the value of the effective sense
SEN
+
, and the DCR of the inductor.
PWM1
V
ISEN
COMP
TO GATE
CONTROL
LOGIC
+
-
DCR
MODULATOR
RAMP
WAVEFORM
-
(EQ. 9)
-----------------
I
= I
SEN
L
R
ISEN
FILTER f(s)
The effective internal R
resistance is important to the
ISEN
I
I
4
3
2
I
ER
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the gain
of the channel-current balance loop and the overcurrent trip
I
AVG
N
-
+
I
level. The effective internal R
resistance is user
ISEN
programmable and is set through use of the RSET pin. Placing
a single resistor, R , from the RSET pin to the VCC pin
I
1
SET
NOTE: Channel 3 and 4 are optional.
programs the effective internal R
resistance according to
ISEN
Equation 10.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
3
---------
R
=
R
ISEN
SET
(EQ. 10)
400
VID Interface
The ISL6324A supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
pin is used to command the ISL6324A into either the PVI mode
or the SVI mode. Whenever the EN pin is held LOW, both the
multi-phase Core and single-phase North Bridge Regulators
are disabled and the ISL6324A is continuously sampling
voltage on the VID1/SEL pin. When the EN pin is toggled
HIGH, the status of the VID1/SEL pin will latch the ISL6324A
into either PVI or SVI mode. This latching occurs on the rising
edge of the EN signal.If the VID1/SEL pin is held LOW during
the latch, the ISL6324A will be placed into SVI mode. If the
VID1/SEL pin is held HIGH during the latch, the ISL6324A will
be placed into PVI mode. For the ISL6324A to properly enter
into either mode, the level on the VID1/SEL pin must be stable
no less that 1µs prior to the EN signal transitioning from low to
high.
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R resistor
SET
resistors to the
will program all the effective internal R
same value.
ISEN
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to carry
about the same amount of current at any load level. To achieve
this, the currents through each channel must be sampled every
switching cycle. The sampled currents, I , from each active
n
channel are summed together and divided by the number of
6-bit Parallel VID Interface (PVI)
active channels. The resulting cycle average current, I
,
AVG
With the ISL6324A in PVI mode, the single-phase North Bridge
regulator is disabled. Only the multi-phase controller is active
in PVI mode to support uniplane VDD only processors. Table 1
shows the 6-bit parallel VID codes and the corresponding
reference voltage.
provides a measure of the total load current demand on the
converter during each switching cycle. Channel-current
balance is achieved by comparing the sampled current of each
channel to the cycle average current, and making the proper
adjustment to each channel pulse width based on the error.
Intersil’s patented current balance method is illustrated in
Figure 6, with error correction for Channel 1 represented. In
TABLE 1. 6-BIT PARALLEL VID CODES
VID5
VID4
VID3
VID2
VID1
VID0
VREF
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
the figure, the cycle average current, I
, is compared with
the Channel 1 sample, I , to create an error signal I
AVG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
.
1
ER
The filtered error signal modifies the pulse width commanded
by V to correct any unbalance and force I toward zero.
COMP ER
The same method for error signal correction is applied to each
active channel.
FN6880 Rev 1.00
May 14, 2010
Page 14 of 39
2
ISL6324A Hybrid SVI/PVI with I C
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VREF
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
VID5
VID4
VID3
VID2
VID1
VID0
VREF
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6324A. The SVC and SVD
states are decoded with direction from the PWROK and VFIXEN
inputs as described in the following sections. The ISL6324A uses
a digital to analog converter (DAC) to generate a reference
voltage based on the decoded SVI value. See Figure 7 for a
simple SVI interface timing diagram.
FN6880 Rev 1.00
May 14, 2010
Page 15 of 39
2
ISL6324A Hybrid SVI/PVI with I C
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
VDD AND VDDNB
VDDPWRGD
V_SVI
V_SVI
METAL_VID
METAL_VID
VFIXEN
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
PRE-PWROK METAL VID
zero. The VDDPWRGD de-asserts with the loss of enable. The
VDD and VDDNB planes will linearly decrease to near zero.
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the POR
circuitry is satisfied, the ISL6324A begins decoding the inputs
per Table 2. Once the EN input exceeds the rising enable
threshold, the ISL6324A saves the Pre-PWROK metal VID
value in an on-board holding register and passes this target to
the internal DAC circuitry.
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
ISL6324A is designed to support the potential change of state
of these inputs. If VFIXEN is high, the IC decodes the SVC and
SVD states per Table 3.
TABLE 2. PRE-PWROK METAL VID CODES
Once enabled, the ISL6324A begins to soft-start both VDD and
VDDNB planes to the programmed VFIX level. The internal
soft-start circuitry slowly stair steps the reference up to the
target value and this results in a controlled ramp of the power
planes. Once soft-start has ended and both output planes are
within regulation limits, the VDDPWRGD pin transitions high. If
the EN input falls below the enable falling threshold, then the
controller ramps both VDD and VDDNB down to near zero.
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1
1
0
1
0
1
1.1
1.0
0.9
0.8
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
ISL6324A passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded
Pre-PWROK metal VID output level. The digital soft-start
circuitry actually stair steps the internal reference to the target
gradually over a fix interval. The controlled ramp of both output
voltage planes reduces in-rush current during the soft-start
interval. At the end of the soft-start interval, the VDDPWRGD
output transitions high indicating both output planes are within
regulation limits.
TABLE 3. VFIXEN VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1
1
0
1
0
1
1.4
1.2
1.0
0.8
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6324A to prepare for SVI
commands. The controller actively monitors the SVI interface
for set VID commands to move the plane voltages to start-up
VID values. Details of the SVI Bus protocol are provided in the
If the EN input falls below the enable falling threshold, the
ISL6324A ramps the internal reference voltage down to near
FN6880 Rev 1.00
May 14, 2010
Page 16 of 39
2
ISL6324A Hybrid SVI/PVI with I C
AMD Design Guide for Voltage Regulator Controllers
Accepting Serial VID Codes specification.
If the PWROK input is de-asserted, then the controller steps
both VDD and VDDNB planes back to the stored Pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this
time. If PWROK is reasserted, then the on-board SVI interface
waits for a set VID command.
Once the set VID command is received, the ISL6324A
decodes the information to determine which plane and the VID
target required. See Table 4. The internal DAC circuitry steps
the required output plane voltage to the new VID level. During
this time one or both of the planes could be targeted. In the
event the core voltage plane, VDD, is commanded to power off
by serial VID commands, the VDDPWRGD signal remains
asserted. The Northbridge voltage plane must remain active
during this time.
If VDDPWRGD deasserts during normal operation, both
voltage planes are powered down in a controlled fashion. The
internal DAC circuitry stair steps both outputs down to near
zero.
TABLE 4. SERIAL VID CODES
VOLTAGE (V) SVID[6:0]
1.1500 100_0000b
SVID[6:0]
000_0000b
000_0001b
000_0010b
000_0011b
000_0100b
000_0101b
000_0110b
000_0111b
000_1000b
000_1001b
000_1010b
000_1011b
000_1100b
000_1101b
000_1110b
000_1111b
001_0000b
001_0001b
001_0010b
001_0011b
001_0100b
001_0101b
001_0110b
001_0111b
001_1000b
001_1001b
001_1010b
001_1011b
001_1100b
001_1101b
001_1110b
001_1111b
VOLTAGE (V)
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
SVID[6:0]
010_0000b
010_0001b
010_0010b
010_0011b
010_0100b
010_0101b
010_0110b
010_0111b
010_1000b
010_1001b
010_1010b
010_1011b
010_1100b
010_1101b
010_1110b
010_1111b
011_0000b
011_0001b
011_0010b
011_0011b
011_0100b
011_0101b
011_0110b
011_0111b
011_1000b
011_1001b
011_1010b
011_1011b
011_1100b
011_1101b
011_1110b
011_1111b
VOLTAGE (V)
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875*
0.4750*
0.4625*
0.4500*
0.4375*
0.4250*
0.4125*
0.4000*
0.3875*
0.3750*
0.3625*
SVID[6:0]
110_0000b
110_0001b
110_0010b
110_0011b
110_0100b
110_0101b
110_0110b
110_0111b
110_1000b
110_1001b
110_1010b
110_1011b
110_1100b
110_1101b
110_1110b
110_1111b
111_0000b
111_0001b
111_0010b
111_0011b
111_0100b
111_0101b
111_0110b
111_0111b
111_1000b
111_1001b
111_1010b
111_1011b
111_1100b
111_1101b
111_1110b
111_1111b
VOLTAGE (V)
0.3500*
0.3375*
0.3250*
0.3125*
0.3000*
0.2875*
0.2750*
0.2625*
0.2500*
0.2375*
0.2250*
0.2125*
0.2000*
0.1875*
0.1750*
0.1625*
0.1500*
0.1375*
0.1250*
0.1125*
0.1000*
0.0875*
0.0750*
0.0625*
0.0500*
0.0375*
0.0250*
0.0125*
OFF
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
100_0001b
100_0010b
100_0011b
100_0100b
100_0101b
100_0110b
100_0111b
100_1000b
100_1001b
100_1010b
100_1011b
100_1100b
100_1101b
100_1110b
100_1111b
101_0000b
101_0001b
101_0010b
101_0011b
101_0100b
101_0101b
101_0110b
101_0111b
101_1000b
101_1001b
101_1010b
101_1011b
101_1100b
101_1101b
101_1110b
101_1111b
OFF
OFF
OFF
NOTE: * Indicates a VID not required for AMD Family 10h processors.
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
POWER SAVINGS MODE: PSI_L
Voltage Regulation
Bit 7 of the Serial VID code transmitted as part of the 8-bit data
phase over the SVI bus is allocated for the PSI_L. If Bit 7 is 0,
then the processor is at an optimal load for the regulator to
enter power savings mode. If Bit 7 is 1, then the regulator
should not be in power savings mode.
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage, remote-sense
and error amplifiers. Intersil specifies the guaranteed tolerance
of the ISL6324A to include the combined tolerances of each of
these elements.
With the ISL6324A, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set to
0 is received, the ISL6324A will shed phases in a sequential
manner. The default number of phases that the ISL6324A will
run on in Power Savings Mode is two. This number is
The output of the error amplifier, V
, is used by the
COMP
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and regulate
the converter output so that the voltage at FB is equal to the
voltage at REF. This will regulate the output voltage to be equal
to Equation 11. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 8.
2
programmable through the I C interface and can be set to
three phases or to one phase (See “I2C Bus Interface” on
page 23). Phases are shed decrementally, starting with
Channel 4. When a phase is shed, that phase will not go into a
tri-state mode until that phase would have had its PWM go
HIGH.
(EQ. 11)
V
= V
– V
REF DROOP
OUT
The ISL6324A incorporates differential remote-sense
After a phase is shed, the ISL6324A will wait, by default, 1 full
PWM cycle before shedding the next phase. This delay can be
changed to 0, 2 or 4 PWM cycle delays through the I C
interface (See “I2C Bus Interface” on page 23). It should be
noted that with a 0 cycle delay, all phases that are to be shed
will be turned off at the same time. While the option to shed all
phases at once is available, it is not recommended as the Core
voltage could be subjected to large output deviations during
the transition.
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
2
EXTERNAL CIRCUIT
FS
ISL6324A INTERNAL CIRCUIT
TO
R
DROOP
FS
OSCILLATOR
CONTROL
When leaving Power Savings Mode, through the reception of a
Serial VID command with Bit 7 set to 1, the ISL6324A will
sequentially turn on phases starting with the lowest numbered
phase that has been shed. When a phase is being reactivated,
it will not leave a tri-state until the PWM of that phase goes
HIGH.
COMP
C
C
I
AVG
R
C
FB
After a phase is reactivated, the ISL6324A will wait, by default,
1 full PWM cycle before reactivating the next phase. This delay
can be changed to 0, 2 or 4 PWM cycle delays through the I C
-
V
COMP
+
2
ERROR
AMPLIFIER
interface (See “I2C Bus Interface” on page 23). It should be
noted that with a 0 cycle delay, all phases that have been shed
will be turned on at the same time. While the option to
reactivate all phases at once is available, it is not
recommended as the Core voltage could be subjected to large
output deviations during the transition.
+
V
-
R
FB
DROOP
+
VID
DAC
VSEN
RGND
+
+
V
OUT
-
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining Bit 7
at 0, the ISL632A will first exit the Power Savings Mode state
as previously described. The output voltage will then be
stepped up or down to the appropriate VID level. Finally, the
ISL6324A will then re-enter Power Savings Mode.
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
If the Core regulator has had an offset voltage added to the
2
DAC through the I C interface, this offset will, by default,
2
remain while in Power Savings Mode. Through the I C
interface, the offset can be disabled while in Power Savings
Mode (See “I2C Bus Interface” on page 23).
FN6880 Rev 1.00
May 14, 2010
Page 18 of 39
2
ISL6324A Hybrid SVI/PVI with I C
The magnitude of the spike is dictated by the ESR and ESL of
the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the output
voltage under load can effectively be level shifted down so that
a larger positive spike can be sustained without crossing the
upper specification limit.
I
= I
C
DVC
R
FB
VSEN
I
C
I
DVC
R
C
C
C
C
R
DVC
DVC
DVC
FB
COMP
-
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I
through a load-line regulation resistor R . The resulting
, flows from FB
+
AVG
ERROR
AMPLIFIER
FB
voltage drop across R is proportional to the output current,
FB
effectively creating an output voltage droop with a steady-state
VDAC+RGND
ISL6324A INTERNAL CIRCUIT
value defined as in Equation 12:
FIGURE 9. DYNAMIC VID COMPENSATION NETWORK
V
= I
R
AVG FB
(EQ. 12)
DROOP
during a VID change, a VID-on-the-fly compensation network
is required. This network is composed of a resistor and
The regulated output voltage is reduced by the droop voltage
capacitor in series, R
the FB pin.
and C , between the DVC and
DVC
DVC
V
. The output voltage as a function of load current is
DROOP
shown in Equation 13.
This VID-on-the-fly compensation network works by sourcing
AC current into the FB node to offset the effects of the AC
current flowing from the FB to the COMP pin during a VID
transition. To create this compensation current the ISL6324A
sets the voltage on the DVC pin to be 2x the voltage on the
REF pin. Since the error amplifier forces the voltage on the FB
pin and the REF pin to be equal, the resulting voltage across
the series RC between DVC and FB is equal to the REF pin
I
400
3
1
OUT
N
-------------
--------- --------------
V
= V
–
DCR
K R
FB
OUT
REF
R
SET
(EQ. 13)
In Equation 13, V
is the reference voltage, I
is the total
OUT
REF
output current of the converter, K is the DC gain of the RC filter
across the inductor (K is defined in Equation 7), N is the
number of active channels, and DCR is the Inductor DCR
value.
voltage. The RC compensation components, R
and C ,
DVC
DVC
can then be selected to create the desired amount of
Dynamic VID
compensation current.
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6324A through either
the PVI or SVI interface. The ISL6324A manages the resulting
VID-on-the-Fly transition in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The ISL6324A begins slewing the DAC at
3.25mV/µs until the DAC and target voltage are equal. Thus,
the total time required for a dynamic VID transition is
dependent only on the size of the DAC change.
The amount of compensation current required is dependant on
the modulator gain of the system, K1, and the error amplifier
RC components, R and C , that are in series between the FB
C
C
and COMP pins. Use Equations 14, 15 and 16 to calculate the
RC component values, R and C , for the VID-on-the-fly
DVC
DVC
compensation network. For these equations: V is the input
IN
is the oscillator ramp
voltage for the power train; V
P-P
amplitude (1.5V); and R and C are the error amplifier RC
C
C
components between the FB and COMP pins.
K1
K1 – 1
----------------
A =
(EQ. 14)
To further improve dynamic VID performance, ISL6324A also
implements a proprietary DAC smoothing feature. The external
series RC components connected between DVC and FB limit
any stair-stepping of the output voltage during a VID-on-the-Fly
transition.
V
IN
---------------
K1 =
V
P – P
R
= A R
C
(EQ. 15)
(EQ. 16)
RCOMP
C
Compensating Dynamic VID Transitions
C
-------
=
C
RCOMP
A
During a VID transition, the resulting change in voltage on the
FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from the
FB to the COMP pin. This current then flows through the
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
feedback resistor, R , and can cause the output voltage to
FB
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its MOSFET
with minimum and sufficient delay after the other has turned off.
Power-On Reset
The ISL6324A requires VCC, PVCC1_2, and PVCC_NB inputs
to exceed their rising POR thresholds before the ISL6324A has
sufficient bias to guarantee proper operation.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse inductor
current). At this time the UGATE is released to rise. An auto-zero
The bias voltage applied to VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold is
reached, the ISL6324A has enough bias to begin checking the
driver POR inputs, EN, and channel detect portions of the
initialization cycle. Hysteresis between the rising and falling
thresholds assure the ISL6324A will not advertently turn off
unless the bias voltage drops substantially (see “Electrical
Specifications” on page 6).
comparator is used to correct the r
drop in the phase
DS(ON)
voltage preventing false detection of the -0.3V phase level during
conduction period. In the case of zero current, the
r
DS(ON)
UGATE is released after 35ns delay of the LGATE dropping below
0.5V. When LGATE first begins to transition low, this quick
transition can disturb the PHASE node and cause a false trip, so
there is 20ns of blanking time once LGATE falls until PHASE is
monitored.
The bias voltage applied to the PVCC1_2 and PVCC_NB pins
power the internal MOSFET drivers of each output channel. In
order for the ISL6324A to begin operation, both PVCC inputs
must exceed their POR rising threshold to guarantee proper
operation of the internal drivers. Hysteresis between the rising
and falling thresholds assure that once enabled, the ISL6324A
will not inadvertently turn off unless the PVCC bias voltage
drops substantially (see “Electrical Specifications” on page 6).
Depending on the number of active CORE channels
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
determined by the Phase Detect block, the external driver POR
checking is supported by the Enable Comparator.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When
the conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts VDDPWRGD.
Enable Comparator
The ISL6324A features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The
enable comparator holds the ISL6324A in shutdown until the
voltage at EN rises above 0.86V. The enable comparator has
about 110mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their rising POR level before the
ISL6324A becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6324A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
ISL6324A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
PVCC1_2
PVCC_NB
+12V
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for calculating
the proper resistor values. This will prevent improper
sequencing events from creating false trips during soft-start.
POR
CIRCUIT
ENABLE
COMPARATOR
10.7k
EN
+
-
If the controller is configured for 2-phase CORE operation,
then the resistor divider can be used for sequencing the
controller with another voltage rail. The resistor divider to EN
should be selected using a similar approach as the previous
driver discussion.
1.00k
0.86V
ISEN3-
ISEN4-
The EN pin is also used to force the ISL6324A into either PVI
or SVI mode. The mode is set upon the rising edge of the EN
signal. When the voltage on the EN pin rises above 0.86V, the
mode will be set depending upon the status of the VID1/SEL
pin.
CHANNEL
DETECT
SOFT-START
AND
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Phase Detection
The ISEN3- and ISEN4- pins are monitored prior to soft-start to
determine the number of active CORE channel phases.
FN6880 Rev 1.00
May 14, 2010
Page 20 of 39
2
ISL6324A Hybrid SVI/PVI with I C
.
If ISEN4- is tied to VCC, the controller will configure the
channel firing order and timing for 3-phase operation. If ISEN3-
and ISEN4- are tied to VCC, the controller will set the channel
firing order and timing for 2-phase operation (see “PWM
Operation” on page 12 for details). If Channel 4 and/or
Channel 3 are disabled, then the corresponding PWMn and
ISENn+ pins may be left unconnected
V
NB
400mV/DIV
V
CORE
400mV/DIV
Soft-Start Output Voltage Targets
TDA
TDB
EN
Once the POR and Phase Detect blocks and enable
comparator are satisfied, the controller will begin the soft-start
sequence and will ramp the CORE and NB output voltages up
to the SVI interface designated target level if the controller is
set SVI mode. If set to PVI mode, the North Bridge regulator is
disabled and the core is soft started to the level designated by
the parallel VID code.
5V/DIV
VDDPWRGD
5V/DIV
100µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
SVI MODE
Pre-Biased Soft-Start
Prior to soft-starting both CORE and NB outputs, the ISL6324A
must check the state of the SVI interface inputs to determine
the correct target voltages for both outputs. When the
controller is enabled, the state of the VFIXEN, SVD and SVC
inputs are checked and the target output voltages set for both
CORE and NB outputs are set by the DAC (see “Serial VID
Interface (SVI)” on page 15). These targets will only change if
the EN signal is pulled low or after a POR reset of VCC.
The ISL6324A also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by the
DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at the
end of the soft-start period, leading to an abrupt correction in the
output voltage down to the DAC-set level.
Soft-Start
The soft-start sequence is composed of three periods, as
shown in Figure 11. At the beginning of soft-start, the DAC
immediately obtains the output voltage targets for both outputs
by decoding the state of the SVI or PVI inputs. A 100µs fixed
delay time, TDA, proceeds the output voltage rise. After this
delay period the ISL6324A will begin ramping both CORE and
NB output voltages to the programmed DAC level at a fixed
rate of 3.25mV/µs. The amount of time required to ramp the
output voltage to the final DAC voltage is referred to as TDB,
and can be calculated as shown in Equation 17.
Both CORE and NB output support start up into a pre-charged
output.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
V
DAC
OUTPUT PRECHARGED
BELOW DAC LEVEL
------------------------------
TDB =
(EQ. 17)
–3
3.25 10
V
CORE
400mV/DIV
After the DAC voltage reaches the final VID setting,
VDDPWRGD will be set to high.
EN
5V/DIV
100µs/DIV
FIGURE 12. SOFT-START WAVEFORMS FOR
ISL6324A-BASED MULTI-PHASE CONVERTER
FN6880 Rev 1.00
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Page 21 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Overvoltage Protection
The ISL6324A constantly monitors the sensed output voltage on
the VSEN pin to detect if an overvoltage event occurs. When the
output voltage rises above the OVP trip level and exceeds the
VDDPWRGD OV limit actions are taken by the ISL6324A to
protect the microprocessor load.
17.5µA
-
OCL
+
I
1
REPEAT FOR EACH
CORE CHANNEL
12.5µA
-
OCP
At the inception of an overvoltage event, both on-board lower
gate pins are commanded low as are the active PWM outputs
to the external drivers, the VDDPWRGD signal is driven low,
and the ISL6324A latches off normal PWM action. This turns
on the all of the lower MOSFETs and pulls the output voltage
below a level that might cause damage to the load. The lower
MOSFETs remain driven ON until VDIFF falls below 400mV.
The ISL6324A will continue to protect the load in this fashion
as long as the overvoltage condition recurs. Once an
overvoltage condition ends the ISL6324A latches off, and must
be reset by toggling POR, before a soft-start can be re-
initiated.
+
I
12.5µA
NB
-
OCP
+
I
AVG
CORE ONLY
NB ONLY
SOFT-START, FAULT
AND CONTROL LOGIC
DUPLICATED FOR
NB AND CORE
+
1.8V
OVP
-
+
DAC + 250mV
DAC - 300mV
Pre-POR Overvoltage Protection
OV
-
Prior to PVCC and VCC exceeding their POR levels, the
ISL6324A is designed to protect either load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10k resistor tied from PHASE to LGATE,
which turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET should
have a gate threshold well below the maximum voltage rating
of the load/microprocessor.
-
VSEN
UV
+
VDDPWRGD
ISL6324A INTERNAL CIRCUITRY
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
Fault Monitoring and Protection
The ISL6324A actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault monitors
trigger protective measures to prevent damage to either load.
One common power-good indicator is provided for linking to
external system monitors. The schematic in Figure 13 outlines
the interaction between the fault monitors and the power good
signal.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from any
more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, VDDPWRGD gets pulled low. No other
action is taken by the controller. VDDPWRGD will return high if
the output voltage rises above VDAC - 250mV typical.
Power-Good Signal
The power good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6324A is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be tied
to a +5V source through a resistor.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6324A is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and
RGND pins. In the event of an open sense line fault, the
controller will continue to remain off until the fault goes away, at
which point the controller will re-initiate a soft-start sequence.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. VDDPWRGD transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
on either regulator output or when the controller is disabled by
a POR reset or EN. In the event of an overvoltage or
overcurrent condition, the controller latches off and
VDDPWRGD will not return high. Pending a POR reset of the
ISL6324A and successful soft-start, the VDDPWRGD will
return high.
Overcurrent Protection
The ISL6324A takes advantage of the proportionality between
the load current and the average current, I
, to detect an
AVG
overcurrent condition. See “Continuous Current Sampling” on
page 13 and “Channel-Current Balance” on page 14 for more
detail on how the average current is measured. Once the
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
average current exceeds 100µA, a comparator triggers the
converter to begin overcurrent protection procedures. The
Core regulator and the North Bridge regulator have the same
type of overcurrent protection.
Note that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
OUTPUT CURRENT, 50A/DIV
inductor RC filter and the R
resistor. The overcurrent trip
SET
threshold is shown in Equation 18.
V
– N V
V
OUT OUT
N
DCR
1
K
3
IN
–
------------- --- ---------
---------------------------------------- ---------------
I
= 100A
R
OCP
SET
400
2 L f
V
IN
0A
S
(EQ. 18)
OUTPUT VOLTAGE,
500mV/DIV
Where:
K =
R
2
See “Continuous Current Sampling” on
page 13.
--------------------
+ R
R
1
2
0V
f
= Switching Frequency
S
3ms/DIV
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
Equation 18 is valid for both the Core regulator and the North
Bridge regulator. This equation includes the DC load current as
well as the total ripple current contributed by all the phases.
For the North Bridge regulator, N is 1.
NORTH BRIDGE REGULATOR OVERCURRENT
The overcurrent shutdown sequence for the North Bridge
regulator is identical to the Core regulator with the exception that
it is a single phase regulator and will only disable the MOSFET
drivers for the North Bridge. Once 7 retry attempts have been
executed unsuccessfully, the controller will disable UGATE and
LGATE signals for both Core and North Bridge and will latch off
requiring a POR of VCC to reset the ISL6324A.
During soft-start, the overcurrent trip point is boosted by a
factor of 1.4. Instead of comparing the average measured
current to 100µA, the average current is compared to 140µA.
Immediately after soft-start is over, the comparison level
changes to 100µA. This is done to allow for start-up into an
active load while still supplying output capacitor in-rush
current.
Note that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
CORE REGULATOR OVERCURRENT
Individual Channel Overcurrent Limiting
At the beginning of overcurrent shutdown, the controller sets all
of the UGATE and LGATE signals low, puts PWM3 and PWM4
(if active) in a high-impedance state, and forces VDDPWRGD
low. This turns off all of the upper and lower MOSFETs. The
system remains in this state for fixed period of 12ms. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start, as shown in Figure 14. If the fault remains,
the trip-retry cycles will continue until either the fault is cleared or
for a total of seven attempts. If the fault is not cleared on the final
attempt, the controller disables UGATE and LGATE signals for
both Core and North Bridge and latches off requiring a POR of
VCC to reset the ISL6324A.
The ISL6324A has the ability to limit the current in each
individual channel of the Core regulator without shutting down
the entire regulator. This is accomplished by continuously
comparing the sensed currents of each channel with a
constant 140µA OCL reference current. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the rise
of current in that channel, forcing the current in the channel to
decrease. That channel’s UGATE signal will not be able to
return high until the sensed channel current falls back below
the 140µA reference.
It is important to note that during soft start, the overcurrent trip
point is increased by a factor of 1.4. If the fault draws enough
current to trip overcurrent during normal run mode, it may not
draw enough current during the soft-start ramp period to trip
overcurrent while the output is ramping up. If a fault of this type
is affecting the output, then the regulator will complete soft-
start and the trip-retry counter will be reset to zero. Once the
regulator has completed soft-start, the overcurrent trip point will
return to it’s nominal setting and an overcurrent shutdown will
be initiated. This will result in a continuous hiccup mode.
2
I C Bus Interface
The ISL6324A includes an I C bus interface which allows for
2
user programmability of three of the controller’s operating
parameters and programmability of the Power Savings Mode
2
feature. The parameters that can be adjusted through the I C
are:
1. Voltage Margining Offset: The DAC voltage can be offset
in 25mV increments.
FN6880 Rev 1.00
May 14, 2010
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2
ISL6324A Hybrid SVI/PVI with I C
2. VDDPWRGD Trip Level: The PGOOD trip level for either
the Core regulator or the North Bridge regulator can be
increased.
START and STOP Conditions
Figure 16 shows a START (S) condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
3. Overvoltage Trip Level: The OVP trip level of either the
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition..
Core or North Bridge regulator can be increased.
4. Power Savings Mode Options:
a. The number of phases to drop to in Power Savings Mode
can be programmed
SDA
SCL
b. The number of PWM cycles between dropping phases
while entering Power Savings Mode can be programmed.
c. The number of PWM cycles between adding phases when
exiting Power Savings Mode can be programmed.
S
P
d. Core Voltage Margining Offset can be Enabled or
Disabled while in Power Savings Mode.
START
CONDITION
STOP
CONDITION
To adjust these parameters, data transmission from the main
microprocessor to the ISL6324A and vice versa must take place
through the two wire I C bus interface. The two wires of the I C
bus consist of the SDA line, over which all data is sent, and the
SCL line, which is a clock signal used to synchronize
sending/receiving of the data.
FIGURE 16. START AND STOP WAVEFORMS
2
2
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit first (MSB)
and the least significant bit last (LSB).
Both SDA and SCL are bidirectional lines, externally connected to
a positive supply voltage via a pull-up resistor. Pull-up resistor
values should be chosen to limit the input current to less then
3mAWhen the bus is free, both lines are HIGH. The output
stages of ISL6324A have an open drain/open collector in order to
Acknowledge
Each address and data transmission uses 9-clock pulses. The
ninth pulse is the acknowledge bit (A). After the start condition,
the master sends 7 slave address bits and a R/W bit during the
next 8-clock pulses. During the ninth clock pulse, the device
that recognizes its own address holds the data line low to
acknowledge. The acknowledge bit is also used by both the
master and the slave to acknowledge receipt of register
addresses and data as described in Figure 17.
2
perform the wired-AND function. Data on the I C bus can be
transferred up to 100Kbps in the standard-mode or up to 400Kbps
in the fast-mode. The level of logic “0” and logic “1” is dependent
on associated value of V as per electrical specification table.
DD
One clock pulse is generated for each data bit transferred. The
ISL6324A is a “SLAVE only” device, so the SCL line must always
be controlled by an external master.
SCL
2
It is important to note that the I C interface of the ISL6324A
8
2
1
9
only works once the voltage on the VCC pin has risen above
the POR rising threshold. The I C will continue to remain
2
SDA
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
MSB
START
ACKNOWLEDGE
FROM SLAVE
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer to
Figure 15.
2
FIGURE 17. ACKNOWLEDGE ON THE I C BUS
2
ISL6324A I C Slave Address
2
2
All devices on the I C bus must have a 7-Bit I C address in
order to be recognized. The address for the ISL6324A is
1000_110.
2
SDA
Communicating Over the I C Bus
2
Two transactions are supported on the I C interface:
1. Write register
SCL
2. Read register from current address.
DATA LINE CHANGE
2
STABLE
DATA VALID ALLOWED
OF DATA
All transactions start with a control byte sent from the I C
master device. The control byte begins with a Start condition,
followed by 7-Bits of slave address. The last bit sent by the
FIGURE 15. DATA VALIDITY
FN6880 Rev 1.00
May 14, 2010
Page 24 of 39
2
ISL6324A Hybrid SVI/PVI with I C
master is the R/W bit and is 0 for a write or 1 for a read. If any
slaves on the I C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last
clock cycle in the control byte. If no slaves exist at that address
or are not ready to communicate, the data line will be 1,
indicating a Not Acknowledge condition.
RGS1 and receiving an Acknowledge from the ISL6324A,
instead of sending a Stop condition, the master sends the data
byte to be stored in register RGS2. After the ISL6324A
responds with another Acknowledge, the master can either
send a Stop condition to indicate that the current transaction is
complete, or it can send the data byte to be stored in register
RGS3. If register RGS3 is written to, the ISL6324A will respond
with an Acknowledge and the master would send a Stop
condition, completing the transaction. Once this transaction
completes the ISL6324A will immediately update and change
the operating parameters on-the-fly.
2
Once the control byte is sent, and the ISL6324A acknowledges
it, the 2nd byte sent by the master must be a register address
byte. This register address byte tells the ISL6324A which one of
the internal registers it wants to write to or read from. The
address of the first internal register, RGS1, is 0000_0000. This
register sets the North Bridge Offset, Overvoltage trip point and
Power-good trip level. The address of the second internal
register, RGS2, is 0000_0001. This register sets the Core Offset,
Overvoltage trip point and Power-good trip level. The address of
the third register, RGS3, is 0000_0010. The third register is for
programming of the Power Savings Mode features. Once the
ISL6324A receives a correct register address byte, it responds
with an acknowledge.
Reading from the Internal Registers
The ISL6324A has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once it
receives an Acknowledge from the ISL6324A, it sends a
register address byte representing the internal register it wants
to read from (0000_0000 for RGS1, 0000_0001 for RGS2 or
0000_0010 for RGS3). The ISL6324A will respond with an
Acknowledge. The master must then respond with a Stop
condition. After the Stop condition, the master follows with a
new Start condition, and then sends a new control byte with the
R/W bit set to 1, indicating a read. The ISL6324A will then
respond by sending the master an Acknowledge, followed by
the data byte stored in that register. The master must then
send a Not Acknowledge followed by a Stop command, which
will complete the read transaction.
TABLE 5. I2C REGISTER FUNCTIONS
REGISTER ADDRESS
FUNCTION
RGS1
RGS2
RGS3
0000_0000 North Bridge DAC Offset, OVP, PGOOD
0000_0001 Core DAC Offset, OVP, PGOOD
0000_0010 Power Savings Mode Functionality
Writing to the Internal Registers
In order to change any of the three operating parameters via
2
the I C bus, the internal registers must be written to. The two
registers inside the ISL6324A can be written individually with
two separate write transactions or sequentially with one write
transaction by sending two data bytes. See “Reading from the
Internal Registers” on page 25.
It is also possible for all registers to be read consecutively. To
do this the master must read from register RGS1 first. This
transaction begins with the master sending a control byte with
the R/W bit set to 0. If it receives an Acknowledge from the
ISL6324A, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6324A will
respond with an Acknowledge. The master must then respond
with a Stop condition. After the Stop condition the master
follows with a new Start condition, and then sends a new
control byte with the R/W bit set to 1, indicating a read. The
ISL6324A will then respond by sending the master an
Acknowledge, followed by the data byte stored in register
RGS1. The master must then send an Acknowledge, and after
doing so, the ISL6324A will respond by sending the data byte
stored in register RGS2. The master must then send another
Acknowledge, which the ISL6324A will respond to by sending
the data byte stored in register RGS3. The master must then
send a Not Acknowledge followed by a Stop command, which
will complete the read transaction.
To write to a single register in the ISL6324A, the master sends
a control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL6324A, it sends a
register address byte representing the internal register it wants
to write to (0000_0000 for RGS1, 0000_0001 for RGS2 or
0000_0010 for RGS3). The ISL6324A will respond with an
Acknowledge. The master then sends a byte representing the
data byte to be written into the desired register. The ISL6324A
will respond with an Acknowledge. The master then issues a
Stop condition, indicating to the ISL6324A that the current
transaction is complete. Once this transaction completes, the
ISL6324A will immediately update and change the operating
parameters on-the-fly.
It is also possible to write to the all the registers sequentially.
To do this the master must write to register RGS1first. This
transaction begins with the master sending a control byte with
the R/W bit set to 0. If it receives an Acknowledge from the
ISL6324A, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6324A will
respond with an Acknowledge. After sending the data byte to
Resetting the Internal Registers
2
The ISL6324A’s internal I C registers always initialize to the
states shown in Table 6 when the controller first receives
power. Once the voltage on the VCC pin rises above the POR
rising threshold level, these registers can be changed at any
FN6880 Rev 1.00
May 14, 2010
Page 25 of 39
2
ISL6324A Hybrid SVI/PVI with I C
2
TABLE 6. I2C REGISTER INITIAL STATES
time via the I C interface. If the voltage on the VCC pin falls
below the POR falling threshold, the internal registers are
automatically reset to their initial states.
REGISTER
RGS3
ADDRESS
INITIAL STATE
0000_0001
0000_0010
TABLE 6. I2C REGISTER INITIAL STATES
It is possible to reset the internal registers without powering
down the controller and without requiring the controller to stop
regulating and soft-start again. Simply write the initial states to
REGISTER
RGS1
ADDRESS
0000_0000
0000_0001
INITIAL STATE
0000_0000
2
RGS2
0000_0000
the internal registers over the I C interface.
2
I C Read and Write Protocol
WRITE TO A SINGLE REGISTER
S
1000_1100
A
0000_0000
A
RGS1_DATA
RGS1_DATA
A
A
P
WRITE TO ALL REGISTERS
1000_1100 0000_0000
S
A
A
A
A
RGS1_DATA
A
RGS1_DATA
A
P
READ FROM SINGLE REGISTER
1000_1100 REG_ADDR
S
A
P
P
S
S
1000_1101
1000_1101
A
A
RGS1_DATA
RGS1_DATA
N
A
P
READ FROM ALL REGISTERS
1000_1100 0000_0000
S
A
RGS2_DATA
A
RGS3_DATA
N
P
DRIVEN BY MASTER
DRIVEN BY ISL6324A
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE
N = NO ACKNOWLEDGE
FN6880 Rev 1.00
May 14, 2010
Page 26 of 39
2
ISL6324A Hybrid SVI/PVI with I C
TABLE 8. BITS [5:0] REGISTER RGS1 and RGS2
(VOLTAGE MARGINING OFFSET) (Continued)
Register Bit Definitions
The bits for RGS1 and RGS2 are utilized in the same manner
by the ISL6324A (see Table 5). Bit-7 enables the overvoltage
protection trip point to be increased. Bit-6 enables the Power-
good trip point to be increased. These bits will be interpreted
by the ISL6324A according to Table 7. Bits 5 through 0
determine the amount of offset for the particular regulator. See
Table 8 for the bit codes and the corresponding offset voltages
from the nominal DAC.
BIT5
VO5
1
BIT4
VO4
1
BIT3
VO3
0
BIT2
VO2
1
BIT1
VO1
1
BIT0
VO0
0
V
OFFSET
(mV)
-250
-225
-200
-175
-150
-125
-100
-75
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
TABLE 7. BIT [7] AND [6] of REGISTER RGS1 AND RGS2
1
1
1
0
1
0
BIT 7
OVP TRIP LEVEL
1
1
1
0
1
1
0
1
1.8V or V
1.8V or V
+ 250mV, whichever is greater
+ 500mV, whichever is greater
PGOOD TRIP LEVEL
DAC
DAC
1
1
1
1
0
0
1
1
1
1
0
1
BIT 6
0
1
1
1
1
1
0
-50
VDAC
VDAC
+250mV/-300mV
- 300mV
CORE
1
1
1
1
1
1
-25
NB
0
0
0
0
0
0
0
1
VDAC
VDAC
+300mV/-350mV
- 350mV
CORE
0
0
0
0
0
1
25
NB
NOTE: All Pgood trip points have 50mV hysteresis
0
0
0
0
1
0
50
0
0
0
0
1
1
75
TABLE 8. BITS [5:0] REGISTER RGS1 and RGS2
(VOLTAGE MARGINING OFFSET)
0
0
0
1
0
0
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
725
0
0
0
1
0
1
BIT5
VO5
1
BIT4
VO4
0
BIT3
VO3
0
BIT2
VO2
0
BIT1
VO1
0
BIT0
VO0
0
V
OFFSET
(mV)
0
0
0
1
1
0
0
0
0
1
1
1
-800
-775
-750
-725
-700
-675
-650
-625
-600
-575
-550
-525
-500
-475
-450
-425
-400
-375
-350
-325
-300
-275
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
FN6880 Rev 1.00
May 14, 2010
Page 27 of 39
2
ISL6324A Hybrid SVI/PVI with I C
TABLE 8. BITS [5:0] REGISTER RGS1 and RGS2
(VOLTAGE MARGINING OFFSET) (Continued)
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally, the
designer will be concerned with whether components can be
mounted on both sides of the circuit board, whether through-
hole components are permitted, the total board space available
for power-supply circuitry, and the maximum amount of load
current. Generally speaking, the most economical solutions are
those in which each phase handles between 25A and 30A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can be
used, higher per-phase currents are possible. In cases where
board space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks and
forced air to cool the MOSFETs, inductors and heat dissipating
surfaces.
BIT5
VO5
0
BIT4
VO4
1
BIT3
VO3
1
BIT2
VO2
1
BIT1
VO1
1
BIT0
VO0
0
V
OFFSET
(mV)
750
775
0
1
1
1
1
1
The bits for Register RGS3 control some of the functionality of
the ISL6324A for Power Savings Mode. Bits 0 and 1 control the
number of phases that the ISL6324A will drop to when in
Power Savings Mode. Bits 2 and 3 control the number of PWM
cycles between adding of phases when exiting Power Savings
Mode. Bits 4 and 5 control the number of PWM cycles between
dropping of phases when entering Power Savings Mode. Bit 6
will disable/enable the Core DAC offset when in Power
Savings Mode. Bit 7 is reserved. See Table 9 for a complete
description of register RGS3 bits and their functionality.
TABLE 9. BITS [7:0] REGISTER RGS3
MOSFETS
Bit 7
Bit 6
0
Reserved
Core DAC Offset
ENABLED
The choice of MOSFETs depends on the current each MOSFET
will be required to conduct, the switching frequency, the
capability of the MOSFETs to dissipate heat, and the availability
and nature of heat sinking and air flow.
1
DISABLED
LOWER MOSFET POWER CALCULATION
Bits [5:4] Number of PWM Cycles Between Dropping Phases
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to
00
01
10
11
1 PWM Cycle (default)
2 PWM Cycles
current conducted through the channel resistance (r
). In
DS(ON)
Equation 19, I is the maximum continuous output current, I
M
P-
4 PWM Cycles
is the peak-to-peak inductor current (see Equation 20), and d
P
0 PWM Cycles (All Phases Drop at Once)
is the duty cycle (V
/V ).
OUT IN
Bits [3:2] Number of PWM Cycles Between Adding Phases
2
2
I
1 – d
(EQ. 19)
I
LP – P
M
P
= r
DSON
1 – d + ----------------------------------------------
-----
00
01
10
11
1 PWM Cycle (Default)
2 PWM Cycles
LOW 1
12
N
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower-
MOSFET body diode. This term is dependent on the diode
4 PWM Cycles
0 PWM Cycles (All Phases Added at Once)
Bits [1:0] Number of Phases Active in Power Savings Mode
forward voltage at I , V
the length of dead times, t and t , at the beginning and the
end of the lower-MOSFET conduction interval respectively.
, the switching frequency, f , and
M
D(ON)
S
00
01
1X
1 Phase
2 Phases (Default)
3 Phases
d1 d2
I
I
I
I
M
M
P
= V
f
S
P + P
2
P – P
2
t
+
t
---------------
------ –
------ + ---------------
LOW 2
DON
d1
d2
N
N
General Design Guide
(EQ. 20)
This design guide is intended to provide a high-level explanation
of the steps necessary to create a multi-phase power converter. It
is assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following sections. In addition to
this guide, Intersil provides complete reference designs that
include schematics, bills of materials, and example board layouts
for all common microprocessor applications.
The total maximum power dissipated in each lower MOSFET is
approximated by the summation of P and P
.
LOW,2
LOW,1
UPPER MOSFET POWER CALCULATION
In addition to r losses, a large portion of the upper
DS(ON)
MOSFET losses are due to currents conducted across the input
voltage (V ) during switching. Since a substantially higher
IN
portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
FN6880 Rev 1.00
May 14, 2010
Page 28 of 39
2
ISL6324A Hybrid SVI/PVI with I C
components involving the upper-MOSFET switching times, the
Q
GATE
-------------------------------------
C
Q
BOOT_CAP
Q
lower-MOSFET body-diode reverse recovery charge, Q , and
V
rr
BOOT_CAP
(EQ. 25)
the upper MOSFET r
DS(ON)
conduction loss.
PVCC
G1
V
-----------------------------------
=
N
Q1
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the voltage
at the phase node falls below ground. Once the lower
GATE
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of control
MOSFET begins conducting, the current in the upper MOSFET
falls to zero as the current in the lower MOSFET ramps up to
assume the full inductor current. In Equation 21, the required
GS1
MOSFETs. The V
Q1
term is defined as the allowable
BOOT_CAP
droop in the rail of the upper gate drive.
time for this commutation is t and the approximated
1.6
1
associated power loss is P
UP(1)
.
1.4
1.2
1.0
0.8
0.6
t
I
I
(EQ. 21)
1
M
P – P
2
P
V
f
S
----
----- + -------------
UP1
IN
2
N
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t . In Equation 22, the
2
approximate power loss is P
UP(2)
.
(EQ. 22)
I
t
2
2
I
P – P
2
M
Q
= 100nC
GATE
P
V
f
S
-------------
----
----- –
UP2
IN
N
0.4
0.2
0.0
50nC
A third component involves the lower MOSFET
20nC
reverse-recovery charge, Q . Since the inductor current has
rr
fully commutated to the upper MOSFET before the
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V (V)
lower-MOSFET body diode can recover all of Q , it is
rr
BOOT_CAP
conducted through the upper MOSFET across VIN. The power
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
dissipated as a result is P
as shown in Equation 23.
UP(3)
(EQ. 23)
P
= V Q f
IN rr S
UP3
Gate Drive Voltage Versatility
The ISL6324A provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. The controller ties the
upper and lower drive rails together. Simply applying a voltage
from 5V up to 12V on PVCC sets both gate drive rail voltages
simultaneously.
Finally, the resistive part of the upper MOSFET is given in
Equation 24 as P
.
UP(4)
2
2
(EQ. 24)
I
P – P
I
M
P
r
DSON
d +
-------------
12
-----
UP4
N
Package Power Dissipation
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
Equations 21, 22, 23 and 24. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 36 for
thermal transfer improvement suggestions.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
Schottky diode. Simply adding an external capacitor across the
BOOT and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing at
the PHASE node. This reduces voltage stress on the boot to
phase pins.
When designing the ISL6324A into an application, it is
recommended that the following calculations is used to ensure
safe operation at the desired frequency for the selected
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 4V and its capacitance value can be chosen
from Equation 25:
MOSFETs. The total gate drive power losses, P
, due to
Qg_TOT
the gate charge of MOSFETs and the integrated driver’s
FN6880 Rev 1.00
May 14, 2010
Page 29 of 39
2
ISL6324A Hybrid SVI/PVI with I C
internal circuitry and their corresponding average driver current
can be estimated with Equations 26 and 27, respectively.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in the
controller itself is the power dissipated in the upper drive path
P
= P
+ P
+ I VCC
Qg_Q2 Q
(EQ. 26)
Qg_TOT
Qg_Q1
3
2
resistance (P
) the lower drive path resistance (P )
--
P
=
Q
PVCC f
N
N
Q1 PHASE
DR_UP
DR_UP
Qg_Q1
G1
SW
and in the boot strap diode (P
). The rest of the power will
BOOT
be dissipated by the external gate resistors (R and R ) and
P
= Q
PVCC f
+ Q
N
N
PHASE
G1 G2
Qg_Q2
G2
SW
Q2
the internal gate resistors (R
GI1
and R ) of the MOSFETs.
GI2
3
Figures 19 and 20 show the typical upper and lower gate
drives turn-on transition path. The total power dissipation in the
--
I
=
Q
N
N
N
f
+ I
(EQ. 27)
DR
G1
G2
Q1
Q2
PHASE SW Q
2
controller itself, P , can be roughly estimated as Equation 28:
DR
In Equations 26 and 27, P
power loss and P
Qg_Q2
is the total upper gate drive
is the total lower gate drive power loss;
Qg_Q1
P
P
P
= P
+ P
+ P
+ I VCC
DR
DR_UP
DR_LOW
BOOT
Q
the gate charge (Q and Q ) is defined at the particular gate
G1 G2
P
Qg_Q1
to source drive voltage PVCC in the corresponding MOSFET
(EQ. 28)
---------------------
=
BOOT
3
data sheet; I is the driver total quiescent current with no load at
Q
R
R
P
both drive outputs; N and N are the number of upper and
Q1
Q2
HI1
LO1
Qg_Q1
-------------------------------------- --------------------------------------- ---------------------
=
+
DR_UP
R
+ R
R
+ R
EXT1
3
lower MOSFETs per phase, respectively; N
is the number
PHASE
HI1
EXT1
LO1
of active phases. The I *VCC product is the quiescent power of
the controller without capacitive load and is typically 75mW at
300kHz.
Q
R
R
P
Qg_Q2
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
DR_LOW
R
+ R
R
+ R
EXT2
2
HI2
EXT2
LO2
R
R
PVCC
BOOT
GI1
GI2
-------------
-------------
= R
+
R
= R
G2
+
EXT1
G1
EXT2
N
N
D
Q1
Q2
C
R
GD
Inductor DCR Current Sensing Component
R
HI1
G
UGATE
Selection and R
Value Calculation
C
SET
resistor setting the value of the effective
SET
DS
R
With the single R
LO1
R
GI1
C
G1
internal sense resistors for both the North Bridge and Core
regulators, it is important to set the R value and the
GS
Q1
SET
S
inductor RC filter gain, K, properly. See “Continuous Current
Sampling” on page 13 and “Channel-Current Balance” on
PHASE
page 14 for more details on the application of the R
and the RC filter gain.
resistor
SET
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
There are 3 separate cases to consider when calculating these
component values. If the system under design will never utilize
the North Bridge regulator and the ISL6323 will always be in
parallel mode, then follow the instructions for Case 3 and only
calculate values for Core regulator components.
D
C
GD
R
HI2
G
LGATE
C
DS
R
R
LO2
R
GI2
C
G2
For all three cases, use the expected VID voltage that would
GS
Q2
be used at TDC for Core and North Bridge for the V
and
CORE
S
V
variables, respectively.
NB
CASE 1
I
Core
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
MAX
(EQ. 29)
--------------------------
DCR
Core
I
DCR
NB
MAX
NB
N
In Case 1, the DC voltage across the North Bridge inductor at
full load is less than the DC voltage across a single phase of
the Core regulator while at full load. Here, the DC voltage
across the Core inductors must be scaled down to match the
DC voltage across the North Bridge inductor, which will be
impressed across the ISEN_NB pins without any gain. Thus,
the R resistor for the North Bridge inductor RC filter is left
2
unpopulated and K = 1.
FN6880 Rev 1.00
May 14, 2010
Page 30 of 39
2
ISL6324A Hybrid SVI/PVI with I C
3. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
4. Using Equation 38 (also derived from Equation 18),
calculate the value of K for the North bridge regulator.
3
400
1
100A
4. Calculate the value for resistor R using Equation 30:
1
---------
--------------------- -------------------------------------------------------------------------
K =
R
SET
DCR
V
– V
V
NB NB
NB
IN
L
---------------------------- -----------
I
+
NB
(EQ. 30)
OCP
2 L
f
V
IN
-------------------------------------
R
=
NB
NB
S
1
DCR
C
NB
NB
NB
(EQ. 38)
5. Calculate the value for the R
resistor using Equation 31:
SET
5. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
DCR
K
V
– V
V
400
3
NB
IN
NB NB
--------- -----------------------------
---------------------------- -----------
R
=
I
+
SET
OCP
100A
2 L
f
V
IN
NB
NB
S
6. Calculate the values for R and R for North Bridge.
1
2
(EQ. 31)
Where:
K = 1
Equations 39 and 40 will allow for their computation.
R
2
NB
(Derived from Equation 18).
(EQ. 39)
------------------------------------
K =
R
+ R
1
2
6. Using Equation 32 (also derived from Equation 18),
calculate the value of K for the Core regulator.
NB
NB
R
R
2
1
L
3
400
N
100A
NB
NB
NB
(EQ. 40)
---------
----------------------------- -----------------------------------------------------------------------------------------------------------
---------------------
------------------------------------
= C
K =
R
SET
NB
DCR
V
– N V
V
DCR
NB
R
+ R
CORE
IN
CORE
CORE
1
2
NB
NB
-------------------------------------------- --------------------
I
+
OCP
2 L
f
V
IN
CORE
CORE
S
CASE 3
(EQ. 32)
I
Core
MAX
(EQ. 41)
--------------------------
DCR
Core
I
DCR
=
7. Choose a capacitor value for the Core RC filters. A 0.1µF
capacitor is a recommended starting point.
NB
MAX
NB
N
8. Calculate the values for R and R for Core. Equations 33
In Case 3, the DC voltage across the North Bridge inductor at
full load is equal to the DC voltage across a single phase of the
Core regulator while at full load. Here, the full scale DC
inductor voltages for both North Bridge and Core will be
1
2
and 34 will allow for their computation.
R
2
Core
(EQ. 33)
(EQ. 34)
----------------------------------------------
K =
R
+ R
1
2
Core
Core
impressed across the ISEN pins without any gain. So, the R
2
R
R
2
resistors for the Core and North Bridge inductor RC filters are
left unpopulated and K = 1 for both regulators.
1
L
Core
Core
Core
--------------------------
----------------------------------------------
=
C
Core
DCR
Core
R
+ R
2
1
Core
Core
For this Case, it is recommended that the overcurrent trip point
for the North Bridge regulator be equal to the overcurrent trip
point for the Core regulator divided by the number of core
phases.
CASE 2
I
Core
MAX
(EQ. 35)
--------------------------
I
DCR
DCR
Core
NB
NB
N
MAX
1. Choose a capacitor value for the North Bridge RC filter. A
0.1µF capacitor is a recommended starting point.
In Case 2, the DC voltage across the North Bridge inductor at
full load is greater than the DC voltage across a single phase
of the Core regulator while at full load. Here, the DC voltage
across the North Bridge inductor must be scaled down to
match the DC voltage across the Core inductors, which will be
2. Calculate the value for the North Bridge resistor R :
1
L
NB
C
NB
(EQ. 42)
-------------------------------------
R
=
1
DCR
NB
NB
impressed across the ISEN pins without any gain. So, the R
resistor for the Core inductor RC filters is left unpopulated and
K = 1.
2
3. Choose a capacitor value for the Core RC filter. A 0.1µF
capacitor is a recommended starting point.
4. Calculate the value for the Core resistor R :
1
1. Choose a capacitor value for the Core RC filter. A 0.1µF
capacitor is a recommended starting point.
L
Core
(EQ. 43)
-----------------------------------------------
R
=
1
DCR
C
Core
Core
Core
2. Calculate the value for resistor R :
1
5. Calculate the value for the R
resistor using Equation 44:
SET
L
Core
(EQ. 36)
-----------------------------------------------
R
=
DCR
K
V
– V
V
1
400
3
CORE
IN
CORE CORE
DCR
C
Core
Core
--------- --------------------------------------
------------------------------------- -------------------
Core
R
=
I
+
SET
OCP
100A N
2 L
f
V
IN
CORE
CORE
S
3. Calculate the value for the R
resistor using
Equation 37:(Derived from Equation 18).
SET
(EQ. 44)
Where:
K = 1
6. Calculate the OCP trip point for the North Bridge regulator
using Equation 45. If the OCP trip point is higher than
desired, then the component values must be recalculated
utilizing Case 1. If the OCP trip point is lower than desired,
DCR
K
V
– V
V
CORE CORE
400
3
CORE
IN
--------- --------------------------------------
------------------------------------- --------------------
R
=
I
+
SET
OCP
100A N
2 L
f
V
IN
CORE
CORE
S
Where:
K = 1
(EQ. 37)
FN6880 Rev 1.00
May 14, 2010
Page 31 of 39
2
ISL6324A Hybrid SVI/PVI with I C
then the component values must be recalculated utilizing
Case 2.
Due to errors in the inductance and/or DCR it may be
necessary to adjust the value of R and R to match the time
1
2
V
– V
V
constants correctly. The effects of time constant mismatch can
be seen in the form of droop overshoot or undershoot during
the initial load transient spike, as shown in Figure 22. Follow
the steps below to ensure the RC and inductor L/DCR time
constants are matched accurately.
1
3
400
IN
NB NB
--------------------- ---------
---------------------------- -----------
I
= 100A
R
+
OCP
SET
DCR
2 L
f
V
IN
NB
NB
NB
S
(EQ. 45)
NOTE: The values of R
must be greater than 20k and
SET
less than 80k. For all of the 3 cases, if the calculated value of
is less than 20k, then either the OCP trip point needs to
1. If the regulator is not utilizing droop, modify the circuit by
placing the frequency set resistor between FS and Ground
for the duration of this procedure.
R
SET
be increased or the inductor must be changed to an inductor
with higher DCR. If the R resistor is greater than 80k,
SET
that is less than 80k must be chosen
2. Capture a transient event with the oscilloscope set to about
L/DCR/2 (sec/div). For example, with L = 1µH and DCR =
1m, set the oscilloscope to 500µs/div.
then a value of R
SET
and a resistor divider across both North Bridge and Core
inductors must be set up with proper gain. This gain will
represent the variable “K” in all equations. It is also very
3. Record V1 and V2 as shown in Figure 22. Select new
values, R
and R
) for the time constant
1(NEW)
2(NEW
important that the R
resistor be tied between the RSET pin
SET
resistors based on the original values, R
and
1(OLD)
and the VCC pin of the ISL6323.
R
using Equations 46 and 47.
2(OLD)
Inductor DCR Current Sensing Component Fine
Tuning
V
1
(EQ. 46)
(EQ. 47)
---------
R1NEW = R1OLD
V
2
I
V
IN
L
n
V
UGATE(n)
LGATE(n)
1
---------
R21NEW = R2OLD
L
V
DCR
V
OUT
MOSFET
DRIVER
2
4. Replace R and R with the new values and check to see
1
2
INDUCTOR
-
C
OUT
that the error is corrected. Repeat the procedure if
V (s)
L
necessary.
-
V
(s)
C
C
R
1
R
2
ISL6323 INTERNAL CIRCUIT
V
2
V
1
I
n
V
OUT
SAMPLE
+
-
I
TRAN
ISENn-
-
V
(s)
C
I
ISENn+
VCC
R
ISEN
I
SEN
RSET
FIGURE 22. TIME CONSTANT MISMATCH BEHAVIOR
R
SET
Loadline Regulation Resistor
The loadline regulation resistor, labeled R in Figure 8, sets
FB
the desired loadline required for the application. Equation 48
C
SET
FIGURE 21. DCR SENSING CONFIGURATION
can be used to calculate R
.
FB
V
DROOP
MAX
---------------------------------------------------------------------
R
=
(EQ. 48)
FB
I
OUT
400
3
DCR
MAX
--------- ------------------------- --------------
K
N
R
SET
Where K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be tied
between the FS pin and VCC. To choose the value for R in
FB
FN6880 Rev 1.00
May 14, 2010
Page 32 of 39
2
ISL6324A Hybrid SVI/PVI with I C
this situation, please refer to “Compensation Without Loadline
Regulation” on page 33.
value of R while observing the transient performance on an
C
oscilloscope until no further improvement is noted. Normally,
C
will not need adjustment. Keep the value of C from
C
C
Compensation With Loadline Regulation
Equation 49 unless some performance issue is noted.
The load-line regulated converter behaves in a similar manner
to a peak current mode controller because the two poles at the
output filter L-C resonant frequency split with the introduction
of current information into the control loop. The final location of
these poles is determined by the system function, the gain of
the current signal, and the value of the compensation
The optional capacitor C , is sometimes needed to bypass
2
noise away from the PWM comparator (see Figure 23). Keep a
position available for C , and be prepared to install a high
2
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
.
components, R and C .
C
C
1
------------------------------- > f
0
C
(OPTIONAL)
2 L C
2
Case 1:
2 f V
L C
0
P-P
----------------------------------------------------------
FB
R
C
= R
C
0.66 V
C
IN
C
R
C
COMP
FB
0.66 V
IN
= -----------------------------------------------------
C
1
2 V
R f
0
P-P
FB
1
-------------------------------
2 L C
f < -------------------------------------
ISL6324A
0
2 C ESR
Case 2:
R
FB
2
2
V
2 f L C
0
PP
VSEN
----------------------------------------------------------------
FB
R
C
= R
(EQ. 49)
C
C
0.66 V
IN
0.66 V
IN
= --------------------------------------------------------------------------------------
2 f V
2
2
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6324A CIRCUIT
R
L C
0
P-P
FB
1
Case 3:
f > -------------------------------------
Since the system poles and zero are affected by the values of
the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C poles
and the ESR zero of the voltage mode approximation, yields a
solution that is always stable with very close to ideal transient
performance.
0
2 C ESR
2 f V
L
0
P-P
---------------------------------------------
R
C
= R
FB
C
C
0.66 V ESR
IN
0.66 V ESR
C
IN
= -----------------------------------------------------------------
2 V R f
0
L
P-P
FB
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled as
a voltage-mode regulator with two poles at the L-C resonant
frequency and a zero at the ESR frequency. A type-III
controller, as shown in Figure 24, provides the necessary
compensation.
Select a target bandwidth for the compensated system, f . The
0
target bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-channel
switching frequency. The values of the compensation
The first step is to choose the desired bandwidth, f , of the
0
components depend on the relationships of f to the L-C pole
0
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3 of
the switching frequency. The type-III compensator has an extra
frequency and the ESR zero frequency. For each of the
following three, there is a separate set of equations for the
compensation components.
high-frequency pole, f . This pole can be used for added noise
rejection or to assure adequate attenuation at the error amplifier
high-order pole and zero frequencies. A good general rule is to
HF
In Equation 49, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent series resistance of the bulk
choose f = 10f , but it can be higher if desired. Choosing f to
HF HF
0
output filter capacitance; and V
is the peak-to-peak
P-P
be lower than 10f can cause problems with too much phase shift
0
sawtooth signal amplitude as described in the “Electrical
Specifications” table on page 6.
below the system bandwidth as shown in Equation 50.
Once selected, the compensation values in Equation 49
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R . Slowly increase the
C
FN6880 Rev 1.00
May 14, 2010
Page 33 of 39
2
ISL6324A Hybrid SVI/PVI with I C
C
2
1
1
-------------------------------
f < -------------------------------------
0
2 C ESR
Case 2:
2 L C
2
2
C
C
V
2 f L C
0
R
C
P-P
COMP
FB
-----------------------------------------------------------------
FB
R
C
= R
(EQ. 51)
C
C
0.66 V
IN
0.66 V
IN
= --------------------------------------------------------------------------------------
2
2
2 f V
R
L C
C
0
P-P
FB
1
ISL6324A
R
R
FB
1
1
Case 3:
f > -------------------------------------
0
2 C ESR
VSEN
2 f V
L
0
P-P
---------------------------------------------
R
C
= R
FB
C
C
0.66 V ESR
IN
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
0.66 V ESR
C
IN
= -----------------------------------------------------------------
2 V R f
0
L
.
P-P
FB
C ESR
L C – C ESR
-------------------------------------------
FB
R
C
= R
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter limits the system transient response. The output
capacitors must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
1
1
(EQ. 50)
L C – C ESR
= -------------------------------------------
R
FB
0.75 V
IN
C
= --------------------------------------------------------------------------------------------------------
2
2
2 f f
L C R V
0
HF
FB P – P
2
2
f f
L C R
FB
V
0
HF
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit. Output
filter design begins with minimizing the cost of this part of the
circuit. The critical load parameters in choosing the output
capacitors are the maximum size of the load step, I, the load-
current slew rate, di/dt, and the maximum allowable output-
PP
R
C
= ----------------------------------------------------------------------------------------
C
C
2 f
L C–1
0.75
V
IN
HF
0.75 V 2 f
L C–1
IN
HF
= --------------------------------------------------------------------------------------------------------
2
2 f f
L C R V
0
HF
FB P – P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
voltage deviation under transient loading, V
. Capacitors
MAX
are characterized according to their capacitance, ESR, and ESL
(equivalent series inductance).
Equation 51, R is selected arbitrarily. The remaining
FB
compensation components are then selected according to
Equation 51.
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage drop
across the ESL. As the load current increases, the voltage
drop across the ESR increases linearly until the load current
reaches its final value. The capacitors selected must have
sufficiently low ESL and ESR so that the total output voltage
deviation is less than the allowable maximum. Neglecting the
contribution of inductor current and regulator response, the
output voltage initially deviates by an amount as shown in
Equation 52:
In Equation 51, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent-series resistance of the bulk
output-filter capacitance; and V
sawtooth signal amplitude as described in “Electrical
Specifications” on page 6.
is the peak-to-peak
P-P
Output Filter Design
1
------------------------------- > f
Case 1:
0
2 L C
di
dt
(EQ. 52)
----
V ESL + ESR I
2 f V
L C
0
P-P
----------------------------------------------------------
R
C
= R
C
C
FB
0.66 V
IN
The filter capacitor must have sufficiently low ESL and ESR so
that V < V
0.66 V
IN
.
MAX
= -----------------------------------------------------
2 V R f
0
P-P
FB
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited high-
frequency performance. Minimizing the ESL of the high-
FN6880 Rev 1.00
May 14, 2010
Page 34 of 39
2
ISL6324A Hybrid SVI/PVI with I C
frequency capacitors allows them to support the output voltage
as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with
less output voltage deviation.
10.61 – 1.035 logf
(EQ. 56)
S
R
= 10
T
1k
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source
the inductor AC ripple current (see “Interleaving” on page 11
and Equation 3), a voltage develops across the bulk capacitor
ESR equal to I
(ESR). Thus, once the output capacitors
C(P-P)
are selected, the maximum allowable ripple voltage, V
100
P-
, determines the lower limit on the inductance.
P(MAX)
V
V
– N V
IN
OUT
OUT
(EQ. 53)
L
-------------------------------------------------------------------
ESR
f
V V
IN P – PMAX
S
10
10k
100k
1M
10M
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
SWITCHING FREQUENCY (Hz)
FIGURE 25. R vs SWITCHING FREQUENCY
T
Input Capacitor Selection
before the output voltage decreases more than V
. This
MAX
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs which
is related to duty cycle and the number of active phases.
places an upper limit on inductance.
Equation 54 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 55
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually less
than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of the
two results. In each equation, L is the per-channel inductance,
C is the total output capacitance, and N is the number of active
channels.
0.3
I
I
= 0
= 0.25 I
I
I
= 0.5 I
O
L(P-P)
L(P-P)
L(P-P)
L(P-P)
= 0.75 I
O
O
0.2
0.1
0
2 N C V
O
(EQ. 54)
---------------------------------
L
V
– I ESR
MAX
2
I
N C
1.25
(EQ. 55)
– I ESR V – V
MAX IN O
----------------------------
L
V
2
I
Switching Frequency
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 28, and they establish the upper limit for the
switching frequency. The lower limit is established by the
requirement for fast transient response and small output-voltage
ripple as outlined in “Output Filter Design” on page 34. Choose
the lowest switching frequency that allows the regulator to meet
the transient-response requirements.
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V
V
)
O/ IN
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a 4-phase design, use Figure 26 to determine the
input-capacitor RMS current requirement set by the duty cycle,
maximum sustained output current (I ), and the ratio of the
O
peak-to-peak inductor current (I
) to I . Select a bulk
L(P-P)
O
capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated.
Switching frequency is determined by the selection of the
frequency-setting resistor, R . Figure 25 and Equation 56 are
T
provided to assist in selecting the correct value for R .
T
The voltage rating of the capacitors should also be at least
1.25x greater than the maximum input voltage. Figures 27 and
28 provide the same input RMS current information for
3-phase and two-phase designs respectively. Use the same
approach for selecting the bulk capacitor type and number.
FN6880 Rev 1.00
May 14, 2010
Page 35 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET turn
on and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitics and maximize suppression.
0.3
0.2
0.1
0
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes voltage
spikes across the interconnecting impedances and parasitic
circuit elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit and lead to device overvoltage stress.
Careful component selection, layout, and placement minimizes
these voltage spikes. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the upper
MOSFET was carrying channel current. During the turn-off,
current stops flowing in the upper MOSFET and is picked up by
the lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
I
I
I
= 0
L(P-P)
L(P-P)
L(P-P)
= 0.5 I
O
= 0.75 I
O
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V
V
)
IN/
O
FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
There are two sets of critical components in a DC/DC converter
using a ISL6324A controller. The power components are the most
critical because they switch large amounts of energy. Next are
small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across
all power trains. Equidistant placement of the controller to the
CORE and NB power trains it controls through the integrated
drivers helps keep the gate drive traces equally short, resulting
in equal trace impedances and similar drive capability of all sets
of MOSFETs.
0.3
I
I
= 0
I
I
= 0.5 I
O
L(P-P)
L(P-P)
= 0.25 I
= 0.75 I
O
L(P-P)
O
L(P-P)
0.2
0.1
0
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally
possible. Input high-frequency capacitors, C , should be placed
HF
close to the drain of the upper FETs and the source of the lower
FETs. Input bulk capacitors, CBULK, case size typically limits
following the same rule as the high-frequency input capacitors.
Place the input bulk capacitors as close to the drain of the upper
FETs as possible and minimize the distance to the source of the
lower FETs.
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V
V
)
IN/
O
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable to
the decoupling target, making use of the shortest connection
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
FN6880 Rev 1.00
May 14, 2010
Page 36 of 39
2
ISL6324A Hybrid SVI/PVI with I C
The critical small components include the bypass capacitors
layers with vias should also be avoided, but if so, use two vias
for interconnection when possible.
(C
) for VCC and PVCC, and many of the components
FILTER
surrounding the controller including the feedback network and
current sense components. Locate the VCC/PVCC bypass
capacitors as close to the ISL6324A as possible. It is especially
important to locate the components associated with the
feedback circuit close to their respective controller pins, since
they belong to a high-impedance circuit loop, sensitive to EMI
pick-up.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces
in as close proximity as possible to reduce their inductances.
Current Sense Component Placement and Trace
Routing
A multi-layer printed circuit board is recommended. Figure 28
shows the connections of the critical components for the
One of the most critical aspects of the ISL6324A regulator
layout is the placement of the inductor DCR current sense
components and traces. The R-C current sense components
must be placed as close to their respective ISEN+ and
ISEN- pins on the ISL6324A as possible.
converter. Note that capacitors C and C
could each
IN OUT
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from the
PHASE terminal to output inductors short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring.
The sense traces that connect the R-C sense components to
each side of the output inductors should be routed on the
bottom of the board, away from the noisy switching
components located on the top of the board. These traces
should be routed side by side, and they should be very thin
traces. It’s important to route these traces as far away from
any other noisy traces or planes as possible. These traces
should pick up as little noise as possible.
Routing UGATE, LGATE, and PHASE Traces
Thermal Management
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall
impedance and inductance. They should be sized to carry at
least one ampere of current (0.02” to 0.05”). Going between
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal GND
pad of the ISL6324A to the ground plane with multiple vias is
recommended. This heat spreading allows the part to achieve
its full thermal potential. It is also recommended that the
controller be placed in a direct path of airflow if possible to help
thermally manage the part.
© Copyright Intersil Americas LLC 2009-2010. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6880 Rev 1.00
May 14, 2010
Page 37 of 39
2
ISL6324A Hybrid SVI/PVI with I C
R
FB
C
2
+12V
+12V
C
C
R
C
R
C
3_2
IN
FB
C
VSEN
BOOT
C
BOOT
COMP
ISEN3+
ISEN3-
PWM3
C
IN
C
BOOT1
R
BOOT1
3
3_1
UGATE1
PHASE1
UGATE1
PHASE1
LGATE1
R
C
APA
R
1_1
APA
C
LGATE1
PGND
1
PWM1
APA
DVC
R
1_2
ISEN1-
ISEN1+
+12V
ISL6614
+12V
V_CORE
+5V
C
+12V
PVCC1_2
VCC
C
C
FILTER
FILTER
IN
BOOT2
PVCC
VCC
FS
C
IN
C
BOOT
C
BOOT
C
FILTER
BOOT2
C
C
BULK
HF
UGATE2
PHASE2
GND
UGATE2
R
FS
CPU
LOAD
PHASE2
LGATE2
PWM2
R
C
R
SET
R
4
4_1
C
2_1
2
LGATE2
RSET
R
4_2
R
2_2
VFIXEN
SEL
ISEN2-
ISEN2+
SVD
SVC
VID4
RGND
NC
NC
VID5
PWROK
VDDPWRGD
ISEN4+
ISEN4-
GND
SCL
SDA
PWM4
+12V
ISL6324A
+12V
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
PVCC_NB
R
EN1
EN2
C
C
FILTER
C
IN
EN
OFF
BOOT_NB
ON
BOOT_NB
R
UGATE_NB
V_NB
PHASE_NB
LGATE_NB
C
BULK
C
R
HF
1_NB
C
1_NB
RED COMPONENTS:
LOCATE CLOSE TO IC TO
MINIMIZE CONNECTION PATH
R
2_NB
NB
LOAD
ISEN_NB-
ISEN_NB+
BLUE COMPONENTS:
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
COMP_NB
FB_NB
R
C_NB
C_NB
C
MAGENTA COMPONENTS:
LOCATE CLOSE TO SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
R
FB_NB
FIGURE 29. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN6880 Rev 1.00
May 14, 2010
Page 38 of 39
2
ISL6324A Hybrid SVI/PVI with I C
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X
5.5
7.00
A
44X
6
0.50
B
PIN #1 INDEX AREA
37
48
6
1
36
PIN 1
INDEX AREA
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4
0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0 . 90 ± 0 . 1
BASE PLANE
( 6 . 80 TYP )
SEATING PLANE
0.08 C
(
4 . 30 )
SIDE VIEW
( 44X 0 . 5 )
0 . 2 REF
5
C
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6880 Rev 1.00
May 14, 2010
Page 39 of 39
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4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
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ISL6326B
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_2.jpg)
ISL6326BCRZ
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_2.jpg)
ISL6326BCRZ-T
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_2.jpg)
ISL6326BIRZ
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326B_526989_files/ISL6326B_526989_2.jpg)
ISL6326BIRZ-T
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326CRZ_526990_files/ISL6326CRZ_526990_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00099/img/page/ISL6326CRZ_526990_files/ISL6326CRZ_526990_2.jpg)
ISL6326CRZ
4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision DCR Differential Current Sensing
INTERSIL
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