ISL6398IRTZ-TK_技术文档

DATASHEET

ISL6398

FN8575

Rev 1.00

Aug 13, 2015

Advanced Linear EAPP Digital 6-Phase Green PWM Controller for Digital Power

Management with NVM and AUTO Phase Shedding

The ISL6398 is a smart and smallest 6-Phase Green PWM

Features

controller, designed for networking, datacenter, and POL

2

• SMBus/PMBus/I C Compatible

applications. It includes programmable functions and

telemetries for easy use and system flexibility using SMBus,

PMBus, or I C interface, which is designed to program NVM

banks up to 8 different compensations and system

parameters. This minimizes external components and

significantly reduces design complexity and PCB area, and

simplifies the manufacturing process.

- Programmable IMAX, TMAX, BOOT, and address

- Programmable soft-start rate and DVID rate

- Up to 1.5MHz

2

- NVM to store up to 8 Configurations with programmable

frequency, droop, auto, faults (OCP, UVP, CFP), etc.

- No firmware requirement and hassle

The ISL6398 utilizes Intersil’s proprietary Advanced Linear EAPP

(Enhanced Active Pulse Positioning) Digital control scheme to

achieve the extremely fast linear transient response with fewer

output capacitors and overcomes many hurdles of traditional

digital approach, which uses non-linear, discrete control method

for both voltage loop and current balance loop and runs into beat

frequency oscillation and non-linear response. The ISL6398

accurately monitors the load current via the IMON pin and

reports this information via the READ_IOUT register for power

management. The ISL6398 features auto-phase shedding. In low

power operation, the magnetic core and switching losses are

significantly reduced with lower phase count operation, yielding

high efficiency at light load. When APA is triggered, the dropped

phase(s) are added back to sustain heavy load transient

response and efficiency. It optimizes the efficiency from light to

full load for Greener Environment without sacrificing the transient

performance.

• Advanced Linear EAPP Digital control scheme (patented)

- Digitally programmable compensation

- Auto phase shedding option for greener environment

- Variable frequency control during load transients to

reduce beat frequency oscillation

- Linear control with evenly distributed PWM pulses for

better phase current balance during load transients

- Voltage feed-forward and ramp adjustable options

- High frequency compensation option

- Active phase adding and dropping for enhanced light load

efficiency

• Phase doubler and coupled-inductor compatibility

• Differential remote voltage sensing with ±0.5% accuracy

• Programmable minimum phase count operation

• Programmable slew rate of dynamic VID with dynamic VID

compensation (DVC)

The ISL6398 senses the output current continuously by a

dedicated current sense resistor or the DCR of the output

inductor. The sensed current flows through a digitally

programmable 1% droop resistor for precision load line control.

Current sensing circuits also provide the needed signals for

channel-current balancing, average overcurrent protection and

individual phase current limiting. The TM pin senses an NTC

thermistor’s temperature, which is internally digitized for thermal

monitoring and for integrated thermal compensation of the

current sense elements of the regulator.

• Support 3-state 5V or 3.3V PWM DrMOS and driver

• Zero current shutdown with ISL6627

• Precision resistor or DCR differential current sensing

- Accurate load-line (Droop) programming and control

- Accurate current monitoring and channel-current

balancing with calibration capability

• True input current sensing for catastrophic failure protection

• Average overcurrent protection and channel current limiting

• High common mode current sense input (VCC-1.5V)

• Open sensing and single point of loop failure protection

• Thermal monitoring and integrated compensation

• 1- to 6-Phase option and up to 2MHz per phase

• Start-up into precharged load

The ISL6398 features remote voltage sensing and completely

eliminates any potential difference between remote and local

grounds. This improves regulation and protection accuracy. The

threshold-sensitive enable input is available to accurately

coordinate the start-up of the ISL6398 with other voltage rails.

• Pb-free (RoHS Compliant)

• 40 Ld 5x5 Plastic Package

Applications

• High efficiency and high density digital power

• High performance multi-phase POL and network

• Cloud Computing, Router, Data Center and Storage

• General processor power

FN8575 Rev 1.00

Aug 13, 2015

Page 1 of 57

ISL6398

Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . 26

Table of Contents

VR_Ready Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Thermal Monitoring (VR_HOT#) . . . . . . . . . . . . . . . . . . . . . . . 27

Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Integrated Temperature Compensation . . . . . . . . . . . . . . . . 29

Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Dynamic VID Compensation (DVC) . . . . . . . . . . . . . . . . . . . . . . . . .30

Programmable Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Catastrophic Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . 30

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Driver Recommendation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ISL6398 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 5

Typical Application: 6-Phase VR with DrMOS and

2

PMBus/SMBus/I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typical Application: 4-Phase VR with DrMOS and

2

PMBus/SMBus/I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Application: 6-Phase VR for General Processor

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Input Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Auto-phase Shedding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Resistor Reader (Patented) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Typical Application: 12-Phase VR for Over-clocking

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .10

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Recommended Operating Conditions . . . . . . . . . . . . . . . . .10

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . .14

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2

SMBus, PMBus and I C Operation . . . . . . . . . . . . . . . . . . . . 35

General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Current Sensing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Load-line Regulation Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 51

Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . 52

Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PWM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DrMOS and Driver Compatibility . . . . . . . . . . . . . . . . . . . . . . . 17

Phase Doubler Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Precharged Start-up Capability . . . . . . . . . . . . . . . . . . . . . . . . 17

Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Layout and Design Considerations . . . . . . . . . . . . . . . . . . . . . . 53

Pin Noise Sensitivity, Design and Layout Consideration . . . 53

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Powering Up And Open-Loop Test . . . . . . . . . . . . . . . . . . . . 55

Voltage Regulator (VR) Design Materials. . . . . . . . . . . . . . 55

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

R

and L/DCR Matching for Coupled inductor. . . . . . . . . . 19

SET

Channel-current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Voltage Regulation (5mV and 10mV Mode). . . . . . . . . . . . . . 20

Load-line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dynamic VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Current Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FN8575 Rev 1.00

Aug 13, 2015

Page 2 of 57

ISL6398

Ordering Information

PART NUMBER

PART

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 2, 3)

MARKING

ISL6398HRTZ

ISL6398 HRTZ

ISL6398 IRTZ

-10 to +100

-40 to +85

40 Ld 5x5 TQFN

L40.5x5

ISL6398IRTZ

ISL6398EVAL1Z

NOTES:

120A 3-Phase Evaluation Board with On Board Transient

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6398. For more information on MSL please see techbrief TB363.

Pin Configuration

ISL6398

(40 LD 5X5 TQFN)

TOP VIEW

35

32 31

40 39 38 37

36

34

33

ISEN6-

ISEN6+

ISENIN-

1

2

30 PWM6

29

28

27

26

25

24

PWM3

PWM1

3

4

PWM4

PWM2

ISENIN+

EN_PWR_CFP

RGND

5

GND

6

PWM5

7

VSEN

VCC

VSEN_OVP

8

23

22

RSET

9

VRSEL_ADDR

AUTO

10

NVM_BANK_BT

21

TM_EN_OTP

11

12 13 14 15 16 17 18 19 20

FN8575 Rev 1.00

Aug 13, 2015

Page 3 of 57

ISL6398

Driver Recommendation

QUIESCENT

CURRENT (mA)

GATE DRIVE

# OF

DRIVERS

DIODE EMULATION

(DE)

DRIVER

ISL6627

(V)

COMMENTS

1.0

5V

Single

Yes

For dropped phases or all channels with Diode Emulation

(DE) for low stress shutdown or phase dropping.

ISL6596

0.19

0.24

5V

Single

Dual

No

For dropped phases or all channels without DE.

ISL6610

ISL6610A

ISL6611A

ISL6617

1.25

5.0

5V

N/A

5V

Dual

N/A

No

Phase Doubler with Integrated Drivers, up to 12-Phase. For

all channels with DE Disabled.

PWM Doubler for DrMOS, up to 12- or 24-Phase. For all

channels with DE Disabled.

ISL99140

0.47

Single

Yes

DrMOS with 40A current capability. ISL99140’s diode

emulation is not compatible with ISL6398. Both DrMOS and

ISL6398 should disable their diode emulation operation.

NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow for dual footprint layout implementation to optimize MOSFET selection and

efficiency. The 5V Drivers are more suitable for high frequency and high power density applications.

FN8575 Rev 1.00

Aug 13, 2015

Page 4 of 57

ISL6398

ISL6398 Internal Block Diagram

RSET

HIGH SPEED AND

HIGH FREQUENCY

ISEN1+

BALANCE

ISEN1-

PWM1

ISEN2+

ISEN2-

TEMPERATURE

COMPENSATION

LINEAR CONTROL

EAPP PWM

MODULATOR

PWM2

PWM3

PWM4

ISEN3+

ISEN3-

ISEN4+

CHANNEL

CURRENT

SENSE

PWM

DRIVERS

DIGITAL

COMPENSATION:

DROOP, DVID,

PSICOMP, AUTO,

THERMAL COMP

PWM5

PWM6

ISEN4-

ISEN5+

ISEN5-

ISEN6+

ISEN6-

AVERAGE

OVERCURRENT AND

CYCLE-BY-CYCLE

CURRENT LIMITING

PROTECTION

RGND

VSEN

OUTPUT VOLTAGE

SENSE

VSEN_OVP

DAC (VID AND OFFSET)

AND SOFT-START

VR_RDY

PROTECTION

FEEDFORWARD

CLOCK AND RAMP

CONTROL

REAL-TIME AND

HIGH-SPEED

VR_HOT#

FAULT LOGIC

ISENIN+

ISENIN-

INPUT I/V

SENSE

STATE MACHINE

TEMP SENSE

TM_EN_OTP

INTERFACES

CONTROL, MONITOR

REGISTERS, TELEMETRY

AND CALIBRATION

POWER-ON

RESET (POR)

VCC

IMON

AUTO

AUTO PHASE

CONTROL

EN_PWR_CFP

SM_PM_I2CLK

SM_PM_ALERT#

SM_PM_I2DATA

CORE/MEMORY

ADDRESS AND

NVM

VRSEL_ADDR

PMBus

NVM_BANKS_BT

BANKS CONTROL

NVM

ADC

FN8575 Rev 1.00

Aug 13, 2015

Page 5 of 57

ISL6398

2

Typical Application: 6-Phase VR with DrMOS and PMBus/SMBus/I C

+5V

VCC

VSEN_OVP

VSEN

VIN

RGND

VINF

R_SENIN

R_ISENIN2

R_ISENIN1

ISENIN-

ISENIN+

VR_RDY

VR_HOT#

VINF

+5V

ISL99140

UG

SM_PM_I2DA

VCC

BOOT

PHASE

SM_PMALERT#

SM_PM_I2CLK

PWM1

PWM

LG

VINF

ISEN1-

ISEN1+

EN_PWR_CFP

VINF

+5V

ISL99140

UG

BOOT

PHASE

VCC

CFP

ISL6398

PWM4

PWM

LG

IMON

ISEN4-

ISEN4+

+5V

PWM2,5

ISEN2,5-

NVM_BANKS_BT

VRSEL_ADDR

2X

ISEN2,5+

+5V

VINF

AUTO

ISL99140

UG

LOAD

BOOT

PHASE

VCC

PWM3

PWM

LG

RSET

ISEN3-

ISEN3+

VINF

+5V

ISL99140

UG

BOOT

PHASE

VCC

TM_EN_OTP

PWM6

PWM

LG

NTC

ISEN6-

ISEN6+

GND

NTC: BETA = 3477

NTC1 NETWORK IS NOT NEEDED

IF TMS IS USED FOR VR1, GPU

FN8575 Rev 1.00

Aug 13, 2015

Page 6 of 57

ISL6398

2

Typical Application: 4-Phase VR with DrMOS and PMBus/SMBus/I C

+5V

VCC

VSEN_OVP

VSEN

VIN

VINF

RGND

R_SENIN

R_ISENIN2

R_ISENIN1

ISENIN-

ISENIN+

VR_RDY

VINF

+5V

VR_HOT#

ISL99140

UG

BOOT

PHASE

VCC

SM_PM_I2DA

SM_PMALERT#

SM_PM_I2CLK

PWM1

PWM

LG

VINF

ISEN1-

ISEN1+

EN_PWR_CFP

VINF

+5V

ISL99140

UG

VCC

BOOT

PHASE

ISL6398

CFP

PWM3

PWM

LG

IMON

ISEN3-

ISEN3+

+5V

VINF

+5V

ISL99140

UG

BOOT

PHASE

VCC

NVM_BANK_BT

VRSEL_ADDR

2X

PWM2

PWM

LG

AUTO

LOAD

ISEN2-

ISEN2+

VINF

+5V

ISL99140

UG

RSET

BOOT

PHASE

VCC

PWM4

ISEN4-

PWM

LG

+5V

ISEN4+

PWM6

TM_EN_OTP

NTC

OPEN

ISEN5,6+

ISEN5,6-

PWM5

NTC: BETA = 3477

VCC

GND

NTC1 NETWORK IS NOT NEEDED

IF TMS IS USED FOR VR1, GPU

FN8575 Rev 1.00

Aug 13, 2015

Page 7 of 57

ISL6398

Typical Application: 6-Phase VR for General Processor Power

+5V

VCC

VSEN_OVP

VSEN

VIN

VINF

RGND

R_SENIN

R_ISENIN2

R_ISENIN1

ISENIN-

ISENIN+

VINF

VR_RDY

BOOT

UGATE

VR_HOT#

+5V

SM_PM_I2DA

VCC

PHASE

GND

ISL6627

DRIVER

SM_PMALERT#

SM_PM_I2CLK

LGATE

PWM1

VINF

ISEN1-

ISEN1+

EN_PWR_CFP

VINF

CFP

BOOT

+5V

ISL6398

UGATE

VCC

PHASE

GND

ISL6627

DRIVER

IMON

LGATE

PWM4

+5V

ISEN4-

ISEN4+

NVM_BANK_BT

VRSEL_ADDR

2X

AUTO

LOAD

PWM2,3,5

ISEN2,3,5-

ISEN2,3,5+

RSET

VINF

BOOT

+5V

UGATE

VCC

PHASE

GND

ISL6627

DRIVER

TM_EN_OTP

NTC

LGATE

PWM6

ISEN6-

ISEN6+

GND

NTC: BETA = 3477

FN8575 Rev 1.00

Aug 13, 2015

Page 8 of 57

ISL6398

Typical Application: 12-Phase VR for Over-clocking Applications

+12V

+5V

ISL99140

+5V

V

IN

V

CC

PWMA

PWM PHASE

GND

+5V

EN_PH_SYNC

+5V

V

+5V

V

ISENA-

CC

PWMA

ISENA+

ISENB+

CC

PWMIN

ISENB-

EN_PH_SYNC

+12V

ISL99140

VSEN_OVP

VSEN

ISL6617

VIN

PWM PHASE

GND

V

ISENA-

ISENA+

I

O

OUT

PWMB

RGND

GND

LOAD

+12V

PWMIN

PWM1

+5V

ISL99140

+5V

V

IN

V

CC

ISL6617

PWM PHASE

GND

PWMA

EN_PH_SYNC

I

ISEN1-

ISEN1+

OUT

I

ISENB-

ISENB+

OUT

ISENA-

ISENA+

ISENB+

ISL99140

MAIN

ISENB-

PWMIN

PWMB

GND

CONTROL

ISL6398

+12V

PWM

V

IN

PHASE

ISL6617

PWMB

GND

PWM2-5

+12V

+5V

ISEN2-5-

ISL99140

+5V

ISEN2-5+

V

IN

V

CC

PWMA

PWM PHASE

GND

+5V

EN_PH_SYNC

EN_PH_SYNC2

ISENA-

V

CC

PWMA

ISENA+

ISENB+

PWMIN

ISL99140

ISENB-

EN_PH_SYNC

+12V

ISL6617

V

IN

ISENA-

ISENA+

I

OUT

PWMB

PWM PHASE

GND

PWMIN

+12V

PWM6

+5V

ISL99140

+5V

V

IN

V

CC

ISL6617

PWM PHASE

GND

PWMA

ISEN6-

ISEN6+

EN_PH_SYNC

I

OUT

ISENB-

ISENB+

I

OUT

ISENA-

ISENA+

ISENB+

GND

ISL99140

ISENB-

PWMB

PWMIN

+12V

V

ISL6617

PWMB

GND

IN

PWM PHASE

GND

FN8575 Rev 1.00

Aug 13, 2015

Page 9 of 57

ISL6398

Absolute Maximum Ratings

Thermal Information

VCC, VR_RDY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V

ISENIN± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to 27V

Thermal Resistance (Notes 4, 5)

40 Ld 5x5 TQFN Package . . . . . . . . . . . . . .



(°C/W)

29



(°C/W)

1

JA

JC

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to V + 0.3V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

CC

Recommended Operating Conditions

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

CC

EEPROM Write and Store Command Temperature . . . . . .-40°C to +85°C

Ambient Temperature

ISL6398HRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

ISL6398IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, V = 5V, Unless Otherwise specified. Boldface limits apply across the

CC

operating temperature range.

MIN

MAX

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

V

CC

Nominal Supply

Shutdown Supply

V

= 5VDC; EN_PWR = 5VDC; F

= 400kHz

-

35

27

45

33

mA

CC

SW

= 5VDC; EN_PWR = 0VDC; F

= 400kHz

CC

POWER-ON RESET AND ENABLE

V

Rising POR Threshold

Falling POR Threshold

4.22

4.00

3.5

4.35

4.10

3.6

4.55

4.22

3.7

V



V

CC

EN_PWR_CFP High Level Turn-OFF Threshold

EN_PWR_CFP High Level Turn-ON Threshold

EN_PWR_CFP Latch-OFF Level

Externally Driven

3.33

4.80

-

3.52

-

3.58

-

Internally Driven, 5mA Load

EN_PWR_CFP Internal Pull-Up Impedance

EN_PWR_CFP Rising Threshold

12

34

0.83

0.70

0.85

0.77

0.87

0.84

EN_PWR_CFP Falling Threshold

DAC (VID+OFFSET)

DAC = 1.5V to 3.04 V

DAC = 0.8V to 1.49V

DAC = 0.25V to 0.795V

DAC = 1.5V to 3.04 V

DAC = 0.8V to 1.49V

DAC = 0.25V to 0.795V

DAC = 1.5V to 3.04 V

DAC = 0.8V to 1.49V

DAC = 0.25V to 0.795V

-0.5

-5

-

0.5

5

%VID

mV

System Accuracy of Commercial Temperature

(T = 0°C to +70°C, Note 6, Closed-Loop)

J

-8

8

mV

-0.55

-7

0.55

7

%VID

mV

System Accuracy of ISL6398HRTZ

(T = -10°C to +100°C, Note 6, Closed-Loop)

J

-9

9

mV

-0.6

-10

0.6

10

%VID

mV

System Accuracy of ISL6398IRTZ

(T = -40°C to +85°C, Note 6, Closed-Loop)

J

mV

FN8575 Rev 1.00

Aug 13, 2015

Page 10 of 57

ISL6398

Electrical Specifications Recommended Operating Conditions, V = 5V, Unless Otherwise specified. Boldface limits apply across the

CC

operating temperature range. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

OSCILLATORS

390kHz, F3[2:0] = 0h = Original, ISL6398HRTZ

390kHz, F3[2:0] = 0h = Original, ISL6398IRTZ

355

348

-

390

425

kHz

Accuracy of Switching Frequency Setting

390

425

2.025

-

MHz

Maximum Switching Frequency

Minimum Switching Frequency

-

0.120

-

MHz

DVID = 0.3125mV/µs, Minimum

DVID = 2.5mV/µs

0.3125

2.5

-

3.0

6.0

-

3.4

7.0

-

mV/µs

%

Soft-start Ramp Rate

DVID = 5.0mV/µs

5.0

DVID = 13.25mV/µs, Maximum

DVID = 0.3125mV/µs, Minimum

DVID = 13.25mV/µs, Maximum

390kHz

13.25

0.3125

13.25

95

Minimum Dynamic VID Slew Rate

Maximum Dynamic VID Slew Rate

Maximum Duty Cycle Per PWM

PWM GENERATOR

-

98

99

VR

= 0.7V, ISENIN+ = 12V

= 1.0V, ISENIN+ = 12V

= 1.2V, ISENIN+ = 12V

= 1.5V, ISENIN+ = 12V

-

0.7

1.0

1.2

1.5

-

V

RAMP_ADJ

Sawtooth Amplitude

BUFFERED COMP AMPLIFIER

Open-Loop Gain

R = 10k to ground

-

96

20

-

dB

MHz

V

L

-

Open-Loop Bandwidth

Maximum Output Voltage

Output High Voltage

No Load

3.6

3.4

1.88

4.0

3.9

-

1mA Load

V

Output Low Voltage

1.99

V

PWM OUTPUT (PWM[6:1])

PWM = Low with 1mA Load, for Fast Transition

PWM = Low with 1mA Load, ISL6398HRTZ

PWM = Low with 1mA Load, ISL6398IRTZ

PWM = High, Forced to 3.7V

-

80

285

125

40

-



PWM[6:1] Sink Impedance

170

60

425

400

210

44



PWM[6:1] Source Impedance

PWM Mid-Level



0.4mA Load, 5V PWM

36

%VCC

PWM Mid-Level

0.4mA Load, 3.3V PWM

24

28

31

CURRENT SENSE AND OVERCURRENT PROTECTION

Sensed Current Tolerance

CS Offset and Mirror Error Included,

(T = 0°C to +70°C)

73

72

78

82.5

83

µA

J

(T = -40°C to +100°C, HRTZ, IRTZ)

J

R

= 12.8k

SET

Average OC Trip Level at Normal CCM PWM Mode (T = 0°C to +70°C)

J

96

95

103

111

112

µA

CS Offset and Mirror Error Included,

(T = -40°C to +100°C, HRTZ, IRTZ)

J

R

= 12.8k

SET

Average Overcurrent Trip Level at PSI1/2/3 Mode (T = 0°C to +70°C)

J

92

90

107

125

122

124

µA

CS Offset and Mirror Error Included,

(T = -40°C to +100°C, HRTZ, IRTZ)

J

R

= 12.8k

SET

FN8575 Rev 1.00

Aug 13, 2015

Page 11 of 57

ISL6398

Electrical Specifications Recommended Operating Conditions, V = 5V, Unless Otherwise specified. Boldface limits apply across the

CC

operating temperature range. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

Peak Current Limit for Individual Channel

CS Offset and Mirror Error Included,

(T = 0°C to +70°C)

118

116

125

133

134

µA

J

(T = -40°C to +100°C, HRTZ, IRTZ)

J

R

= 12.8k

SET

IMON OCP Trip Level

2.9

2.45

-

3.0

2.5

10

3.1

2.56

-

V

IMON VOLTAGE IMAX (FF) TRIP POINT

READ_IIN (1F) Maximum Threshold

Input Peak Current Trip Level

Higher than this will be “FF”

µA

13.9

15

16.5

THERMAL MONITORING

VR_HOT# Pull-down Impedance

TM Voltage at VR_HOT# Trip

-

9.2

39.12

3

13



%VCC

°C

µA

V

TMAX = +100°C (see Table 6), Programmable via Tmax

-

VR_HOT# and Thermal Alert# Hysteresis

Leakage Current of VR_HOT#

-

With external pull-up resistor connected to V

-

1

CC

Over-Temperature Shutdown Threshold

Over-Temperature Shutdown Reset Threshold

VR READY AND PROTECTION MONITORS

Leakage Current of VR_RDY

0.91

1.04

0.94

1.07

0.97

1.11

V

With pull-up resistor externally connected to V

4mA Load

-

1

µA

V

CC

VR READY Low Voltage

-

0.3

146

191

236

281

330

378

426

519

72

Voltage below VID E1[3:0] = 0h)

Voltage below VID E1[3:0] = 1h)

Voltage below VID E1[3:0] = 2h)

Voltage below VID E1[3:0] = 3h)

Voltage below VID E1[3:0] = 4h)

Voltage below VID E1[3:0] = 5h)

Voltage below VID E1[3:0] = 6h)

Voltage below VID E1[3:0] = 7h)

Voltage below VID E1[3:0] = 0h)

Voltage below VID E1[3:0] = 1h)

Voltage below VID E1[3:0] = 2h)

Voltage below VID E1[3:0] = 3h)

Voltage below VID E1[3:0] = 4h)

Voltage below VID E1[3:0] = 5h)

Voltage below VID E1[3:0] = 6h)

Voltage below VID E1[3:0] = 7h)

Higher than UVP

65

105

141

178

214

252

291

328

402

41

mV

93

121

149

177

207

233

288

10

Undervoltage Protection Threshold (UVP)

Can Be Disabled by DFh

35

72

109

146

186

226

268

307

389

-

61

103

135

168

202

234

298

19

84

Undervoltage Warning Threshold (UVP Warning)

Can Be Disable by DFh

109

133

157

201

-

Undervoltage Protection Reset Hysteresis

Undervoltage Warning Reset Hysteresis

Higher than UVP Warning

-

17

-

FN8575 Rev 1.00

Aug 13, 2015

Page 12 of 57

ISL6398

Electrical Specifications Recommended Operating Conditions, V = 5V, Unless Otherwise specified. Boldface limits apply across the

CC

operating temperature range. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 7) TYP (Note 7) UNITS

Prior to the End of Soft-start (D8h[4:3] = 0h)

1.51

1.75

2.20

3.10

91

1.58

1.86

2.29

3.32

135

177

218

260

342

425

460

549

110

83

1.70

1.95

2.40

3.50

177

225

274

323

424

526

580

697

180

-

V

Prior to the End of Soft-start (D8h[4:3] = 1h)

V

Prior to the End of Soft-start (D8h[4:3] = 2h)

V

Prior to the End of Soft-start (D8h[4:3] = 3h)

V

End of Soft-start, the voltage above VID D8[2:0] = 0h)

End of Soft-start, the voltage above VID D8[2:0] = 1h)

End of Soft-start, the voltage above VID D8[2:0] = 2h)

End of Soft-start, the voltage above VID D8[2:0] = 3h)

End of Soft-start, the voltage above VID D8[2:0] = 4h)

End of Soft-start, the voltage above VID D8[2:0] = 5h)

End of Soft-start, the voltage above VID D8[2:0] = 6h)

End of Soft-start, the voltage above VID D8[2:0] = 7h)

Prior to the end of Soft-start, lower than OVP

During operation, lower than OVP

mV

125

158

191

254

318

347

395

55

Overvoltage Protection Threshold (OVP)

Can Be Disabled by DFh

Overvoltage Protection Reset Hysteresis

-

End of Soft-start, the voltage above VID D8[2:0] = 0h)

End of Soft-start, the voltage above VID D8[2:0] = 1h)

End of Soft-start, the voltage above VID D8[2:0] = 2h)

End of Soft-start, the voltage above VID D8[2:0] = 3h)

End of soft-start, the voltage above VID D8[2:0] = 4h)

End of soft-start, the voltage above VID D8[2:0] = 5h)

End of soft-start, the voltage above VID D8[2:0] = 6h)

End of soft-start, the voltage above VID D8[2:0] = 7h)

Lower than OVP Warning

22

54

83

60

96

129

176

225

324

427

476

578

-

97

138

179

264

347

389

474

42

132

205

273

308

377

-

Overvoltage Warning Threshold (OVP)

Can Be Disabled by DFh

Overvoltage Warning Reset Hysteresis

2

SMBus/PMBus/I C

Signal Input Low Voltage

Signal Input High Voltage

Signal Output Low Voltage

ALERT# Pull-down Impedance

DATA Pull-down Impedance

CLOCK Maximum Speed

CLOCK Minimum Speed

Time-out

-

0.8

VCC

0.4

50

V

2.1

-

4mA loading on Alert#

-

V

-

28

-

Ω

50

Ω

1.5

-

MHz

ms

-

0.05

35

25

30

EEPROM

Number of NVM_BANK

NVM_BANK Loading Time

NOTES:

-

8

-

Including POR delay and Resistor Reading Time

16

20

ms

6. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN8575 Rev 1.00

Aug 13, 2015

Page 13 of 57

ISL6398

RGND - This pin compensates the offset between the remote

ground of the load and the local ground of this device for

precision regulation. Connect this pin to the negative rail remote

sensing point of the microprocessor or load.

Functional Pin Descriptions

Refer to Table 19 on page 53 for Design and Layout

Considerations.

VCC - Supplies the power necessary to operate the chip. Connect

this pin directly to a +5V supply with a high quality ceramic

bypass capacitor. The controller start to operate, when the

voltage on this pin exceeds the rising POR threshold and shuts

down when the voltage on this pin drops below the falling POR

threshold.

VR_RDY - VR_RDY indicates that soft-start has completed and the

output remains in normal operation. It is an open-drain logic output.

When OCP, UVP, OVP, or CFP occurs, VR_RDY is pulled low.

TM_EN_OTP - Input pin for the temperature measurement.

Connect this pin through an NTC thermistor to GND and a resistor

to VCC of the controller. The voltage at this pin is inversely

proportional to the VR temperature. The device monitors the VR

temperature based on the voltage at the TM pin. Combined with

“TCOMP” setting, the sensed current is thermally compensated.

The VR_HOT# asserts low if the sensed temperature at this pin is

higher than the maximum desired temperature, “TMAX”. The NTC

should be placed close to the current sensing element, the output

inductor or dedicated sense resistor on Phase 1. A decoupling

capacitor (0.1µF) is typically needed in close proximity to the

controller. In addition, the controller is disabled when this pin’s

voltage drops below 0.95 (typically) and is active when it is above

1.05V (typically); it can serve as Enable and Over-Temperature

functions, however, when it is used as an Enable toggle input,

bit2 of STATUS_BYTE (78h) will flag OT; CLEAR_FAULTS (03h)

command must be sent to clear the fault after VR start-up. If not

GND - The bottom metal base of ISL6398 is return of VCC supply.

It is also the return of the PMBus as well as all PWM output

drivers. Connect it to system ground; also externally connect pins

13, 14, and 15 to system GND.

ISENIN+, ISENIN- - These pins are current sense inputs to the

differential amplifier of the input supply. The sensed current is

used for input power monitoring and power management of the

system. When not used, connect ISENIN+ to VIN and a resistor

divider with a ratio of 1/3 on ISENIN± pin, say 499kΩ in between

ISENIN± pins and then 1.5MΩ from ISENIN- to ground

(see Figure 29). Refer to “Input Current Sensing” on page 30 for

configuration details. Regardless input current sense is used or

not, ISENIN+ should be connected to input voltage (V ) for

IN

feed-forward compensation to maintain a constant loop gain

over the input line variation.

used, connect a 1MΩ/2MΩ resistor divider or tie to V

.

CC

PWM[6:1] - Pulse width modulation outputs. Connect these pins

to the PWM input pins of the Intersil driver IC(s). The number of

active channels is determined by the state of PWM[6:2]. Tie

PWM(N+1) to VCC to configure for N-phase operation. The PWM

firing order is sequential from 1 to N with N being the number of

active phases. If PWM1 is tied high, the VR is disabled.

EN_PWR_CFP - This pin is a threshold-sensitive enable input and

a catastrophic failure protection (CFP) output. Connecting the

power train input supply to this through an appropriate resistor

divider provides input undervoltage protection and a means to

synchronize the power sequencing of the controller and the

MOSFET driver ICs. When EN_PWR_CFP is driven above 0.85V

but below 3.3V, the controller is actively depending on status of

the TM_EN_OTP, the internal POR, and pending fault states.

Driving EN_PWR_CFP below 0.75V or above 3.7V will turn off the

controller, clear all fault states (except for CFP fault) and prepare

the ISL6398 to soft-start when re-enabled. In addition, this pin

will be latched high (VCC) by the input overcurrent (monitored by

ISENIN±) or VR overvoltage event. The latch resets by cycling VCC

and cannot reset by TM_EN_OTP or EN_PWR_CFP since when the

catastrophic failure (CFP) is triggered, the input power is

removed from VR so is the VTT voltage rail and it is PGOOD

signal. To keep CFP active, VCC should be biased with a standby

supply. This feature means to provide protection to the case that

the VR with shorted high-side MOSFET draws insufficient current

to trigger the input supply’s over current trip level, this pin will

send an active high signal (CFP) to disconnect the input supply

before catching fire or further damage of PCB. Refer

ISEN[6:1]+, ISEN[6:1] - The ISEN+ and ISEN- pins are current

sense inputs to individual differential amplifiers of VR. The

sensed current is used for channel current balancing, overcurrent

protection, and droop regulation. Inactive channels should have

their respective current sense inputs, ISEN[6:#]- grounded, and

ISEN[6:#]+ open. For example, ground ISEN[6:5]- and open

ISEN[6:5]+ for 4-phase operation. DO NOT ground ISEN[6:1]+. For

DCR sensing, connect each ISEN- pin to the node between the RC

sense elements. Tie the ISEN+ pin to the other end of the sense

capacitor (typically output rail). The voltage across the sense

capacitor is proportional to the inductor current. Therefore, the

sensed current is proportional to the inductor current and scaled

by the DCR of the inductor and R

.

SET

BUF_COMP - Buffered output of internal COMP.

VR_HOT# - Indicator of VR temperature reaching above TMAX set

by PMBus E8[2:0]. It is an open-drain logic output. Normally open

if the measured VR temperature is less than TMAX, and pulled

low when the measured VR temperature exceeds TMAX.

“Catastrophic Fault Protection” on page 30 for more details.

VSEN_OVP - This pin monitors the regulator output for

overvoltage protection. Connect this pin to the positive rail

remote sensing point of the microprocessor or load. This pin

tracks with the VSEN pin. If a resistive divider is placed on the

VSEN pin, a resistive divider with the same ratio should be placed

on the VSEN_OVP pin to track UVP and OVP.

RSET - A resistor connected from this pin to ground sets the

current gain of the current sensing amplifier. The RSET resistor

value can be set from 3.84k to 60.4k and is 64x of the

equivalent R

resistor value. Therefore, the effective current

ISEN

sense resistor value can be set between 60 and 943.

VSEN - This pin compensates the voltage drop between the load

and local output rail for precision regulation. Connect this pin to

the positive rail remote sensing point of the microprocessor or

load. It also is the APA level sensing input.

FN8575 Rev 1.00

Aug 13, 2015

Page 14 of 57

ISL6398

IMON - IMON is the output pin of sensed, thermally compensated

(if internal thermal compensation is used) average current of VR0.

The voltage at the IMON pin is proportional to the load current and

the resistor value. When it reaches to 3.0V, it initiates an overcurrent

shutdown, while 2.5V IMON voltage corresponds to READ_IOUT

(8Ch) maximum reading. By choosing the proper value for the

resistor at IMON pin, the overcurrent trip level can be set lower than

the fixed internal overcurrent threshold. During dynamic VID, the

OCP function of this pin is disabled to avoid false triggering. Tie it to

GND if not used. Refer to “Current Sense Output” on page 25 for

more details.

Multiphase Power Conversion

High Power processor load current profiles have changed to the

point that the advantages of multiphase power conversion are

impossible to ignore. The technical challenges associated with

producing a single-phase converter (which are both cost-effective

and thermally viable), have forced a change to the cost-saving

approach of multiphase. The ISL6398 controller helps reduce the

complexity of implementation by integrating vital functions and

requiring minimal output components. The typical application

circuits diagrams on pages 6 through 9 provide the top level views of

multiphase power conversion using the ISL6398 controller.

AUTO - A resistor from the pin to ground sets the current

Interleaving

threshold of phase dropping for operation. The AUTO mode can be

permanently disabled by pulling this pin to ground or PMBus D4h[2].

See Table 2 on page 17 and Table 8 on page 32 for more details.

The switching of each channel in a multiphase converter is timed to

be symmetrically out-of-phase with each of the other channels. In a

3-phase converter, each channel switches 1/3 cycle after the

previous channel and 1/3 cycle before the following channel. As a

result, the 3-phase converter has a combined ripple frequency three

times greater than the ripple frequency of any one phase, as

illustrated in Figure 1. The three channel currents (IL1, IL2 and IL3)

combine to form the AC ripple current and the DC load current. The

ripple component has three times the ripple frequency of each

individual channel current. Each PWM pulse is terminated 1/3 of a

cycle after the PWM pulse of the previous phase. The DC

SM_PM_I2CLK - Synchronous clock signal input of

SMBus/PMBus/I C.

2

SM_PM_I2DATA - I/O pin for transferring data signals

2

SMBus/PMBus/I C and VR controller.

SM_PMALERT# - Output pin for transferring the active low signal

driven asynchronously from the VR controller to SMBus/PMBus.

VRSEL_ADDR - Register pin used to program VR address

(PMBus) and to determine 5m/step or 10mV/step mode.

components of the inductor currents combine to feed the load.

To understand the reduction of ripple current amplitude in the

multiphase circuit, examine Equation 1, which represents an

individual channel’s peak-to-peak inductor current.

NVM_BANK_BT - Register pin to select NVM memory bank to use

(up to 8 configuration banks) and boot voltage, which can be set

by this pin or the value stored in NVM bank.

V – V

  V

OUT

IN

OUT

(EQ. 1)

I

= ---------------------------------------------------------

p-p

L  F

 V

Operation

SW

IN

The ISL6398 is the smallest 6-Phase PWM controller. It utilizes

Intersil’s proprietary Advanced Linear EAPP (Enhanced Active Pulse

Positioning) digital control scheme that can process voltage and

current information in real time for fast control and high speed

protection and realize digital power management capability and

flexibility. It achieves the extremely fast linear transient response

with fewer output capacitors and overcomes many hurdles of

traditional digital approach, which uses non-linear, discrete control

method for both voltage loop and current balance loop and runs into

beat frequency oscillation and non-linear response. The ISL6398 is

designed to cloud computing, networking, datacenter, and POL

applications. The system parameters and required registers are

programmable and can be stored into selected NVM_BANK via

PMBus, no firmware required. It allows up to 8 memory banks, i.e.,

8 different applications. This greatly simplifies the system design

for various platforms and lowers inventory complexity and cost by

using a single device.

In Equation 1, V and V

IN OUT

respectively, L is the single-channel inductor value, and F

the switching frequency.

are the input and output voltages

is

SW

IL1 + IL2 + IL3, 7A/DIV

IL1, 7A/DIV

PWM1, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

1µs/DIV

In addition, this controller is compatible with phase doublers

(ISL6611A and ISL6617), which can double or quadruple the phase

count. For instance, the multi-phase PWM can realize up to

24-phase count system. A higher phase count system can improve

thermal distribution and power conversion efficiency at heavy load.

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR

3-PHASE CONVERTER

The ISL6398 also supports coupled (2-Phase CI) inductor design.

Refer to Intersil’s application note, AN1268 for detailed coupled

inductor discussion.

FN8575 Rev 1.00

Aug 13, 2015

Page 15 of 57

ISL6398

In the case of multiphase converters, the capacitor current is the

sum of the ripple currents from each of the individual channels.

Compare Equation 1 to the expression for the peak-to-peak

current after the summation of N symmetrically phase-shifted

inductor currents in Equation 2, the peak-to-peak overall ripple

INPUT-CAPACITOR CURRENT, 10A/DIV

current I

channels, as shown in Figure 2.

decreases with the increase in the number of

C(P-P)

CHANNEL 1

INPUT CURRENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

N=1

CHANNEL 3

INPUT CURRENT

10A/DIV

2

1µs/DIV

3

FIGURE 3. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR

RMS CURRENT FOR 3-PHASE CONVERTER

4

5

The converter depicted in Figure 3 delivers 36A to a 1.5V load from

a 12V input. The RMS input capacitor current is 5.9A. Compare this

to a single-phase converter also stepping down 12V to 1.5V at 36A.

6

The single-phase converter has 11.9A

input capacitor current.

RMS

DUTY CYCLE (V

/V )

OUT IN

The single-phase converter must use an input capacitor bank with

twice the RMS current capacity as the equivalent three-phase

converter.

FIGURE 2. RIPPLE CURRENT MULTIPLIER VS. DUTY CYCLE

Output voltage ripple is a function of capacitance, capacitor

Equivalent Series Resistance (ESR), and the summed inductor

ripple current. Increased ripple frequency and lower ripple

amplitude means that the designer can use less per-channel

inductance and few or less costly output capacitors for any

performance specification.

Figures 37, 38 and 39, as described in “Input Capacitor

Selection” on page 52, can be used to determine the input

capacitor RMS current based on load current, duty cycle, and the

number of channels. They are provided as aids in determining

the optimal input capacitor solution. Figure 40 shows the single

phase input-capacitor RMS current for comparison.

V

OUT

(EQ. 2)

-------------------

I

=

K

cp – p

RCM

L  F

SW

N  D – m + 1  m – N  D

PWM Modulation Scheme

K

= ----------------------------------------------------------------------------

RCM

N  D

The ISL6398 adopts Intersil's proprietary Enhanced Active Pulse

Positioning (EAPP) modulation scheme to improve transient

performance. The EAPP is a unique dual-edge PWM modulation

scheme with both PWM leading and trailing edges being

independently moved to give the best response to transient

loads. The EAPP has an inherited function, similar to Intersil's

proprietary Adaptive Phase Alignment (APA) technique, to turn

on all phases together to further improve the transient response,

when there are sufficiently large load step currents. The EAPP is

a variable frequency architecture, providing linear control over

transient events and evenly distributing the pulses among all

phases to achieve very good current balance and eliminate beat

frequency oscillation over a wide range of load transient

frequencies.

for

m – 1  N  D  m

m = ROUNDUPN  D 0

Another benefit of interleaving is to reduce input ripple current.

Input capacitance is determined in part by the maximum input

ripple current. Multiphase topologies can improve overall system

cost and size by lowering input ripple current and allowing the

designer to reduce the cost of input capacitors. The example in

Figure 3 illustrates input currents from a three-phase converter

combining to reduce the total input ripple current.

To further improve the line and load transient responses, the

multi-phase PWM features feed-forward function to change the

up ramp with the input line (voltage on ISENIN+ pin) to maintain

a constant overall loop gain over a wide range input voltage. The

up ramp of the internal sawtooth is defined in Equation 3.

V

 V

RAMP_ADJ

12V

IN

V

= -----------------------------------------------

(EQ. 3)

RAMP

FN8575 Rev 1.00

Aug 13, 2015

Page 16 of 57

ISL6398

With EAPP control and feed-forward function, the ISL6398 can

achieve excellent transient performance over wide frequency

range of load step, resulting in lower demand on the output

capacitors.

TABLE 2. PHASE DROPPING CONFIGURATION AT LOW POWER

NPSI

D2[1:0]

AUTO MINIMUM

PHASE COUNT

CODE

SI1

0h

1h

2h

3h

SI, (N-1)-CI

SI, (N-2)-CI

2-Phase CI

1-Phase

2-Phase

1-Phase

2-Phase

Under steady state conditions, the operation of the ISL6398

PWM modulator is similar to a conventional trailing edge

modulator. Conventional analysis and design methods can

therefore be used for steady state and small signal analysis.

SI2

CI1

CI2

NOTE: For 2-Phase CI option, the dropped coupled phase turns on LGATE

to circulate current when PWM1 is high. Programmable via PMBus.

PWM Operation

The timing of each channel is set by the number of active

channels. The default channel setting for the ISL6398 is six. The

switching cycle is defined as the time between PWM pulse

termination signals of each channel. The cycle time of the pulse

signal is the inverse of the switching frequency. The PWM signals

command the MOSFET driver to turn on/off the channel

MOSFETs.

While the controller is operational (V above POR, TM_EN_OTP

CC

and EN_PWR_CFP are both high, valid VID inputs), it can pull the

PWM pins to ~40% of V (~2V for 5V V bias, for 5V PWM) or

CC CC

~28% of V (for 3.3V PWM) during various stages, such as

CC

soft-start delay, phase shedding operation, or fault conditions

(OC or OV events). The matching driver's internal PWM resistor

divider can further raise the PWM potential, but not lower it

below the level set by the controller IC. Therefore, the controller's

PWM outputs are designed to be compatible with DrMOS and

Intersil drivers that require 3.3V and 5V PWM signal amplitudes,

programmed by PMBus.

The ISL6398 can work in a 0 to 6-Phase configuration. Tie

PWM(N+1) to VCC to configure for N-phase operation. PWM firing

order is sequential from 1 to N with N being the number of active

phases, as summarized in Table 1. For 6-phase operation, the

channel firing sequence is 1-2-3-4-5-6, and they are evenly

spaced over 1/6 of a cycle. Connecting PWM6 to V configures

5-phase operation, the channel firing order is 1-2-3-4-5 and the

DrMOS and Driver Compatibility

In operational mode, the ISL6398 can actively drive PWM into

tri-state level (mid level), which can be programmed to be

compatible with 3.3V or 5V PWM input DrMOS or Drivers. The

ISL6398’s PWM “LOW” level is 0V and PWM “HIGH” level is V (5V).

The PWM “HIGH” minimum threshold of the DrMOS should be

CC

phase spacing is 1/5 of a cycle. If PWM2 is connected to V

,

CC

only Channel 1 operation is selected. If PWM1 is connected to

V

, the VR operation is turned off.

CC

TABLE 1. PHASE NUMBER AND PWM FIRING SEQUENCE

higher than 33% of V for 3.3V PWM logic and 44% of V for 5V

PWM# TIED

TO V

ACTIVE PHASE

CC CC

PWM logic, while the PWM “LOW” maximum threshold of the

DrMOS should be lower than 26% of V for 3.3V PWM logic and

N

5

4

3

2

1

0

PHASE SEQUENCE

AT 0A LOAD

PWM1/3

PWM1/2

PWM1

CC

1-2-3-4-5

1-2-3-4

1-2-3

1-2

None

36% of V for 5V PWM logic. Since most of industrial DrMOS

CC

PWM5

PWM4

PWM3

PWM2

PWM1

devices are not compatible with Intersil’s PWM protocol for diode

emulation, therefore, the diode emulation mode should be disabled

in both controller and DrMOS. Coupling with the ISL6627, zero

current shutdown can be achieved, which minimizes the power

stage stress.

1

OFF

Phase Doubler Compatibility

The controller starts phase shedding the next switching cycle. The

controller reduces the number of active phases according to the

logic state on Table 2. “NPSI” register and AUTO pin program the

controller in operation of standard (SI), 2-phase coupled, or

(N-x)-phase coupled inductors. Different cases yield different PWM

output behaviors on both dropped phase(s) and operational

phase(s) as load changes. When APA is triggered, it pulls the

controller back to full phase operation to sustain an immediate

heavy transient load. Note that “N-x” means N-x phase(s) coupled

and x phase(s) are uncoupled.

The ISL6398 is compatible with phase doublers (ISL6611A and

ISL6617), which can double or quadruple the phase count. For

instance, the multi-phase PWM can realize up to 24-phase count

system. A higher phase count system can improve thermal

distribution and power conversion efficiency at heavy load.

Non-Intersil Phase doubler typically does not have current balance

and is not compatible with Intersil’s multi-phase controllers.

Precharged Start-up Capability

Since the ISL6398 uses 5V bias and the high efficiency power train

mostly uses 5V driver, this makes the ISL6398 digital power system

much more robust and reliable for power-up and down as well as

precharged start-up, which is typically hardly managed for a system

that deals with 3.3V, 5V, and 12V supplies.

For 2-Phase coupled inductor (CI) operation, both coupled phases

should be 180° out-of-phase. In low power conditions, it drops to

2-phase and the opposite phase of the operational phase turns

on its low-side MOSFET to circulate inductor current to minimize

conduction loss when Phase 1 is high.

Switching Frequency

The VR’s switching frequency is programmable from 120kHz to

2.025MHz via PMBus. It is 15kHz/step with a slew rate of

step/20µs.

In low power condition, VR is in single-phase CCM operation with

PWM1, or 2-phase CCM operation with PWM1 and 2, 3 or 4, as

shown in Table 1. The number of operational phases is

configured by “NPSI” register, shown in Table 2.

FN8575 Rev 1.00

Aug 13, 2015

Page 17 of 57

ISL6398

voltage across the capacitor V is equal to the voltage drop across

C

the DCR, i.e., proportional to the channel current.

Current Sensing

The ISL6398 senses current continuously for fast response. The

ISL6398 supports inductor DCR sensing, or resistive sensing

techniques. The associated channel current sense amplifier uses

the ISEN inputs to reproduce a signal proportional to the inductor

With the internal low-offset current amplifier, the capacitor

voltage V is replicated across the sense resistor R

.

C

ISEN

, is proportional

Therefore, the current out of the ISENS+ pin, I

to the inductor current.

SEN

current, I . The sense current, I

, is proportional to the inductor

L

SEN

current. The sensed current is used for current balance, load-line

regulation, and overcurrent protection.

Equation 6 shows that the ratio of the channel current to the

sensed current, I , is driven by the value of the sense resistor

SEN

and the DCR of the inductor.

The internal circuitry, shown in Figures 4 and 5, represents one

channel of the VR output, respectively. The ISEN± circuitry is

repeated for each channel, but may not be active depending on

the status of the PWM[6:2] pins, as described in “PWM

Operation” on page 17. The input bias current of the current

sensing amplifier is typically 25nA; less than 8k input

impedance is preferred to minimized the offset error, i.e., a larger

C value as needed.

DCR

DCR  64

-----------------

------------------------

I

= I



= I

(EQ. 6)

SEN

L

R

ISEN

SET

RESISTIVE SENSING

For more accurate current sensing, a dedicated current-sense

resistor R in series with each output inductor can serve as the

SENSE

current sense element (see Figure 5). This technique however

reduces overall converter efficiency due to the additional power loss

INDUCTOR DCR SENSING

on the current sense element R

.

SENSE

An inductor’s winding is characteristic of a distributed resistance,

as measured by the Direct Current Resistance (DCR) parameter.

Consider the inductor DCR as a separate lumped quantity, as

I

L

R

ESL

V

SEN

R

shown in Figure 4. The channel current I , flowing through the

OUT

L

inductor, will also pass through the DCR. Equation 4 shows the

C

SENSE

OUT

-

S-domain equivalent voltage across the inductor V .

V

L

R

V (s)

ISL6398

C

V s = I  s  L + DCR

(EQ. 4)

L

C

A simple R-C network across the inductor extracts the DCR

voltage, as shown in Figure 4.

I

n

I

s

L

CURRENT

SENSE

L

DCR

V

OUT

+

-

INDUCTOR

-

R

ISEN(n)

ISEN-(n)

C

OUT

ISL6398

V

L

ISEN+(n)

RSET

-

V (s)

C

R

 64

R

C

SEN

R

I

n

C , Optional

T

--------------------------

= I

SEN

L

SET

CURRENT

SENSE

ISEN-(n)

FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS

+

-

R

ISEN(n)

A current sensing resistor has a distributed parasitic inductance,

known as ESL (equivalent series inductance, typically less than

1nH) parameter. Consider the ESL as a separate lumped

C , Optional

ISEN+(n)

RSET

T

DCR  64

I

quantity, as shown in Figure 5. The channel current I , flowing

------------------------

= I

SEN

L

R

SET

through the inductor, will also pass through the ESL. Equation 7

shows the s-domain equivalent voltage across the resistor V .

R

V

s = I  s  ESL + R



SEN

(EQ. 7)

R

L

FIGURE 4. DCR SENSING CONFIGURATION

A simple R-C network across the current sense resistor extracts

the R voltage, as shown in Figure 5.

The voltage on the capacitor V , can be shown to be proportional

C

to the channel current I (see Equation 5).

SEN

The voltage on the capacitor V , can be shown to be proportional

L







C

-------------

s 

+ 1  DCR  I 

L



(EQ. 5)

DCR

to the channel current I (see Equation 8).

L

V

s = --------------------------------------------------------------------

C

s  RC + 1

ESL







---------------

s 

+ 1  R

 I 

SEN L

(EQ. 8)



R

If the R-C network components are selected such that the RC time

constant matches the inductor time constant (R*C = L/DCR), the

SEN

V

s = -------------------------------------------------------------------------

C

s  RC + 1

FN8575 Rev 1.00

Aug 13, 2015

Page 18 of 57

ISL6398

If the R-C network components are selected such that the RC time

constant matches the ESL-R

time constant (R*C = ESL/R ),

I_OUT

SEN

the voltage across the capacitor V is equal to the voltage drop

C

across the R

, i.e., proportional to the channel current. As an

SEN

example, a typical 1mΩ sense resistor can use R = 348 and

C = 820pF for the matching. Figures 6 and 7 show the sensed

waveforms with and without matching RC when using resistive

sense.

V_OUT

FIGURE 8. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

If the R-C timing constant is too large or too small, V (s) will not

C

accurately represent real-time I

(s) and will worsen the

OUT

transient response. Figure 9 shows the load transient response

when the R-C timing constant is too small. V will sag

OUT

excessively upon load insertion and may create a system failure

or early overcurrent trip. Figure 10 shows the transient response

FIGURE 6. VOLTAGE ACROSS R WITHOUT RC

when the R-C timing constant is too large. V

is sluggish in

OUT

drooping to its final value. There will be excessive overshoot if

load insertion occurs during this time, which may potentially hurt

the reliability.

I_OUT

FIGURE 7. VOLTAGE ACROSS C WITH MATCHING RC

V_OUT

Equation 9 shows that the ratio of the channel current to the

sensed current, I

, is driven by the value of the sense resistor

SEN

and the R

.

ISEN

R

 64

SEN

FIGURE 9. LOAD TRANSIENT RESPONSE WHEN R-C TIME

CONSTANT IS TOO SMALL

SEN

(EQ. 9)

-----------------

--------------------------

I

= I



= I

SEN

L

R

ISEN

SET

However, the R

ISEN

value is determined by the R

be from 3.84kΩ to 60.4kΩ and is 64x of the required I

SEN

resistor of each channel is integrated, while its

resistor. The RSET resistor value can

resistor

I_OUT

SET

value. Therefore, the current sense gain resistor (Integrated R

)

ISEN

V_OUT

value can be effectively set at 60Ωto 943Ω.

The inductor DCR value will increase as the temperature increases.

Therefore, the sensed current will increase as the temperature of

the current sense element increases. In order to compensate the

temperature effect on the sensed current signal, a Negative

Temperature Coefficient (NTC) resistor can be used for thermal

compensation, or the integrated temperature compensation

function of the ISL6398 should be utilized. The integrated

temperature compensation function is described in “Temperature

Compensation” on page 28.

FIGURE 10. LOAD TRANSIENT RESPONSE WHEN R-C TIME

CONSTANT IS TOO LARGE

R

AND L/DCR MATCHING FOR COUPLED INDUCTOR

SET

The current sense circuitry operates in a very similar manner for

negative current feedback, where inductor current is flowing

from the output of the regulator to the PHASE node, opposite of

flow pictured in Figures 4 and 5. However, the range of proper

operation with negative current sensing has a limitation. The

worst-case peak-to-peak inductor ripple current should be kept

less than 80% of the OCP trip point (~80µA). Care should be

taken to avoid operation with negative current feedback

exceeding this threshold, as this may lead to momentary loss of

current balance between phases and disruption of normal circuit

operation. Note that the negative current can especially affect

coupled inductor designs, where the effective inductance is the

leakage between the two channels, much lower than the

specified mutual inductance (LM) and self inductance (L). To limit

the impact, a higher RSET value (1.5x to 2x) is often used to

reduce the effective negative current seen by the controller in

coupled inductor designs.

Decoupling capacitor (C ) on ISEN[6:1]- pins are optional and

T

might be required for long sense traces and a poor layout.

L/DCR OR ESL/R

MATCHING

SEN

Assuming the compensator design is correct, Figure 8 shows the

expected load transient response waveforms if L/DCR or

ESL/R

current I

OUT

is matching the R-C time constant. When the load

has a square change, the output voltage V also

SEN

OUT

has a square response, except for the overshoot at load release.

However, there is always some PCB contact impedance of current

sensing components between the two current sensing points; it

hardly accounts into the L/DCR or ESL/R

matching calculation.

SEN

Fine tuning the matching is necessarily done in the board level to

improve overall transient performance and system reliability.

Refer to Intersil’s application note, AN1268 for detailed coupled

inductor discussion and ripple current calculation.

FN8575 Rev 1.00

Aug 13, 2015

Page 19 of 57

ISL6398

or 10mV offset, a large ratio resistor divider can be placed on the

VSEN pin between the output and GND for positive offset or V

As explained in application note, AN1268 the leakage inductance

(not self inductance or mutual inductance) of the coupled

inductor should be used as the inductance in the time constant

calculation. Therefore, the leakage, self, and mutual inductance

should be well controlled for a good coupled inductor design.

CC

for negative offset, as in Figure 12. The VR operational mode is

programmed by the “VRSEL_ADDR” pin. Table 3 shows the

difference between 5mV and 10mV modes. VOUT_MAX and

VBOOT registers must be programmed accordingly to support

each mode, otherwise, the VR might NOT power-up correctly.

Channel-current Balance

Furthermore, the PMBus register (E4h[9:5]) can program the

The sensed current I from each active channel is summed

n

additional droop current (range from -4µA to 3.75µA) into R for

1

together and divided by the number of active channels. The

DC offset calibration; a negative current will yield a negative

offset, while a positive current will yield a positive offset:

resulting average current I

provides a measure of the total

AVG

load current. Channel current balance is achieved by comparing

the sensed current of each channel to the average current to

make an appropriate adjustment to the PWM duty cycle of each

channel with Intersil’s patented current-balance method.

OFFSET = R * I(E4[9:5]). In droop applications, E4[4:0] can add

1

current out of IMON pin and droop current through R

1

simultaneously (the negative current yields positive offset, and

vice versa).

Channel current balance is essential in achieving the thermal

advantage of multiphase operation. With good current balance,

the power loss is equally dissipated over multiple devices and a

greater area. The ISL6398 can adjust the thermal/current

balance of the VR via registers F7 to FC.

TABLE 3. 5mV vs 10mV DAC Resolution

MAXIMUM

VBOOT

MAXIMUM

VBOOT

(E6)

MODE

(VRSEL)

MAXIMUM

DAC (V)

VOUT_MAX

(24h)

(“BT” pin)

5mV

2.155

3.011

Table 18

1.50

3.00

1.52

3.04

Voltage Regulation (5mV and 10mV Mode)

10mV

Table 4

Follow DAC

The compensation network shown in Figure 11 assures that the

steady-state error in the output voltage is limited only to the error

in the reference voltage (DAC and OFFSET) and droop current

source, remote sense, and error amplifier.

V

CC

The sensed average current I

DROOP

is tied to FB internally and

will develop a voltage drop across the resistor between FB and

for droop control. This current can be disconnected from the

V

OUT

V

VSEN

+

OUT

VSEN

V

OUT

FB node via PMBus for non-droop applications.

+

-

The output of the error amplifier, V , is compared to the internal

COMP

sawtooth waveforms to generate the PWM signals. The PWM

signals control the timing of the Intersil MOSFET drivers and regulate

the converter output to the specified reference voltage.

DAC = VID+OFFSET

HIGHER THAN DAC

DAC = VID+OFFSET

LOWER THAN DAC

B. V

A. V

OUT

For remote sensing, connect the load sensing pins to the

non-inverting input, VSEN, and inverting input, RGND, of the error

amplifier. This configuration effectively removes the voltage error

encountered when measuring the output voltage relative to the local

controller ground reference point.

FIGURE 12. EXTERNAL PROGRAMMABLE REGULATION

TABLE 4. 5mV OR 10mV VID 8-BIT

HEX

5mV

10mV

VID (V) OFFSET (mV) OFFSET (mV)

5mV

10mV

BINARY CODE CODE VID (V)

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

0

1

2

3

4

5

6

7

8

9

A

B

C

D

OFF

0

COMPENSATION

DIGITALLY PROGRAMMABLE VIA PMBUS

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.500

0.510

0.520

0.530

0.540

0.550

0.560

0.570

0.580

0.590

0.600

0.610

0.620

5

10

15

20

25

30

35

40

45

50

55

60

65

20

C₂

R₂

C₃

R₃

C₁

VSEN

RGND

R_FB= R₁

30

FB

INPUT

BUFFER

40

V_OFFSETTRIM

BUF_COMP

(E4[9:5])

DAC

COMP

50

I_DROOP

60

VID+OFFSET

V_OFFSETTrim

(E4[4:0])

70

DROOP

ENABLE

80

FIGURE 11. OUTPUT VOLTAGE AND LOAD-LINE REGULATION

90

A digital-to-analog converter (DAC) generates a reference voltage,

which is programmable via PMBus bus. The DAC decodes the

PMBus set VID command into one of the discrete voltages shown

in Table 4. In addition, the output voltage can be margined in

±5mV step between -640mV and 635mV, ±10mV step between

-1280mV and 1270mV, as shown in Table 4. For a finer than 5mV

100

110

120

130

FN8575 Rev 1.00

Aug 13, 2015

Page 20 of 57

ISL6398

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

5mV

10mV

5mV

10mV

BINARY CODE CODE VID (V) VID (V) OFFSET (mV) OFFSET (mV)

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

00110000

00110001

00110010

00110011

00110100

00110101

00110110

00110111

00111000

00111001

00111010

E

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.630

0.640

0.650

0.660

0.670

0.680

0.690

0.700

0.710

0.720

0.730

0.740

0.750

0.760

0.770

0.780

0.790

0.800

0.810

0.820

0.830

0.840

0.850

0.860

0.870

0.880

0.890

0.900

0.910

0.920

0.930

0.940

0.950

0.960

0.970

0.980

0.990

1.000

1.010

1.020

1.030

1.040

1.050

1.060

1.070

70

140

150

160

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

360

370

380

390

400

410

420

430

440

450

460

470

480

490

500

510

520

530

540

550

560

570

580

00111011

00111100

00111101

00111110

00111111

01000000

01000001

01000010

01000011

01000100

01000101

01000110

01000111

01001000

01001001

01001010

01001011

01001100

01001101

01001110

01001111

01010000

01010001

01010010

01010011

01010100

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

01100000

01100001

01100010

01100011

01100100

01100101

01100110

01100111

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

0.640

0.645

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

1.080

1.090

1.100

1.110

1.120

1.130

1.140

1.150

1.160

1.170

1.180

1.190

1.200

1.210

1.220

1.230

1.240

1.250

1.260

1.270

1.280

1.290

1.300

1.310

1.320

1.330

1.340

1.350

1.360

1.370

1.380

1.390

1.400

1.410

1.420

1.430

1.440

1.450

1.460

1.470

1.480

1.490

1.500

1.510

1.520

295

300

305

310

315

320

325

330

335

340

345

350

355

360

365

370

375

380

385

390

395

400

405

410

415

420

425

430

435

440

445

450

455

460

465

470

475

480

485

490

495

500

505

510

515

590

600

610

620

630

640

650

660

670

680

690

700

710

720

730

740

750

760

770

780

790

800

810

820

830

840

850

860

870

880

890

900

910

920

930

940

950

960

970

980

990

1000

1010

1020

1030

F

75

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

80

85

90

95

100

105

110

115

120

125

130

135

140

145

150

155

160

165

170

175

180

185

190

195

200

205

210

215

220

225

230

235

240

245

250

255

260

265

270

275

280

285

290

FN8575 Rev 1.00

Aug 13, 2015

Page 21 of 57

ISL6398

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

5mV

10mV

5mV

10mV

BINARY CODE CODE VID (V) VID (V) OFFSET (mV) OFFSET (mV)

01101000

01101001

01101010

01101011

01101100

01101101

01101110

01101111

01110000

01110001

01110010

01110011

01110100

01110101

01110110

01110111

01111000

01111001

01111010

01111011

01111100

01111101

01111110

01111111

10000000

10000001

10000010

10000011

10000100

10000101

10000110

10000111

10001000

10001001

10001010

10001011

10001100

10001101

10001110

10001111

10010000

10010001

10010010

10010011

10010100

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

0.765

0.770

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

0.955

0.960

0.965

0.970

0.975

0.980

0.985

1.530

1.540

1.550

1.560

1.570

1.580

1.590

1.600

1.610

1.620

1.630

1.640

1.650

1.660

1.670

1.680

1.690

1.700

1.710

1.720

1.730

1.740

1.750

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

1.840

1.850

1.860

1.870

1.880

1.890

1.900

1.910

1.920

1.930

1.940

1.950

1.960

1.970

520

525

530

535

540

545

550

555

560

565

570

575

580

585

590

595

600

605

610

615

620

625

630

635

-640

-635

-630

-625

-620

-615

-610

-605

-600

-595

-590

-585

-580

-575

-570

-565

-560

-555

-550

-545

-540

1040

1050

1060

1070

1080

1090

1100

1110

1120

1130

1140

1150

1160

1170

1180

1190

1200

1210

1220

1230

1240

1250

1260

1270

-1280

-1270

-1260

-1250

-1240

-1230

-1220

-1210

-1200

-1190

-1180

-1170

-1160

-1150

-1140

-1130

-1120

-1110

-1100

-1090

-1080

10010101

10010110

10010111

10011000

10011001

10011010

10011011

10011100

10011101

10011110

10011111

10100000

10100001

10100010

10100011

10100100

10100101

10100110

10100111

10101000

10101001

10101010

10101011

10101100

10101101

10101110

10101111

10110000

10110001

10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

1.075

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.980

1.990

2.000

2.010

2.020

2.030

2.040

2.050

2.060

2.070

2.080

2.090

2.100

2.110

2.120

2.130

2.140

2.150

2.160

2.170

2.180

2.190

2.200

2.210

2.220

2.230

2.240

2.250

2.260

2.270

2.280

2.290

2.300

2.310

2.320

2.330

2.340

2.350

2.360

2.370

2.380

2.390

2.400

2.410

2.420

-535

-530

-525

-520

-515

-510

-505

-500

-495

-490

-485

-480

-475

-470

-465

-460

-455

-450

-445

-440

-435

-430

-425

-420

-415

-410

-405

-400

-395

-390

-385

-380

-375

-370

-365

-360

-355

-350

-345

-340

-335

-330

-325

-320

-315

-1070

-1060

-1050

-1040

-1030

-1020

-1010

-1000

-990

-980

-970

-960

-950

-940

-930

-920

-910

-900

-890

-880

-870

-860

-850

-840

-830

-820

-810

-800

-790

-780

-770

-760

-750

-740

-730

-720

-710

-700

-690

-680

-670

-660

-650

-640

-630

FN8575 Rev 1.00

Aug 13, 2015

Page 22 of 57

ISL6398

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

TABLE 4. 5mV OR 10mV VID 8-BIT (Continued)

HEX 5mV 10mV

5mV

10mV

5mV

10mV

BINARY CODE CODE VID (V) VID (V) OFFSET (mV) OFFSET (mV)

11000010

11000011

11000100

11000101

11000110

11000111

11001000

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1.265

1.270

1.275

1.280

1.285

1.290

1.295

1.300

1.305

2.430

2.440

2.450

2.460

2.470

2.480

2.490

2.500

2.510

2.520

2.530

2.540

2.550

2.560

2.570

2.580

2.590

2.600

2.610

2.620

2.630

2.640

2.650

2.660

2.670

2.680

2.690

2.700

2.710

2.720

2.730

2.740

2.750

2.760

2.770

2.780

2.790

2.800

2.810

2.820

2.830

2.840

2.850

2.860

-310

-305

-300

-295

-290

-285

-280

-275

-270

-265

-260

-255

-250

-245

-240

-235

-230

-225

-220

-620

-610

-600

-590

-580

-570

-560

-550

-540

-530

-520

-510

-500

-490

-480

-470

-460

-450

-440

11101110

11101111

11110000

11110001

11110010

11110011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

1.435

1.440

1.445

1.450

1.455

1.460

1.465

1.470

1.475

1.480

1.485

1.490

1.495

1.500

1.505

1.510

1.515

1.520

2.870

2.880

2.890

2.900

2.910

2.920

2.930

2.940

2.950

2.960

2.970

2.980

2.990

3.000

3.010

3.020

3.030

3.040

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

-180

-170

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Load-line Regulation

Some applications require a precisely controlled output

resistance. This dependence of output voltage on load current is

often termed “droop” or “load-line” regulation. By adding a well

controlled output impedance, the output voltage can effectively

be level shifted in a direction, which works to achieve the

load-line regulation required by these manufacturers.

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

11011110

11011111

11100000

11100001

11100010

11100011

11100100

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

1.310

1.315

1.320

1.325

1.330

1.335

1.340

1.345

1.350

1.355

1.360

1.365

1.370

1.375

1.380

1.385

-215

-210

-205

-200

-195

-190

-185

-180

-175

-170

-165

-160

-155

-150

-145

-140

-430

-420

-410

-400

-390

-380

-370

-360

-350

-340

-330

-320

-310

-300

-290

-280

In other cases, the designer may determine that a more

cost-effective solution can be achieved by adding droop. Droop

can help to reduce the output-voltage spike that results from fast

load-current demand changes.

The magnitude of the spike is dictated by the ESR and ESL of the

output capacitors selected. By positioning the no-load voltage level

near the upper specification limit, a larger negative spike can be

sustained without crossing the lower limit. By adding a well

controlled output impedance, the output voltage under load can

effectively be level shifted down so that a larger positive spike can

be sustained without crossing the upper specification limit.

As shown in Figure 11, a current proportional to the average

current of all active channels, I

load-line regulation resistor R , i.e., R . The resulting voltage

drop across R is proportional to the output current, effectively

creating an output voltage droop with a steady-state value

defined, as shown in Equation 10:

, flows from FB through a

AVG

FB

1

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

E5

E6

E7

E8

E9

EA

EB

EC

ED

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

-135

-130

-125

-120

-115

-110

-105

-100

-95

-270

-260

-250

-240

-230

-220

-210

-200

-190

FB

V

= I

 R

AVG

FB

(EQ. 10)

DROOP

FN8575 Rev 1.00

Aug 13, 2015

Page 23 of 57

ISL6398

The regulated output voltage is reduced by the droop voltage

TABLE 5. SLEW RATE OPTIONS

DVID SLEW RATE

V

. The output voltage as a function of load current is

DROOP

DVID SLEW RATE

(MINIMUM RATE)

(mV/µs)

derived by combining Equation 10 with the appropriate sample

current expression defined by the current sense method

employed, as shown in Equation 11:

DVID

F6h[4:0]

(MINIMUM RATE)

(mV/µs)

DVID

F6h[4:0]

0h

1h

2h

3h

4h

5h

6h

7h

0.315

0.625

1.25

2.5

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

4.0

4.44

5.0

I

R

X

R

ISEN







LOAD

N

(EQ. 11)

V

= V

– ---------------- ----------------- R



REF FB

OUT





5.6

where V

is the reference voltage (DAC), I

is the total

is the sense resistor

REF

output current of the converter, R

LOAD

2.85

3.07

3.33

3.63

6.66

8.0

ISEN

connected to the ISEN+ pin, and R is the feedback resistor, N is

FB

the active channel number, and R is the DCR, or R

X

SENSE

10

depending on the sensing method.

13.25

Therefore, the equivalent loadline impedance, i.e. Droop

impedance, is equal to Equation 12:

During dynamic VID transition and VID step up, the overcurrent

trip point increases by 140% to avoid falsely triggering OCP

circuits, while the overvoltage trip point will follow the DAC+OVP

level, programmable via PMBus (D8h[2:0]).

R

X

FB

R

= ------------ -----------------

(EQ. 12)

LL

N

R

ISEN

The major regulation error comes from the current sensing

elements. To improve load-line regulation accuracy, a tight DCR

tolerance of inductor or a precision sensing resistor should be

considered.

Operation Initialization

Prior to converter initialization, proper conditions must exist on

the enable inputs and V . When the conditions are met, the

CC

controller begins soft-start. Once the output voltage is within the

proper window of operation, VR_RDY asserts logic high.

In addition, the overall load-line can be programmed to fit the

application needed by the PMBus registers: B0h[7:0] for

Load-Line and E4h[9:5] for DC offset. Curve 3 shown in Figure 13,

makes a steeper load line than the target to fully utilize the total

tolerance band, reduce the output capacitor count and cost.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state (or pulled to 40% of V ) to assure the

CC

drivers remain off. The following input conditions must be met

before the ISL6398 is released from shutdown mode.

OFFSET = R1* {I(E4h[9:5])-* I(E4h[4:0])}*D3[0]

V_{OUT_MAX}

1. The bias voltage applied at V must reach the internal

CC

2

power-on reset (POR) rising threshold. Once this threshold is

reached, proper operation of all aspects of the ISL6398 is

guaranteed. Hysteresis between the rising and falling

thresholds assure that once enabled, ISL6398 will not

inadvertently turn off unless the bias voltage drops

substantially (see “Electrical Specifications” on page 10).

4

1

OFFSET + LL_TARGET

R1 = LL_TARGET

3

OFFSET + (> LL_TARGET

R1 > LL_TARGET

)

V_{OUT_MIN}

LOAD (A)

2. The ISL6398 features an enable input (EN_PWR_CFP) for

power sequencing between the controller bias voltage and

another voltage rail. The enable comparator holds the

ISL6398 in shutdown until the voltage at EN_PWR_CFP rises

above 0.85V. The enable comparator has about 100mV of

hysteresis to prevent bounce. It is important that the drivers

reach their POR level before the ISL6398 becomes enabled.

The schematic in Figure 14 demonstrates sequencing the

ISL6398 with ISL99140 DrMOS and the ISL66xx family of

Intersil MOSFET drivers.

FIGURE 13. PROGRAMMABLE LOAD-LINE REGULATION

Dynamic VID

Some applications need to make changes to their voltage as part

of normal operation. They direct the core-voltage regulator to do

this by making changes to the VID during regulator operation.

The power management solution is required to monitor the DAC

and respond to on-the-fly VID changes in a controlled manner.

Supervising the safe output voltage transition within the DAC

range of the load without discontinuity or disruption is a

necessary function of the voltage regulator.

3. The voltage on TM_EN_OTP must be higher than 1.08V

(typically) to enable the controller. This pin is typically

connected to the output of VTT VR. However, since the

TM_EN_OTP pin is also used for thermal monitoring, it will

assert SM_PMALERT# pin low due to thermal alert prior to

start-up, therefore, it needs to use CLEAR_FAULT (03h)

command to clear the SM_PMALERT# pin and

STATUS_BYTE (78h) after power-up. There is no effect on

normal operation if SM_PMALERT# and STATUS_BYTE are not

used.

Sixteen different slew rates can be selected for soft-start and

during Dynamic VID (DVID) transition for VR.

FN8575 Rev 1.00

Aug 13, 2015

Page 24 of 57

ISL6398

When all conditions previously mentioned are satisfied, the

ISL6398 begins the soft-start and ramps the output voltage to

the Boot Voltage set by hard-wired “BT” registers. After remaining

at the boot voltage for some time, the ISL6398 reads the VID

code. If the VID code is valid, ISL6398 will regulate the output to

the final VID setting. If the VID code is “OFF” code, ISL6398 will

remain shut down.

V

– V

BOOT

VID

(EQ. 15)

---------------------------------------

s

t

=

D4

DVID RATE

For example, when the V

BOOT

set at 5mV/µs, the first soft-start ramp time t will be around

220µs and the second soft-start ramp time t will be at

D4

maximum of 80µs if an SET_VID command for 1.5V is received

is set at 1.1V and DVID slew rate is

D2

after t

.

ISL6398

D3

EXTERNAL CIRCUIT

V

+12V

CC

100kΩ

POR

ENABLE

COMPARATOR

CIRCUIT

EN_PWR_CFP

+

-

t

D2

D3

VCC

D1

D4

9.09kΩ

TM_EN_OTP

VR_Ready

0.85V

1kΩ

TM_EN_OTP

+

-

6.8kΩ

NTC

FIGURE 15. SOFT-START WAVEFORMS

1.08V

Current Sense Output

The current flowing out of the IMON pin is equal to the sensed

average current inside the ISL6398. In typical applications, a

resistor is placed from the IMON pin to GND to generate a

voltage, which is proportional to the load current and the resistor

value, as shown in Equation 16:

SOFT-START

AND

FAULT LOGIC

FIGURE 14. POWER SEQUENCING USING THRESHOLD-SENSITIVE

ENABLE (EN) FUNCTION

R

X

R

ISEN

IMON

N

(EQ. 16)

V

= -------------------- -----------------I

LOAD

IMON

Soft-start

where V

is the voltage at the IMON pin, R

is the resistor

IMON

The ISL6398 based VR has 4 periods during soft-start, as shown in

Figure 15. After V , TM_EN_OTP and EN_PWR_CFP reach their

between the IMON pin and GND, I

of the converter, R

is the total output current

LOAD

is the sense resistor connected to the

CC

ISEN

POR/enable thresholds and the NVM_BANK loading time (typically

16ms, and worst case 20ms) expired, the controller will have a fixed

ISEN+ pin, N is the active channel number, and R is the DC

resistance of the current sense element, either the DCR of the

X

delay period t . After this delay period, the VR will begin first soft-

inductor or R

depending on the sensing method.

D1

SENSE

start ramp until the output voltage reaches the V

BOOT

voltage at a

The resistor from the IMON pin to GND should be chosen to

ensure that the voltage at the IMON pin is typically 2.5V at the

maximum load current, typically corresponding to the I

register. The IMON voltage is linearly digitized every 88µs and

stored in the READ_IOUT register (8Ch). When the IMON voltage

reaches 2.5V or higher, the digitized I

fixed slew rate, as in Table 5. Then, the controller will regulate the VR

voltage at V for another period t until PMBus sends a new

BOOT D3

CCMAX

VID command. If the VID code is valid, ISL6398 will initiate the

second soft-start ramp at a slew rate, set by DVID command in

Table 5, until the voltage reaches the new VID voltage. The soft-start

time is the sum of the 4 periods, as shown in Equation 13.

will reach the

OUT

maximum value of ICCMAX and the SM_PMALERT# pin is pulled

low.

(EQ. 13)

t

= t + t + t + t

D1 D2 D3 D4

SS

2.5V R

N

ISEN

(EQ. 17)

t

is a fixed delay with the typical value as 20µs. t is determined

D3

R

= ------------------------------- --------------------------------------

D1

IMON

R

I

CC_MAX_21h

X

by the time to obtain a new valid VID voltage from PMBus. If the VID

is valid before the output reaches the boot voltage, the output will

turn around to respond to the new VID code.

A small capacitor can be placed between the IMON pin and GND

to reduce the noise impact and provide averaging. If this pin is

not used, tie it to GND.

During t and t , the ISL6398 digitally controls the DAC

D2 D4

voltage change at 5mV per step. The soft-start ramp time t

D2

and t can be calculated based on Equations 14 and 15:

D4

V

BOOT

-------------------------------

t

=

s

(EQ. 14)

D2

DVIDRATE

FN8575 Rev 1.00

Aug 13, 2015

Page 25 of 57

ISL6398

To deal with layout and design variation of different platforms,

the ISL6398 is intentionally trimmed to negative range at no

load, thus, an offset can easily be added to calibrate the digitized

IMON reading (8Ch in PMBus) whenever needed by PMBus (E4h)

or the external pull-up resistor in Figure 16. Hence, the slope on

the IMON pin is set by the equivalent impedance of

Two actions are taken by ISL6398 to protect the load when an

overvoltage condition occurs.

At the inception of an overvoltage event, all PWM outputs are

commanded low instantly. This causes the Intersil drivers to turn on

the lower MOSFETs and pull the output voltage below a level to avoid

damaging the load. When the output voltage falls below the DAC

plus 100mV, PWM signals enter a high-impedance state. The Intersil

drivers respond to the high-impedance input by turning off both

upper and lower MOSFETs. If the overvoltage condition reoccurs, the

ISL6398 will again command the lower MOSFETs to turn on. The

ISL6398 will continue to protect the load in this fashion as long as

the overvoltage condition occurs.

R

//R

=R . Additional offset can be added by

MON1

IOUT_CAL_OFFSET (E5h).

MON2

IMON

V

R

CC IMON

R

= --------------------------------------------------------------------------

MON2

MON1

V

IMON_OFFSET_DESIRED

(EQ. 18)

R

IMON2 IMON

= --------------------------------------------------

– R

R

IMON2

IMON

Once an overvoltage condition is detected, the respective VR

ceases the normal PWM operation and pulls its VR_Ready low

until the ISL6398 is reset. Cycling the voltage V below the

ISL6398

CC

EXTERNAL CIRCUIT

POR-falling threshold will reset the controller. Cycling

EN_PWR_CFP or TM_EN_OTP will NOT reset the controller.

V

CC

R

= #MΩ

MON 2

VR_RDY

IMON

PMBus DIGITIZED IOUT (8Ch)

100µA*F4[3:0]

VSEN

RGND

+

-

OPEN SENSE

PROTECTION

OC

R

= #kΩ

MON1

I

AVG

FIGURE 16. IMON NO LOAD OFFSET CALIBRATION

SOFT-START, FAULT

AND CONTROL LOGIC

In addition, if the IMON pin voltage is higher than 3.0V,

overcurrent shutdown will be triggered, as described in

“Overcurrent Protection” on page 27.

3.0V

VSEN_OVP

+

OV

OC

Fault Monitoring and Protection

-

IMON

The ISL6398 actively monitors output voltage and current to detect

fault conditions. Fault monitors trigger protective measures to

prevent damage to a microprocessor load. One common

power-good indicator (VR_RDY) is provided for linking to external

system monitors. The schematic in Figure 17 outlines the

interaction between the fault monitors and the VR_RDY signal.

ISL6398

VID + OVP

D8[2:3]

PRE_OVP

D8[4:3]

FIGURE 17. VR_RDY AND PROTECTION CIRCUITRY

In addition, the ISL6398 features open sensing protection to

detect an open of the output voltage sensing as an OVP event,

which suspends the controller operation. Without this protection,

the VR can regulate up to maximum duty cycle and damage the

load and power trains when the output sensing is broken open.

Furthermore, since the regulation loop is sensed via the VSEN pin

and the OVP is sensed via the VSEN_OVP pin, they are

independent paths to keep output within target and below OVP

level, respectively. Thus, the ISL6398 protects against a single

point of failure.

VR_Ready Signal

The VR_RDY pin is an open-drain logic output which indicates

that the soft-start period is complete and the output voltage is

within the regulated range. The VR_RDY is pulled low during

shutdown and releases high after a successful soft-start. VR_RDY

will be pulled low when an fault (OCP, OTP, UVP, or OVP) condition

is detected, or the controller is disabled by a reset from

EN_PWR_CFP, TM_EN_OTP, POR, or VID OFF-code.

Overvoltage Protection

Regardless of the VR being enabled or not, the ISL6398

overvoltage protection (OVP) circuit will be active after its POR. The

OVP thresholds are different under different operation conditions.

When VR is not enabled and during the soft-start intervals t , the

D1

OVP threshold is programmable via PMBus (D8h[4:3]). Once the

VR completes the soft-start, the OVP trip point will change to a

tracking level of DAC+OVP, programmable via PMBus (D8h[2:0]).

FN8575 Rev 1.00

Aug 13, 2015

Page 26 of 57

ISL6398

the average current is measured. The average current is

continually compared with a reference current (typically 100µA,

programmable via F2[2:0]), as shown in Figure 17. Once the

average current exceeds the reference current, a comparator

triggers the converter to shut down. In addition, the current out of

V

CC

V

OUT

V

VSEN_OVP

DAC + OVP

OUT

VSEN_OVP

+

OV

-

OV

the IMON pin is equal to the sensed average current I

. With a

AVG

-

resistor from IMON to GND, the voltage at IMON will be

proportional to the sensed average current and the resistor value.

The ISL6398 continuously monitors the voltage at the IMON pin. If

the voltage at the IMON pin is higher than 3.0V, a precision

comparator triggers the overcurrent shutdown. Since the internal

current comparator has wider tolerance than the voltage

comparator, the IMON voltage comparator is the preferred one for

OCP trip. Therefore, the resistor between IMON and GND can be

scaled such that the overcurrent protection threshold is tripping

lower than 100µA. For example, the overcurrent threshold for the

DAC + OVP

A. INCREASED OVP

B. REDUCED OVP

FIGURE 18. EXTERNAL PROGRAMMABLE OVP

Furthermore the regulation loop (VSEN pin) and the OVP sense

(VSEN_OVP) are separated paths, the OVP level can be

programmed higher or lower than the target, as in Figure 18. The

OVP level cannot be scaled too close to DAC to ensure that the

OVP is not triggered during transient response and start-up.

sensed average current I

can be set to 95µA by using a 31.5k

AVG

resistor from IMON to GND. Thus, the internal 100µA comparator

might only be triggered at its lower corner. However, IMON OCP trip

should NOT be too far away from 125µA, which is used for

cycle-by-cycle protection and inductor saturation.

In addition, the ISL6398 also provides early OVP warning; when it

is triggered, it asserts STATUS_WORD (79h Upper Byte, Bit7) and

SM_PMALERT#. It however does not shutdown the system,

assert STATUS_BYTE, or pull VR_RDY low. Disregard this if both

STATUS_WORD and SM_PMALERT# are not used or disable OVP

Warning as needed via DFh.

OUTPUT CURRENT

Undervoltage Protection

When the output voltage drops below a level programmed by

PMBus (E1[3:0]), the VR_RDY is pulled low. The controller can

respond to UVP with two different options programmed by

PMBus (E1[6]): 1) acts as a OCP event, hiccup the output with

9ms duration and pull VR_RDY low; or 2) acts like a PGOOD, pull

VR_RDY low, monitor only. To avoid faulty triggering at

0A

OUTPUT VOLTAGE

transient/DVID events, the UVP delay is programmable by

E1[5:4]. Furthermore, the UVP is not enabled during soft-start

and also can be disabled by DF[5]. The ISL6398 also provides

early UVP warning; when it is triggered, it asserts STATUS_WORD

(79h Upper Byte, Bit7) and SM_PMALERT#. It however does not

shutdown the system, assert STATUS_BYTE or pull VR_RDY low.

Disregard this if both STATUS_WORD and SM_PMALERT# are not

used or disable UVP Warning as needed via DFh.

0V

2ms/DIV

FIGURE 19. OVERCURRENT BEHAVIOR IN HICCUP MODE

F

= 500kHz

SW

At the beginning of overcurrent shutdown, the controller places all

PWM signals in a high-impedance state, commanding the Intersil

MOSFET driver ICs to turn off both upper and lower MOSFETs. The

system remains in this state a period of 9ms. If the controller is still

enabled at the end of this wait period, it will attempt a soft-start. If

the fault remains, the trip-retry cycles will continue indefinitely

(as shown in Figure 19) until either controller is disabled or the fault

is cleared. Note that the energy delivered during trip-retry cycling is

much less than during full-load operation, so there is no thermal

hazard during this kind of operation.

Overcurrent Protection

The ISL6398 has two levels of overcurrent protection. Each phase

is protected from a sustained overcurrent condition by limiting its

peak current, while the combined phase currents are protected on

an instantaneous basis.

For the individual channel overcurrent protection, the ISL6398

continuously compares the sensed peak current (~50ns filter)

signal of each channel with the reference current (I , typically

CL

125µA, programmable via F4[5:3] and F3[2:0]). If one channel

current exceeds the reference current, the ISL6398 will pull PWM

signal of this channel to low for the rest of the switching cycle.

This PWM signal can be turned on next cycle if the sensed

channel current is less than the reference current. The peak

current limit of individual channels will only use cycle-by-cycle

current limiting and will not trigger the converter to shut down.

Thermal Monitoring (VR_HOT#)

VR_HOT# indicates the temperature status of the voltage

regulator. VR_HOT# is an open-drain output, and an external

pull-up resistor is required. This signal is valid only after the

controller is enabled.

The VR_HOT# signal can be used to inform the system that the

temperature of the voltage regulator is too high.

In instantaneous protection mode, the ISL6398 utilizes the

sensed average current I

to detect an overcurrent condition.

AVG

Refer to “Current Sensing” on page 18 for more details on how

FN8575 Rev 1.00

Aug 13, 2015

Page 27 of 57

ISL6398

The block diagram of thermal monitoring function is shown in

Figure 20. One NTC resistor should be placed close to the

respective power stage of the voltage regulator VR to sense the

operational temperature, and pull-up resistors are needed to form

the voltage dividers for the TM pins. As the temperature of the

power stage increases, the resistance of the NTC will reduce,

resulting in the reduced voltage at the TM pin. Figure 21 shows the

TM voltage over the temperature for a typical design with a

recommended 6.8k NTC (P/N: NTHS0805N02N6801 from

TM

40.98%*VCC

39.12%*VCC

VR_HOT#

Vishay, b = 3477) and 1k resistor R . It is recommended to use

TM

those resistors for the accurate temperature compensation since

the internal thermal digital code is developed based upon these

two components. If a different value is used, the temperature

TEMPERATURE

T1

T2

coefficient must be close to 3477 and R must be scaled

TM

FIGURE 22. VR_HOT# SIGNAL (TMAX = +100°C) vs TM VOLTAGE

accordingly. For instance, NTC = 10k (b = 3477), then R

should be 10k/6.8k*1k = 1.47k.

TM

Based on the NTC temperature characteristics and the desired

threshold of the VR_HOT# signal, the pull-up resistor R of TM

TM

pin is given by Equation 19:

V_CC

THERMAL TRIP POINT

LOOKUP TABLE

R

= 1.557xR

NTCT2

(EQ. 19)

(+90 TO +120⁰C)

TM

R_TM

VR_HOT#

R

is the NTC resistance at the VR_HOT# threshold

NTC(T2)

TMAX

TM

temperature T2. The VR_HOT# is de-asserted at temperature T1,

as shown in Table 6. The NTC directly senses the temperature of

the PCB and not the exact temperature of the hottest component

on the board due to airflow and varied thermal impedance.

Therefore, the user should select a lower TMAX number,

depending upon the mismatch between NTC and the hottest

components, than such component to guarantee a safe

operation.

+

-

R_NTC1

o

c

ISL6398

NTC BETA ~ 3477

FIGURE 20. BLOCK DIAGRAM OF THERMAL MONITORING

FUNCTION

TABLE 6. VR_HOT# TYPICAL TRIP POINT AND HYSTERESIS

TMAX

(°C)

VR_HOT# LOW (°C;

T2, %V

VR_HOT# OPEN

(°C; T1, %V

HYSTERESIS

(°C)

There is a comparator with hysteresis to compare the TM pin

voltage to the threshold set by the TMAX register (programmable

via PMBus E8[2:0]) for VR_HOT# signal. With TMAX set at

+100°C, the VR_HOT# signal is pulled to GND when TM voltage is

)

CC

85

90

83.1; 48.94%

88.6; 45.52%

94.3; 42.26%

100.0; 39.12%

106.1; 36.14%

109.1; 33.32%

115.5; 30.68%

118.7; 28.24%

80.3; 51.04%

85.9; 47.56%

91.4; 44.20%

97.1; 40.98%

103.0; 37.92%

106.1; 35.00%

112.3; 32.24%

115.5; 29.7%

2.7

2.9

3.1

3.0

3.2

lower than 39.12% of V voltage, and is open (pulled high

CC

95

through TM) when TM voltage increases to above 40.98% of V

voltage. The comparator trip point will be programmable by

TMAX values. Figure 21 shows the operation of those signals.

100

CC

100

105

110

115

120

90

80

70

60

50

40

30

20

In addition, as the temperature increase, the voltage on the TM

pin drops. The controller is disabled when the TM pin voltage drops

below 0.95 (typically) and becomes active again when it is above

1.05V (typically).

Temperature Compensation

0

20

40

60

80

100

120

140

°

TEMPERATURE ( C)

The ISL6398 supports inductor DCR sensing, or resistive sensing

techniques. The inductor DCR has a positive temperature

coefficient, which is about +0.385%/°C. Since the voltage across

the inductor is sensed for the output current information, the

sensed current has the same positive temperature coefficient as

the inductor DCR. n order to obtain the correct current

information, there should be a way to correct the temperature

impact on the current sense component.

FIGURE 21. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE

WITH RECOMMENDED PARTS

FN8575 Rev 1.00

Aug 13, 2015

Page 28 of 57

ISL6398

that, the NTC should be placed in proximity to the channel 1 and

the output rail; DON’T place it close to the MOSFET side, which

generates much more heat.

Integrated Temperature Compensation

The ISL6398 utilizes the voltage at the TM pin and “TCOMP”

register to compensate the temperature impact on the sensed

current. The block diagram of this function is shown in Figure 23.

The ISL6398 multiplexes the “TCOMP” value with the TM digital

signal to obtain the adjustment gain to compensate the

temperature impact on the sensed channel current. The

compensated channel current signal is used for droop and

overcurrent protection functions.

V_CC

I_sen4

I_sen3

I_sen2

I_sen1

ISL6398

CHANNEL

CURRENT

SENSE

TABLE 7. “TCOMP” VALUES

R_TM

E9h

0h

1h

2h

3h

4h

5h

6h

7h

TCOMP (°C)

E9h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

TCOMP (°C)

16

NON-LINEAR

A/D

TM

OFF

-2.5

0

I₄

I₃

I₂

I₁

^oc

R_NTC

18.9

21.6

24.3

27

k_i

D/A

2.5

5

PLACE NTC

CLOSE TO

CHANNEL 1

7

29.7

32.4

35.1

4-BIT

A/D

DROOP AND

OVERCURRENT

PROTECTION

10

13

TCOMP

When a different NTC type or different voltage divider is used for

the TM function, the TCOMP voltage can also be used to

compensate for the difference between the recommended TM

voltage curve in Figure 21 and that of the actual design. If the

same type NTC ( = 3477) but different value is used, the pull-up

resistor needs to be scaled, as shown in Equation 20:

FIGURE 23. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE

COMPENSATION

When the NTC is placed close to the current sense component

(inductor), the temperature of the NTC will track the temperature

of the current sense component. Therefore, the TM voltage can

be utilized to obtain the temperature of the current sense

component. Since the NTC could pick up noise from phase node,

a 0.1µF ceramic decoupling capacitor is recommended on the

TM pin in close proximity to the controller.

1k  R

NTC_NEW

(EQ. 20)

R

= -----------------------------------------------

TM

6.8k

Design Procedure

1. Properly choose the voltage divider for the TM pin to match

the TM voltage vs temperature curve with the recommended

curve in Figure 21.

Based on the V voltage, the ISL6398 converts the TM pin

CC

voltage to a 6-bit TM digital signal for temperature

compensation. With the non-linear A/D converter of ISL6398, the

TM digital signal is linearly proportional to the NTC temperature.

For accurate temperature compensation, the ratio of the TM

voltage to the NTC temperature of the practical design should be

similar to that in Figure 21.

2. Run the actual board under the full load and the desired

cooling condition.

3. After the board reaches the thermal steady state, record the

temperature (T

) of the current sense component (inductor

CSC

or MOSFET) and the voltage at TM and V pins.

CC

4. Use Equation 21 to calculate the resistance of the NTC, and

find out the corresponding NTC temperature T

from the

NTC

NTC datasheet or using Equation 22, where b is equal to 3477

for recommended NTC.

PHASE1

POWER

STAGE

OUTPUT INDUCTOR

VOUT

V

xR

TM

(EQ. 21)

(EQ. 22)

R

T

T

 = -----------------------------

NTC NTC

V

– V

CC

TM



= ------------------------------------------------------------------------ – 273.15

NTC

RTM







------------------------------------

ln

+ -----------------

FIGURE 24. RECOMMENDED PLACEMENT OF NTC







R

T

298.15

NTC NTC

Since the NTC attaches to the PCB, but not directly to the current

sensing component, it inherits high thermal impedance between

the NTC and the current sensing element. The “TCOMP” register

values can be utilized to correct the temperature difference

between NTC and the current sense component. Figure 24 shows

5. In Intersil design worksheet, choose a number close to the

result as in Equation 23 in the “TCOMP” cell to calculate the

needed resistor network for the register “TCOMP” pin.

Note: for worksheet, please contact Intersil Application

support at www.intersil.com/design.

FN8575 Rev 1.00

Aug 13, 2015

Page 29 of 57

ISL6398

Catastrophic Fault Protection

A catastrophic failure is a failure that will result in an exothermic

event if the power source is not removed. A predominate

catastrophic failure is a high-side FET shorting, which can cause

either output overvoltage or input overcurrent event. When the

ISL6398 detects either event, an internal switch is turned on to pull

(EQ. 23)

T

= T

– T

CSC NTC

COMP

6. Run the actual board under full load again with the proper

resistors connected to the “TCOMP” pin.

7. Record the output voltage as V1 immediately after the output

voltage is stable with the full load. Record the output voltage

as V2 after the VR reaches the thermal steady state.

the EN_PWR_CFP pin to V , as an indication of a component

CC

failure in the regulator’s power train. As shown in Figure 26, a CFP

fault signal can be generated by using a resistor divider on this pin.

To be able to apply the signal to the PS_ON# switch of an ATX power

supply or a simply external switch (2N7002), the CFP fault signal

8. If the output voltage increases over 3mV as the temperature

increases, i.e. V2 - V1 > 3mV, reduce “TCOMP” value; if the

output voltage decreases over 3mV as the temperature

increases, i.e. V1 - V2 > 3mV, increase “TCOMP” values.

should be lower than 0.8V at maximum input voltage, V

and

IN(max)

higher than 3V at lowest normal operational V (4.5V) when the

CC

input voltage (VIN) is removed. Given such conditions, the equivalent

Dynamic VID Compensation (DVC)

(in parallel) impedance of the upper leg (R ) and lower leg

UP

During DVID transitions, extra current builds up in the output

capacitors due to the C*dv/dt. The current is sensed by the

controller and fed across the feedback resistor creating extra

droop (if enabled) and causing the output voltage not properly

tracking the DAC voltage. An independent compensation for

DVID up and DVID down are implemented to optimize the DVID

transition (Patent Pending), programmable by D7 and D9,

respectively.

(R

DW

= R

DW1

+ R

) should be higher than 1k. For instance, if

DW1

we select the total lower leg impedance (R ) as 9.39k, then the

DW

R

is calculated as in Equation 25, 100k for a maximum POR of

UP

10.72V, The lower leg impedance is then calculated by 2.74k and

6.65k, as in Equations 26 and 27, respectively.

(EQ. 24)

R

= R

+ R

DW1 DW2

DW

VINPOR max – 0.92V

(EQ. 25)

Programmable Compensation

------------------------------------------------------------------

R

=

 R

UP

DW

0.92V

The ISL6398 controller utilizes Intersil’s proprietary Advanced Linear

EAPP Digital control scheme that is the best modulation scheme in

the industry to achieve linear response for both transient and

current balance and can process voltage and current information in

real time for fast control and high speed protection and realize

digital power management capability and flexibility and. The digital

compensation covers a wide range of poles and zeros, as in

Figure 25, suitable for computing, networking, ASIC, and many

general purpose applications. Refer ISL6398 GUI on Table 16 for

more details and advanced features.

VINmax

(EQ. 26)

(EQ. 27)

---------------------------

R

=

 R

+ R

DW



DW1

DW2

UP

0.8V

= R

– R

DW1

DW

VCC

VIN

CFP

R_UP

EN_PWR_CFP

EN_PWR

RESET

R_DW1

CFP

R_DW2

ISL6375, ISL6376

FIGURE 26. BI-DIRECTIONAL EN_PWR_CFP

Prior to an exothermic event, the fault signal (CFP) should be used

on the platform to remove the power source either by firing a

shunting SCR to blow a fuse or by turning off the AC power supply.

Input Current Sensing

The input current sensing uses Intersil patented technique to

overcome the high common-mode input requirement challenge.

An R-C network with thermal compensation across the inductor

(LIN) extracts the DCR voltage, as shown in Figure 27, while the C

might need to be split into 2, one close the LIN and one close to

the controller. The input inductor can be used for current sensing

and has benefit of isolating noise from the rest of the board.

However, when there are insufficient bulk capacitors on the

power-stage side, a resonant tank can be formed by input

FIGURE 25. TYPE III Compensation Poles and Zero Range

FN8575 Rev 1.00

Aug 13, 2015

Page 30 of 57

ISL6398

ceramic capacitors and the inductor, yielding oscillation or audio

noise during audio frequency range of heavy load transient. In

VIN_HS_MOSFET

addition, since Z

network steals portion of sensed current

NTC

PLACE CLOSE

from R , input current reading will have offset.

IN1

TO THE

CONTROLLER

1.5M

In many cases, a narrow input-rail PCB trace (but wide enough to

carry DC current) is sufficient to serve as the isolation path. Thus,

the input current sensing can simply be realized with a dedicated

power resistor, as shown in Figure 28.

499k

0.1µF

ISENIN-

(PIN 1)

ISENIN+

(PIN 2)

DCR

LIN

50nH

0.3m 

FIGURE 29. DISABLE PIN AND IIN CONFIGURATION

V_IN

VIN_HS_MOSFET

Auto-phase Shedding

Z_NTC

PLACE NTC

CLOSE TO

LIN

165R_IN1

NTC

2k

The ISL6398 incorporates auto-phase shedding feature to

improve light to medium load range. The phase current dropping

threshold is programmable with the resistor on auto pin. The

efficiency-optimized current trip point (I1) from 1-Phase to

2-Phase operation is approximated with Equation 28, which is kx

larger than the efficiency-optimized current trip step

(dI = I3 - I2) in between from 2-phase to 3-phase (I2) and from

3-phase to 4-phase (I3). The optimized-efficiency current trip

point difference between phases remain constant I1/k, as

expressed in Equation 29 and Figure 30

Rsn

215

Rpn

10.2k

1.8µF

10nF

0.1µF

402R_IN2

PLACE CLOSE

TO THE

CONTROLLER

ISENIN-

(PIN 1)

ISENIN+

(PIN 2)

FIGURE 27. INPUT DCR-SENSING CONFIGURATION

2  P

+ P



COSS

QG

CORE

(EQ. 28)

I1  ---------------------------------------------------------------------------------

ESR  D + R + L  F

IN

ON

DS

SW

The full scale of input current sensing is 10µA, read 1Fh with

READ_IIN(89h), via PMBus, while the input over-current trip point

is at 15µA (Programmable via F6[6:5]). A greater than 40µs time

R

= D  r

+ 1 – D  r + DCR

DSON_LOW

ON

DSON_UP

constant [C*R *R )/(R +R )] might be needed if the

IN1 IN2 IN1 IN2

where P is the per-phase gate charge loss, P

is the

QG

CORE

is the sum of high-side and low-side

MOSFETs’ output charge loss.

average input current reporting is preferred; and it also reduces

chance to trigger CFP during heavy load transient depending

upon the input filter. A design worksheet to select these

components is available for use. Please contact Intersil

Application support at www.intersil.com/design.

inductor core loss, P

QOSS

I5

I4

I3

I2

I1

L_{R_SENIN}

1nH

R_SENIN

0.3m

VIN

43.2R_IN1

VIN_HS_MOSFET

0.1µF

C

0.1µF

562

R_IN2

10nF

PLACE CLOSE

TO THE

CONTROLLER

ISENIN-

(PIN 1)

ISENIN+

(PIN 2)

FIGURE 28. INPUT R-SENSING CONFIGURATION

LOAD (A)

When not used, connect ISENIN+ to VIN and a resistor divider

with a ratio of 1/3 on ISENIN± pin, say 499k Ohm in between

ISENIN± pins and then 1.5MΩ from ISENIN- to ground

(see Figure 29).

FIGURE 30. EFFICIENCY VS. PHASE NUMBER

64  DCR  I1

(EQ. 29)

(EQ. 30)

------------------------------------



I

IMON_OPTIMIZED_1_PHASE

1.2V

N

 R

MAX

SET

R

= --------------------------------------------------------------------------

AUTO

I

IMON_OPTIMIZED_1_PHASE

FN8575 Rev 1.00

Aug 13, 2015

Page 31 of 57

ISL6398

TABLE 8. PHASE DROPPING SEQUENCE

1.2V  N

 R

SET

MAX

(EQ. 31)

(EQ. 32)

-----------------------------------------------------



R

AUTO

PWM# TIED TO V

CC

64  DCR  I1

N

6

5

4

3

2

(VCORE)

PHASE SEQUENCE

NONE

6-3-5-2-4-1

5-4--2-3-1

4-2-3-1

3-2-1

1

K





---

I

 I1  1 +  N – 1

N

PWM6

PWM5

PWM4

PWM3





Equations 30 and 31 helps approximate the AUTO resistor, while

the trip point hysteresis can be programmed via PMBus D1[5:4].

Typically, the higher the inductor ripple current, the higher

percentage of hysteresis and k it requires. Following is an easy

2-1

way to estimate R

value:

To ensure dropped phases have sufficient energy to turn on

high-side MOSET and sustain instant load apply after VR0 staying

in light load condition for a long time (hours to days), a

boot-refresh circuit turns on Low-side MOSFET of each dropped

phase to refresh the boot capacitor at a rate of slightly above

20kHz. The boot-fresh circuit is automatically turned off to boot

efficiency when DAC drops to 0.60V.

AUTO

1. Before AUTO trip point tuning, calibrate IMON current close to

zero with PMBus E4[4:0].

2. Disable AUTO mode via D4[2] or by tying AUTO pin GND

3. Obtain efficiency curve for 1- to 6-phase, programmed via

D0,with appropriate load (~25A/Phase. 0.5A step); and APA

disabled via D4h as needed.

Resistor Reader (Patented)

Intersil has developed a high resolution ADC using a patented

technique with simple 1%, 100ppm/k or better temperature

coefficient resistor divider. The same type of resistors are

preferred so that it has similar change over-temperature. In

addition, the divider is compared to the internal divider off V

and GND nodes and therefore must refer to VCC and GND pins,

not through any RC decoupling network.

4. Determine I1 from the above test result.

5. Short AUTO pin to ground with a current meter to measure the

IMON current (I

) when VR is at I1 load.

IMON_OPTIMIZED_1_PHASE

6. Calculate R

AUTO

as in Equation 31.

and enable AUTO mode.

7. Solder down R

AUTO

CC

8. Take efficiency curve and compare it with the 1-to 6-Phase

Efficiency Curves.

9. Tweak R

AUTO

and D1 (k, I1, Hysteresis) as needed for optimal

EXTERNAL CIRCUIT

ISL6398

Efficiency performance at targeted operating input and

output voltage as well as airflow.

V

CC

10. Obtain efficiency curve for couple boards and tweak R

re-center overall efficiency of these boards.

to

AUTO

R

UP

REGISTER

TABLE

ISL6398

ADC

EXTERNAL CIRCUIT

PHASE

SHEDDING

CURRENT

THRESHOLD

SELECTION

AUTO

R

DW

R

AUTO

FIGURE 32. SIMPLIFIED RESISTOR DIVIDER ADC

NVM_BANK_BT pin is designed to allow the user to select

different NVM Banks (Pre-configured IC) and/or Boot Voltage

Level even without PMBus communications; while VRSEL_ADDR

is to select different operation mode (5mV or 10mV), indirectly

control Boot Voltage Level and DAC resolution, and PMBus

Addresses. The programmed values of resistor reader are stored

in DC and DD of PMBus.

FIGURE 31. SIMPLIFIED AUTO-PHASE SHEDDING CIRCUIT

2

In addition, the SMBus, PMBus, or I C gives flexibility to program

Auto K-factor (D1[3:2]), hysteresis (D1[5:4]), I1 (D1[7:6]), and

number of operating phases after soft-start and when auto mode

is disabled by D4[2]. However, all phases will be added back

when APA is triggered; and if APA is disabled, all phase are

added back only after reset or OCP retry.

As an example, Table 9 shows the R and R

UP DW

values of each

pin for a specific system design; DATA for corresponding registers

can be read out via PMBus commands (DC and DD). In addition,

some tie-high and tie-low options are available for easy

programming (save resistor dividers) and can also be used to

validate the VR operation during In-Circuit Test (ICT). For instance,

when the system boot voltage is required at 0V, the

The minimum of auto-phase shedding is defaulted by NPSI in

PSI1 mode and can also be programmed by the bus command

code D1h[1:0], as in Table 14. The phase dropping sequence is

summarized in Table 8.

NVM_BANK_BT pin can be set to different voltage level, prior to

power-up, to get a known boot voltage to check VR operation with

ICT. Resistor reader calculator is available, please contact Intersil

Application support at www.intersil.com/design.

FN8575 Rev 1.00

Aug 13, 2015

Page 32 of 57

ISL6398

TABLE 10. PMBus (DD) RESISTOR READER EXAMPLE (Continued)

TABLE 9. PMBus (DC) RESISTOR READER EXAMPLE

R

DW

(kΩ

R

PMBus

RECOMMENDED

(k^UΩ^P

NVM

BT

DW

PMBus (DC)

(k^UΩ^P

(kΩ 8-Bit ADDRESS APPLICATIONS

PMBus (DD)

32h

40.2

45.3

NVM1

0.9V, 5mV/Step

1.8V, 10mV/Step

00h

01h

02h

03h

08h

09h

0Ch

0Dh

10h

11h

14h

15h

80h

81h

82h

83h

88h

89h

8Ch

8Dh

90h

91h

94h

95h

OPEN

49.9

45.3

43.2

29.4

28

10

80

82

84

86

C0

C2

C8

CA

E0

E2

E8

EA

80

82

84

86

C0

C2

C8

CA

E0

E2

E8

EA

10mV/Step

5mV/Step

12.4

12.7

13.3

15

55h

79h

9Fh

59

84.5

163

367

NVM2

NVM3

NVM4

1.0V, 5mV/Step

2.0V, 10mV/Step

78.7

95.3

1.2V, 5mV/Step

2.4V, 10mV/Step

1.5V, 5mV/Step

2.0V, 10mV/Step

15.4

17.4

17.8

19.6

20.5

23.2

24.3

499

93.1

95.3

100

113

115

130

133

147

154

174

182

24.3

23.2

20

B2h

DAh

196

215

226

475

NVM5

NVM6

1.8V, 10mV/Step

2.5V, 10mV/Step

NOTE: More options in resistor reader calculator. NVM_BT = Boot Voltage

Loaded from the Bank, not fixed by resistor reader.

19.6

17.4

16.9

OPEN

374

340

316

221

210

182

174

150

147

130

127

Memory Banks

The ISL6398 has 8 memory banks to store up

(STORE_USER_ALL, 15h) to 8 different configurations, selectable

via PMBus (DEh) or resistor to GND on the NVM_BANK pin, as in

Table 11. No decoupling capacitor is allowed on the pin. Prior to

the soft-start, the selection of memory bank is stored in the data

registers of PMBus (DDh). They are reset by V POR. In addition,

CC

the selected memory bank can be overridden by PMBus (DEh).

Only the selected memory bank’s configuration is loaded

(RESTORE_USER_ALL,16h) into the operating memory to have

control on the VR system prior to issuing soft-start.

TABLE 11. MEMORY BANK (PMBus, DD)

DEh

00h

01h

02h

03h

04h

05h

06h

07h

MEMORY BANK NAME

USER_NVM0

USER_NVM1

USER_NVM2

USER_NVM3

USER_NVM4

USER_NVM5

USER_NVM6

USER_NVM7

TABLE 10. PMBus (DD) RESISTOR READER EXAMPLE

R

(k^UΩ^P

R

DW

(kΩ

PMBus (DD)

00h

NVM

BT

NVM_BT

0.0V

OPEN

118

196

294

422

590

825

OPEN

49.9

20

10

NVM0

NVM1

NVM2

NVM3

NVM4

NVM5

NVM6

NVM7

NVM0

20h

26.1

43.2

64.9

93.1

130

182

499

12.4

19.6

15.4

40h

Other than device’s PMBus Addresses and VR operation mode,

all system design parameters are programmed by PMBus, as

summarized in Table 12 and detailed in Table 14.

60h

80h

A0h

C0h

E0h

01h

10h

1.7V, 10mV/Step

09h

28

0.6V, 5mV/Step

1.2V, 10mV/Step

FN8575 Rev 1.00

Aug 13, 2015

Page 33 of 57

ISL6398

TABLE 12. SYSTEM PARAMETER SUMMARY (Continued)

PMBus

TABLE 12. SYSTEM PARAMETER SUMMARY

PMBus

CODE

DESCRIPTION

RANGE

CODE

DESCRIPTION

RANGE

REG

D6

DA

DB

D3

E4

REG

LOCK_VID_OFFSET

Set_VID

0h to 3h

up to 3.04V

80-8E, C0-CE,

E0-EE, F0-FE

PM_ADDR N/A

VR_MODE N/A

PMBus Address

By “VRSEL” pin

5m Step Boot Voltage

10mV Step Boot Voltage

DVID Slew Rate

5mV or 10mVstep

0, 0.25 to 1.52V

Set_OFFSET

Droop Enable

Negative Droop

Positive Droop

IDROOP_TRIM

Output Offset Trim

NPHASE

up to 1.270V

Enable or Disable

100% to 5%

Output

Voltage

Regulation

BT

E6

0, 0.5, 0.51 to 3.04V

0.315 to 13.25mV/µs

Offset, Gain, Slope

F6

D7

D9

0mV, 4mV to 32mV

-4µA to +3.75µA

1 TO 6-PHASE

1.0, 1.25, 1.5, 1.7

12.5, 16.6, 25, 50%

80, 90, 100, 110%

1 TO 4-PHASE

0.6ms to 4.6ms

tsw/8 to tsw

DVID

DVID UP Compensation

DVID Down Compensation

E4

Maximum Operating

Temperature

+85°C to +120°C

(5°C/Step)

D0

D1

D2

D4

99

9A

9B

9D

TMAX

IMAX

NPSI

E8

EA

D2

AUTO_K

I

of Platforms

0-255A, 1A/LSB

SI1, SI2, CI1, CI2

CCMAX

AUTO_HYS

Minimum Number of

Operational Phases in Auto

AUTO_I1

D2

E1

D8

24

DF

F6

E9

Frequency Limiter

SET_UV

2F , 1.5F , Infinity

SW SW

Minimum Phase

AUTO Blanking

APA Time Constant

APA_Stackup_Delay

APA LEVEL

105mV to 402mV

136mV to 549mV

Up to 3.11V

AUTO

SET_OV

Maximum Output Voltage

PROTECTION_DISABLE

INPUT OCP

0 to 300ns

All Faults

10 to 70mV

Protection

100% to 130%

75% to 100%

BOOT REFRESH

AUTO Enable

MFR_ID

Enable or Disable

2 BYTES

Thermal APA

AVG_OCP

CYCLE_LIMITING

1.0 TO 1.6

125% to 70%

F4

MFR_MODEL

MFR_REV

2 BYTES

USER

F7-FC

E4

Current Balance

IMON_TRIM

-12% to +9%

-4µA to +3.75µA

-4h to 3h

2 BYTES

DIGITAL

IOUT (8Ch)

MFR_DATE

3 BYTES

E5

IOUT_CAL_OFFSET

UP Ramp Amplitude

NVM_BANK

D8

0.75, 1.0, 1.2, 1.5V

Up to 8 Banks

DE

D4

Dither Enable

Enable or Disable

Mismatching Temperature

Compensation between

sensing element and NTC

OFF, -2.5°C to

+35.1°C

E9

E2

PS Mode Transition

Compensation

PS Mode Transition

LOOP

E2[4:3]: 20m- 80mV

E3: Phase Count

Original Speedup

High Frequency Transient

Compensation

E2, E3

F5

SET_FREQ

120k TO 2.025MHz

B0-BF

COMPENSATION

R -R3 and C1-C3

1

Original, 2p-16pF

25mV - 200mV

F3

SP_VdBand_K

0 to 0.75, Disable

FN8575 Rev 1.00

Aug 13, 2015

Page 34 of 57

ISL6398

2

before the NVM configuration is loaded completely, the controller

SMBus, PMBus and I C Operation

will issue soft-start 16ms (typically, worst case 20ms) after V

above its POR.

CC

There are 32 PMBus address, which can be programmed by a

resistor divider on VRSEL_ADDR pin, as shown in Figure 32 and

summarized in Table 13.

88h-8Eh are two-byte word read with PEC (if applicable), while

78h, F2h, and other write command codes are one-byte word

read with PEC (if applicable).

2

The ISL6398 features SMBus, PMBus and I C with

programmable address via VRSEL_ADDR pin, as in Table 13,

while SMBus/PMBus includes an Alert# line and Packet Error

Check (PEC) to ensure data properly transmitted. In addition, the

output voltage, droop slope, enable, operating phase number,

and overvoltage setpoint can be written and read via this bus, as

summarized in Table 14. Input, output, fault, and temperature

telemetries can be read as summarized in Table 15. For proper

When PMBus is not used, simply leave the respective pull-up on

their pins and not connect to the bus..

2

TABLE 13. SMBus/PMBus/I C 8-BIT AND 7-BIT FORMAT ADDRESS (HEX)

8-BIT

80/81

82/83

84/85

86/87

88/89

8A/8B

8C/8D

8E/8F

C0/C1

C2/C3

C4/C6

CE/CF

7-BIT

40

41

42

43

44

45

46

47

8-BIT

C8/C9

CA/CB

CC/CD

CE/CF

E0/E1

E2/E3

E4/E5

E6/E7

E8/E9

EA/EB

EC/ED

EE/EF

7-BIT

64

65

66

67

70

71

8-BIT

F0/F1

F2/F3

F4/F5

F6/F7

F8/F9

FA/FB

FC/FD

FE/FF

7-BIT

78

79

7A

7B

7C

2

operation, users should follow the SMBus, PMBus, and I C

protocol, as shown Figure 36. Note that STOP (P) bit is NOT

allowed before the repeated START condition when “reading”

contents of register, as shown in Figure 36.

2

The supported SMBus/PMBus/I C addresses are in 8-bit format

7D

7E

(including write and read bit): 80-8E, E0- EE, C0-CE, F0-FE. The

least significant bit of the 8-bit address is for write (0h) and read

(1h). For reference purposes, the 7-bit format addresses are also

summarized in Table 13. There are a series set of read and write

commands as summarized in Tables 14 and 15, respectively. The

72

73

74

7F

60

61

62

63

75

76

77

2

SMBus/PMBus/I C allows to program the registers as in

2

Table 12, except for SMBus/PMBus/I C addresses, 16ms

(typically, worst case 20ms) after V above POR and prior to

CC

Enable pins (EN_PWR_CFP) high. The bus can also program

default content during this period. If all Enable pins are high

5V

V

CC

WRITE AND READ

CONFIGURATION

WRITE AND READ

CONFIGURATION

LOAD NVM

WRITE AND READ

CONFIGURATION

WRITE AND READ

CONFIGURATION

VCC POR

TIMEOUT

READER

DONE

CONFIGURATION

5 MS

10MS

0MS TO INFINITY

1 MS

0MS TO INFINITY

ENABLE

PMBUS COMMUNICATION NOT ACTIVATED

PMBUS

COMMAND

VBOOT

0 V

V

OUT

2

FIGURE 33. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM

5V

V

CC

WRITE AND READ

CONFIGURATION

WRITE AND READ

CONFIGURATION

LOAD NVM

CONFIGURATION

10MS

VCC POR

TIMEOUT

5 MS

READER

DONE

1 MS

WRITE AND READ

CONFIGURATION

0MS TO INFINITY

ENABLE

PMBUS

COMMAND

PMBUS COMMUNICATION NOT ACTIVATED

PMBUS

COMMAND

PMBUS

COMMAND

VBOOT

V

0 V

OUT

2

FIGURE 34. SIMPLIFIED SMBus/PMBus/I C INITIALIZATION TIMING DIAGRAM WITH ENABLE HIGH BEFORE COMPLETING NVM LOADING

FN8575 Rev 1.00

Aug 13, 2015

Page 35 of 57

ISL6398

S: Start Condition

1. Send Byte Protocol

A: Acknowledge (“0”)

1

7 + 1

1

8

1

8

1

N: Not Acknowledge (“1”)

S

A

Command Code

Slave Address_0

A

PEC

A

P

W: Write (“0”)

RS: Repeated Start Condition

R: Read (“1”)

Optional 9 Bits for SMBus/PMBus

2

PEC: Packet Error Checking

P: Stop Condition

NOT used in I C

Example command: 03h Clear Faults

(This will clear all of the bits in Status Byte for the selected Rail)

Acknowledge or DATA from Slave,

ISL6398

Not Used for One Byte Word

2. Write Byte/Word Protocol

1

7 + 1

1

8

1

8

1

8

1

8

1

S

A

Command Code

Slave Address_0

A

High Data Byte

Low Data Byte

A

PEC

A

P

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

Example command: DAh SET_VID (one word, High Data Byte and ACK are not used)

3. Read Byte/Word Protocol

1

7 + 1

1

8

1

Not Used for One Byte Word Read

S

A

Command Code

Slave Address_0

A

1

7 + 1

1

8

1

8

1

8

1

RS

Low Data Byte

A

Slave Address_1

A

High Data Byte

A

PEC

P

N

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

Example command: 8B READ_VOUT (Two words, read voltage of the selected rail).

NOTE: All Writable commands are read with one byte word protocol.

STOP (P) bit is NOT allowed before the repeated START condition when “reading” contents of a register.

4. Block Write Protocol

1

7 + 1

1

8

1

8

1

8

1

8

1

S

Slave Address_0

A

Command Code

A

Lowest Data Byte

Byte Count = N

A

Data Byte 2

A

1

8

1

8

1

A

Data Byte N

A

PEC

A

P

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

Example command: 9Dh MFR_DATA (3 Data Byte)

2

FIGURE 35. SMBus/PMBus/I C PROTOCOL

FN8575 Rev 1.00

Aug 13, 2015

Page 36 of 57

ISL6398

5. Block Read Protocol

1

7 + 1

1

8

1

7 + 1

8

S

Byte Count = N

Lowest Data Byte

Slave Address_0

A

Command Code

A

RS

Slave Address_1

1

8

1

8

1

Data Byte 2

A

Data Byte N

A

PEC

P

N

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

Example command: 8B READ_VOUT (Two words, read voltage of the selected rail).

NOTE: All Writable commands are read with one byte word protocol.

STOP (P) bit is NOT allowed before the repeated START condition when “reading” contents of a register.

6. Group Command Protocol - No more than one command can be sent to the same Address

1

7 + 1

1

8

1

8

1

8

1

8

1

S

A

Command Code

Slave ADDR1_0

A

Low Data Byte

A

High Data Byte

A

PEC

A

1

8

7 + 1

1

8

1

RS

Command Code

Slave ADDR2_0

A

Data Byte

A

PEC

A

1

8

1

8

7 + 1

1

8

1

8

1

Command Code

A

RS

A

High Data Byte

Slave ADDR3_0

A

Low Data Byte

A

PEC

A

P

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

2

7. Alert Response Address (ARA, 0001_1001, 25h) for SMBus and PMBus, not used for I C

1

7 + 1

1

8

7+1

1

S

Slave_Address_1

A

PEC

ALERT Addr_1

A

P

Optional 9 Bits for SMBus/PMBus

2

NOT used in I C

2

FIGURE 36. SMBus/PMBus/I C PROTOCOL

FN8575 Rev 1.00

Aug 13, 2015

Page 37 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

DESCRIPTION

01h[2:0]

40h

EN pin

OPERATION (or ENABLE)

Bit[7]: 0 = OFF (0-F); 1 = ON (80-8Fh)

Bit[6:4] = 0;

Bit[3:0] = Don’t care

10h[7:5]

R/W

NOT

80h

WRITE_PROTECT_ISL

80h = Disable all standard writes (including send bytes) except

for WRITE_PROTECT_ISL command.

40h = Disable all standard writes (including send bytes), all

compensation registers and some Intersil defined commands,

BUT not WRITE_PROTECT, OPERATION, CLEAR_FAULT, and some

Intersil defined commands.

20h = Disable all standard writes, all compensation registers

and some Intersil defined commands, BUT NOT

WRITE_PROTECT, OPERATION, CLEAR_FAULT and some Intersil

defined commands: LOCK_VID_OFFSET, SET_VID, SET_OFFSET.

10h = Disable all compensation registers and some Intersil

defined commands, BUT not WRITE_PROTECT, OPERATION,

CLEAR_FAULT and some Intersil defined commands (at WRITE

PROTECTION LEVEL OF 20h): LOCK_VID_OFFSET, Set_VID,

Set_OFFSET, Configurations (UVP, OVP, OCP, CFP, IMAX, TMAX,

AUTO, NPHASE, BAL_XX, FREQ, BOOT_VOLTAGE, etc).

00h = Enable all write commands.

Reject all command code except for 80h, 40h, 20h, 10h, 0h

Not support PAGE and ON_OFF_CONFIG; Equivalent

VOUT_COMAND is Set_VID, Set_OFFSET, LOCK_VID_OFFSET.

“WRITE PROTECT LEVEL” = ANYTHING SPECIFIED IN THIS LEVEL

OR BELOW IS ALLOWED TO BE WRITTEN.

15h

16h

SEND

R/W

00h

N/A

STORE_USER_ALL

RESTORE_USER_ALL

VOUT_MAX

Store user configuration (operating memory) into selected

USER_NVM#. The device will declare busy at the assertion of this

command, a new command addressed to this device should be

sent 300ms afterward.

Restore user configuration (USER_NVM#) into operating

memory. The device will declare busy at the assertion of this

command, a new command addressed to this device should be

sent 6ms afterward.

24h[8:0]

NVM_BANK

Set maximum output voltage that VR can command

(VOUT_MAX = VID+OFFSET > BOOT_Voltage).

5mV Mode: Up to 2.155 (H Byte: 01h; L Byte 7Eh, see Table 18);

10mV Mode: Up to 3.11V (High Byte: 01h; Low Byte 06h).

99[15:0]

9A[15:0]

9B[15:0]

9D[23:0]

BLOCK

R/W

00h

N/A

00h

MFR_ID

MFR_MODEL

User stores ID.

BLOCK

R/W

User stores model number.

User stores board and/or configuration revision number.

User stores date.

BLOCK

R/W

MFR_REVISION

MFR_DATE

BLOCK

R/W

AD[15:0] BLOCK R

IC_DEVICE_ID

Intersil Device ID: product ID (update byte, hardcoded) + ISL

configuration revision (lower byte).

AE[15:0]

D0h[2:0]

BLOCK R

R/W

IC_DEVICE_REV

OPERATE_PHASE_NUMBER

Intersil Device Revision: Silicon revision (upper byte, hardcoded)

+ ISL configuration revision (lower byte).

N

By

0h = 7h = N

; 1h=1 Phase;2h = 2 Phases; 3h = 3 Phases;

PHASE

MAX

4h = 4 Phases; 5h = 5 Phases; 6h = 6 Phases. N

set by PWMx

MAX

= 5 Phases. D0

hard wired; for instance if PWM6 = V , N

CC MAX

should NOT be written until 50ms after soft-start and re-written

after DVID. When AUTO (R to GND, not shorted to GND) function

is enabled, D0h cannot use to program phase number but it

reports the operating phase number.

FN8575 Rev 1.00

Aug 13, 2015

Page 38 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

NVM_BANK

COMMAND NAME

DESCRIPTION

D1h[7:0]

00h

NMIN_AUTOK_HYS_I1

Bit[1:0] - Minimum Number of Auto Phase Shedding

0h = 1-Phase;1h = 2-Phase; 2h = 3-Phase; 3h = 4-Phase; Default

by N

PSI

Bit[3:2] - AUTO Mode K Factor:

0h = 1.25; 1h = 1.5; 2h = 1.75; 3h = 1.0; Default by AUTO pin

Bit[5:4] - AUTO Mode Hysteresis Factor

0h = 50%; 1h = 25%; 2h = 16.6%; 3h = 12.5%; Default by AUTO pin

Bit[7:6] - AUTO Mode I1 Factor:

0h = 100%; 1h = 80%; 2h = 90%; 3h = 110% of AUTO pin

D2h[9:0]

R/W

00h

NVM_BANK NPSI_AUTOBLK_FLIMITER_APATC Bit[1:0] - Lower Power Phase Number:

0h = SI1, 1-Phase;

1h = SI2, 2-Phase;

2h = CI1, 1-Phase;

3h = CI2, 2-Phase;

Bit[3:2] - Time between subsequent phase drops:

0h = 4.6ms; 1h = 2.3ms; 2h = 1.2ms; 3h = 0.6ms, Default 0h

Bit[5:4] - Maximum PWM frequency under repetitive Load:

0h = 2 F ; 1h = 3/2 F ; 2h = 3h = Infinity; Default 0h

SW SW

Bit[7:6] - APA Time Constant:

0h = Tsw; 1h = Tsw/2; 2h = Tsw/4; 3h = Tsw/8. Default 3h

Bit[9:8] - APA Stackup Delay:

0h = 0ns; 1h=100ns; 2h = 200ns; 3h = 300ns

D3h[6:0]

R/W

10h

NVM_BANK

NEGLL_POSLL

Bit[0] - Droop Enable:

0h = Disabled, 1h = Enabled;

Bit[3:1] Droop Trim (NEGLL) of Full Scale:

0h = 100%, 1h = 75%, 2h =5 0%, 3h = 25%, 4h = 5%

Adjust R for finer resolution

1

Bit[4]: Positive Load Line Enable:

0h = Disabled; 1h = Enabled

Bit[6:5]: Positive Load Line Range (POSLL):

0h = 4mV, 1h = 8mV; 2h = 16mV, 3h = 32mV at IMON Full Scale

D4h[6:0]

R/W

10h

NVM_BANK BTR_DE_AUTO_DITHER_APALVL Bit[0] - Boot-Refresh Enable:

0h = Disabled; 1h = Enabled. Boot refresh circuits is

automatically turned off when DAC is lower than 0.605V

Bit[1] - Diode Emulation Enable

0h = Disabled; 1h = Enabled

Bit[2] - AUTO Enable:

0h = Disabled; 1h = Enabled

Bit[3] - DITHER Enable:

0h = OFF, 1h = -15kHz, 0, 15kHz

Bit[6:4] - APA Level:

0h = Disable; 1h = 10mV; 2h = 20mV; 3h = 30mV; 4h = 40mV;

5h = 50mV; 6h = 60mV; 7h = 70mV

D5h[1:0]

D6h[1:0]

R/W

00h

20h

NVM_BANK

00h

PWMTRI-LEVEL

Bit[0] - PWM Support: 0h = Compatible with 3.3V PWM Tri-State

(Mid) Level (PWM High is still V , 5V); 1h = Compatible with

CC

5.0V PWM Tri-State (Mid) Level. 5.0V PWM Driver is also

compatible with “0h”, but not vice versa.

LOCK_VID_OFFSET

Secondary output voltage control protection:

0h= VID and OFFSET NOT CONTROLLABLE

1h = Program Small OFFSET, not VID allowed

2h = Program Large OFFSET, not VID allowed

3h = VID and OFFSET CONTROLLABLE

(see Table 16 for details)

D7h[13:0]

BLOCK

R/W

10h

NVM_BANK

DVID_UP_OS_GAIN_SLP

BIT[5:0] - DVID_UP_OFFSET

00h = 0mV

01h = 5mV

02h = 10mV

…

FN8575 Rev 1.00

Aug 13, 2015

Page 39 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

DEFAULT

COMMAND NAME

DESCRIPTION

D7h[13:0]

BLOCK

R/W

10h

NVM_BANK

DVID_UP_OS_GAIN_SLP

3Fh = 315mV

BIT[8:6] - DVID_UP_GAIN

00 = deltavid*0

01h = deltavid/32

02h = deltavid/16

...

07h = deltavid * 7/32

BIT[13:9] - DVID_UP_SLOPE

00h = every 4 clocks(125ns per step - 40mV/µs)

01h = every 8 clocks(250ns per step - 20mV/µs)

...

1Fh = every 128 clocks (4µs per step - 1.25mV/µs)

D8h[6:0]

R/W

10h

NVM_BANK

SET_OV_VRAMP

Bit[2:0] - OVP above VID during normal operation:

0h = 135mV, 1h = 177mV, 2h = 218V, 3h = 260mV, 4h = 342mV,

5h = 425mV, 6h = 460mV, 7h = 549mV; OVP = VID+Bit[2:0] with

hysteresis of 83mV. OVP_WARNING = VID+Bit[2:0]-80mV with

hysteresis of 42mV (see Electrical Specification on Page 10 for

more details). OVP and OVP Warning can be disabled via DFh.

Bit [4:3], soft-start OVP (with 110mV Hysteresis):

0h = 1.58V, 1h = 1.86V; 2h = 2.29V; 3h = 3.32V

Bit[6:5] - VRAMP

0h = 0.75V; 1h = 1.0V; 2h = 1.2V; 3h = 1.5V

D9h[13:0]

BLOCK

R/W

10h

NVM_BANK

DVID_DW_OS_GAIN_SLP

BIT[5:0] - DVID_DW_OFFSET

00h = 0mV

01h = 5mV

02h = 10mV

…

3Fh = 315mV

BIT[8:6] - DVID_DW_GAIN

00 = deltavid*0

01h = deltavid/32

02h = deltavid/16

...

07h = deltavid * 7/32

BIT[13:9] - DVID_DW_SLOPE

00h = every 4 clocks(125ns per step - 40mV/µs)

01h = every 8 clocks(250ns per step - 20mV/µs)

...

1Fh = every 128 clocks(4us per step - 1.25mV/µs)

DAh[7:0]

DBh[7:0]

DCh[4:0]

DDh[7:0]

DEh[2:0]

R/W

R

20h

N/A

20h

00h

NVM_BANK

SET_VID

PMBus VID Code (See Table 4)

PMBus OFFSET Code (See Table 4)

Reference to Resistor Reader. DC

Reference to Resistor Reader. DD

SET_OFFSET

Config Registers

NVM_BANK

R

R/W

Bit[2:0]:

0h = USER_NVM#0

1h = USER_NVM#1

2h = USER_NVM#2

3h = USER_NVM#3

4h = USER_NVM#4

5h = USER_NVM#5

6h = USER_NVM#6 (Copy of NVM#0, otherwise, overwritten)

7h = USER_NVM#7 (Copy of NVM#1, otherwise, overwritten)

Select which memory bank to store or load the configurations

FN8575 Rev 1.00

Aug 13, 2015

Page 40 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

DESCRIPTION

DFh[8:0]

E1h[6:0]

10h

NVM_BANK

PROTECTION_DISABLE

[UV_WARN, OV_WARN,OTP, UVP, IPH_LIMIT, OCP_V, OCP_I,

IIN_OCP, OVP]; OCP_V = IMON_3V Trip; OCP_I = 100uA trip;

IIN_OCP = input OCP; OVP = Output overvoltage trip;

IPH_LIMIT = Phase Current Limiting; UVP = Undervoltage

Protection; OTP = TMAX Trip; OV_WARN = Overvoltage

Warning; UV_WARN = Undervoltage warning.

R/W

10h

NVM_BANK

SET_UVP_DLY_ACTION

Bit[3:0] - Output Under-voltage Protection Level:

0h = 105mV, 1h = 141mV; 2h = 178mV; 3h = 214mV;

4h = 252mV; 5h = 291mV; 6h = 328V; 7h = 402mV;

UVP = DAC - UVP Level with 19mV hysteresis;

UVP_WARNING = DAC-UVP+66mV (or higher) with 17mV

Hysteresis (see Electrical Specification on Page 10 for more

details). UVP and UVP Warning can be disabled via DFh.

Bit[5:4]: Output Under-voltage Protection delay:

0h = 10µs, 1h = 20µs, 2h= 40µs, 3h = 120µs

Bit[6] - UVP_Actions:

0h= Monitor Only; 1h = Hiccup (same as OCP timing)

E2[11:0]

R/W

10h

NVM_BANK ADVANCED_PSCOMP_CONFIG Bit[2:0] PS2 to PS1/0 DCM OFFSET, but make PS0/1 to 2

transition worse, which can help with Bit[8:6]. C2_pop1

momentarily offsets it back up so no dip if C2_pop1 > = bit[2:0]

(NOT USED).

0h = 0mV, 1h = 20mV…….7h = 140mV.

Bit[4:3]: High-Frequency Transient VCOMP Bottom Clamp; the

lower the better.

0h = 20mV, 1h = 40mV, 2h = 60mV, 3h = 80mV

Bit[5] - DECAY_COMP_OFFSET, higher is better (NOT USED))

0h = 100mV, 1h = 200mV

Bit[8:6] - PS0/1 to PS2 Offset (C2_pop1), This likely will take the

same value as Bit[2:0] or higher. This improve PS0/1 to PS2

transition, no affect on PS2 to PS1/0.

0h = 0mV, 1h = 20mV…….7h = 140mV

Bit[10:9] PS1 to PS0 Offset (C2_pop2), no affect on other

transitions.

0h = 0, 1h = 20mv, 2h = 40mV, 3h = 60mV

NOTE:

PS2: Diode Emulation (DE) Operation (Not used)

PS1: 1-Phase or 2-Phase Operation in Auto Based Upon NPSI

PS0: > NSPI Operation Phase

FN8575 Rev 1.00

Aug 13, 2015

Page 41 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

DESCRIPTION

E3[13:0]

10h

NVM_BANK

ADVANCED_MOD_CONFIG

Use these registers to Optimize High Frequency Transient

Response at Different Phase Count with Original Speed up

(F3[2:0] = 0h = Original)

Bit[0]: 1 PHASE dBAND;

0h = normal dBand; 1h = reduced dBand (faster);

Bit[2:1]: 1 PHASE SPEEDUP

0h = 3h = 1/2 decay; 1h = normal decay; 2h = 1/4 decay (faster);

Bit[3]: 2 PHASE dBAND;

0h = normal dBand; 1h = reduced dBand (faster);

Bit[5:4]: 2 PHASE SPEEDUP

0h = 3h = 1/2 decay; 1h = normal decay; 2h = 1/4 decay (faster);

Bit[6]: 3+ PHASE dBAND;

0h = normal dBand; 1h = reduced dBand (faster);

Bit[8:7]: 3+ PHASE SPEEDUP

0h =3h = 1/2 decay; 1h = normal decay; 2h = 1/4 decay (faster);

Bit[10:9]: Peak-Detect CAP

0h = 1pF, 1h = 2pF, 2h = 3pF; 3h = 4pF (smaller cap is less

sensitive)

Bit[12:11]: High-pass CAP

0h = 1pF, 1h = 2pF, 2h = 3pF; 3h = 4pF (bigger cap, more

sensitive)

Bit[13]: High-Frequency Balance Gain

0h = 1x; 1h= 2x gain

E4[9:0]

R/W

20h

NVM_BANK

IMON_IDROOP_TRIM

Bit[4:0] - No Load IMON Trim (-4.0 µA to 3.75µA), add current

through R at droop enabled and out of IMON pin together

1

0h = 0µA......................................10h = -0.25µA

1h = 0.25µA................................11h = -0.50µA

2h = 0.50µA................................12h = -0.75µA

3h = 0.75µA................................13h = -1.00µA

4h = 1.00µA................................14h = -1.25µA

5h = 1.25µA................................15h = -1.50µA

6h = 1.50µA................................16h = -1.75µA

7h = 1.75µA................................17h = -2.00µA

8h = 2.00µA................................18h = -2.25µA

9h = 2.25µA................................19h = -2.50µA

Ah = 2.50µA................................1Ah = -2.75µA

Bh = 2.75µA................................1Bh = -3.00µA

Ch = 3.00µA................................1Ch = -3.25µA

Dh = 3.25µA................................1Dh = -3.50µA

Eh = 3.50µA.................................1Eh = -3.75µA

Fh = 3.75µA.................................1Fh = -4.00µA

Bit[9:5] - No Load IDROOP Trim (-4.0 µA to 3.75µA), add current

through R regardless droop enabled or disabled; use it to fine

1

tune DC offset

0h = 0µA .....................................10h = -0.25µA

1h = 0.25µA................................11h = -0.50µA

2h = 0.50µA................................12h = -0.75µA

3h = 0.75µA................................13h = -1.00µA

4h = 1.00µA................................14h = -1.25µA

5h = 1.25µA................................15h = -1.50µA

6h = 1.50µA................................16h = -1.75µA

7h = 1.75µA................................17h = -2.00µA

8h = 2.00µA................................18h = -2.25µA

9h = 2.25µA................................19h = -2.50µA

Ah = 2.50µA................................1Ah = -2.75µA

Bh = 2.75µA................................1Bh = -3.00µA

Ch = 3.00µA................................1Ch = -3.25µA

Dh = 3.25µA................................1Dh = -3.50µA

Eh = 3.50µA.................................1Eh = -3.75µA

Fh = 3.75µA.................................1Fh = -4.00µA

FN8575 Rev 1.00

Aug 13, 2015

Page 42 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

DESCRIPTION

E5[8:0]

20h

NVM_BANK

IOUT_CAL_OFFSET

OFFSETfor PMBus READ_IOUT (8Ch):

Bit[2:0] 1-Phase: 0h = 0h; 1h = 1h; 2h = 2h; 3h = 3h; 4h = -4h;

5h = -3h; 6h = -2h; 7h = -1h;

Bit[5:3] 2-Phase = 0h = 0h; 1h = 1h; 2h = 2h; 3h = 3h; 4h = -4h;

5h = -3h; 6h = -2h; 7h = -1h;

Bit[8:6] 3-6Phase = 0h = 0h; 1h = 1h; 2h = 2h; 3h = 3h; 4h = -4h;

5h = -3h; 6h = -2h; 7h = -1h;

E6[7:0]

R/W

10h

NVM_BANK

B00T_Voltage

TMAX_IINMAX

10mV: 0, 0.5V, 0.51 to 3.04V;

5mV: 0, 0.25, 0.255 To1.52V (see Table 4).

The data in this register does not represent the boot voltage

programmed by “BT” pin, which can be read via SET_VID.

E7[7:0]

E8[6:0]

R/W

10h

NVM_BANK

Reserved_RSET

Bit[2:0] - Tmax:

0h: 100°C

1h: 105°C

2h: 110°C

3h: 115°C

4h: 120°C

5h: 85°C

6h: 90°C

7h: 95°C

Bit[5:3] - IINMAX (Scale IIN_READ):

0h = 31A; 1h = 15A; 2h = 7A; 3h = 3A; 4h = 1A

E9[5:0]

R/W

10h

NVM_BANK

THERMAL_TCOMP_APA

Bit[3:0] - Thermal Compensation Offset:

0h: OFF

1h: -2.5°C

2h: 0.0°C

3h: 2.5°C

4h: 5.0°C

5h: 7.0°C

6h: 10.0°C

7h: 13.0°C

8h: 16.0°C

9h: 18.9°C

Ah: 21.6°C

Bh: 24.3°C

Ch: 27.0°C

Dh: 29.7°C

Eh: 32.4°C

Fh: 35.1°C

Bit[5:4]- Thermal APA:

0h = 75%; 1h = 82%; 2h = 91%;3h = 100% of TMAX

EA[7:0]

R/W

10h

NVM_BANK

IMAX

Scale READ_IOUT (IMON = 2.5V will read IMAX)

[0h, 1h:FFh] = [0A, 1A: 255A], 1A/step

F3h[8:0]

SPUP_dBAND_K

For Advanced User ONLY. Speedup (other than Bit[2:0] = Original)

will disable frequency limiter so the switching frequency could

increase with the load repetitive rate. The higher the

capacitance, the faster the speed, which could lead to PSI1/2 to

PS0 transition oscillation. Use with caution.

Bit[2:0] Speed UP

0h = Original; 1h = 2pF; 2h = 4pF; 3h = 6pF; 4h = 8pF; 5h = 10pF;

6h = 12pF; 7h = 16pF

Bit[5:3] VCOMP-dBand

0h = 25mV; 1h = 50mV; 2h = 75mv; 3h = 100mV; 4h = 125mV;

5h = 150mV; 6h = 175mV; 7h = 200mV;

Bit[7:6] K-Factor

0h = 0; 1h = 0.25; 2h = 0.5; 3h = 0.75

Bit[8] K-Disabled in DCM

0h = Enable; 1h = Disable

FN8575 Rev 1.00

Aug 13, 2015

Page 43 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

OCP_ICL_TRIM

DESCRIPTION

F4[5:0]

10h

NVM_BANK

Bit [3:0]- OCP Level (IOCP_AVG and ICL):

0h = 1.0, 1h = 1.1, 2h = 1.2; 3h = 1.4, 4h = 1.5, 5h = 1.6 of IMON

Bit [5:4]- Output Current Cycle Limiting (ICL):

0h = 125%, 01h = 110%, 2h = 100%; 3h = 95%, 4h = 0%,

5h = 85%, 6h = 80%, 7h = 70%

F5h[6:0]

F6h[6:0]

R/W

10h

NVM_BANK

SET_FREQ

DVID_CFP

0h- 7Fh = 120kHz to 2025kHz, 15kHz/Step

Bit[4:0] - Soft-Start and DVID Rate

0h = 0.315mV/µs; 1h = 0.625mV/µs; 2h = 1.25mV/µs;

3h = 2.5mV/µs; 4h = 2.85mV/µs; 5h = 3.07mV/µs;

6h = 3.33mV/µs; 7h = 3.63mV/µs, 8h = 4.0mV/µs,

9h = 4.44 mV/µs; Ah = 5.0mV/µs; Bh = 5.6mV/µs;

Ch = 6.66mV/µs; Dh = 8.0mV/µs; Eh = 10mV/µs;

Fh = 13.25mV/µs

Bit[6:5] - IN_OCP

0h = 100%, 1h = 110%, 2h = 120%,3h = 130%

F7h[2:0]

F8h[2:0]

F9h[2:0]

FAh[2:0]

FBh[2:0]

FCh[2:0]

R/W

10h

NVM_BANK

F7 = BAL_TRIM_PHASE1

F8 = BAL_TRIM_PHASE2

F9 = BAL_TRIM_PHASE3

FA = BAL_TRIM_PHASE4

FB = BAL_TRIM_PHASE5

FC = BAL_TRIM_PHASE6

0h = -12% of full scale

1h = -9% of full scale

2h = -6% of full scale

3h = -3% of full scale

4h = No Offset

5h = +3% of full scale

6h = +6% of full scale

7h = +9% of full scale

FD[15:0]

R

N/A

CHECK_SUM

Read Calculated CheckSum for individual NVM Bank checksum

10ms after execute EEh(80h) command and 60ms for the total

checkSum after execute EEh(40h).

03h

ARA

W

R

40h

CLEAR_FAULTS

Clear “Latched” Fault Registers in 78h For Selected Rail

ALERT_RESPONSE_ADDRESS 8-bit Address: 0001_1001, 19h; 7-bit Address: 0C

COMPENSATION REGISTERS

B0h[7:0]

R/W

00h

NVM_BANK

R

250 Steps: 1.01018x

00h = 599.0

01h = 605.1

...

1

F9h = 7471

B1h[4:0]

R/W

R2

30 Steps: 1.1x

00h = 2k

01h = 2.2

...

1Dh = 32K

B2h[4:0]

B3h[4:0]

B4h[4:0]

B5h[4:0]

B6h[4:0]

B7h[4:0]

R/W

00h

NVM_BANK

R3_6PHASE

R3_5PHASE

R3_4PHASE

R3_3PHASE

R3_2PHASE

R3_1PHASE

30 Steps: 1.1x

00h = 50k

01h= 55

...

1Dh =790

B2 = 1Fh, will Remove R3/C3 for all Phase Count.

Larger R3 and/or smaller C3 help reduce output noise coupling.

Recommend to keep R3/C3 the same values for highest phase

count (Nmax) and Nmax-1 Phase count for smoother transition.

B8h[5:0]

R/W

00h

NVM_BANK

C1

42 Steps: 1.1x

00h = 10pF

01h = 11pF

...

29h = 500pF

FN8575 Rev 1.00

Aug 13, 2015

Page 44 of 57

ISL6398

2

TABLE 14. SMBus, PMBus, AND I C WRITE AND READ REGISTERS

WRITE

PROTECT

LEVEL

COMMAND

CODE

ACCESS

R/W

DEFAULT

COMMAND NAME

C2

DESCRIPTION

B9h[5:0]

00h

NVM_BANK

42 Steps: 1.1x

00h = 330pF

01h = 363pF

...

29h = 16.4nF

BAh[5:0]

BBh[5:0]

BCh[5:0]

BDh[5:0]

BEh[5:0]

BFh[5:0]

R/W

00h

NVM_BANK

C3_6PHASE

C3_5PHASE

C3_4PHASE

C3_3PHASE

C3_2PHASE

C3_1PHASE

42 Steps: 1.1x

00h = 100pF

01h = 110pF

...

29h = 5.0nF

DIRECT ACCESS TO EEPROM (ADVANCED USER AND TEST MODE ONLY)

EC[7:0]

R/W

00h

EEP_ADDR_REG

EEP_DATA_REG

Give user access to EEPROM Address

ED[31:0]

BLOCK

R/W

ALL ZEROs

User Write 4-bytes (32-bits) of data into called address by EC

EE[7:0]

R/W

00h

0000h

EEP_ACTIVATE

EEPROM Control Register

Bit[0] = 1h, Start EEPROM Read Procedure

Bit[1] = 1h, Start EEPROM Write Procedure

Bit[5:2] - Reserved

Bit[6] = 1h, Generate Total Checksum (FD data).

Bit[7] = 1h, Generate Individual NVM BANK Checksum (FD data).

The device will declare busy at the assertion of this command, a

new command addressed to this device should be sent 300ms

afterward

When the controller is reset by the Enable pins (TM_EN_OTP or EN_PWR_CFP), not V , the programmed registers will be stored in operating memory.

CC

2

TABLE 15. SMBus, PMBus, AND I C TELEMETRIES

WORD LENGTH

CODE

(BYTE)

COMMAND NAME

READ_VIN

DESCRIPTION

Input Voltage (25.5V = FF)

TYPICAL RESOLUTION

8-BIT, 100mV

88h[15:0]

TWO

Formula: HEX2DEC(Readout)*0.1V

89h[15:0]

8Bh[15:0]

8Ch[15:0]

TWO

READ_IIN

READ_VOUT

READ_IOUT

Input Current (1Fh = 10µA)

5-BIT, IIN_FULL/31

10-BIT, 5mV

VR Output Voltage (HEX2DEC(Readout)*0.05V)

VR Output Current (2.5V IMON = ICCMAX)

HEX2DEC(Readout)*ICCMAX/255

8-BIT,~1A

8Dh[15:0]

TWO

READ_TEMPERATURE_1 TM Temperature (see Table 17)

8-BIT, ~1°C*

Approximation Formula for Table 19

(T in °C): -0.0000221*T + 0.0094935*T - 1.876*T + 213.75

3

2

96h[15:0]

97h[15:0]

78h[8:0]

TWO

ONE

READ_POUT

READ_PIN

Output Power

Input Power

~ 2W (~1A LSB @ 2V)

~12W (~1A LSB @ 12V)

STATUS_BYTE

Fault Reporting;

Bit7 = Busy

[BUSY, 0, OV, OC, 0, OT,

CML, 0]

Bit6 = 0

Bit5 = OverVoltage;

Bit4 = OverCurrent, I

;

MAX

Bit3 = 0

Bit2 = Over-Temperature, T

;

MAX

Bit1 = PMBus Communication Error

Bit0 = 0

FN8575 Rev 1.00

Aug 13, 2015

Page 45 of 57

ISL6398

2

TABLE 15. SMBus, PMBus, AND I C TELEMETRIES

WORD LENGTH

(BYTE)

CODE

COMMAND NAME

STATUS_WORD

DESCRIPTION

TYPICAL RESOLUTION

79h[15:0]

TWO

Lower Byte Fault Reporting (= 78h);;

Bit7 = Busy

Bit6 = 0

Bit5 = OverVoltage;

Bit4 = OverCurrent, I

;

MAX

Bit3 = 0

Upper Byte: [V , I

OUT OUT,

Bit2= Over-Temperature, T

;

IIN_OCP, 0, 0, 0, 0, 0]

MAX

Bit1 = PMBus Communication Error

Bit0 = 0

Lower Byte: [BUSY, 0, OV,

OC, 0, OT, CML, 0]

Upper Byte Fault Reporting;

Bit7 = V

Bit6 = I

OV, UV, and OV/UV Warning

OC

OUT

Bit5 = INPUT OCP >= 1F;

Bit[4:0] = 0

NOTE: 88h-8Eh are two bytes word, while all others are one byte word.

TABLE 16. LOCK_VID_OFFSET

D6h

00h

01h

02h

03h

SET_VID

Not

SET_OFFSET

FINAL DAC

VBOOT

TARGETED APPLICATIONS

Not

Yes

Not output voltage managed needed

Small offset for compensation

Large Offset for Voltage Margining

Dynamic VID Operation Needed

Not

VBOOT+OFFSET

VBOOT + OFFSET

VID + OFFSET

Not

Yes

NOTE: The ISL6398 is designed to provide secondary output voltage control protection. When D6-0h, it keeps output voltage the same as boot up voltage.

2

When operating in 01h option, SMBus/PMBus/I C’s OFFSET should only adjust slightly higher or lower (say ±20mV, but IC does not limit the range) for

PCB loss compensation. To program full range of OFFSET, the user should select 02h or 03h options. 03h option gives users full control of the output

2

voltage (VID+OFFSET) via SMBus/PMBus/I C, commonly used in over-clocking applications. Prior to a successful written PMBus VID or OFFSET, the

controller will continue stay at boot up level.

FN8575 Rev 1.00

Aug 13, 2015

Page 46 of 57

ISL6398

TABLE 17. TYPICAL TEMPERATURE (8Dh and 8Eh) (Continued)

TABLE 17. TYPICAL TEMPERATURE (8Dh and 8Eh)

TEMPERATURE

(°C)

V

OF CODE TEMPERATURE

V

OF CODE

TM(S)

TEMPERATURE

(°C)

V

OF CODE TEMPERATURE

V

OF CODE

TM(S)

(%) (HEX)

TM(S)

(%) (HEX)

(°C)

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

(%)

(HEX)

54

53

52

50

4F

(°C)

(%)

(HEX)

96

94

92

90

8E

8D

8B

89

87

85

83

82

80

7E

7C

7B

79

77

75

74

CC

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

80.2

79.7

79.1

78.5

77.9

77.3

76.7

76.1

75.5

74.8

74.2

73.5

72.9

72.2

71.6

70.9

70.2

69.5

68.8

68.2

67.5

66.8

66.1

65.4

64.6

63.9

63.2

62.5

61.8

61.1

60.3

59.6

CC

CB

C9

C8

C6

C5

C3

C2

C0

BE

BD

BB

B9

B8

B6

B4

B3

B1

AF

AD

AC

AA

A8

A6

A4

A3

A1

9F

9D

9B

99

98

33.3

0

95.0

94.8

94.6

94.4

94.1

93.9

93.6

93.4

93.1

92.8

92.6

92.3

92.0

91.6

91.3

91.0

90.7

90.3

89.9

89.6

89.2

88.8

88.4

88.0

87.6

87.2

86.7

86.3

85.8

85.4

84.9

84.4

83.9

83.4

82.9

82.4

81.9

81.3

80.8

F2

F1

F0

EF

71

58.9

32.8

32.2

31.7

31.2

30.7

30.2

29.7

29.2

28.7

28.2

27.8

27.3

26.9

26.4

26.0

25.5

25.1

24.7

24.3

23.9

23.5

23.1

22.7

22.3

21.9

21.6

21.2

20.8

20.5

20.1

1

72

58.2

57.5

56.7

56.0

55.3

54.6

53.9

53.2

52.4

51.7

51.0

50.3

49.6

48.9

48.2

47.6

46.9

46.2

45.5

44.9

44.2

43.5

42.9

42.3

41.6

41.0

40.4

39.7

39.1

38.5

37.9

37.3

36.7

36.1

35.5

35.0

34.4

33.9

2

73

3

74

4

75

4E

4D

4B

4A

49

48

46

45

44

43

42

41

40

3E

3D

3C

3B

3A

39

38

37

36

35

34

33

5

76

6

EE

ED

EC

EB

EA

E9

E8

E7

E6

E5

E4

E3

E2

E1

E0

DF

DE

DD

DC

DA

D9

D8

D7

D6

D4

D3

D2

D0

CF

CD

77

7

78

8

79

9

80

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

81

82

83

84

85

86

87

88

89

90

91

72

70

6F

6D

6B

6A

68

66

65

63

62

60

5F

5D

5C

5A

59

57

56

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

FN8575 Rev 1.00

Aug 13, 2015

Page 47 of 57

ISL6398

TABLE 18. VOUT_MAX (24h) in 5MV/STEP MODE (Continued)

TABLE 18. VOUT_MAX (24h) in 5MV/STEP MODE

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

VOUT (V)

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

VOUT (V)

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1.265

1.270

VOUT (V)

1.720

1.725

1.730

1.735

1.740

1.745

1.750

1.755

1.760

1.765

1.770

1.775

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

1.825

1.830

1.835

1.840

1.845

1.850

1.855

1.860

1.865

1.870

1.875

1.880

1.885

1.890

1.895

1.900

1.905

1.910

VOUT (V)

0.000

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

VOUT (V)

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

0.955

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

1.075

VOUT (V)

1.525

1.530

1.535

1.540

1.545

1.550

1.555

1.560

1.565

1.570

1.575

1.580

1.585

1.590

1.595

1.600

1.605

1.610

1.615

1.620

1.625

1.630

1.635

1.640

1.645

1.650

1.655

1.660

1.665

1.670

1.675

1.680

1.685

1.690

1.695

1.700

1.705

1.710

1.715

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

127

128

129

12A

12B

12C

12D

12E

12F

130

131

132

133

134

135

136

137

138

139

13A

13B

13C

13D

13E

13F

140

141

142

143

144

145

146

147

148

149

14A

14B

14C

14D

0

1

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

100

101

102

103

104

105

106

107

108

109

10A

10B

10C

10D

10E

10F

110

111

112

113

114

115

116

117

118

119

11A

11B

11C

11D

11E

11F

120

121

122

123

124

125

126

2

3

4

5

6

7

8

9

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

FN8575 Rev 1.00

Aug 13, 2015

Page 48 of 57

ISL6398

TABLE 18. VOUT_MAX (24h) in 5MV/STEP MODE (Continued)

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

Code

(HEX)

VOUT (V)

0.635

0.640

0.645

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

VOUT (V)

1.275

1.280

1.285

1.290

1.295

1.300

1.305

1.310

1.315

1.320

1.325

1.330

1.335

1.340

1.345

1.350

1.355

1.360

1.365

1.370

1.375

1.380

1.385

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

1.435

1.440

1.445

1.450

1.455

1.460

1.465

VOUT (V)

1.915

1.920

1.925

1.930

1.935

1.940

1.945

1.950

1.955

1.960

1.965

1.970

1.975

1.980

1.985

1.990

1.995

2.000

2.005

2.010

2.015

2.020

2.025

2.030

2.035

2.040

2.045

2.050

2.055

2.060

2.065

2.070

2.075

2.080

2.085

2.090

2.095

2.100

2.105

VOUT (V)

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

VOUT (V)

1.470

1.475

1.480

1.485

1.490

1.495

1.500

1.505

1.510

1.515

1.520

VOUT (V)

2.110

2.115

2.120

2.125

2.130

2.135

2.140

2.145

2.150

2.155

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

14E

14F

150

151

152

153

154

155

156

157

158

159

15A

15B

15C

15D

15E

15F

160

161

162

163

164

165

166

167

168

169

16A

16B

16C

16D

16E

16F

170

171

172

173

174

75

76

77

78

79

7A

7B

7C

7D

7E

7F

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

175

176

177

178

179

17A

17B

17C

17D

17E

General Design Guide

This design guide is intended to provide a high-level explanation of

the steps necessary to create a multiphase power converter. It is

assumed that the reader is familiar with many of the basic skills

and ‘techniques referenced in the following. In addition to this

guide, Intersil provides complete reference designs, which include

schematics, bills of materials, and example board layouts for

multi-phase VR applications.

Power Stages

The first step in designing a multiphase converter is to determine

the number of phases. This determination depends heavily upon

the cost analysis, which in turn depends on system constraints

that differ from one design to the next. Principally, the designer

will be concerned with whether components can be mounted on

both sides of the circuit board; whether through-hole components

are permitted; and the total board space available for power

supply circuitry. Generally speaking, the most economical

solutions are those in which each phase handles between 15A

and 25A. All surface mount designs will tend toward the lower

end of this current range. If through-hole MOSFETs and inductors

can be used, higher per-phase currents are possible. In cases

where board space is the limiting constraint, current can be

pushed as high as 40A per phase, but these designs require heat

sinks and forced air to cool the MOSFETs, inductors and heat

dissipating surfaces.

MOSFETs

The choice of MOSFETs depends on the current each MOSFET will

be required to conduct; the switching frequency; the capability of

the MOSFETs to dissipate heat; and the availability and nature of

heat sinking and air flow.

F0

F1

F2

F3

F4

FN8575 Rev 1.00

Aug 13, 2015

Page 49 of 57

ISL6398

commutation is t and the approximated associated power loss

LOWER MOSFET POWER CALCULATION

1

is P

.

UP,1

The calculation for heat dissipated in the lower MOSFET is

simple, since virtually all of the heat loss in the lower MOSFET is

due to current conducted through the channel resistance

t



1

I



M

p-p

2







(EQ. 36)

P

 V

F

SW

 ---- 

----- + --------

UP,1

IN



2

N





(r

). In Equation 33, I is the maximum continuous output

DS(ON)

M

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 37, the approximate

current; I

P-P

on page 15); d is the duty cycle (V

is the peak-to-peak inductor current (see Equation 1

/V ); and L is the

2

OUT IN

power loss is P

.

per-channel inductance.

UP,2

t

I













I

(EQ. 37)

2

M

p-p

2







P

 V

F

SW

----

----- – --------

2

UP,2

IN

2

I



2

N













I

p-p

(EQ. 33)

M

P

= r

+ ---------  1 – d

-----

LOW 1

DSON

12

N

A third component involves the lower MOSFET’s reverse-recovery

charge, Q . Since the inductor current has fully commutated to the

upper MOSFET before the lower MOSFET’s body diode can draw all

rr

An additional term can be added to the lower MOSFET loss

equation to account for additional loss accrued during the dead

time when inductor current is flowing through the lower MOSFET

body diode. This term is dependent on the diode forward voltage

of Q , it is conducted through the upper MOSFET across V . The

rr

IN

power dissipated as a result is P

and is approximated in

UP,3

Equation 38:

at I , V

; the switching frequency, F ; and the length of

M

D(ON)

SW

(EQ. 38)

P

= V

Q F

dead times, t and t , at the beginning and the end of the

d1 d2

UP,3

IN rr SW

lower MOSFET conduction interval respectively.

The resistive part of the upper MOSFET’s is given in Equation 33

as P

.

UP,4

2













I

p-p

I

(EQ. 39)

M

P

 r

+

 d

---------

12

-----

UP,4

DSON

N









I

M

 N

I









M

p-p

2

(EQ. 34

p-p

2 

P

= V

F

DON SW

t

d2

+

----- + --------

----- – --------

LOW 2

d1

N

Equation 40 accounts for some power loss due to the drain-

source parasitic inductance (L , including PCB parasitic

DS

inductance) of the upper MOSFETs, although it is not the exact:

2







I







I

p-p

2

M

(EQ. 40)

P

 L

+

--------

-----

UP,5

DS

Finally, the power loss of output capacitance of the lower

MOSFET is approximated in Equation 35:

N

Finally, the power loss of output capacitance of the upper

MOSFET is approximated in Equation 41:

2

3

1.5

(EQ. 35)

--

P



 V

 C



V

 F

DS_LOW SW

LOW,3

IN

OSS_LOW

2

3

1.5

(EQ. 41)

--

P



 V

 C



V

 F

DS_UP SW

UP,6

IN

OSS_UP

where C

OSS_LOW

is the output capacitance of lower MOSFET at the

. Depending on the amount of ringing, the

test voltage of V

DS_LOW

actual power dissipation will be slightly higher than this.

where C

is the output capacitance of lower MOSFET at

OSS_UP

test voltage of V

. Depending on the amount of ringing, the

DS_UP

Thus the total maximum power dissipated in each lower MOSFET is

actual power dissipation will be slightly higher than this.

approximated by the summation of P

, P

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the upper MOSFET

and P

.

LOW,1 LOW,2

LOW,3

The total power dissipated by the upper MOSFET at full load can

now be approximated as the summation of the results from

Equations 36 to 41. Since the power equations depend on

MOSFET parameters, choosing the correct MOSFETs can be an

iterative process involving repetitive solutions to the loss

equations for different MOSFETs and different switching

frequencies.

DS(ON)

losses are due to currents conducted across the input voltage (V )

IN

during switching. Since a substantially higher portion of the upper

MOSFET losses are dependent on switching frequency, the power

calculation is more complex. Upper MOSFET losses can be divided

into separate components involving the upper-MOSFET switching

Current Sensing Resistor

times; the lower MOSFET body-diode reverse-recovery charge, Q ;

rr

and the upper MOSFET r

DS(ON)

conduction loss.

The resistors connected to the ISEN+ pins determine the gains in

the load-line regulation loop and the channel-current balance

loop as well as setting the overcurrent trip point. Select values for

these resistors by using Equation 42:

When the upper MOSFET turns off, the lower MOSFET does not

conduct any portion of the inductor current until the voltage at

the phase node falls below ground. Once the lower MOSFET

begins conducting, the current in the upper MOSFET falls to zero

as the current in the lower MOSFET ramps up to assume the full

inductor current. In Equation 36, the required time for this

R

I

OCP

N

X

(EQ. 42)

R

= -------------------------- -------------

–

ISEN

6

100 10

where R

ISEN

is the sense resistor connected to the ISEN+ pin, N

is the active channel number, R is the resistance of the current

X

FN8575 Rev 1.00

Aug 13, 2015

Page 50 of 57

ISL6398

sense element, either the DCR of the inductor or R

where N is the active channel number, R

is the sense resistor

SENSE

ISEN

connected to the ISEN+ pin, and R is the resistance of the

depending on the sensing method, and I

overcurrent trip point. Typically, I

OCP

is the desired

can be chosen to be 1.2

OCP

X

current sense element, either the DCR of the inductor or R

depending on the sensing method.

SEN

times the maximum load current of the specific application.

With integrated temperature compensation, the sensed current

signal is independent of the operational temperature of the

power stage, i.e. the temperature effect on the current sense

If one or more of the current sense resistors are adjusted for

thermal balance (as in Equation 43), the load-line regulation

resistor should be selected based on the average value of the

current sensing resistors, as given in Equation 46:

element R is cancelled by the integrated temperature

X

compensation function. R in Equation 42 should be the

resistance of the current sense element at the room

temperature.

X

R

LL

R

= ----------

R

ISENn

(EQ. 46)



FB

R

X

n

When the integrated temperature compensation function is

disabled by selecting “OFF” TCOMP code, the sensed current will

be dependent on the operational temperature of the power

stage, since the DC resistance of the current sense element may

where R

is the current sensing resistor connected to the

ISEN(n)

th

n

ISEN+ pin.

Output Filter Design

be changed according to the operational temperature. R in

X

The output inductors and the output capacitor bank together to

form a low-pass filter responsible for smoothing the pulsating

voltage at the phase nodes. The output filter also must provide

the transient energy until the regulator can respond. Because it

has a low bandwidth compared to the switching frequency, the

output filter necessarily limits the system transient response. The

output capacitor must supply or sink load current while the

current in the output inductors increases or decreases to meet

the demand.

Equation 42 should be the maximum DC resistance of the

current sense element at the all operational temperature.

In certain circumstances, especially for a design with an

unsymmetrical layout, it may be necessary to adjust the value of

one or more ISEN resistors for VR. When the components of one

or more channels are inhibited from effectively dissipating their

heat so that the affected channels run cooler than the average,

choose new, larger values of R

for the affected phases (see

ISEN

the section entitled “Current Sensing” on page 18). Choose

in proportion to the desired increase in temperature rise

in order to cause proportionally more current to flow in the cooler

phase, as shown in Equation 43:

In high-speed converters, the output capacitor bank is usually the

most costly (and often the largest) part of the circuit. Output filter

design begins with minimizing the cost of this part of the circuit.

The critical load parameters in choosing the output capacitors are

the maximum size of the load step, DI; the load-current slew rate,

di/dt; and the maximum allowable output-voltage deviation under

R

ISEN,2

T

2

R

= R

----------

ISEN,2

ISEN

T

(EQ. 43)

1

transient loading, DV

. Capacitors are characterized according

MAX

R

– R

ISEN

ISEN,2

to their capacitance, ESR, and ESL (equivalent series inductance).

In Equation 43, make sure that T is the desired temperature rise

At the beginning of the load transient, the output capacitors supply

all of the transient current. The output voltage will initially deviate by

an amount approximated by the voltage drop across the ESL. As the

load current increases, the voltage drop across the ESR increases

linearly until the load current reaches its final value. The capacitors

selected must have sufficiently low ESL and ESR so that the total

output-voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount, as

shown in Equation 47:

2

above the ambient temperature, and T is the measured

1

temperature rise above the ambient temperature. Since all

channels’ R

are integrated and set by one RSET, a resistor

) can be in series with the cooler channel’s ISEN+ pin to

ISEN

(R

ISEN

raise this phase current. However, the ISL6398 can adjust the

thermal/current balance of the VR via registers F7 to FC.

Load-line Regulation Resistor

The load-line regulation resistor is labelled R in Figure 11. Its

FB

di

value depends on the desired loadline requirement of the

application.

(EQ. 47)

V  ESL ---- + ESR I

dt

The filter capacitor must have sufficiently low ESL and ESR so

that V < V

The desired loadline can be calculated using Equation 44:

.

MAX

V

DROOP

R

= ------------------------

(EQ. 44)

LL

I

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination with

bulk capacitors having high capacitance but limited high

frequency performance. Minimizing the ESL of the high

frequency capacitors allows them to support the output voltage

as the current increases. Minimizing the ESR of the bulk

capacitors allows them to supply the increased current with less

output voltage deviation.

FL

where I is the full load current of the specific application, and

FL

VR

is the desired voltage droop under the full load

DROOP

condition.

Based on the desired loadline R , the loadline regulation

LL

resistor can be calculated using Equation 45:

 R

N  R

LL

ISEN

R

X

R

= -----------------------------------------

(EQ. 45)

FB

The ESR of the bulk capacitors also creates the majority of the

output-voltage ripple. As the bulk capacitors sink and source the

FN8575 Rev 1.00

Aug 13, 2015

Page 51 of 57

ISL6398

inductor AC ripple current (see “Interleaving” on page 15 and

Equation 2), a voltage develops across the bulk-capacitor ESR

0.3

0.2

0.1

0

equal to I

(ESR). Thus, once the output capacitors are

c(p-p)

selected, the maximum allowable ripple voltage, V

,

P-P(MAX)

determines the lower limit on the inductance, as shown in

Equation 48.

V

 K

OUT

RCM

(EQ. 48)

L

----------------------------------------------------------

 ESR 

F

 V  V

IN

SW

PPMAX

Since the capacitors are supplying a decreasing portion of the

load current while the regulator recovers from the transient, the

capacitor voltage becomes slightly depleted. The output

inductors must be capable of assuming the entire load current

I

= 0

L(P-P)

= 0.5 I

O

= 0.75 I

0.2

O

0

0.4

0.6

0.8

1.0

before the output voltage decreases more than DV

. This

MAX

DUTY CYCLE (V

/V

)

OUT IN

places an upper limit on inductance.

FIGURE 37. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR 2-PHASE CONVERTER

Equation 49 gives the upper limit on L for the cases when the

trailing edge of the current transient causes a greater output-

voltage deviation than the leading edge. Equation 50 addresses

the leading edge. Normally, the trailing edge dictates the

selection of L because duty cycles are usually less than 50%.

Nevertheless, both inequalities should be evaluated, and L

should be selected based on the lower of the two results. In each

equation, L is the per-channel inductance, C is the total output

capacitance, and N is the number of active channels.

For a 2-phase design, use Figure 37 to determine the input capacitor

RMS current requirement given the duty cycle, maximum sustained

output current (I ), and the ratio of the per-phase peak-to-peak

O

inductor current (I

) to I . Select a bulk capacitor with a ripple

L(P-)P

O

current rating which will minimize the total number of input

capacitors required to support the RMS current calculated. The

voltage rating of the capacitors should also be at least 1.25 times

greater than the maximum input voltage.

2  N  C  V

OUT

(EQ. 49)

L  ----------------------------------------- V

– I  ESR

MAX

2

0.3





I

I

= 0

I

= 0.5 I

O

L(P-P)

= 0.25 I

= 0.75 I

O

L(P-P)

O

L(P-P)

(EQ. 50)

 N  C

1.25







L  ---------------------------- V

– I  ESR

V

– V

IN OUT

MAX

2







I

0.2

0.1

0

Switching Frequency Selection

There are a number of variables to consider when choosing the

switching frequency, as there are considerable effects on the upper-

MOSFET loss calculation. These effects are outlined in “MOSFETs”

on page 49, and they establish the upper limit for the switching

frequency. The lower limit is established by the requirement for fast

transient response and small output-voltage ripple as outlined in

“Output Filter Design” on page 51. Choose the lowest switching

frequency that allows the regulator to meet the transient-response

and output-voltage ripple requirements.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

/V

OUT IN

)

FIGURE 38. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR 3-PHASE CONVERTER

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper MOSFETs.

Their RMS current capacity must be sufficient to handle the AC

component of the current drawn by the upper MOSFETs which is

related to duty cycle and the number of active phases. The input

RMS current can be calculated with Equation 51.

(EQ. 51)

2

I

=

K

 Io + K

 I

IN RMS

IN CM

RAMP CM

Lo p-p

N  D – m + 1  m – N  D

(EQ. 52)

K

=

---------------------------------------------------------------------------

IN CM

2

N

2

3

2

3

m N  D – m + 1 + m – 1 m – N  D

=

------------------------------------------------------------------------------------------------------------------

RAMP CM

2

12N D

(EQ. 53)

FN8575 Rev 1.00

Aug 13, 2015

Page 52 of 57

ISL6398

0.3

Layout and Design Considerations

I

= 0

= 0.25 I

I

= 0.5 I

O

L(P-P)

= 0.75 I

O

The following layout and design strategies are intended to minimize

the noise coupling, the impact of board parasitic impedances on

converter performance and to optimize the heat-dissipating

capabilities of the printed-circuit board. This section highlights some

important practices which should be followed during the layout

process. A layout check list is available for use.

0.2

0.1

Pin Noise Sensitivity, Design and Layout

Consideration

Table 19 shows the noise sensitivity of each pin and their design

and layout consideration. All pins and external components

should not be across switching nodes and should be placed in

general proximity to the controller.

0

0.2

0.4

DUTY CYCLE (V

0.6

/V

OUT IN

0.8

1.0

)

FIGURE 39. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR 4-PHASE CONVERTER

TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION

NOISE

Figures 38 and 39 provide the same input RMS current

information for 3 and 4-phase designs respectively. Use the

same approach to selecting the bulk capacitor type and number

as previously described.

PIN NAME

ISENIN-

SENSITIVE

Yes

DESCRIPTION

Connect to input supply side of the input

inductor or resistor pin with L/DCR or

ESL/R matching network in close

Low capacitance, high-frequency ceramic capacitors are needed

in addition to the bulk capacitors to suppress leading and falling

edge voltage spikes. The result from the high current slew rates

produced by the upper MOSFETs turn on and off. Select low ESL

ceramic capacitors and place one as close as possible to each

upper MOSFET drain to minimize board parasitic impedances

and maximize noise suppression.

proximity to the controller. Place NTC in

the close proximity to input inductor for

thermal compensation. A local 10nF

decoupling capacitor between ISENIN+

and ISENIN- is preferred. DCR sensing

with thermal compensation will yield no

load offset reading. Resistor sensing is

preferred for accurate input current

reporting. > 40 µs time constant

0.6

0.4

0.2

[C*R *R )/(R +R )] might

IN1 IN2 IN1 IN2

be needed if the average input

current reporting is preferred; and it

also reduces chance to trigger CFP

during heavy load transient.

ISENIN+

Yes

Connects to the Drain of High-side

MOSFET side of the input inductor or

resistor pin. A local 0.1µF ceramic

capacitor is recommended. When not

used, connect ISENIN+ to V and a

IN

I

= 0

= 0.5 I

= 0.75 I

L(P-P)

resistor divider with a ratio of 1/3 on

ISENIN± pin, say 499kΩ in between

ISENIN± pins and then 1.5MΩ from

ISENIN- to ground (see Figure 29). The

voltage of this pin is used feed-forward

compensation.

O

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V

/V )

OUT IN

FIGURE 40. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR SINGLE-PHASE CONVERTER

EN_PWR_CFP

Yes

There is an internal 1µs filter. Decoupling

capacitor is NOT needed, but if needed,

use a low time constant one to avoid too

large a shut-down delay. It will also be the

output of CFP function: 34 strong

pull-up. 25 mils spacing from other

traces.

MULTIPHASE RMS IMPROVEMENT

Figure 40 is provided as a reference to demonstrate the dramatic

reductions in input-capacitor RMS current upon the

implementation of the multiphase topology. For example,

compare the input RMS current requirements of a 2-phase

converter versus that of a single phase. Assume both converters

have a duty cycle of 0.25, maximum sustained output current of

40A, and a ratio of I

would require 17.3A

converter would only require 10.9A

RGND

VSEN

Yes

Pair up (within 20 mils) with the positive

rail remote sensing line that connected to

FB resistor, and routing them to the load

sensing points.

to I of 0.5. The single phase converter

L,PP

RMS

O

current capacity while the 2-phase

. The advantages become

Pair up (within 20 mils) with the negative

rail of remote sensing line that connected

to RGND, and route them to the load

sensing points.

RMS

even more pronounced when output current is increased and

additional phases are added to keep the component cost down

relative to the single phase approach.

FN8575 Rev 1.00

Aug 13, 2015

Page 53 of 57

ISL6398

TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION (Continued)

NOISE

TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION (Continued)

NOISE

PIN NAME

SENSITIVE

DESCRIPTION

PIN NAME

SENSITIVE

DESCRIPTION

VSEN_OVP

Yes

Used for Overvoltage protection sensing.

V

Yes

Place a high quality ceramic capacitor

(~ 1µF) in close proximity to the

controller.

CC

VRSEL_ADDR

No

Register setting is locked prior to soft-

start. Since the external resistor-divider

ratio compares with the internal resistor

NVM_BANK_BT

PWM1-6

NO

Avoid the respective PWM routing across

or under other phase’s power

ratio of the V , their rail should be

CC

exactly tied to the same point as V pin,

CC

not through an RC filter. DON’T use

decoupling capacitors on these pins.

trains/planes and current sensing

network. Don’t make them across or

under external components of the

controller. Keep them at least 20mils

away from any other traces.

VR_RDY

IMON

No

Open drain and high dv/dt pin. Avoid its

pull-up higher than V Tie it to ground

CC.

when not used.

ISEN[6:1]+

ISEN[6:1]-

Yes

Connect to the output rail side of the

respective channel’s output inductor or

resistor pin. Decoupling is optional and

might be required for long sense traces

and a poor layout.

Yes

Refer to GND, not RGND. Place R and C in

general proximity to the controller. The

time constant of RC should be sufficient,

typically 200µs, as an averaging function

for the digital IOUT.

Connect to the phase node side of the

respective channel’s output inductor or

VR_HOT#

No

Open drain and high dv/dt pin during

transitions. Avoid its pull-up rail higher

resistor pin with L/DCR or ESL/R

SEN

matching network in close proximity to

the ISEN± pins of VR. Differentially

routing back to the controller by paring

with respective ISEN+; at least 20 mils

spacing between pairs and away from

other traces. Each pair should not cross or

go under the other channel’s switching

nodes [PHASE, UGATE, LGATE] and power

planes even though they are not in the

same layer.

than V . 30 mils spacing from other

traces.

CC

SM_PM_I2CL

SM_PM_I2DA

Yes

50kHz to 1.5MHz signal when the SMBus,

2

PMBus, or I C is sending commands,

pairing up with PMALERT# and routing

2

carefully back to SMBus, PMBus or I C.

20 mils spacing within I2DATA,

PMALERT#, and I2CLK; and more than 30

mils to all other signals. Refer to the

2

SMBus, PMBus or I C design guidelines

GND

Yes

This EPAD is the return of PWM output

drivers and PMBus. Use 4 or more vias to

directly connect the EPAD to the power

ground plane. Avoid using only single via

or 0Ω resistor connection to the power

ground plane. Also connect pins 13, 14

and 15 to ground plane.

and place proper terminated (pull-up)

resistance for impedance matching.

Ground them when not used.

PMALERT#

No

Open drain and high dv/dt pin during

transitions. Route it in the middle of

I2DATA and I2LK. Also see above. Leave it

open or tie it ground when not used.

General

Comments

The layer next to the Top or Bottom layer

is preferred to be ground players, while

the signal layers can be sandwiched in

the ground layers if possible.

BUF_COMP

TM_EN_OTP

Yes

Buffer output of internal Comp Signal.

Place NTC in close proximity to the output

inductor of Channel 1 and to the output

rail, not close to MOSFET side (see Figure

24); the return trace should be 25 mils

away from other traces. Place 1k pull-

up and decoupling capacitor (typically

0.1µF) in close proximity to the controller.

The pull-up resistor should be exactly tied

to the same point as V pin, not through

CC

an RC filter. If not used, connect this pin to

1M /2M  resistor divider, or tie to V

.

CC

AUTO

RSET

Yes

Program AUTO phase shedding threshold

a resistor from this pin to GND. AUTO

phase shedding is disabled when this pin

tied to GND.

Place the R in close proximity to the

controller. DON’T use decoupling

capacitor on this pin.

FN8575 Rev 1.00

Aug 13, 2015

Page 54 of 57

ISL6398

Sometimes the gate might measure short due to residual

gate charge. Therefore, a measured short gate with

ohmmeter cannot validate if the MOSFET is damaged unless

the Drain to Source is also measured short.

Component Placement

Within the allotted implementation area, orient the switching

components first. The switching components are the most critical

because they carry large amounts of energy and tend to generate

high levels of noise. Switching component placement should take

into account power dissipation. Align the output inductors and

MOSFETs such that space between the components is minimized

while creating the PHASE plane. Place the Intersil MOSFET driver

IC as close as possible to the MOSFETs they control to reduce the

parasitic impedances due to trace length between critical driver

input and output signals. If possible, duplicate the same

6. When re-work is needed for the L/DCR matching network, use

an ohmmeter across the C to see if the correct R value is

measured before powering the VR up; otherwise, the current

imbalance due to improper re-work could damage the power

trains.

7. After everything is checked, apply low input voltage (1-5V)

with appropriate current limiting (~0.5A). All phases should

be switching evenly when AUTO disabled.

placement of these components for each phase.

8. Remove the pull-up from EN_PWR_CFP pin, using bench

Next, place the input and output capacitors. Position the high

frequency ceramic input capacitors next to each upper MOSFET

drain. Place the bulk input capacitors as close to the upper

MOSFET drains as dictated by the component size and

dimensions. Long distances between input capacitors and

MOSFET drains result in too much trace inductance and a

reduction in capacitor performance. Locate the output capacitors

between the inductors and the load, while keeping ceramic

capacitors in close proximity to the microprocessor socket.

power supplies, power-up V with current limiting

CC

(typically ~ 0.25A if 5V drivers included) and slowly increase

Input Voltage with current limiting. For typical application, V

limited to 0.25A, VIN limited to 0.5A should be safe for

powering up with no load. High core-loss inductors likely need

to increase the input current limiting. All phases should be

switching evenly.

CC

Voltage Regulator (VR) Design

Materials

To improve the chance of first pass success, it is very important

to take time to follow the above outlined design guidelines and

Intersil generated layout check list, see more details in

“Voltage Regulator (VR) Design Materials” on page 55. Proper

planning for the layout is as important as designing the circuits.

Running things in a hurry, you could end up spending weeks and

months to debug a poorly-designed and improperly laid out

board.

To support VR design and layout, Intersil also developed a set of

worksheets and evaluation boards, as listed in Tables 20 and 21,

respectively. The tolerance band calculation (TOB) worksheets for

VR output regulation and IMON have been developed using the

Root Sum Squared (RSS) method with 3 sigma distribution point

of the related components and parameters. Note that the

“Electrical Specifications” table beginning on page 10 specifies

no less than 6 sigma distribution point, not suitable for RSS TOB

calculation. Contact Intersil’s local office or field support for the

latest available information.

Powering Up And Open-Loop Test

The ISL6398 features very easy debugging and powering up. For

first-time powering up, an open-loop test can be done by applying

sufficient voltage (current limiting to 0.25A) to V , signal high to

CC

TABLE 20. AVAILABLE DESIGN ASSISTANCE MATERIALS

TM_EN_OTP (>1.05V) and EN_PWR_CFP (>0.9V and less than

3.5V) pins with the input voltage (VIN) disconnected.

ITEM

DESCRIPTION

0

1

Design and Validation

1. Each PWM output should operate at maximum duty cycle and

correct switching frequency.

Design Worksheet for Compensation and Component

Selection

2. Read data in DC and DD of PMBus to confirm its proper

setting.

2

3

4

5

SMBus/PMBus/I C Communication Tool with Software

3. If 5V drivers are used and share the same rail as V , the

CC

Resistor Register Calculator

Layout Design Guidelines

proper switching on UGATEs and LGATEs should be seen.

4. If 12V drivers are used and can be disconnected from VIN and

sourced by an external 12V supply, the proper switching on

UGATEs and LGATEs should be observed.

Evaluation Board Schematics in OrCAD Format and Layout in

Allegro Format

5. If the above is not properly operating, you should check

soldering joint, resistor register setting, Power Train

connection or damage, i.e, shorted gates, drain and source.

NOTE: For worksheets, please contact Intersil Application support

at www.intersil.com/design/.

TABLE 21. AVAILABLE EVALUATION BOARDS

2

EVALUATION BOARDS

ISL6398EVAL1Z

PACKAGE

5x5 40Ld

TARGETED APPLICATIONS

SMBus/PMBus/I C

PEAK EFFICIENCY ICCMAX (A)

3-Phase POL with ISL99140, 6x6 DrMOS

Digital Compensation with NVM

Yes

93%, 1.2V@40A

100A

ISL6398EVAL2Z

5x5 40Ld

6-Phase with ISL99140, 6x6 DrMOS

Digital Compensation with NVM

Yes

94%, 1.8V@50A

215A

FN8575 Rev 1.00

Aug 13, 2015

Page 55 of 57

ISL6398

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN8575.1

CHANGE

2

August 13, 2015

Updated “SMBus/PMBus/I C” section of Electrical Specification table on page 13.

-Added PMBus specs Signal Input Low Voltage, Signal Input High Voltage and Signal Output Low Voltage.

-Added min/max Time-out spec

-Changed the Time-out typical from “35” to “30”.

Updated the second sentence under “Soft-start” on page 25.

Updated Table 9 on page 33 by splitting PMBus (DC) and PMBus (DD) (now Table 10) into two different tables,

also updated R

value for 80h from “10” to “499”.

DW

2

Updated third paragraph under “SMBus, PMBus and I C Operation” on page 35.

Updated Figure 33 on page 35.

Updated Figure 35 on page 36.

Updated Figure 36 on page 37.

Updated DFh[8:0] description in Table 14 on page 41 and changed bit from “[7:0]” to “[8:0]”.

Updated POD to current revision. Changes from revision 1 to revision 2 are as follows:

Added tolerance ± values.

April 18, 2014

FN8575.0

Initial release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8575 Rev 1.00

Aug 13, 2015

Page 56 of 57

ISL6398

Package Outline Drawing

L40.5x5

40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 7/14

4x3.60

36x0.40

A

B

5.00 ±0.05

6

PIN #1 INDEX AREA

PIN 1

INDEX AREA

0.15

(4X)

40x0.4 ± 0.1

0.20

b

BOTTOM VIEW

TOP VIEW

0.10 M

C A B

4

PACKAGE OUTLINE

0.40

0.750 ±0.10

SEE DETAIL “X”

0.10 C

//

BASE PLANE

SEATING PLANE

0.08 C

C

0.050

SIDE VIEW

(36x0.40)

0.2 REF

(40x0.20)

(40x0.60)

5

C

0.00 MIN

0.05 MAX

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance: Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.27mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

JEDEC reference drawing: MO-220WHHE-1

7.

FN8575 Rev 1.00

Aug 13, 2015

Page 57 of 57


型号：	ISL6398IRTZ-TK
厂家：	RENESAS TECHNOLOGY CORP
描述：	Advanced Linear EAPP 6-Ph Green PWM Controller for Digital Power with NVM and AUTO Phase Shedding
文件：	总57页 (文件大小：2881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6398IRTZ-TK [RENESAS]

相关型号：

ISL6401

ISL6401CB

ISL6401CB-T

ISL6401CBZ

ISL6401CBZ-T

ISL6401CR

ISL6401CR-T

ISL6401CRZ

ISL6401CRZ-T

ISL6401IB

ISL6401IB

ISL6401IB-T