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ISL6521

FN9148

Rev 2.00

Feb 8, 2005

PWM Buck DC-DC and Triple Linear Power Controller

The ISL6521 provides the power control and protection for

four output voltages in low-voltage, high-performance

applications. The IC integrates a voltage-mode PWM

controller and three linear controllers, as well as monitoring

and protection functions into a 16-lead SOIC package. The

PWM controller is intended to regulate the low voltage

supply that requires the greatest amount of current (usually

the core voltage for the FPGA, ASIC, or processor) with a

synchronous rectified buck converter. The linears are

intended to regulate other system voltages, such as I/O

(input/output) and memory circuits. Both the switching

regulator and linear voltage reference provide 2% of static

regulation over line, load, and temperature ranges. All

outputs are user-adjustable by means of an external resistor

divider. All linear controllers can supply up to 120mA with no

external pass devices. Employing bipolar NPNs for the pass

transistors, the linear regulators can achieve output currents

of 3A or higher with proper device selection.

Features

• Provides 4 Regulated Voltages

- Switching Regulator 20A Capable

- Three Linear Regulators

- Capable of 120mA

- Capable of up to 3A with an External Transistor

• Externally Resistor-Adjustable Outputs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- All Outputs: 2% Over Temperature

• Overcurrent Fault Monitors

- Switching Regulator Does Not Require Extra Current

The ISL6521 monitors all the output voltages. The PWM

controller’s adjustable overcurrent function monitors the

output current by using the voltage drop across the upper

Sensing Element, Uses MOSFET’s r

DS(ON)

• Small Converter Size

MOSFET’s r

. The linear regulator outputs are

- 300kHz Constant Frequency Operation

- Small External Component Count

DS(ON)

monitored via the FB pins for undervoltage events.

• Commercial and Industrial Temperature Range Support

• Pb-free Available (RoHS Compliant)

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (°C) PACKAGE

DWG. #

Applications

ISL6521CBZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.15

™

•

PowerPC

FPGA and

-based boards

ISL6521CBZ-T

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

• General purpose, low voltage power supplies

Related Literature

• Technical Support Document AG0001, “Power

Management Application Guide for Xilinx FPGAs”

ISL6521IBZ

(Note)

-40 to 85

16 Ld SOIC

(Pb-free)

ISL6521IBZ-T

(Note)

-40 to 85

16 Ld SOIC

(Pb-free)

• Technical Support Document AG0002, “Power

Management Application Guide for Altera FPGAs”

ISL6521EVAL1

Evaluation Board

• Technical Support Document AG0005, “Power

Management Application Guide for Actel FPGAs”

NOTE: Intersil Pb-free products employ special Pb-free material sets;

molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

ISL6521 (SOIC)

Pinout

TOP VIEW

DRIVE2

FB2

1

2

3

4

5

6

7

8

16 FB3

15 DRIVE3

14 FB4

FB

COMP

GND

13 DRIVE4

12 OCSET

11 VCC

PHASE

BOOT

UGATE

10 LGATE

9

PGND

FN9148 Rev 2.00

Feb 8, 2005

Page 1 of 14

ISL6521

Typical Applications

High Output Current PWM Converter With Simple Triple Linears Regulators

L

IN

+5V

+

C

IN

V

OUT2

VCC

2.5V

120mA

BOOT

DRIVE2

FB2

C

BOOT

+

OCSET

C

OUT2

Rs2

Rp2

UGATE

PHASE

Q1

Q2

V

OUT1

1.5V

L

OUT1

V

OUT3

1.8V

120mA

DRIVE3

FB3

+

ISL6521

LGATE

PGND

C

OUT1

CR1

C

OUT3

Rs3

Rp3

FB

V

OUT4

3.3V

Rs1

COMP

120mA

DRIVE4

FB4

C

OUT4

Rs4

Rp1

Rp4

GND

High Output Current PWM Converter and Auxiliary 3.3V Linear Regulator

L

IN

+5V

+

C

IN

V

OUT2

VCC

2.5V

120mA

BOOT

DRIVE2

FB2

C

BOOT

+

OCSET

C

OUT2

Rs2

Rp2

UGATE

PHASE

Q1

Q2

V

OUT1

1.5V

L

OUT1

V

OUT3

1.8V

120mA

DRIVE3

FB3

+

ISL6521

LGATE

PGND

C

OUT1

CR1

+

C

OUT3

Rs3

Rp3

FB

+5V

Rs1

COMP

V

DRIVE4

FB4

OUT4

Q3

3.3V

3A

Rs4

+

Rp1

Rp4

GND

C

OUT4

FN9148 Rev 2.00

Feb 8, 2005

Page 3 of 14

ISL6521

Absolute Maximum Ratings

Thermal Information

UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V

VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V

Thermal Resistance (Typical, Note 1)

_JA(°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

74

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Operating Conditions

Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%

Ambient Temperature Range

ISL6521CBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

ISL6521IBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . -40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Operating Conditions: VCC = 5V, T = 0°C to 70°C, Unless Otherwise Noted. Typical specifications are at

A

T

= 25°C.

A

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply Current

POWER-ON RESET

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

UGATE, LGATE, and DRIVEx Open

-

5

-

mA

CC

Rising VCC Threshold

4.25

3.74

-

4.51

4.0

V

Falling VCC Threshold

OSCILLATOR AND SOFT-START

Free Running Frequency

F

ISL6521CBZ

275

250

-

300

1.5

325

350

-

kHz

OSC

ISL6521IBZ (-40°C to 85°C)

Ramp Amplitude

V

V

P-P

OSC

SS

Soft-Start Interval

T

6.25

6.83

7.40

ms

REFERENCE VOLTAGE

Reference Voltage (All Regulators)

All Outputs Voltage Regulation

V

0.780 0.800 0.820

V

REF

ISL6521CBZ

-2.0

-2.5

-

+2.0

+2.5

%

ISL6521IBZ (-40°C to 85°C)

LINEAR REGULATORS (OUT2, OUT3, AND OUT4)

Output Drive Current (All Linears)

VCC > 4.5V

100

-

120

70

-

mA

%

Undervoltage Level (V /V

)

V

UV

FB REF

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain

-

15

-

80

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/s

COMP = 10pF

6

PWM CONTROLLER GATE DRIVERS

UGATE Source

I

VCC = 5V, V

= 2.5V

-

-1

1

-

A

UGATE

UGATE Sink

I

V

= 2.5V

UGATE

UGATE-PHASE

LGATE Source

I

VCC = 5V, V

= 2.5V

-1

2

LGATE

LGATE Sink

I

V

= 2.5V

LGATE

PROTECTION

OCSET Current Source

I

ISL6521CBZ

ISL6521IBZ (-40°C to 85°C)

34

40

46

48

A

OCSET

31.5

FN9148 Rev 2.00

Feb 8, 2005

Page 4 of 14

ISL6521

capable of providing 120mA of load current or drive current for

the pass transistors.

Functional Pin Descriptions

VCC (Pin 11)

FB2, 3, 4 (Pins 2, 16, 14)

Provide a well decoupled 5V bias supply for the IC to this pin.

This pin also provides the gate bias charge for the lower

MOSFET controlled by the PWM section of the IC, as well as

the drive current for the linear regulators. The voltage at this

pin is monitored for Power-On Reset (POR) purposes.

Connect the output of the corresponding linear regulators to

these pins through properly sized resistor dividers. The voltage

at these pins is regulated to 0.8V. These pins are also

monitored for undervoltage events.

Quickly pulling and holding any of these pins above 1.25V

(using diode-coupled logic devices) shuts off the respective

regulators. Releasing these pins from the pull-up voltage

initiates a soft-start sequence on the respective regulator.

GND (Pin 5)

Signal ground for the controller. All voltage levels are

measured with respect to this pin.

PGND (Pin 9)

Description

This is the power ground connection. Tie the source of the

lower MOSFET of the synchronous PWM converter to this pin.

Operation

The ISL6521 monitors and precisely controls one

BOOT (Pin 7)

synchronous PWM converter and three configurable linear

regulators from a +5V bias input. The PWM controller is

designed to regulate the core voltage of an embedded

processor or simple down conversion for high current

applications. The PWM controller drives two MOSFETs (Q1

and Q2) in a synchronous-rectified buck converter

Floating bootstrap supply pin for the upper gate drive. The

bootstrap capacitor provides the necessary charge to turn and

hold the upper MOSFET on. Connect a suitable capacitor

(0.47F recommended) from this pin to PHASE.

OCSET (Pin 12)

Connect a resistor from this pin to the drain of the upper PWM

MOSFET. This resistor, an internal 40A current source

(typical), and the upper MOSFET’s on-resistance set the

converter overcurrent trip point. An overcurrent trip cycles the

soft-start function.

configuration and regulates the output voltage to a level

programmed by a resistor divider. The linear controllers are

designed to regulate three additional system voltages.

Typically, these include any I/O, memory, or clock voltages

that might be required. All three linear controllers support up

to 120mA of load current without external pass devices or

higher currents with external NPN bipolar transistors.

The voltage at this pin is monitored for power-on reset (POR)

purposes and pulling this pin below 1.25V with an open

drain/collector device will shut down the switching controller.

Initialization

The ISL6521 automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

monitors the input bias supply voltage. The POR monitors the

bias voltage at the VCC pin. The POR function initiates soft-

start operation after the bias supply voltage exceeds its POR

threshold.

PHASE (Pin 6)

Connect this pin to the source of the PWM converter upper

MOSFET. This pin is used to monitor the voltage drop across

the upper MOSFET for overcurrent protection.

UGATE (Pin 8)

Connect UGATE pin to the PWM converter’s upper MOSFET

gate. This pin provides the gate drive for the upper MOSFET.

Soft-Start

The POR function initiates the soft-start sequence. The PWM

error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). Similarly,

all linear regulators’ reference inputs are clamped to a voltage

proportional to the soft-start voltage. The ramp-up of the

internal soft-start function provides a controlled output voltage

rise.

LGATE (Pin 10)

This pin provides the gate drive for the synchronous rectifier

lower MOSFET. Connect LGATE to the gate of the lower

MOSFET.

COMP and FB (Pins 4, 3)

COMP and FB are the available external pins of the PWM

converter error amplifier. The FB pin is the inverting input of the

error amplifier. Similarly, the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-mode

control feedback loop of the synchronous PWM converter.

Figure 1 shows the soft-start sequence for a typical application.

At T0 the +5V bias voltage starts to ramp up crossing the 4.5V

POR threshold at time T1. On the PWM section, the oscillator’s

triangular waveform is compared to the clamped error amplifier

output voltage. As the internal soft-start voltage increases, the

pulse-width on the PHASE pin increases to reach its steady-

state duty cycle at time T2. Also at time T2, the error amplifier

DRIVE2, 3, 4 (Pins 1, 15, 13)

Connect these pins to the point of load or to the base terminals

of external bipolar NPN transistors. These pins are each

FN9148 Rev 2.00

Feb 8, 2005

Page 5 of 14

ISL6521

references of the linear controllers, ramp to their final value

bringing all outputs within regulation limits.

V

(3.3V)

(1.8V)

OUT4

V

OUT3

+5V

V

(1.5V)

OUT1

V

(2.5V)

OUT2

(0.5V/DIV.)

0V

V

(3.3V)

OUT4

0V

(1V/DIV)

V

(2.5V)

(1.8V)

OUT2

SOFT-START

FUNCTION

OUT3

UV MONITORING

V

(1.5V)

OUT1

V

INACTIVE

ACTIVE

OUT1

0V

V

OUT2

(0.5V/DIV)

T0

T1

T2

TIME

T0

T1

T2

T3T4

TIME

FIGURE 1. SOFT-START INTERVAL

FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION

RESPONSE

Overcurrent Protection

Overcurrent protection is performed on the synchronous

switching regulator on a cycle-by-cycle basis. OC monitoring is

active as long as the regulator is operational. Since the

overcurrent protection on the linear regulators is performed

through undervoltage monitoring at the feedback pins (FB2,

FB3, and FB4), this feature is activated approximately 25%

into the soft-start interval (see Figure 2).

All outputs are protected against excessive overcurrents. The

PWM controller uses the upper MOSFET’s on-resistance,

r

to monitor the current for protection against a shorted

DS(ON)

output. All linear controllers monitor their respective FB pins for

undervoltage events to protect against excessive currents.

A sustained overload (undervoltage on linears or overcurrent on

the PWM) on any output results in an independent shutdown of

the respective output, followed by subsequent individual re-start

attempts performed at an interval equivalent to 3 soft-start

intervals. Figure 2 describes the protection feature. At time T0,

an overcurrent event sensed across the switching regulator’s

A resistor (R

) programs the overcurrent trip level for

OCSET

the PWM converter. As shown in Figure 3, the internal 40A

current sink (I ) develops a voltage across R

OCSET

(V

) that is referenced to V . The DRIVE signal enables

SET

IN

the overcurrent comparator (OCC). When the voltage across

the upper MOSFET (V ) exceeds V , the

upper MOSFET (r

sensing) triggers a shutdown of the

output. As a result, its internal soft-start initiates a

DS(ON)

SET

overcurrent comparator trips to set the overcurrent latch. Both

and V are referenced to V and a small

V

OUT1

number of soft-start cycles. After a three-cycle wait, the fourth

soft-start initiates a ramp-up attempt of the failed output, at time

T2, bringing the output in regulation at time T4.

V

SET

DS(ON)

OCSET

of V due to MOSFET switching. The overcurrent function

IN

capacitor across R

helps V

track the variations

OCSET

IN

will trip at a peak inductor current (I

To exemplify a UV event on one of the linears, at time T1, the

determined by:

PEAK)

clock regulator (V

) is also subjected to an overcurrent

OUT2

I

 R

OCSET

I

= ---------------------------------------------------

event, resulting in a UV condition. Similarly, after three soft-

start periods, the fourth cycle initiates a ramp-up of this linear

output at time T3. One soft-start period after T3, the linear

output is within regulation limits. UV glitches less than 1s

(typically) in duration are ignored.

PEAK

r

DSON

The OC trip point varies with MOSFET’s r

temperature

DS(ON)

variations. To avoid overcurrent tripping in the normal

operating load range, determine the R

the equation above with:

resistor from

OCSET

FN9148 Rev 2.00

Feb 8, 2005

Page 6 of 14

ISL6521

1. The maximum r

2. The minimum I

3. Determine I

at the highest junction temperature.

from the specification table.

in a parallel connection has to be less than 5k, or otherwise

said, the following relationship has to be met:

DS(ON)

OCSET

for I

> I

PEAK OUT(MAX)

+ (I)/2, where I

R

 R

P

+ R

P

PEAK

S

---------------------

 5k

is the output inductor ripple current.

R

S

OVERCURRENT TRIP:

V

= +5V

IN

To ensure the parallel combination of the feedback resistors

V

> V

> I

DS

SET

i

¥ r

¥ R

equals a certain chosen value, R , use the following

FB

D

DSON OCSET

OCSET

equations:

R

OCSET

V

OUT

---------------

R

=

 R

I

i

OCSET

40A

S

P

FB

D

V

+

V

SET

FB

VCC

UGATE

R

 V

FB

S

+

V

, where

R

V

= --------------------------------

– V

DRIVE

V

DS(ON)

OUT

FB

OC

+

PHASE

- the desired output voltage,

-

OUT

OCC

V

- feedback (reference) voltage, 0.8V.

V

= V – V

FB

PHASE

IN

DS

GATE

CONTROL

PWM

V

= V – V

OCSET

IN

SET

Application Guidelines

FIGURE 3. OVERCURRENT DETECTION

Soft-Start Interval

The soft-start function controls the output voltages rate of rise to

limit the current surge at start-up. The soft-start function is

integrated on the chip and the soft-start interval is fixed.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

Output Voltage Selection

PWM Controller Feedback Compensation

The output voltage of the PWM converter can be resistor-

The PWM controller uses voltage-mode control for output

regulation. This section highlights the design consideration for

a PWM voltage-mode controller. Apply the methods and

considerations only to the PWM controller.

programmed to any level between V and 0.8V. However,

IN

since the value of R is affecting the values of the rest of the

S1

compensation components, it is advisable its value is kept

between 2k and 5k.

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

+5V

IN

(V

) is regulated to the reference voltage level, 0.8V. The

OUT

error amplifier (Error Amp) output (V ) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

E/A

DRIVE3

FB3

Q3

V

OUT3

C

modulated (PWM) wave with an amplitude of V at the

IN

PHASE node. The PWM wave is smoothed by the output filter

(L and C ).

R

S3

+

R

O

OUT3

P3

ISL6521

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

V

OUT4

DRIVE4

FB4

OUT E/A

Gain, given by V /V

, and shaped by the output filter, with

IN OSC

a double pole break frequency at F and a zero at F

.

C

LC ESR

OUT4

R

S4

R

P4

R









S

V

= 0.8  1 + -------



R

OUT



P

FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF

THE FOUR REGULATORS (OUTPUTS 3 AND 4

PICTURED)

Output voltage selection on the linear regulators is set by

means of external resistor dividers as shown in Figure 4. The

two resistors used to set the voltage on each of the three linear

regulators have to meet the following criteria: their value while

FN9148 Rev 2.00

Feb 8, 2005

Page 7 of 14

ISL6521

Compensation Break Frequency Equations

V

IN

DRIVER1

OSC

1

F

= -----------------------------------

F

= ------------------------------------------------------

P1

P2

Z1

Z2

2  R2  C1

C1  C2





----------------------

PWM

2  R



L

2





O

C1 + C2

COMP

V

OUT

SYNC

DRIVER

1

-

F

= ----------------------------------------------------------

F

= -----------------------------------

2  R3  C3

PHASE

+

2  R + R3  C3

V

C

OSC

O

S1

ESR

(PARASITIC)

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown in Figure 5. Using the above guidelines

should yield a Compensation Gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

Z

FB

Z

IN

V

E/A

+

0.8V

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

gain. Check the compensation gain at F with the capabilities

P2

of the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 6 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the compensation

transfer function and plotting the gain.

Z

FB

V

OUT

C2

Z

IN

C1

C3

R3

R2

R

S1

COMP

The compensation gain uses external impedance networks

FB

Z

and Z to provide a stable, high bandwidth (BW) overall

-

FB

IN

+

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

R

P1

ISL6521

0.8V

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

OPEN LOOP

ERROR AMP GAIN

F

P1

F

Z1

Z2

P2

100

80

V













IN

------------

20log

Modulator Break Frequency Equations

V

PP

60

1

F

= ---------------------------------------

F

= -----------------------------------------

LC

ESR

2  ESR  C

40

2 

L  C

O O

COMPENSATION

GAIN

O

20

The compensation network consists of the error amplifier

0

(internal to the ISL6521) and the impedance networks Z and













IN

R2

------------

20log

R

Z

. The goal of the compensation network is to provide a

FB

closed loop transfer function with high 0dB crossing frequency

(f ) and adequate phase margin. Phase margin is the

S1

-20

-40

-60

CLOSED LOOP

GAIN

MODULATOR

GAIN

F

ESR

LC

0dB

difference between the closed loop phase at f

and 180

0dB

10

100

1K

10K

100K

1M

10M

degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 5. Use these guidelines for

locating the poles and zeros of the compensation network:

FREQUENCY (Hz)

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

Individual Output Disable

2. Place 1 Zero Below Filter’s Double Pole (~75% F

ND

)

LC

The PWM and linear controllers can independently be

shutdown.

3. Place 2

Zero at Filter’s Double Pole

ST

4. Place 1 Pole at the ESR Zero

ND

To disable the switching regulator, use an open-drain or open-

collector device capable of pulling the OCSET pin (with the

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

attached R

pull-up) below 1.25V. To minimize the

OCSET

possibility of OC trips at levels different than predicted, a

capacitor with a value of an order of magnitude larger

C

OCSET

than the output capacitance of the pull-down device, has to be

FN9148 Rev 2.00

Feb 8, 2005

Page 8 of 14

ISL6521

used in parallel with R

off of the pull-down device, the switching regulator undergoes

a soft-start cycle.

(1nF recommended). Upon turn-

are those connected to sensitive nodes or those supplying

critical bypass current.

OCSET

The power components and the controller IC should be placed

first. Locate the input capacitors, especially the high-frequency

ceramic decoupling capacitors, close to the power switches.

Locate the output inductor and output capacitors between the

MOSFETs and the load. Locate the PWM controller close to

the MOSFETs.

To disable a particular linear controller, pull and hold the

respective FB pin above a typical threshold of 1.25V. One way

to achieve this task is by using a logic gate coupled through a

small-signal diode. The diode should be placed as close to the

FB pin as possible to minimize stray capacitance to this pin.

Upon turn-off of the pull-up device, the respective output

undergoes a soft-start cycle, bringing the output within

regulation limits. On regulators implementing this feature, the

parallel combination of the feedback resistors has to be

sufficiently high to allow ease of driving from the external

device. Considering the other restriction applying to the upper

range of this resistor combination (see ‘Output Voltage

Selection’ paragraph), it is recommended the values of the

feedback resistors on the linear regulator output meet the

following constraint:

The critical small signal components include the bypass

capacitor for VCC and the feedback resistors. Locate these

components close to their connecting pins on the control IC.

A multi-layer printed circuit board is recommended. Figure 7

shows the connections of the critical components in the

converter. Note that the capacitors C and C

each can

IN

OUT

represent numerous physical capacitors. Dedicate one solid

layer for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. The power plane should

support the input power and output power nodes. Use copper

filled polygons on the top and bottom circuit layers for the

PHASE nodes, but do not unnecessarily oversize these

particular islands. Since the PHASE nodes are subjected to

very high dv/dt voltages, the stray capacitor formed between

these islands and the surrounding circuitry will tend to couple

switching noise. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the control IC to

the MOSFET gate and source should be sized to carry 2A

peak currents.

R

 R

P

+ R

P

S

---------------------

2k 

 5k

R

S

Important Note When Using External Pass Devices

If the collector voltage to a linear regulator pass transistor (Q3,

Q4, or Q5 shown in Figure 7) is lost, the respective regulator

has to be shut down by pulling high its FB pin. This measure is

necessary in order to avoid possible damage to the ISL6521 as

a result of overheating. Overheating can occur in such

situations due to sheer power dissipation inside the chip’s

linear drivers.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage spikes

in the converter. Consider, as an example, the turn-off

transition of the upper PWM MOSFET. Prior to turn-off, the

upper MOSFET was carrying the full load current. During the

turn-off, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET or Schottky diode. Any

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide circuit traces minimize the magnitude of

voltage spikes.

There are two sets of critical components in a DC-DC

converter using an ISL6521 controller. The switching power

components are the most critical because they switch large

amounts of energy, and as such, they tend to generate equally

large amounts of noise. The critical small signal components

FN9148 Rev 2.00

Feb 8, 2005

Page 9 of 14

ISL6521

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage and

the initial voltage drop following a high slew-rate transient’s

edge. An aluminum electrolytic capacitor’s ESR value is

related to the case size with lower ESR available in larger case

sizes. However, the equivalent series inductance (ESL) of

these capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

L

IN

+5V

IN

+

+12V

C

IN

C

VCC

VCC GND

OCSET

C

OCSET

R

OCSET

Q1

L

UGATE

PHASE

V

OUT2

+

OUT

V

OUT1

C

+

OUT2

DRIVE2

C

OUT1

CR1

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Q3

LGATE

Q2

V

OUT3

+

V

OUT4

ISL6521

Linear Output Capacitors

+

C

OUT3

DRIVE4

PGND

DRIVE3

The output capacitors for the linear regulators provide dynamic

load current. The linear controllers use dominant pole

compensation integrated into the error amplifier and are

insensitive to output capacitor selection. Output capacitors

should be selected for transient load regulation.

C

OUT4

Q5

Q4

+3.3V

KEY

IN

PWM Output Inductor Selection

ISLAND ON POWER PLANE LAYER

The PWM converter requires an output inductor. The output

inductor is selected to meet the output voltage ripple

requirements and sets the converter’s response time to a load

transient. The inductor value determines the converter’s ripple

current and the ripple voltage is a function of the ripple current.

The ripple voltage and current are approximated by the

following equations:

ISLAND ON CIRCUIT OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

Component Selection Guidelines

V

– V

V

OUT

IN

OUT

V

= I  ESR

------------------------------- ---------------

I =



OUT

Output Capacitor Selection

F

 L

V

IN

S

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic load regulation requirements.

Additionally, the PWM converters require an output capacitor to

filter the current ripple. The load transient for some embedded

processors requires high quality capacitors to supply the high

slew rate (di/dt) current demands.

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values increase

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6521 will provide either 0% or 100% duty cycle in response

to a load transient. The response time is the time interval

required to slew the inductor current from an initial current

value to the post-transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor(s).

Minimizing the response time can minimize the output

capacitance required.

PWM Output Capacitors

High performance embedded processors can produce

transient load rates above 1A/ns. High frequency capacitors

initially supply the transient current and slow the load rate-of-

change seen by the bulk capacitors. The bulk filter capacitor

values are generally determined by the ESR (effective series

resistance) and voltage rating requirements rather than actual

capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

The response time to a transient is different for the application

of load and the removal of load. The following equations give

the approximate response time interval for application and

removal of a transient load:

L

 I

TRAN

– V

OUT

L

 I

TRAN

V

O

t

= -------------------------------

t

= ------------------------------

RISE

FALL

V

IN

OUT

FN9148 Rev 2.00

Feb 8, 2005

Page 10 of 14

ISL6521

where: I

is the transient load current step, t

is the

that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature and air flow.

TRAN

response time to the application of load, and t

RISE

is the

FALL

response time to the removal of load. Be sure to check both of

these equations at the minimum and maximum output levels

for the worst case response time.

Input Capacitor Selection

2

I

 r

 V

I

 V  t

 F

SW S

The important parameters for the bulk input capacitors are the

voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum input

voltage and a voltage rating of 1.5 times is a conservative

guideline. The RMS current rating requirement for the input

capacitor of a buck regulator is approximately 1/2 of the

summation of the DC load current.

O

DSON

OUT

O

IN

P

= ------------------------------------------------------------ + ----------------------------------------------------

UPPER

LOWER

V

2

IN

2

I

 r

 V – V



OUT

O

DSON

IN

= --------------------------------------------------------------------------------

V

IN

Given the reduced available gate bias voltage (5V) logic-level

or sub-logic-level transistors have to be used for both N-

MOSFETs. Caution should be exercised with devices

exhibiting very low V

characteristics, as the low gate

GS(ON)

threshold could be conducive to some shoot-through (due to

the Miller effect), in spite of the counteracting circuitry present

aboard the ISL6521.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance for

the high frequency decoupling and bulk capacitors to supply

the RMS current. Small ceramic capacitors can be placed very

close to the upper MOSFET to suppress the voltage induced in

the parasitic circuit impedances.

+5V OR LESS

+5V

VCC

BOOT

+

C

BOOT

For a through-hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These capacitors

must be capable of handling the surge-current at power-up.

ISL6521

Q1

Q2

UGATE

PHASE

NOTE:

_GSV -0.5V

V

CC

VCC

CR1

LGATE

PGND

-

Transistors Selection/Considerations

+

NOTE:

The ISL6521 can employ up to 5 external transistors. Two

N-channel MOSFETs are used in the synchronous-rectified

buck topology of PWM converter. The linear controllers can

each drive an NPN bipolar transistor as a pass element. All

V

_GSV

CC

GND

FIGURE 8. MOSFET GATE BIAS

these transistors should be selected based upon r

,

DS(ON)

current gain, saturation voltages, gate/base supply

requirements, and thermal management considerations.

Rectifier CR1 is a clamp that catches the negative inductor

swing during the dead time between the turn off of the lower

MOSFET and the turn on of the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to omit

the diode and let the body diode of the lower MOSFET clamp

the negative inductor swing, providing the body diode is fast

enough to avoid excessive negative voltage swings at the

PHASE pin. The diode's rated reverse breakdown voltage

must be greater than the maximum input voltage.

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the dominant

design factors. The power dissipation includes two loss

components; conduction loss and switching loss. These losses

are distributed between the upper and lower MOSFETs

according to duty factor (see the equations below). The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper MOSFET

has significant switching losses, since the lower device turns

on and off into near zero voltage.

Linear Controller Transistor Selection

The main criteria for selection of transistors for the linear

regulators is package selection for efficient removal of heat.

The power dissipated in a linear regulator is:

The equations below assume linear voltage-current transitions

and do not model power loss due to the reverse-recovery of

the lower MOSFET’s body diode. The gate-charge losses are

dissipated by the ISL6521 and don't heat the MOSFETs.

P

= I  V – V



OUT

LINEAR

O

IN

However, large gate-charge increases the switching time, t

SW

which increases the upper MOSFET switching losses. Ensure

FN9148 Rev 2.00

Feb 8, 2005

Page 11 of 14

ISL6521

Select a package and heatsink that maintains the junction

temperature below the rating with a the maximum expected

ambient temperature.

powering an embedded processor. The circuit provides the

processor core voltage (V ), the I/O voltage (V ), the

CORE

I/O

clock voltage (V

), and memory voltage (V )

CLOCK MEMORY

from a single +5V supply. A component selection table

provides the recommended component values at various load

current steps.

If bipolar NPN transistors have to be used with the linear

controllers, insure the current gain at the given operating V

is sufficiently large to provide the desired maximum output load

current when the base is fed with the minimum driver output

current.

CE

Intersil’s portfolio of multiple output controllers continues to

expand with new selections to better fit our customer’s needs.

Refer to our website for updated information: www.intersil.com

ISL6521 DC-DC Converter Application

Circuit

Figure 9 shows a power management application circuit for

+5V

C2

1F

+

C1

D1

C7

VCC

0.1F

MA732

ISL6521

BOOT

R5

OCSET

DRIVE2

FB2

V

Q3

I/O

2.5V

C3

0.47F

UGATE

PHASE

Q1

Q2

R6

12.7k

V

CORE

1.5V

L

OUT

+

R7

5.9k

C8

C11

10F

+

LGATE

PGND

C4

C10

10F

DRIVE3

FB3

V

CLOCK

3.3V

2.0k

FB

R8

18.2k

C5

R1

R9

5.9k

COMP

C9

100F

C12

10F

C14

R12

R2

C6

+5V

R3

2.26k

DRIVE4

FB4

Q4

V

MEMORY

R11

+

R10

C

13

14

GND

FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR AN EMBEDDED PROCESSOR

FN9148 Rev 2.00

Feb 8, 2005

Page 12 of 14

ISL6521

Component Selection Table

I

L

Q1

Q2

Q3

C1

C4

CC_INT

OUT

5A

7.5H

IRF7910

FZT649

1 x 1000F

1 x 1200F

Pulse P1172.103

(1A or less)

10MBZ1000M 10x12.5

6.3MBZ1200M 8x16

10A

15A

20A

4.8H

Sumida CDEP134

IRF7460

IRF7821

IRF7476

IRF7832

2SD1802

(3A or less)

2 x 1000F

10MBZ1000M 10x12.5

2 x 1800F

6.3MBZ1800M 10x16

1.6H

Sumida CDEP134

2SD1802

(3A or less)

2 x 1800F

10MBZ1800M 10x20

2 x 3300F

6.3MBZ3300M 10x23

0.5H

2 x

2SD1802

3 x 1500F

3 x 3300F

Pulse PG0006.601

IRF7821

IRF7832

(3A or less)

10MBZ1500M 10x16

6.3MBZ3300M10x23

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9148 Rev 2.00

Feb 8, 2005

Page 13 of 14

ISL6521

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES

MIN

MILLIMETERS

INDEX

M

B

0.25(0.010)

H

SYMBOL

MAX

0.069

0.010

0.019

0.010

0.394

0.157

MIN

1.35

0.10

0.35

0.19

9.80

3.80

MAX

1.75

NOTES

AREA

E

A

A1

B

C

D

E

e

0.053

0.004

0.014

0.007

0.386

0.150

-

-B-

0.25

-

0.49

9

1

2

3

L

0.25

-

10.00

4.00

3

SEATING PLANE

A

4

-A-

o

D

h x 45

0.050 BSC

1.27 BSC

-

H

h

0.228

0.010

0.016

0.244

0.020

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

-C-



µ

5

e

A1

L

6

C

B

0.10(0.004)

N



16

7

M

S

B

o

0.25(0.010)

C

A

0

8

0

8

-

Rev. 1 02/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

FN9148 Rev 2.00

Feb 8, 2005

Page 14 of 14


型号：	ISL6521CBZA
厂家：	RENESAS TECHNOLOGY CORP
描述：	PWM Buck DC/DC and Triple Linear Power Controller; SOIC16; Temp Range: See Datasheet 开关光电二极管
文件：	总14页 (文件大小：705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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