ISL6522IBZ-T [RENESAS]
Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller; QFN16, SOIC14, TSSOP14; Temp Range: See Datasheet;型号: | ISL6522IBZ-T |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller; QFN16, SOIC14, TSSOP14; Temp Range: See Datasheet 开关 光电二极管 |
文件: | 总16页 (文件大小:818K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MMENDS
NS, INTERSIL RECO
FOR NEW DESIG
DATASHEET
5
PRODUCT - ISL653
DROP-IN ENHANCED
ISL6522
FN9030
Rev 8.00
Mar 10, 2006
Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller
The ISL6522 provides complete control and protection for a
DC-DC converter optimized for high-performance micro-
Features
• Drives two N-Channel MOSFETs
• Operates from +5V or +12V input
processor applications. It is designed to drive two N-Channel
MOSFETs in a synchronous rectified buck topology. The
ISL6522 integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
• Simple single-loop control design
- Voltage-mode PWM control
The output voltage of the converter can be precisely
regulated to as low as 0.8V, with a maximum tolerance of
1% over temperature and line voltage variations.
• Fast transient response
- High-bandwidth error amplifier
- Full 0–100% duty ratio
The ISL6522 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/s slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0–100%.
• Excellent output voltage regulation
- 0.8V internal reference
- 1% over line voltage and temperature
• Overcurrent fault monitor
- Does not require extra current sensing element
- Uses MOSFETs r
DS(ON)
• Converter can source and sink current
• Small converter size
The ISL6522 protects against overcurrent conditions by
inhibiting PWM operation. The ISL6522 monitors the current
- Constant frequency operation
by using the r
of the upper MOSFET which eliminates
DS(ON)
- 200kHz free-running oscillator programmable from
50kHz to over 1MHz
the need for a current sensing resistor.
• 14-lead SOIC and TSSOP package and 16-lead 5x5mm
QFN Package
SOIC, TSSOP
TOP VIEW
Pinouts
• QFN Package
14
13
12
11
10
9
RT
OCSET
SS
1
2
3
4
5
6
7
VCC
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline.
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
COMP
FB
• Pb-free plus anneal available (RoHS compliant)
EN
8
GND
Applications
QFN
TOP VIEW
®
®
• Power supply for Pentium , Pentium Pro, PowerPC and
AlphaPC™ microprocessors
• High-power 5V to 3.xV DC-DC regulators
• Low-voltage distributed power supplies
16 15 14 13
SS
COMP
FB
1
2
3
4
12 PVCC
11 LGATE
GND
10
9
PGND
BOOT
EN
5
6
7
8
FN9030 Rev 8.00
Mar 10, 2006
Page 1 of 16
ISL6522
Ordering Information
Ordering Information (Continued)
PART
PART
TEMP.
PKG.
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE
DWG. #
NUMBER
MARKING RANGE (°C) PACKAGE
DWG. #
ISL6522CB
ISL6522CB
0 to 70
0 to 70
14 Ld SOIC
M14.15
M14.15
ISL6522CR ISL6522CR
0 to 70
0 to 70
16 Ld 5x5 QFN L16.5x5B
ISL6522CBZ 6522CBZ
(Note)
14 Ld SOIC
(Pb-free)
ISL6522CRZ ISL6522CRZ
(Note)
16 Ld 5x5 QFN L16.5x5B
(Pb-free)
ISL6522CBZA 6522CBZ
(Note)
0 to 70
14 Ld SOIC
(Pb-free)
M14.15
ISL6522IR
ISL6522IR
-40 to 85 16 Ld 5x5 QFN L16.5x5B
ISL6522IRZ ISL6522IRZ
(Note)
-40 to 85 16 Ld 5x5 QFN L16.5x5B
(Pb-free)
ISL6522IB
ISL6522IB
-40 to 85 14 Ld SOIC
M14.15
M14.15
ISL6522IBZ 6522IBZ
(Note)
-40 to 85 14 Ld SOIC
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL6522CV
ISL6522CV
0 to 70
0 to 70
14 Ld TSSOP M14.173
ISL6522CVZ ISL6522CVZ
(Note)
14 Ld TSSOP M14.173
(Pb-free)
ISL6522IV
ISL6522IV
-40 to 85 14 Ld TSSOP M14.173
Add “-T” for tape and reel.
ISL6522IVZ ISL6522IVZ
(Note)
-40 to 85 14 Ld TSSOP M14.173
(Pb-free)
Typical Application
12V
+5V OR +12V
V
CC
OCSET
SS
MONITOR AND
PROTECTION
EN
BOOT
RT
OSC
UGATE
PHASE
ISL6522
+V
O
REF
+12V
PV
CC
LGATE
PGND
-
+
+
-
FB
COMP
GND
FN9030 Rev 8.00
Mar 10, 2006
Page 2 of 16
ISL6522
Block Diagram
VCC
POWER-ON
RESET (POR)
EN
SS
10A
SOFT-
START
+
-
OCSET
OVER
CURRENT
BOOT
4V
UGATE
200A
PHASE
PWM
0.8V
COMPARATOR
REF
GATE
CONTROL
LOGIC
REFERENCE
INHIBIT
PWM
+
+
-
-
PV
CC
ERROR
AMP
LGATE
PGND
GND
FB
COMP
RT
OSCILLATOR
FN9030 Rev 8.00
Mar 10, 2006
Page 3 of 16
ISL6522
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Thermal Resistance (Typical, Note 1)
(°C/W)
(°C/W)
JC
CC
JA
Boot Voltage, V
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
- V
. . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
PHASE
SOIC Package (Note 1) . . . . . . . . . . . .
TSSOP Package (Note 1) . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
67
95
36
n/a
n/a
5
+0.3V
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
CC
Ambient Temperature Range, ISL6522C. . . . . . . . . . . . 0°C to 70°C
Ambient Temperature Range, ISL6522I. . . . . . . . . . . .-40°C to 85°C
Junction Temperature Range, ISL6522C. . . . . . . . . . . 0°C to 125°C
Junction Temperature Range, ISL6522I . . . . . . . . . .-40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. is measured with the component mounted on a highs effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech
JA
Brief TB379.
3. For , the "case temp" location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY CURRENT
CC
Nominal Supply
I
EN = V ; UGATE and LGATE Open
CC
-
-
5
-
mA
CC
Shutdown Supply
POWER-ON RESET
EN = 0V
50
100
A
Rising V
Threshold
Threshold
V
V
= 4.5VDC
= 4.5VDC
-
-
10.4
-
V
V
V
V
V
CC
OCSET
OCSET
Falling V
8.1
0.8
0.8
-
-
CC
Enable-Input Threshold Voltage
ISL6522C, V
= 4.5VDC
-
-
2.0
2.1
-
OCSET
ISL6522I, V
= 4.5VDC
OCSET
Rising V
Threshold
1.27
OCSET
OSCILLATOR
Free Running Frequency
ISL6522C, R = OPEN, V
= 12
CC
175
160
-20
-
200
200
-
230
230
+20
-
kHz
%
T
ISL6522I, R = OPEN, V
= 12
T
CC
Total Variation
6k < R to GND < 200k
T
Ramp Amplitude
V
R
= OPEN
1.9
V
P-P
OSC
T
REFERENCE
Reference Voltage Tolerance
V
Commercial
Industrial
-1
-2
-
-
-
1
+1
-
%
%
V
REF
Reference Voltage
ERROR AMPLIFIER
DC Gain
0.800
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/s
COMP = 10pF
GATE DRIVERS
Upper Gate Source
I
V
- V
PHASE
= 12V, V
= 6V
350
500
-
mA
UGATE
BOOT
UGATE
FN9030 Rev 8.00
Mar 10, 2006
Page 4 of 16
ISL6522
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
Upper Gate Sink
SYMBOL
TEST CONDITIONS
= 0.3A
MIN
TYP
5.5
5.5
450
3.5
3.5
MAX
10
UNITS
R
ISL6522C, I
-
UGATE
LGATE
= 0.3A
ISL6522I, I
-
7.2
-
LGATE
Lower Gate Source
Lower Gate Sink
I
V
= 12V, V
= 6V
300
mA
LGATE
CC
LGATE
R
ISL6522C, I
= 0.3A
-
-
6.5
4.5
LGATE
LGATE
= 0.3A
ISL6522I, I
LGATE
PROTECTION
OCSET Current Source
Soft-Start Current
I
V
= 4.5VDC
170
-
200
10
230
-
A
A
OCSET
OCSET
I
SS
Typical Performance Curves
80
70
60
50
40
30
20
10
0
R
PULLUP
TO +12V
T
1000
100
10
C
= 3300pF
GATE
R
PULLDOWN
C
= 1000pF
T
GATE
TO V
SS
C
= 10pF
GATE
100 200 300 400 500 600 700 800 900 1000
10
100
SWITCHING FREQUENCY (kHz)
1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
T
RT
Functional Pin Descriptions
This pin provides oscillator switching frequency adjustment.
SOIC
and
TSSOP
14
13
12
11
10
9
1
2
3
4
5
6
7
RT
OCSET
SS
VCC
By placing a resistor (R ) from this pin to GND, the nominal
T
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
200kHz switching frequency is increased according to the
following equation:
COMP
FB
6
5 10
Fs 200kHz + ------------------
(R to GND)
R
T
T
EN
8
GND
Conversely, connecting a pull-up resistor (R ) from this pin
T
to V
reduces the switching frequency according to the
CC
following equation:
QFN
7
4 10
Fs 200kHz – ------------------
16 15 14 13
(R to 12V)
T
R
T
SS
COMP
FB
1
2
3
4
12 PVCC
11 LGATE
GND
10
9
PGND
BOOT
EN
5
6
7
8
FN9030 Rev 8.00
Mar 10, 2006
Page 5 of 16
ISL6522
OCSET
LGATE
Connect a resistor (R
) from this pin to the drain of the
, an internal 200A current source
Connect LGATE to the lower MOSFET gate. This pin provides
the gate drive for the lower MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the lower MOSFET has turned off.
OCSET
upper MOSFET. R
(I
OCSET
), and the upper MOSFET on-resistance (r
OCS DS(ON)
) set
the converter overcurrent (OC) trip point according to the
following equation:
PVCC
I
R
OCSET
OCS
Provide a bias supply for the lower gate drive to this pin.
I
= -------------------------------------------
PEAK
r
DSON
VCC
An overcurrent trip cycles the soft-start function.
Provide a 12V bias supply for the chip to this pin.
SS
Functional Description
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10A current source, sets the soft-start
interval of the converter.
Initialization
The ISL6522 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
COMP and FB
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
voltage (V ) on the OCSET pin. The level on OCSET is
IN
equal to V Less a fixed voltage drop (see overcurrent
IN
protection). With the EN pin held to V , the POR function
CC
EN
initiates soft-start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft-start pin is
discharged and the UGATE and LGATE pins are held low.
+12V power source, V and V
are equivalent and the
IN
CC
+12V power source must exceed the rising V
before POR initiates operation.
threshold
CC
GND
The POR function inhibits operation with the chip disabled
(EN pin low). With both input supplies above their POR
thresholds, transitioning the EN pin high initiates a soft-start
interval.
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PHASE
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.
Soft-Start
The POR function initiates the soft-start sequence. An internal
10A current source charges an external capacitor (C ) on
the SS pin to 4V. Soft-start clamps the error amplifier output
SS
UGATE
(COMP pin) to the SS pin voltage. Figure 3 shows the soft-
start interval. At t in Figure 3, the SS and COMP voltages
1
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET. This pin is also
monitored by the adaptive shoot through protection circuitry to
determine when the upper MOSFET has turned off.
reach the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2, at which
point the output is in regulation and the clamp on the COMP
pin is released. This method provides a rapid and controlled
output voltage rise.
BOOT
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND
This is the power ground connection. Tie the lower MOSFET
source to this pin.
FN9030 Rev 8.00
Mar 10, 2006
Page 6 of 16
ISL6522
is reference to V . When the voltage across the upper
IN
VOLTAGE
MOSFET (also referenced to V ) exceeds the voltage
IN
V
across R
, the overcurrent function initiates a soft-start
SOFT START
OCSET
sequence. The soft-start function discharges C with a
SS
10A current sink and inhibits PWM operation. The soft-start
function recharges C , and PWM operation resumes with
the error amplifier clamped to the SS voltage. Should an
SS
V
OUT
overload occur while recharging C , the soft-start function
inhibits PWM operation while fully charging C to 4V to
SS
SS
V
COMP
complete its cycle. Figure 4 shows this operation with an
V
OSC(MIN)
overload condition. Note that the inductor current increases
to over 15A during the C charging interval and causes an
SS
overcurrent trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
CLAMP ON V
STEADY STATE
RELEASED AT
TIME
COMP
t
t
t
0
2
1
C
SS
The overcurrent function will trip at a peak inductor current
-----------
t
t
=
V
1
OSCMIN
I
SS
(I
determined by:
PEAK)
V
OUT
C
SS
SteadyState
----------- ------------------------------------------------
V
OSC
= t – t
=
I
R
OCSET
SoftStart
2
1
OCSET
I
V
I
= ---------------------------------------------------
SS
IN
PEAK
r
DSON
C
I
= Soft Start Capacitor
Where:
SS
= Soft Start Current = 10A
where I
is the internal OCSET current source (200A
SS
OCSET
V
V
= Bottom of Oscillator = 1.35V
is typical). The OC trip point varies mainly due to the
MOSFETs r variations. To avoid overcurrent tripping
OSC(MIN)
= Input Voltage
IN
DS(ON)
V
V
= Peak to Peak Oscillator Voltage = 1.9V
in the normal operating load range, find the R
from the equation above with:
resistor
OSC
OCSET
= Steady State Output Voltage
OUTSteadyState
The maximum r
DS(ON)
at the highest junction temperature.
FIGURE 3. SOFT-START INTERVAL
1. The minimum I
2. Determine I
from the specification table.
OCSET
for I
I
PEAK
+ I 2 ,
PEAK
where I is the output inductoOr UriTppMleAXcu rrent.
4V
2V
0V
For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across R in the
OCSET
OCSET
15A
presence of switching noise on the input voltage.
10A
5A
Current Sinking
The ISL6522 incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6522 when it is known that
the converter may sink current.
0A
TIME (20ms/DIV)
FIGURE 4. OVERCURRENT OPERATION
When the converter is sinking current, it is behaving as a boost
converter that is regulating its input voltage. This means that
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
the converter is boosting current into the V rail, the voltage
IN
that is being down-converted. If there is nowhere for this current
to go, such as to other distributed loads on the V rail, through
IN
r
to monitor the current. This method enhances the
DS(ON)
a voltage limiting protection device, or other methods, the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
capacitance on the V bus will absorb the current. This
IN
situation will cause the voltage level of the V rail to increase. If
IN
The overcurrent function cycles the soft-start function in a
the voltage level of the rail is boosted to a level that exceeds the
maximum voltage rating of the MOSFETs or the input
capacitors, damage may occur to these parts. If the bias
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the overcurrent trip level. An internal 200A
(typical) current sink develops a voltage across R
that
OCSET
voltage for the ISL6522 comes from the V rail, then the
IN
FN9030 Rev 8.00
Mar 10, 2006
Page 7 of 16
ISL6522
maximum voltage rating of the ISL6522 may be exceeded and
the IC will experience a catastrophic failure and the converter
will no longer be operational. Ensuring that there is a path for
the current to follow other than the capacitance on the rail will
prevent these failure modes.
+V
Q1
IN
BOOT
D1
C
L
O
BOOT
PHASE
+12V
VCC
V
OUT
ISL6522
SS
C
Q2
O
Application Guidelines
Layout Considerations
C
VCC
C
SS
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
GND
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V ) is regulated to the reference voltage level. The error
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
OUT
amplifier (error amp) output (V ) is compared with the
E/A
oscillator (OSC) triangular wave to provide a pulse-width
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
modulated (PWM) wave with an amplitude of V at the
IN
PHASE node. The PWM wave is smoothed by the output filter
(L and C ).
together as possible. Please note that the capacitors C
O
O
IN
and C each represent numerous physical capacitors.
O
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
Locate the ISL6522 within three inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the ISL6522 must be sized to
handle up to 1A peak current.
OUT E/A
gain and the output filter (L and C ), with a double pole
O
O
break frequency at F and a zero at F
. The DC gain of
LC ESR
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage V
.
OSC
V
IN
ISL6522
UGATE
Q1
Q2
L
O
V
OUT
PHASE
C
IN
C
D2
O
LGATE
PGND
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10A. Provide local V decoupling between VCC and
CC
GND pins. Locate the capacitor, C
as close as practical
BOOT
to the BOOT and PHASE pins.
FN9030 Rev 8.00
Mar 10, 2006
Page 8 of 16
ISL6522
ST
4. Place 1 Pole at the ESR Zero
V
IN
ND
OSC
DRIVER
DRIVER
5. Place 2
Pole at Half the Switching Frequency
PWM
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
L
O
COMPARATOR
V
OUT
-
PHASE
+
V
OSC
C
O
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
ESR
(PARASITIC)
Z
FB
V
E/A
Z
-
IN
+
REFERENCE
ERROR
AMP
compensation gain at F with the capabilities of the error
P2
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
DETAILED COMPENSATION COMPONENTS
Z
FB
V
OUT
C2
Z
IN
100
C1
C3
R3
R2
F
F
P1
F
F
Z2
Z1
P2
80
60
40
20
0
R1
OPEN LOOP
ERROR AMP GAIN
COMP
FB
-
+
20LOG
(R2/R1)
20LOG
ISL6522
(V /V
)
OSC
REF
IN
COMPENSATION
GAIN
MODULATOR
GAIN
-20
-40
-60
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
CLOSED LOOP
GAIN
F
LC
F
ESR
10
100
1K
10K
100K
1M
10M
Modulator Break Frequency Equations
FREQUENCY (Hz)
1
1
F
= --------------------------------------
F
= --------------------------------------------
ESR
LC
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
2 ESR C
2
L C
O O
O
The compensation gain uses external impedance networks
The compensation network consists of the error amplifier
(internal to the ISL6522) and the impedance networks Z
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
and Z . The goal of the compensation network is to provide
FB
a closed loop transfer function with the highest 0dB crossing
frequency (f
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f and
0dB
0dB
180 degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Compensation Break Frequency Equations
1
1
F
= ----------------------------------
F
= ------------------------------------------------------
Z1
P1
2 R2 C1
C1 C2
----------------------
2 R2
C1 + C2
1
1
----------------------------------
F
= -----------------------------------------------------
F
=
Z2
P2
2 R3 C3
2 R1 + R3 C3
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
1. Pick Gain (R2/R1) for desired converter bandwidth
ST
2. Place 1 Zero Below Filter’s Double Pole
(~75% F
ND
3. Place 2
)
LC
Zero at Filter’s Double Pole
FN9030 Rev 8.00
Mar 10, 2006
Page 9 of 16
ISL6522
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
equations give the approximate response time interval for
application and removal of a transient load:
L
I
L I
O TRAN
O
TRAN
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0F
ceramic capacitors in the 1206 surface-mount package.
t
= -------------------------------
t
= ------------------------------
RISE
FALL
V
– V
V
IN
OUT
OUT
where: I
is the transient load current step, t
is the
TRAN
response time to the application of load, and t
RISE
is the
FALL
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
V
- V
V
OUT
V
IN
IN
OUT
------------------------------- ---------------
I =
V
= I x ESR
OUT
Fs x L
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
MOSFET Selection/Considerations
The ISL6522 requires two N-Channel power MOSFETs.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6522 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
These should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower
The response time to a transient is different for the
application of load and the removal of load. The following
FN9030 Rev 8.00
Mar 10, 2006
Page 10 of 16
ISL6522
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
D
BOOT
+12V
VCC
+5V OR +12V
-
+
V
D
Losses while Sourcing Current
2
1
2
BOOT
--
D + Io V t
P
= Io r
F
SW
UPPER
DSON
IN
S
ISL6522
C
BOOT
2
Q1
P
= Io x r
x (1 - D)
DS(ON)
LOWER
UGATE
PHASE
NOTE:
V
G-S V - V
CC
D
Losses while Sinking Current
2
P
= Io x r
x D
UPPER
DS(ON)
+5V
OR +12V
2
1
2
PVCC
--
1 – D + Io V t
P
= Io r
F
SW S
LOWER
DSON
IN
D2
Q2
Where: D is the duty cycle = V
/ V ,
OUT
IN
LGATE
PGND
-
NOTE:
G-S PVCC
t
is the switching interval, and
is the switching frequency.
+
SW
V
F
S
GND
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522 and do not
heat the MOSFETs. However, large gate-charge increases
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is +5V
or
DC
the switching interval, t
which increases the upper
SW
less. The peak upper gate-to-source voltage is approximately
less the input supply. For +5V main power and +12V
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
V
CC
DC
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to PV
.
CC
+12V
Standard-gate MOSFETs are normally recommended for
use with the ISL6522. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
+5V OR LESS
VCC
BOOT
ISL6522
Q1
UGATE
PHASE
NOTE:
G-S V - 5V
V
CC
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V . The boot capacitor, C
develops a floating supply voltage referenced to the PHASE
+5V
OR +12V
CC
BOOT
PVCC
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V ) when the lower MOSFET, Q2
D
turns on. A logic-level MOSFET can only be used for Q1 if
D2
CC
Q2
LGATE
PGND
-
NOTE:
G-S PVCC
+
V
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V . For Q2, a
CC
GND
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
FIGURE 10. UPPER GATE DRIVE - DIRECT V
DRIVE OPTION
CC
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
FN9030 Rev 8.00
Mar 10, 2006
Page 11 of 16
ISL6522
implemented using the ISL6522 controller without any
modifications. Detailed information on the circuit, including a
complete bill of materials and circuit board description, can be
found in Application Note AN9722. See Intersil’s home page on
the web: http://www.intersil.com.
ISL6522 DC-DC Converter Application
Circuit
Figure 11 shows a DC-DC converter circuit for a
microprocessor application, originally designed to employ the
HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522 controllers, the circuit can be
12V
CC
V
IN
C17-18
2x 1F
1206
C1-3
3x 680F
RTN
C12
1F
C19
R7
10K
1206
VCC
14
1000pF
R6
CR1
4148
OCSET
2
6
ENABLE
MONITOR AND
PROTECTION
SS
RT
3
3.01K
Q1
PHASE
TP2
10 BOOT
1
C20
0.1F
9
UGATE
OSC
L1
R1
SPARE
C13
0.1F
U1
ISL6522
PHASE
PVCC
8
REF
V
OUT
13
CR2
Q2
LGATE
PGND
C6-9
4x 1000F
12
11
-
+
-
MBR
340
+
5
FB
RTN
4
7
R2
1K
GND
JP1
COMP
C14
33pF
C15
R5
COMP
TP1
15K
0.01F
C16
SPARE
R4
SPARE
R3
1K
Component Selection Notes:
C1-C3 - Three each 680F 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000F 6.3W VDC, Sanyo MV-GX or equivalent.
L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.
Q1, Q2 - Fairchild MOSFET; RFP25N05
FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT
FN9030 Rev 8.00
Mar 10, 2006
Page 12 of 16
ISL6522
© Copyright Intersil Americas LLC 2001-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9030 Rev 8.00
Mar 10, 2006
Page 13 of 16
ISL6522
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN9030 Rev 8.00
Mar 10, 2006
Page 14 of 16
ISL6522
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
9
D
c
-
-C-
D
3
E1
e
4
A2
e
A1
c
0.026 BSC
0.65 BSC
-
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 6/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN9030 Rev 8.00
Mar 10, 2006
Page 15 of 16
ISL6522
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.28
2.95
2.95
0.33
0.40
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.80 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
16
4
4
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare providedtoassist with PCB LandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9030 Rev 8.00
Mar 10, 2006
Page 16 of 16
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