ISL6526ACBZ [RENESAS]
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; QFN16, SOIC14; Temp Range: See Datasheet;
| 型号： | ISL6526ACBZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller; QFN16, SOIC14; Temp Range: See Datasheet 开关 光电二极管 |
| 文件： | 总18页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EW DESIGNS
EMENT PART
ENDED FOR N
NOT RECOMM
DED REPLAC
DATASHEET
RECOMMEN
ISL8105
ISL6526, ISL6526A
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
FN9055
Rev 12.00
Sep 30, 2015
The ISL6526, ISL6526A make simple work out of
implementing a complete control and protection scheme for
a DC/DC stepdown converter. Designed to drive N-Channel
MOSFETs in a synchronous buck topology, the ISL6526,
ISL6526A integrate the control, output adjustment,
Features
• Operates from 3.3V to 5V Input
• 0.8V to V Output Range
IN
- 0.8V Internal Reference
monitoring and protection functions into a single package.
- ±1.5% Over Load, Line Voltage and Temperature
The ISL6526, ISL6526A provide simple, single feedback
loop, voltage-mode control with fast transient response. The
output voltage can be precisely regulated to as low as 0.8V,
with a maximum tolerance of ±1.5% over-temperature and
line voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
• Drives N-Channel MOSFETs
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
The error amplifier features a 15MHz gain-bandwidth
product and 6V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
• Lossless, Programmable Overcurrent Protection
- Uses Upper MOSFET’s r
DS(on)
• Converter can Source and Sink Current
• Small Converter Size
Protection from overcurrent conditions is provided by
- Internal Fixed Frequency Oscillator
monitoring the r
of the upper MOSFET to inhibit PWM
DS(ON)
-
-
ISL6526: 300kHz
ISL6526A: 600kHz
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
• Internal Soft-Start
• 14 Ld SOIC or 16 Ld 5x5 QFN
• QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors
- PCs
- Embedded Controllers
• Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
- DDR SDRAM Bus Termination Supply
• Cable Modems, Set-Top Boxes, and DSL Modems
• DSP and Core Communications Processor Supplies
• Memory Supplies
• Personal Computer Peripherals
• Industrial Power Supplies
• 3.3V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
FN9055 Rev 12.00
Sep 30, 2015
Page 1 of 18
ISL6526, ISL6526A
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP
RANGE (°C)
PKG
DWG. #
PACKAGE
14 Ld SOIC (Pb-free)
14 Ld SOIC (Pb-free)
14 Ld SOIC (Pb-free)
ISL6526CBZ
6526CBZ
6526CBZ
0 to +70
0 to +70
0 to +70
M14.15
ISL6526CBZ-T (Note 1)
M14.15
M14.15
ISL6526ACBZ (No longer available, 6526ACBZ
recommended replacement:
ISL6526AIRZ)
ISL6526ACBZ-T (Note 1) (No longer 6526ACBZ
available, recommended
replacement: ISL6526AIRZ-T)
0 to +70
0 to +70
0 to +70
14 Ld SOIC (Pb-free)
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
M14.15
ISL6526CRZ (No longer available,
recommended replacement:
ISL6526IRZ)
ISL6526 CRZ
ISL6526 CRZ
L16.5x5B
L16.5x5B
ISL6526CRZ-T (Note 1) (No longer
available, recommended
replacement: ISL6526IRZ-T)
ISL6526IBZ
6526IBZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
14 Ld SOIC (Pb-free)
M14.15
ISL6526IBZ-T (Note 1)
ISL6526IRZ
6526IBZ
14 Ld SOIC (Pb-free)
M14.15
ISL 6526IRZ
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
16 Ld 5x5 QFN (Pb-free)
L16.5x5B
L16.5x5B
L16.5x5B
L16.5x5B
L16.5x5B
L16.5x5B
ISL6526IRZ-T (Note 1)
ISL6526IRZ-TK (Note 1)
ISL6526AIRZ
ISL 6526IRZ
ISL 6526IRZ
ISL65 26AIRZ
ISL6526AIRZ-T (Note 1)
ISL6526AIRZ-TK (Note 1)
ISL6526EVAL1
ISL65 26AIRZ
ISL65 26AIRZ
ISL6526 SOIC Evaluation Board
ISL6526 QFN Evaluation Board
ISL6526A SOIC Evaluation Board
ISL6526A QFN Evaluation Board
ISL6526EVAL2
ISL6526AEVAL1
ISL6526AEVAL2
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6526, ISL6526A. For more information on MSL please see tech
brief TB363.
FN9055 Rev 12.00
Sep 30, 2015
Page 2 of 18
ISL6526, ISL6526A
Pinouts
ISL6526, ISL6526A
(14 LD SOIC)
TOP VIEW
ISL6526, ISL6526A
(16 LD QFN)
TOP VIEW
GND
1
2
3
4
5
6
7
14 UGATE
BOOT
PHASE
VCC
13
12
11
LGATE
CPVOUT
CT1
16 15 14 13
CPVOUT
CT1
1
2
3
4
12 PHASE
11 VCC
10 CPGND
CT2
9
8
ENABLE
COMP
OCSET
FB
10
9
CT2
CPGND
NC
OCSET
5
6
7
8
FN9055 Rev 12.00
Sep 30, 2015
Page 3 of 18
ISL6526, ISL6526A
Typical Application - 3.3V Input
3.3V
V
IN
C
IN
C
BULK
VCC
OCSET
CT1
CT2
R
OCSET
C
PUMP
CPVOUT
ISL6526, ISL6526A
D
C
BOOT
BOOT
C
DCPL
C
HF
BOOT
CPGND
GND
UGATE
PHASE
Q
Q
1
L
OUT
C
V
OUT
ENABLE
COMP
LGATE
OUT
2
FB
DISABLE
C
I
R
FB
R
C
F
F
R
OFFSET
Typical Application - 5V Input
+5V
V
IN
C
BULK
VCC
OCSET
CT1
CT2
R
OCSET
CPVOUT
ISL6526, ISL6526A
D
C
BOOT
N/C
C
IN
C
HF
BOOT
CPGND
GND
BOOT
UGATE
PHASE
Q
Q
1
L
OUT
V
OUT
ENABLE
COMP
C
LGATE
OUT
2
FB
DISABLE
C
I
R
FB
R
C
F
F
R
OFFSET
FN9055 Rev 12.00
Sep 30, 2015
Page 4 of 18
ISL6526, ISL6526A
Block Diagram
VCC
CPVOUT
CT1
CT2
CHARGE
PUMP
POWER-ON
ENABLE
RESET (POR)
CPGND
OCSET
BOOT
+
-
SOFT-START
OC
UGATE
COMPARATOR
20µA
PHASE
PWM
COMPARATOR
ERROR
AMP
GATE
CONTROL
LOGIC
+
-
+
-
+
-
PWM
0.8V
LGATE
FB
OSCILLATOR
COMP
FIXED 300kHz OR 600kHz
GND
FN9055 Rev 12.00
Sep 30, 2015
Page 5 of 18
ISL6526, ISL6526A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Thermal Resistance
(°C/W)
(°C/W)
JC
JA
Absolute Boot Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
Upper Driver Supply Voltage, V
SOIC Package (Note 4) . . . . . . . . . . . .
QFN Package (Notes 5, 6). . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
67
35
N/A
5
- V
. . . . . . . . . . . +7.0V
BOOT
PHASE
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, unless otherwise noted V
= 3.3V ±5% and T = +25°C.
A
CC
MIN
MAX
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
I
6.1
6.9
7.7
mA
BIAS
POWER-ON RESET
Rising CPVOUT POR Threshold
POR
Commercial
Industrial
4.25
4.10
0.3
4.30
4.30
0.6
4.42
4.50
0.9
V
V
V
CPVOUT POR Threshold Hysteresis
OSCILLATOR
Frequency
f
IC = ISL6526C, Commercial
IC = ISL6526I, Industrial
275
250
554
524
-
300
300
600
600
1.5
325
340
645
650
-
kHz
kHz
kHz
kHz
OSC
IC = ISL6526AC, Commercial
IC = ISL6526AI, Industrial
Ramp Amplitude
V
V
P-P
OSC
REFERENCE
Reference Voltage Tolerance
Nominal Reference Voltage
CHARGE PUMP
-
-
-
1.5
-
%
V
V
0.800
REF
Nominal Charge Pump Output
Charge Pump Output Regulation
ERROR AMPLIFIER
DC Gain
V
V
= 3.3V, No Load
VCC
-
-
5.1
2
-
-
V
CPVOUT
%
(Note 7)
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
MHz
V/µs
SOFT-START
Soft-Start Slew Rate
Commercial
Industrial
6.2
6.2
-
-
7.3
7.6
ms
ms
FN9055 Rev 12.00
Sep 30, 2015
Page 6 of 18
ISL6526, ISL6526A
Electrical Specifications Recommended Operating Conditions, unless otherwise noted V
= 3.3V ±5% and T = +25°C. (Continued)
A
CC
MIN
MAX
PARAMETER
GATE DRIVERS
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
Upper Gate Source Current
Upper Gate Sink Current
Lower Gate Source Current
Lower Gate Sink Current
PROTECTION/DISABLE
OCSET Current Source
I
V
V
- V
PHASE
= 5V, V = 4V
UGATE
-
-
-
-
-1
1
-
-
-
-
A
A
A
A
UGATE-SRC
BOOT
I
UGATE-SNK
I
= 3.3V, V = 4V
LGATE
-1
2
LGATE-SRC
VCC
I
LGATE-SNK
I
Commercial
Industrial
18
16
-
20
20
-
22
22
µA
µA
V
OCSET
Disable Threshold
NOTE:
V
0.8
DISABLE
7. Limits should be considered typical and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
COMP and FB
Functional Pin Descriptions
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the internal
error amplifier and the COMP pin is the error amplifier
output. These pins are used to compensate the voltage
control feedback loop of the converter.
14 LD SOIC
TOP VIEW
GND
1
2
3
4
5
6
7
14 UGATE
BOOT
13
12
11
10
9
LGATE
CPVOUT
CT1
PHASE
VCC
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
CPGND
ENABLE
COMP
CT2
OCSET
FB
8
PHASE
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
16 LD 5X5 QFN
TOP VIEW
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
16 15 14 13
CPVOUT
1
2
3
4
12 PHASE
11 VCC
CT1
CT2
10 CPGND
BOOT
OCSET
9
NC
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-Channel MOSFET.
5
6
7
8
LGATE
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
VCC
This pin provides the bias supply for the ISL6526, ISL6526A.
Connect a well-decoupled 3.3V supply to this pin.
FN9055 Rev 12.00
Sep 30, 2015
Page 7 of 18
ISL6526, ISL6526A
Figure 1 shows the soft-start sequence for a typical application.
At t0, the +3.3V VCC voltage starts to ramp-up. At time t1, the
Charge Pump begins operation and the +5V CPVOUT IC bias
voltage starts to ramp-up. Once the voltage on CPVOUT
crosses the POR threshold at time t2, the output begins the
soft-start sequence. The triangle waveform from the PWM
oscillator is compared to the rising error amplifier output
voltage. As the error amplifier voltage increases, the pulse
width on the UGATE pin increases to reach the steady-state
duty cycle at time t3.
OCSET
Connect a resistor (R
upper MOSFET (V ). R
IN OCSET
source (I
) from this pin to the drain of the
, an internal 20µA current
), and the upper MOSFET ON-resistance
OCSET
OCSET
(r ) set the converter overcurrent (OC) trip point
DS(ON)
according Equation 1:
I
xR
OCSET
OCSET
(EQ. 1)
I
= -------------------------------------------------
PEAK
r
DSON
An overcurrent trip cycles the soft-start function.
ENABLE
(1V/DIV)
CPVOUT (5V)
This pin is the open-collector enable pin. Pulling this pin to a
level below 0.8V will disable the controller. Disabling the
ISL6526, ISL6526A causes the oscillator to stop, the LGATE
and UGATE outputs to be held low, and the soft-start
circuitry to re-arm.
VCC (3.3V)
CT1 and CT2
V
(2.50V)
OUT
These pins are the connections for the external charge
pump capacitor. A minimum of a 0.1µF ceramic capacitor is
recommended for proper operation of the IC.
0V
t3
t0
t1
t2
CPVOUT
TIME
This pin represents the output of the charge pump. The
voltage at this pin is the bias voltage for the IC. Connect a
decoupling capacitor from this pin to ground. The value of the
decoupling capacitor should be at least 10x the value of the
charge pump capacitor. This pin may be tied to the bootstrap
circuit as the source for creating the BOOT voltage.
FIGURE 1. SOFT-START INTERVAL
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulator from a shoot-through condition, the ISL6526,
ISL6526A incorporate specialized circuitry which insures
that the complementary MOSFETs are not ON
simultaneously.
CPGND
This pin represents the signal and power ground for the
charge pump. Tie this pin to the ground island/plane through
the lowest impedance connection available.
The adaptive shoot-through protection utilized by the
ISL6526, ISL6526A look at the lower gate drive pin, LGATE,
and the upper gate drive pin, UGATE, to determine whether
a MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the complementary
MOSFET is turned ON. This method of shoot-through
protection allows the regulator to sink or source current.
Functional Description
Initialization
The ISL6526, ISL6526A automatically initialize upon receipt
of power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the output voltage of the charge pump. During
POR, the charge pump operates on a free running oscillator.
Once the POR level is reached, the charge pump oscillator
is synched to the PWM oscillator. The POR function also
initiates the soft-start operation after the charge pump output
voltage exceeds its POR threshold.
Since the voltage of the lower MOSFET gate and the upper
MOSFET gate are being measured to determine the state of
the MOSFET, the designer is encouraged to consider the
repercussions of introducing external components between
the gate drivers and their respective MOSFET gates before
actually implementing such measures. Doing so may
interfere with the shoot-through protection.
Soft-Start
The POR function initiates the digital soft-start sequence.
The PWM error amplifier reference is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). This
method provides a rapid and controlled output voltage rise.
The soft-start sequence typically takes about 6.5ms.
Output Voltage Selection
The output voltage can be programmed to any level between
V
and the internal reference, 0.8V. An external resistor
IN
divider is used to scale the output voltage relative to the
FN9055 Rev 12.00
Sep 30, 2015
Page 8 of 18
ISL6526, ISL6526A
reference voltage and feed it back to the inverting input of
the error amplifier; see Figure 2. However, since the value of
R1 affects the values of the rest of the compensation
components, it is advisable to keep its value less than 5k.
R4 can be calculated based Equation 2:
internal soft-start cycle initiates a normal soft-start ramp of the
output, at time t1. The output is brought back into regulation
by time t2, as long as the overcurrent event has cleared.
Had the cause of the overcurrent still been present after the
delay interval, the overcurrent condition would be sensed and
the regulator would be shut down again for another delay
interval of three soft-start cycles. The resulting hiccup mode
style of protection would continue to repeat indefinitely.
R1 0.8V
(EQ. 2)
R4 = -------------------------------------
V
– 0.8V
OUT1
If the output voltage desired is 0.8V, simply route the output
back to the FB pin through R1, but do not populate R4.
+3.3V
V
(2.5V)
OUT
VIN
VCC
CPVOUT
D1
BOOT
0V
C4
Q1
UGATE
ISL6526,
ISL6526A
L
OUT
INTERNAL SOFT-START FUNCTION
DELAY INTERVAL
V
OUT
PHASE
LGATE
Q2
+
C
OUT
FB
C1
R1
C3
COMP
R3
t0
t1
t2
TIME
C2
R2
FIGURE 3. OVERCURRENT PROTECTION RESPONSE
R4
The overcurrent function will trip at a peak inductor current
FIGURE 2. OUTPUT VOLTAGE SELECTION
(I
determined by Equation 3:
PEAK)
I
x R
OCSET
OCSET
(EQ. 3)
I
= ----------------------------------------------------
PEAK
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET ON-resistance, r
r
DSON
,
where I is the internal OCSET current source (20µA
OCSET
DS(ON)
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
typical). The OC trip point varies mainly due to the MOSFET
r
variations. To avoid overcurrent tripping in the
DS(ON)
normal operating load range, find the R
resistor from
OCSET
Equation 3 with:
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
1. The maximum r
temperature.
at the highest junction
OCSET
DS(ON)
programs the overcurrent trip level (see “Typical Application -
3.3V Input” on page 4 and “Typical Application - 5V Input” on
page 4). An internal 20µA (typical) current sink develops a
2. The minimum I
3. Determine I
from the specification table.
OCSET
I
2
I
I
+ ----------
OUTMAX
for
,
PEAK
PEAK
voltage across R
that is referenced to V . When the
OCSET
IN
whereI is the output inductor ripple current.
voltage across the upper MOSFET (also referenced to V )
IN
exceeds the voltage across R
initiates a soft-start sequence.
, the overcurrent function
OCSET
For the ripple current, see Equation 11 in “Output Inductor
Selection” on page 12.
Figure 3 illustrates the protection feature responding to an
overcurrent event. At time t0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function begins
producing soft-start ramps. The delay interval seen by the
output is equivalent to three soft-start cycles. The fourth
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across
R
in the
OCSET
presence of switching noise on the input voltage.
OCSET
FN9055 Rev 12.00
Sep 30, 2015
Page 9 of 18
ISL6526, ISL6526A
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
Current Sinking
The ISL6526, ISL6526A incorporate a MOSFET shoot-through
protection method which allows a converter to sink current as
well as source current. Care should be exercised when
designing a converter with the ISL6526, ISL6526A when it is
known that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the input
rail of the regulator. If there is nowhere for this current to go,
(such as to other distributed loads on the rail or through a
voltage limiting protection device), the capacitance on this
rail will absorb the current. This situation will allow the
voltage level of the input rail to increase. If the voltage level
of the rail is boosted to a level that exceeds the maximum
voltage rating of any components attached to the input rail,
then those components may experience an irreversible
failure or experience stress that may shorten their lifespan.
Ensuring that there is a path for the current to flow other than
the capacitance on the rail will prevent this failure mode.
+3.3V V
IN
ISL6526, ISL6526A
VCC
C
VCC
CPVOUT
C
BP
C
IN
GND
D1
BOOT
C
BOOT
Application Guidelines
Q1
UGATE
PHASE
Layout Considerations
L
OUT
V
PHASE
OUT
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz or 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise
into the circuit, and lead to device overvoltage stress.
Careful component layout and printed circuit board design
minimize the voltage spikes in the converters.
Q2
C
LGATE
COMP
OUT
C
2
C
1
R
2
R
1
FB
C
R
3
3
R4
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET
and is picked up by the lower MOSFET. Any parasitic
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
traces minimize the magnitude of voltage spikes.
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
There are two sets of critical components in a DC/DC
converter using the ISL6526, ISL6526A. The switching
components are the most critical because they switch large
amounts of energy, and therefore tend to generate large
amounts of noise. Next are the small signal components
which connect to sensitive nodes or supply critical bypass
current and signal coupling.
The switching components should be placed close to the
ISL6526, ISL6526A first. Minimize the length of the connections
between the input capacitors, C , and the power switches by
IN
placing them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper MOSFET and lower MOSFET and the load.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
The critical small signal components include any bypass
capacitors, feedback components, and compensation
converter. Note that capacitors C and C
could each
IN
OUT
components. Position the bypass capacitor, C , close to
BP
represent numerous physical capacitors. Dedicate one solid
layer (usually a middle layer of the PC board) for a ground
plane and make all critical component ground connections
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
FN9055 Rev 12.00
Sep 30, 2015
Page 10 of 18
ISL6526, ISL6526A
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
networks Z and Z . The goal of the compensation
IN FB
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f ) and adequate phase
0dB
margin. Phase margin is the difference between the closed
loop phase at f and 180°. Equations 6, 7, 8 and 9 relate
Feedback Compensation
0dB
the compensation network’s poles, zeros and gain to the
components (R , R , R , C , C , and C ) in Figure 5. Use
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
1
2
3
1
2
3
(V
) is regulated to the Reference voltage level. The
OUT
these guidelines for locating the poles and zeros of the
compensation network:
error amplifier (Error Amp) output (V ) is compared with
E/A
the oscillator (OSC) triangular wave to provide a pulse
width modulated (PWM) wave with an amplitude of V at
1. Pick gain (R /R ) for desired converter bandwidth.
2 1
IN
the PHASE node. The PWM wave is smoothed by the output
2. Place first zero below filter’s double pole (~75% f ).
LC
filter (L and C ).
O
O
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
OUT E/A
Gain and the output filter (L and C ), with a double pole
O
O
break frequency at f and a zero at f
. The DC Gain of
LC ESR
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage V
OSC
.
Compensation Break Frequency Equations
1
(EQ. 6)
(EQ. 7)
(EQ. 8)
f
= ----------------------------------
Z1
2 R C
V
IN
DRIVER
2
2
OSC
PWM
COMPARATOR
L
O
V
OUT
1
f
= ------------------------------------------------------
2 x R + R x C
3
Z2
1
3
-
DRIVER
PHASE
+
V
C
O
OSC
1
f
= --------------------------------------------------------
P1
ESR
(PARASITIC)
C
x C
1
2
---------------------
2 x R
x
2
Z
C
+ C
2
FB
1
V
E/A
1
Z
f
= -----------------------------------
-
IN
(EQ. 9)
P2
2 x R x C
+
3
3
REFERENCE
ERROR
AMP
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the previously mentioned guidelines
should give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
DETAILED COMPENSATION COMPONENTS
Z
FB
V
OUT
C
1
Z
IN
C
C
R
R
3
2
3
2
gain. Check the compensation gain at f with the capabilities
P2
R
1
of the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
COMP
FB
-
+
compensation transfer function and plotting the gain.
ISL6526, ISL6526A
REFERENCE
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45°. Include worst case component variations when
determining phase margin.
Modulator Break Frequency Equations
1
(EQ. 4)
f
= -----------------------------------------
LC
2 x
L
x C
O O
1
(EQ. 5)
f
= ------------------------------------------
ESR
2 x ESR x C
O
The compensation network consists of the error amplifier
(internal to the ISL6526, ISL6526A) and the impedance
FN9055 Rev 12.00
Sep 30, 2015
Page 11 of 18
ISL6526, ISL6526A
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
OPEN LOOP
ERROR AMP GAIN
f
f
f
P1
f
Z1
Z2
P2
100
80
V
IN
-----------------
20log
V
OSC
60
40
COMPENSATION
GAIN
20
0
R2
-------
20log
R1
-20
-40
-60
Output Inductor Selection
MODULATOR
GAIN
LOOP GAIN
10M
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equations 11 and 12:
f
f
ESR
LC
1k
10
100
10k
100k
1M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Charge Pump Capacitor Selection
V
- V
V
IN
f x L
OUT
OUT
(EQ. 11)
I =
V
x
V
s
IN
(EQ. 12)
= I x ESR
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6526, ISL6526A when
operating the IC from 3.3V. Selecting the proper capacitance
value is important so that the bias current draw and the
current required by the MOSFET gates do not overburden
the capacitor. A conservative approach is presented in
Equation 10.
OUT
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6526, ISL6526A will provide either 0% or 100% duty
cycle in response to a load transient. The response time is
the time required to slew the inductor current from an initial
current value to the transient current level. During this
interval, the difference between the inductor current and
the transient current level must be supplied by the output
capacitor. Minimizing the response time can minimize the
output capacitance required.
I
BiasAndGate
(EQ. 10)
------------------------------------
C
=
1.5
PUMP
V
f
s
CC
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
The response time to a transient is different for the
application of load and the removal of load. Equations 13
and 14 give the approximate response time interval for
application and removal of a transient load:
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
L x I
TRAN
- V
OUT
(EQ. 13)
t
=
RISE
V
IN
L x I
TRAN
t
=
(EQ. 14)
FALL
V
OUT
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
where: I
is the transient load current step, t
is the
TRAN
response time to the application of load, and t
RISE
is the
FALL
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
FN9055 Rev 12.00
Sep 30, 2015
Page 12 of 18
ISL6526, ISL6526A
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q turns on. Place the
1
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q and the source of Q .
Losses while Sourcing Current
1
2
2
1
2
--
D + Io V t
P
P
= Io r
f
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
UPPER
DSON
IN SW s
2
= Io x r
x (1 - D)
(EQ. 16)
LOWER
DS(ON)
Losses while Sinking Current
2
P
= Io x r
x D
DS(ON)
UPPER
2
1
2
--
1 – D + Io V t
P
= Io r
f
LOWER
DSON
IN SW
s
Where: D is the duty cycle = V
/V ,
OUT IN
t
is the combined switch ON and OFF time, and
SW
f is the switching frequency.
s
(EQ. 17)
The maximum RMS current required by the regulator may be
closely approximated using Equation 15:
Given the reduced available gate bias voltage (5V), logic-level
or sub-logic-level transistors should be used for both
N-MOSFETs. Caution should be exercised with devices
2
VOUT
-------------
VIN
VIN – VOUT VOUT
2
1
12
------ ---------------------------- -------------
IRMS
=
IOUT
+
L fs
VIN
MAX
MAX
(EQ. 15)
exhibiting very low V
characteristics. The shoot-through
GS(ON)
protection present aboard the ISL6526, ISL6526A may be
circumvented by these MOSFETs if they have large parasitic
impedances and/or capacitances that would inhibit the gate of
the MOSFET from being discharged below its threshold level
before the complementary MOSFET is turned on.
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by the
external bootstrap circuitry, as shown in Figure 7. The boot
MOSFET Selection/Considerations
The ISL6526, ISL6526A require two N-Channel power
MOSFETs. These should be selected based upon r
,
DS(ON)
capacitor, C
, develops a floating supply voltage
BOOT
gate supply requirements, and thermal management
requirements.
referenced to the PHASE pin. This supply is refreshed each
cycle, when D conducts, to a voltage of CPVOUT less the
BOOT
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor. The
switching losses seen when sourcing current will be different
from the switching losses seen when sinking current. When
sourcing current, the upper MOSFET realizes most of the
switching losses. The lower switch realizes most of the
switching losses when the converter is sinking current (see
Equations 16 and 17). These equations assume linear
voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are
boot diode drop, V , plus the voltage rise across Q
D
.
LOWER
CPVOUT
ISL6526,
ISL6526A
D
BOOT
+
V
-
V
IN
D
BOOT
C
BOOT
UGATE
PHASE
Q
Q
UPPER
NOTE:
= V -V
D
V
G-S
CC
LGATE
LOWER
-
+
NOTE:
= V
V
G-S
CC
GND
dissipated by the ISL6526, ISL6526A and don't heat the
MOSFETs. However, large gate-charge increases the
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
switching interval, t which increases the MOSFET
SW
FN9055 Rev 12.00
Sep 30, 2015
Page 13 of 18
ISL6526, ISL6526A
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance is
complete, the voltage on the bootstrap capacitor is at its lowest
point during the switching cycle. The charge lost on the
bootstrap capacitor will be equal to the charge transferred to
the equivalent gate-source capacitance of the upper MOSFET
as shown in Equation 18:
Typical gate charge values for MOSFETs considered in these
types of applications range from 20 to 100nC. Since the
voltage drop across Q
LOWER
is negligible, V
is simply
BOOT1
- V . A Schottky diode is recommended to minimize
V
CPVOUT
the voltage drop across the bootstrap capacitor during the on-
time of the upper MOSFET. Initial calculations with V no
D
BOOT2
less than 4V will quickly help narrow the bootstrap capacitor
range.
(EQ. 18)
Q
= C
V
– V
BOOT2
GATE
BOOT
BOOT1
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q , of 100nC. Limiting the voltage drop
g
where Q
MOSFET, C
is the maximum total gate charge of the upper
GATE
across the bootstrap capacitor to 1V results in a value of no
less than 0.1µF. The tolerance of the ceramic capacitor should
also be considered when selecting the final bootstrap
capacitance value.
is the bootstrap capacitance, V
is the
is
BOOT
BOOT1
bootstrap voltage immediately before turn-on, and V
the bootstrap voltage immediately after turn-on.
BOOT2
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle ends
when the upper MOSFET is turned on again, which varies
depending on the switching frequency and duty cycle.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q , would have
RR
to be added to the gate charge of the MOSFET and taken into
consideration when calculating the minimum bootstrap
capacitance.
The minimum bootstrap capacitance can be calculated by
rearranging the previous equation and solving for C
.
BOOT
Q
GATE
ISL6526, ISL6526A DC/DC Converter
Application Circuit
(EQ. 19)
C
= ----------------------------------------------------
BOOT
V
– V
BOOT1
BOOT2
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete Bill of
Materials and circuit board description, can be found in
Application Note AN1021:
http://www.intersil.com/data/an/an1021.pdf.
FN9055 Rev 12.00
Sep 30, 2015
Page 14 of 18
ISL6526, ISL6526A
3.3V
GND
C
0.1µF
1
C
2
1000pF
11
U
1
TP
C
1
3
VCC
6
3
4
5
OCSET
CT1
CT2
R
1
TP
ISL6526, ISL6526A
3
9.76k
C
4
0.22µF
CPVOUT
C
10µF
CERAMIC
CAP
5
D
C
1
C
6
13
1µF
BOOT
10
1
CPGND
GND
0.1µF
7
14
12
UGATE
PHASE
L
1
2.5V @ 5A
9
ENABLE
ENABLE
2
C
LGATE
8, 9
Q
1
COMP
8
FB
7
C
10
R
3
33pF
C
R
11
2
2.26k
R
C
4
12
6.49k 5600pF
GND
124 8200pF
R
5
1.07k
FIGURE 8. 3.3V TO 2.5V 5A DC/DC CONVERTER
Component Selection Notes:
C
C
C - Each 150µF, Panasonic EEF-UE0J151R or Equivalent.
3, 8,
D1 - 30mA Schottky Diode, MA732 or Equivalent
L - 1µH Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent.
9
1
Q - Fairchild MOSFET; ITF86110DK8.
1
FN9055 Rev 12.00
Sep 30, 2015
Page 15 of 18
ISL6526, ISL6526A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
Sep 30, 2015
FN9055.12 Updated Ordering Information Table on page 2.
Added Revision History.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2001-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9055 Rev 12.00
Sep 30, 2015
Page 16 of 18
ISL6526, ISL6526A
Package Outline Drawing
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/08
4X
2.4
5.00
0.80
12X
A
6
B
13
16
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
12
1
3 . 10 ± 0 . 15
9
4
(4X)
0.15
5
8
0.10 M C A B
+0.15
-0.10
16X 0 . 60
TOP VIEW
4
0.33 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10
C
C
1.00 MAX
BASE PLANE
SEATING PLANE
0.08
C
( 4 . 6 TYP )
SIDE VIEW
(
3 . 10 )
( 12X 0 . 80 )
5
C
0 . 2 REF
( 16X 0 .33 )
( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9055 Rev 12.00
Sep 30, 2015
Page 17 of 18
ISL6526, ISL6526A
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A
3
6
DETAIL"A"
0.22±0.03
D
14
8
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
(0.35) x 45°
4° ± 4°
5
0.31-0.51
0.25M C A-B D
B
3
6
TOP VIEW
0.10 C
H
1.75 MAX
1.25 MIN
0.25
GAUGE PLANE
SEATING PLANE
C
0.10-0.25
1.27
0.10 C
SIDE VIEW
DETAIL "A"
(1.27)
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
(1.50)
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN9055 Rev 12.00
Sep 30, 2015
Page 18 of 18
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