ISL6540ACRZA [RENESAS]
4A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PQCC28, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28;型号: | ISL6540ACRZA |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 4A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PQCC28, 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28 开关 |
文件: | 总22页 (文件大小:427K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6540A
®
Data Sheet
October 7, 2008
FN6288.5
Single-Phase Buck PWM Controller with
Integrated High Speed MOSFET Driver
and Pre-Biased Load Capability
Features
• VIN and Power Rail Operation from +3.3V to +20V
• Fast Transient Response - 0 to 100% Duty Cycle
- 15MHz Bandwidth Error Amplifier with 6V/µs Slew Rate
- Voltage-Mode PWM Leading and Trailing-Edge
Modulation Control
The ISL6540A is an improved version of the ISL6540
single-phase voltage-mode PWM controller with input voltage
feed-forward compensation to maintain a constant loop gain for
optimal transient response, especially for applications with a
wide input voltage range. Its integrated high speed
synchronous rectified MOSFET drivers and other sophisticated
features provide complete control and protection for a DC/DC
converter with minimum external components, resulting in
minimum cost and less engineering design efforts.
- Input Voltage Feedforward Compensation
• 2.9V to 5.5V High Speed 2A/4A MOSFET Gate Drivers
- Tri-state for Power Stage Shutdown
• Internal Linear Regulator (LR) - 5.5V Bias from VIN
• External LR Drive for Optimal Thermal Performance
• Voltage Margining with Independently Adjustable Upper and
Lower Settings for System Stress Testing and Over Clocking
The output voltage of the converter can be precisely regulated
with an internal reference voltage of 0.591V, and has an
improved system tolerance of ±0.68% over commercial
temperature and line load variations. An external voltage can
be used in place of the internal reference for voltage
tracking/DDR applications.
• Reference Voltage I/O for DDR/Tracking Applications
• Improved 0.591V Internal Reference with Buffered Output
- ±0.68%/±1.0% Over Commercial/Industrial Range
• Source and Sink Overcurrent Protections
- Low-and High-Side MOSFET r
Sensing
DS(ON)
• Overvoltage and Undervoltage Protections
• Small Converter Size - QFN package
The ISL6540A has an internal linear regulator or external linear
regulator drive options for applications with only a single supply
rail. The internal oscillator is adjustable from 250kHz to 2MHz.
The integrated voltage margining, programmable pre-biased
soft-start, differential remote sensing amplifier, and
programmable input voltage POR features enhance the
ISL6540A value.
• Oscillator Programmable from 250kHz to 2MHz
• Differential Remote Voltage Sensing with Unity Gain
• Programmable Soft-Start with Pre-Biased Load Capability
• Power-Good Indication with Programmable Delay
• EN Input with Voltage Monitoring Capability
• Pb-Free (RoHS Compliant)
Pinout
Applications
ISL6540A
(28 LD 5x5 QFN)
TOP VIEW
• Power Supply for some Microprocessors and GPUs
• Wide and Narrow Input Voltage Range Buck Regulators
• Point of Load Applications
• Low-Voltage and High Current Distributed Power Supplies
28 27 26 25 24 23 22
Ordering Information
VSEN+
1
2
3
4
5
6
7
21 BOOT
20 UGATE
19 PHASE
PART
NUMBER*
(Note)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
VSEN-
REFOUT
REFIN
SS
ISL6540ACRZ* ISL6540 ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5
ISL6540AIRZ* ISL6540 AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
ISL6540AIRZA* ISL6540 AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
GND
PGND
LGATE
PVCC
18
17
16
15
BOTTOM
SIDE PAD
OFS+
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
LINDRV
OFS-
These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
8
9
10 11 12 13 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006 - 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VCC
EN
LIN_DRV
VIN
POWER-ON
REFERENCE
= 0.591 V
RESET (POR)
REFIN
INTERNAL SERIES
LINEAR
EXTERNAL SERIES
LINEAR DRIVER
V
REF
HSOC
REFOUT
100µA
MAR_CTRL
OFS+
BOOT
SOFT-START
VOLTAGE
AND
SOURCE OCP
MARGINING
FAULT LOGIC
OFS-
UGATE
OTA
PWM
COMP
PHASE
SS
FB
GATE
CONTROL
LOGIC
EA
COMP
PVCC
LGATE
PGND
VCC
1.8V
OV/UV
COMP
OSCILLATOR
SOURCE
OCP
PGOOD
COMP
VSEN+
VSEN-
GND
GND
G = -1
G = 1
UNITY GAIN
DIFF AMP
100μA
SINKING OCP
PG_DLY
VMON
PG
LSOC
VFF
FS
ISL6540A
Typical Application I (Internal Linear Regulator with Remote Sense)
V
IN
L
IN
R
*
D
BOOT
CC
C
HFIN
C
BIN
C
F2
R
VIN
C
*
F1
Note: R *C <10µs
CC F1
*
VCC
PVCC
VIN
INTERNAL 5.6V BIAS
LINEAR REGULATOR
BOOT
HSOC
R
VFF
R
HSOC
VFF
C
C
VFF
C
F3
BOOT
C
HSOC
UGATE
PHASE
Q1
L
OUT
EN
V
VCC
OUT
REFIN
C
HFOUT
C
BOUT
REFOUT
PG
LGATE
PGND
LSOC
Q2
R
LSOC
C
PG_DLY
PG_DLY
FS
ISL6540A
10Ω
10Ω
C
LSOC
COMP
R
FS
C
2
C
R
3
3
Z
FB
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
R
VMON
R
MARG
V
FB
SENSE+
VSEN+
R
OFS-
OFS-
SS
C
SEN
R
OS
V
SENSE-
VSEN-
LINDRV
GND GND
C
SS
FN6288.5
October 7, 2008
3
ISL6540A
Typical Application II (External Linear Regulator without Remote Sense)
V
IN
L
IN
D
BOOT
C
HFIN
C
BIN
C
F2
R
DRV
R
*
CC
*
C
F1
C
R
LC
LC
Note: R *C <10µs
CC F1
*
VCC
PVCC
BOOT
R
VIN
LINDRV
R
HSOC
HSOC
C
F3
R
VIN
VFF
C
BOOT
C
HSOC
VFF
REFOUT
REFIN
C
VFF
UGATE
Q1
L
OUT
V
VCC
OUT
PHASE
LGATE
1kΩ
C
BOUT
EN
PG
C
Q2
HFOUT
PGND
LSOC
C
PG_DLY
R
LSOC
PG_DLY
FS
ISL6540A
C
LSOC
COMP
R
FS
C
2
Z
C
R
3
FB
3
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
R
VMON
OS
R
MARG
VCC
OFS-
SS
VSEN+
VSEN-
R
OFS-
R
vmon1
R
vmonOS
GND
GND
C
SS
FN6288.5
October 7, 2008
4
ISL6540A
Typical Application III (Dual Data Rate I or II)
VDDQ
1.8V or 2.5V
L
IN
5V
D
BOOT
C
HFIN
C
BIN
R
CC
*
C
R
F2
VFF
R
EN1
*
C
F1
C
ENABLE
VFF
Note: R *C <10µs
CC F1
*
VIN
VCC
PVCC
BOOT
VFF
EN
1kΩ
R
HSOC
HSOC
C
BOOT
C
R
F4
EN2
C
V
HSOC
TT
(DDR I)
(DDR II)
1.25V
0.9V
UGATE
Q1
L
OUT
1k
PHASE
LGATE
PGND
LSOC
REFIN
C
HFOUT
C
BOUT
REFOUT
15nF
DIMM
1k
Q2
PG
PG_DLY
FS
R
C
LSOC
PG_DLY
ISL6540A
C
R
LSOC
FS
COMP
C
2
Z
FB
C
R
3
3
C
1
MARCTRL
OFS+
R
2
Z
IN
R
1
FB
R
OFS+
R
VMON
R
MARG
FB
VSEN+
R
OFS-
OFS-
SS
C
SEN
VSEN-
LINDRV GND GND
C
SS
FN6288.5
October 7, 2008
5
ISL6540A
Absolute Maximum Ratings
Thermal Information
Input Voltage, VIN, VFF, HSOC . . . . . . . . . . . . . . . . -0.3V to +22.0V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Notes 1, 2)
θ
(°C/W)
θ
(°C/W)
5
JA
JC
QFN Package . . . . . . . . . . . . . . . . . 32
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
BOOT Voltage, V
BOOT to PHASE Voltage (V
. . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V
) . . . . . -0.3V to 7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)
BOOT
V
BOOT- PHASE
PHASE Voltage, V
. . . . . . . . . V
BOOT
- 7V to V
+ 0.3V
+ 0.3V
PHASE
BOOT
- 9V (<10ns) to V
BOOT
. . . . . . . . . . . . . . . . . . . . . .V
BOOT
UGATE Voltage . . . . . . . . . . . . . . . . V
Recommended Operating Conditions
- 0.3V (DC) to V
PHASE
- 5V (<20ns Pulse Width, 10µJ) to V
BOOT
BOOT
Input Voltage, VIN, VFF. . . . . . . . . . . . . . . . . . . . 3.3V to 20V ±10%
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V
Boot to Phase Voltage (Overcharged), V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
V
PHASE
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V
- V
. . . . . .<6V
BOOT
PHASE
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JA
2. θ , "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
JC
3. Limits should be considered typical and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLY CURRENTS
I
Nominal VCC Supply Current
Nominal PVCC Supply Current
Nominal VIN Supply Current
Shutdown VCC Supply Current
VIN = VCC = PVCC = 5V, Fs = 600kHz,
UGATE and LGATE Open
-
-
-
8
3
13
4
mA
mA
mA
VCC
I
VIN = VCC = PVCC = 5V; Fs = 600kHz,
UGATE and LGATE Open
PVCC
I
VIN = VCC = PVCC = 5V; Fs = 600kHz,
UGATE and LGATE Open
0.5
1
VIN
I
EN = 0V, VCC = PVCC = VIN = 5V
-
-
-
3
1
4
2
1
mA
mA
mA
VCC_S
I
Shutdown PVCC Supply Current EN = 0V, VCC = PVCC = VIN = 5V
Shutdown VIN Supply Current EN = 0V, VCC = PVCC = VIN = 5V
POWER-ON RESET
PVCC_S
I
0.5
VIN_S
POR
POR
POR
Rising VCC Threshold
Falling VCC Threshold
VCC Hysterisis
2.79
2.59
187
-
2.89
2.69
250
V
V
VCC_R
-
VCC_F
215
mV
V
VCC_H
POR
POR
POR
Rising PVCC Threshold
Falling PVCC Threshold
PVCC Hysterisis
2.79
2.59
193
-
2.91
2.70
250
PVCC_R
PVCC_F
PVCC_H
-
215
-
V
mV
V
POR
POR
POR
Rising VFF Threshold
Falling VFF Threshold
VFF Hysterisis
1.48
1.35
127
1.54
1.41
146
VFF_R
VFF_F
VFF_H
-
V
137
mV
ENABLE
V
Input Reference Voltage
Hysteresis Source Current
Maximum Input Voltage
0.485
7.5
-
0.500
10
0.515
11.5
-
V
µA
V
EN_REF
I
EN_HYS
V
VCC + 0.3
EN
FN6288.5
October 7, 2008
6
ISL6540A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
OSC
Nominal Maximum Frequency
Nominal Minimum Frequency
Total Variation
(Note 3)
(Note 3)
-
2000
250
-
kHz
kHz
%
FMAX
OSC
-
-
FMIN
ΔOSC
FS = 250kHz to 2MHz, VFF = 3.3V to 20V
-17
-
+17
ΔV
Ramp Amplitude
-
-
-
0.16*VFF
1.0
-
-
-
V
OSC
P-P
V
V
Ramp Bottom
OSC_MIN
VFF
Minimum Usable VFF Voltage
VCC = 5V
3.3
V
PWM
D
Maximum Duty Cycle
Minimum Duty Cycle
Leading and Trailing-edge Modulation
Leading and Trailing-edge Modulation
-
-
100
0
-
-
%
%
MAX
D
MIN
REFERENCE TRACKING
V
Input Voltage Range
VCC = 5V
0.068
-
0
VCC - 1.8V
V
REFIN
V
External Reference Offset
Maximum Drive Current
Output Voltage Range
REFIN = 0.6V
-1.8
2.2
mV
mA
V
REFIN_OS
I
C = 1µF, VCC = 5V, REFOUT = 1.25V
-
19
-
-
REFOUT
L
V
C = 1µF
0.01
VCC - 1.8V
REFOUT
L
V
Maximum Output Voltage Offset C = 1µF REFOUT = 1.25V
-6
-
11
mV
µF
V
REFOUT_OS
REFOUT_MIN
L
C
Minimum Load Capacitance
Input Disable Voltage
REFOUT = 1.25V
VCC = 5V
-
1.0
-
-
V
VCC - 0.6
VCC - 0.58
REFIN_DIS
REFERENCE
V
Reference Voltage
T
= 0°C to +70°C
= -40°C to +85°C
= 0°C to +70°C
T = -40°C to +85°C
A
0.587
0.585
-0.68
-1.0
0.591
0.595
0.597
0.68
1.0
V
V
REF_COM
A
V
T
0.591
REF_IND
A
V
System Accuracy
T
-
-
%
%
SYS_COM
A
V
SYS_IND
ERROR AMPLIFIER
DC Gain
R = 10k, C = 100p, at COMP Pin
-
-
-
88
15
6
-
-
-
dB
L
L
UGBW
SR
Unity Gain-Bandwidth
Slew Rate
R = 10k, C = 100p, at COMP Pin
MHz
V/µs
L
L
R = 10k, C = 100p, at COMP Pin
L
L
DIFFERENTIAL AMPLIFIER
UG
UGBW
SR
DC Gain
Standard Instrumentation Amplifier
COMP = 10pF
-
0
-
dB
MHz
V/µs
mV
µA
V
Unity Gain Bandwidth
Slew Rate
-
20
-
-
10
-
V
Offset
-1.9
0
6
1.9
OFFSET_IND
I
Negative Input Source Current
Input Common Mode Range Max
Input Common Mode Range Min
VSEN- Disable Voltage
-
-
-
-
-
-
-
-
VSEN-
VCC - 1.8
-0.2
V
V
VCC
V
VSEN_DIS
INTERNAL LINEAR REGULATOR
I
Maximum Current
-
-
200
2
-
mA
Ω
VIN
R
Saturated Equivalent Impedance
Linear Regulator Voltage
V
V
= 3.3V, Load = 100mA
= 20V, Load = 100mA
3.9
5.71
LIN
IN
IN
PVCC
5.30
5.50
V
FN6288.5
October 7, 2008
7
ISL6540A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
SYMBOL
VIN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum VIN DV/DT
V
= 0 V to V step, PVCC < 2.0V at V
IN
-
1
-
V/µs
DV/DT_Max
IN
IN
application; V > 6.5V
IN
V
= 2.0 V to V step, 2.0V < PVCC at V
IN
-
0.05
-
V/µs
IN
IN
application; V > 6.5V
IN
EXTERNAL LINEAR REGULATOR
LIN_DRV
Maximum Sinking Drive Current LIN_DRV = VIN = 20V
LIN_DRV = VIN = 3.3V
1.30
1.67
4.17
3.88
5.30
4.67
mA
mA
OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA)
DC Gain
C
C
= 0.1µF, at SS Pin
= 0.1µF, at SS Pin
-
88
37
-
dB
µA
SS
SS
Drive Capability
30
44
GATE DRIVERS
R
Ugate Source Resistance
Ugate Source Saturation Current
Ugate Sink Resistance
500mA Source Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
-
-
-
-
-
-
-
-
1.0
2.0
1.0
2.0
1.0
2.0
0.4
4.0
-
-
-
-
-
-
-
-
Ω
A
Ω
A
Ω
A
Ω
A
UGATE
I
V
UGATE
UGATE-PHASE
500mA Sink Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
R
UGATE
I
Ugate Sink Saturation Current
Lgate Source Resistance
Lgate Source Saturation Current
Lgate Sink Resistance
V
UGATE
UGATE-PHASE
500mA Source Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
R
LGATE
I
V
LGATE
LGATE
500mA Sink Current, PVCC = 5.0V
= 2.5V, PVCC = 5.0V
R
LGATE
I
Lgate Sink Saturation Current
V
LGATE
LGATE
OVERCURRENT PROTECTION (OCP)
I
Low Side OCP (LSOC) Current
Source
LSOC = 0V to VCC - 1.0V, T = 0°C to +70°C
86
84
-
100
100
±2
107
109
-
µA
µA
mV
µA
µA
µA
mV
LSOC
A
LSOC = 0V to VCC - 1.0V, T = -40°C to +85°C
A
I
LSOC Maximum Offset Error
VCC = 2.9V and 5.6V T < 10µs
SAMPLE
LSOC_OFSET
I
High Side OCP (HSOC) Current HSOC = 0.8V to 22V T = 0°C to +70°C
A
Source
91
89
84
-
100
100
-
106
107
107
-
HSOC
HSOC = 0.8V to 22V T = -40°C to +85°C
A
I
HSOC = 0.3V to 0.8V
HSOC_LOW
I
HSOC Maximum Offset Error
VCC = 2.9V and 5.5V T
< 10µs
SAMPLE
±2
HSOC_OFSET
MARGINING CONTROL
V
V
N
Minimum Margining Voltage of
Internal Reference
R
= 10kΩ, R
= 6.01kΩ,
= 6.01kΩ,
-187
185
-197
197
-209
208
mV
mV
MARG
MARG
MARG
MARG
MAR_CRTL = 0V
OFS-
Maximum Margining Voltage of
Internal Reference
R
= 10kΩ, R
MARG OFS+
MAR_CRTL = VCC
Margining Transfer Ratio
Positive Margining Threshold
Negative Margining Threshold
Tri-state Input Level
N
= (V -V )/V
OFS- OFS+ MARG
4.84
1.51
0.75
1.21
5
5.22
2.02
1.05
1.40
SDR
V
MARG
1.8
MAR_CTRL
MAR_CTRL
MAR_CTRL
0.9
V
Disable Mode
1.325
V
POWER GOOD MONITOR
V
Undervoltage Rising Trip Point
Undervoltage Falling Trip Point
Overvoltage Rising Trip Point
Overvoltage Falling Trip Point
PGOOD Delay
-7%
-13%
13%
7%
-
-9%
-15%
15%
9%
-11%
-17%
17%
11%
-
V
UVR
SS
V
V
V
UVF
SS
V
OVR
SS
V
V
OVF
SS
T
I
C
= 0.1µF
7.1
ms
µA
PG_DLY
PG_DLY
PGOOD Delay Source Current
17
21
24
PG_DLY
FN6288.5
October 7, 2008
8
ISL6540A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parts are 100% tested at +25°C. Temperature
limits established by characterization and are not production tested. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
1.45
-
TYP
MAX
1.52
0.150
-
UNITS
V
PGOOD Delay Threshold Voltage
PGOOD Low Output Voltage
Maximum Sinking Current
Maximum Open Drain Voltage
1.49
V
V
PG_DLY
I
I
= 5mA
-
-
PG_LOW
PGOOD
I
V
= 0.8V
23
-
mA
V
PG_MAX
PGOOD
V
VCC = 3.3V
6
-
PG_MAX
and OFS- is divided by 5 and imposed on the system
reference. The maximum designed offset of 1V between
OFS+ and OFS- pins translates to a 200mV offset.
Functional Pin Description
VSEN+ (Pin 1)
This pin provides differential remote sense for the ISL6540A.
It is the positive input of a standard instrumentation amplifier
topology with unity gain, and should connect to the positive
rail of the load/processor. The voltage at this pin should be
set equal to the internal system reference voltage (0.591V
typical).
OFS- (Pin 7)
This pin sets the negative margining offset voltage. Resistors
should be connected to GND (R
from this pin. With MAR_CTRL logic low, the internal 0.591V
reference is developed at the OFS- pin across resistor
) and OFS+ (R )
OFS-
MARG
R
R
. The voltage on OFS- is driven from OFS+ through
OFS-
VSEN- (Pin 2)
. The resulting voltage differential between OFS+
MARG
This pin provides differential remote sense for the regulator.
It is the negative input of the instrumentation amplifier, and
should connect to the negative rail of the load/processor.
Typically 6µA is sourced from this pin. The output of the
remote sense buffer is disabled (High Impedance) by pulling
VSEN- to VCC.
and OFS- is divided by 5 and imposed on the system
reference. The maximum designed offset of -1V between
OFS+ and OFS- pins translates to a -200mV offset of the
system reference.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL6540A analog circuitry.
The pin should be connected to a 2.9V to 5.5V bias through
an RC filter from PVCC to prevent noise injection into the
analog circuitry. A 0.1µF capacitor is sufficient for decoupling
of the VCC pin. The time constant of the RC filter should be
no more than 10µs. This pin can be powered off the internal
or external linear regulator options.
REFOUT (Pin 3)
This pin connects to the unmargined system reference
through an internal buffer. It has a 19mA drive capability with
an output common mode range of GND to VCC. The
REFOUT buffer requires at least 1µF of capacitive loading to
be stable. This pin should not be left floating.
REFIN (Pin 4)
MARCTRL (Pin 9)
When the external reference pin (REFIN) is NOT within
~1.8V of VCC, the REFIN pin is used as the system
reference instead of the internal 0.591V reference. The
recommended REFIN input voltage range is ~68mV to
VCC - 1.8V.
The MARCTRL pin controls margining function, a logic high
enables positive margining, a logic low sets negative
margining, a high impedance disables margining.
PG_DLY (Pin 10)
Provides the ability to delay the output of the PGOOD
assertion by connecting a capacitor from this pin to GND. A
0.1µF capacitor produces approximately a 7ms delay.
SS (Pin 5)
This pin provides soft-start functionality for the ISL6540A. A
capacitor connected to ground along with the internal 37µA
Operational Transconductance Amplifier (OTA), sets the
soft-start interval of the converter. This pin is directly
connected to the non-inverting input of the error amplifier. To
prevent noise injection into the error amplifier the SS
capacitor should be located next to the SS and GND pins.
PGOOD (Pin 11)
Provides an open drain Power-Good signal when the output
is within 9% of nominal output regulation point with 6%
hysteresis (15%/9%), and after soft-start is complete.
PGOOD monitors the VMON pin.
EN (Pin 12)
OFS+ (Pin 6)
This pin is compared with an internal 0.50V reference and
enables the soft-start cycle. This pin also can be used for
voltage monitoring. A 10µA current source to GND is active
while the part is disabled, and is inactive when the part is
enabled. This provides functionality for programmable
hysteresis when the EN pin is used for voltage monitoring. In
many applications, this pin is susceptible to excessive
This pin sets the positive margining offset voltage. Resistors
should be connected to GND (R
) and OFS- (R
)
OFS+
MARG
from this pin. With MAR_CTRL logic low, the internal 0.591V
reference is developed at the OFS+ pin across resistor
R
R
. The voltage on OFS+ is driven from OFS- through
OFS+
. The resulting voltage differential between OFS+
MARG
FN6288.5
October 7, 2008
9
ISL6540A
transient voltages that could result in electrical overstress
(EOS) damage. It is recommended that a 1kΩ resistor be
placed in series with this pin.
UGATE (Pin 20)
This pin provides the drive for the high side MOSFET and
should be connected to its gate.
VFF (Pin 13)
BOOT (Pin 21)
The voltage at this pin is used for input voltage feed-forward
compensation and sets the internal oscillator ramp
peak-to-peak amplitude at 0.16*VFF. An external RC filter
may be required at this pin in noisy input environments. The
minimum recommended VFF voltage is 2.97V.
This pin provides the bootstrap bias for the high side driver.
The absolute maximum voltage differential between BOOT
and PHASE is 6.0V (including the voltage added due to the
overcharging of the bootstrap capacitor); its operational
voltage range is 2.5V to 5.5V with respect to PHASE. Should
overcharging of the BOOT capacitor occur, it is
VIN (Pin 14, Internal Linear Regulator Input)
recommended that a 2.2Ω resistor be placed in series with
the bootstrap diode.
This pin should be tied directly to the input rail when using
the internal or external linear regulator options. It provides
power to the External/Internal linear drive circuitry. When
used with an external 3.3V to 5V supply, this pin should be
tied directly to PVCC.
HSOC (Pin 22)
The high side sourcing current limit is set by connecting this
pin with a resistor and capacitor to the drain of the high side
MOSFET. A 100µA current source develops a voltage
across the resistor which is then compared with the voltage
developed across the high side MOSFET. An initial ~120ns
blanking period is used to eliminate sampling error due to
the switching noise before the current is measured.
LIN_DRV (Pin 15, External Linear Regulator Drive)
This pin allows the use of an external pass element to power
the IC for input voltages above 5.0V. It should be connected
to GND when using an external 5V supply or the internal
linear regulator. When using the external linear regulator
option, this pin should be connected to the gate of a PMOS
pass element, a pull-up resistor must be connected between
the PMOS device’s gate and source for proper operation.
LSOC (Pin 23)
The low side source and sinking current limit is set by
placing a resistor (R
) and capacitor between this pin
LSOC
and PGND. A 100µA current source develops a voltage
across R which is then compared with the voltage
PVCC (Pin 16, Driver Bias Voltage)
LSOC
This pin is the output of the internal series linear regulator. It
also provides the bias for both low side and high side
MOSFET drivers. The maximum voltage differential between
PVCC and PGND is 6V. Its recommended operational
voltage range is 2.9V to 5.5V. At minimum, a 10µF capacitor
is required for decoupling PVCC to PGND. For proper
operation the PVCC capacitor should be located next to the
PVCC and the PGND pins and should be connected to these
pins with dedicated traces.
developed across the low side MOSFET when on. The
sinking current limit is set at 1x of the nominal sourcing limit
in ISL6540A. An initial ~120ns blanking period is used to
eliminate the sampling error due to switching noise before
the current is measured.
FS (Pin 24)
This pin provides oscillator switching frequency adjustment
by placing a resistor (R ) from this pin to GND.
FS
LGATE (Pin 17)
COMP (Pin 25)
This pin provides the drive for the low side MOSFET and
should be connected to its gate.
This pin is the error amplifier output. It should be connected
to the FB pin through the desired compensation network.
PGND (Pin 18, Power Ground)
FB (Pin 26)
This pin connects to the low side MOSFET's source and
provides the ground return path for the lower MOSFET driver
and internal power circuitries. In addition, PGND is the return
This pin is the inverting input of the error amplifier and has a
maximum usable voltage of VCC - 1.8V. When using the
internal differential remote sense functionality, this pin
should be connected to VMON by a standard feedback
network. In the event the remote sense buffer is disabled,
the VMON pin should be connected to VOUT by a resistor
divider along with FB’s compensation network.
path for the low side MOSFET’s r
circuit.
current sensing
DS(ON)
PHASE (Pin 19)
This pin connects to the source of the high side MOSFET
and the drain of the low side MOSFET. This pin represents
the return path for the high side gate driver. During normal
switching, this pin is used for high side and low side current
sensing.
GND (Pin 27, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
VMON (Pin 28)
This pin is the output of the differential remote sense
instrumentation amplifier. It is connected internally to the
FN6288.5
October 7, 2008
10
ISL6540A
OV/UV/PGOOD comparators. The VMON pin should be
input rails greater than a 3.3V and require a specific input rail
POR and Hysteresis levels for better undervoltage
protection. Consider for a 12V application choosing
connected to the FB pin by a standard feedback network. In
the event of the remote sense buffer is disabled, the VMON
pin should be connected to VOUT by a resistor divider along
with FB’s compensation network. An RC filter should be
used if VMON is to be connected directly to FB instead of to
VOUT through a separate resistor divider network.
R
= 97.6kΩ and R
= 5.76kΩ there by setting the
UP
rising threshold (V
DOWN
) to ~10V and the falling threshold
EN_RTH
(V
) to ~9V, for ~1V of hysteresis (V
). Care
EN_FTH EN_HYS
should be taken to prevent the voltage at the EN pin from
exceeding VCC when using the programmable UVLO
functionality.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. This pin should not be left floating.
Soft-Start
The POR function activates the internal 37µA OTA which
Functional Description
begins charging the external capacitor (C ) on the SS pin to a
SS
target voltage of VCC. The ISL6540A’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
Initialization
The ISL6540A automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC, VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.50V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
voltage (V
), and the SS pin is ramped up or down
REF_MARG
accordingly. This method reduces start-up surge currents due
to a pre-charged output by inhibiting regulator switching until
the control loop enters its linear region. By ramping the positive
HIGH = ABOVE POR; LOW = BELOW POR
input of the error amplifier to VCC and then to V
, it is
VCC POR
VFF POR
REF_MARG
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the error amplifier,
noise on this pin should be kept to a minimum through careful
routing and part placement. To prevent noise injection into the
error amplifier the SS capacitor should be located within 150
mils of the SS and GND pins. Soft-start is declared done when
the drivers have been enabled and the SS pin is within ±3mV of
AND
SOFT-START
PVCC POR
EN POR
FIGURE 1. SOFT-START INITIALIZATION LOGIC
VIN
R
UP
V
.
REF_MARG
VMON
V
EN_REF
R
EN
1k
+15%
Ω
SYS_ENABLE
EN
+9%
V
REF_MARG
R
DOWN
I
=10µA
EN_HYS
-9%
-15%
V
EN_HYS
-------------------------
R
R
=
– 1kΩ
UP
I
EN_HYS
GOOD
GOOD
(R
+ 1kΩ) • V
EN_REF
UP
------------------------------------------------------------------
=
DOWN
UV
V
– V
OV
UV
EN_FTH
EN_REF
V
= V
EN_RTH
– V
EN_FTH
EN_HYS
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
FIGURE 2. ENABLE POR CIRCUIT
With all input supplies above their POR thresholds, driving
the EN pin above 0.50V initiates a soft-start cycle. In addition
to normal TTL logic, the enable pin can be used as a voltage
monitor with programmable hysteresis through the use of the
internal 10µA sink current and an external resistor divider.
This feature is especially designed for applications that have
1.49V
21μA
(EQ. 1)
---------------
⋅
PG_DLY
T
= C
PG_DLY
FN6288.5
October 7, 2008
11
ISL6540A
The high side sourcing current limit is set by connecting the
HSOC pin with a resistor (R ) and a capacitor to the drain
Power-Good
HSOC
The power-good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown in Figure 3. Additionally,
power-good will not be asserted until after the completion of
the soft-start cycle. A 0.1µF capacitor at the PG_DLY pin will
add an additional ~7ms delay to the assertion of power-good.
PG_DLY does not delay the de-assertion of power-good.
of the high side MOSEFT. A 100µA current source develops a
voltage across the resistor which is then compared with the
voltage developed across the high side MOSFET while on.
When the voltage drop across the MOSFET exceeds the
voltage drop across the resistor, a sourcing OCP event
occurs. A 1000pF or greater filter capacitor should be used in
parallel with R
to prevent on-chip parasitics from
HSOC
Under and Overvoltage Protection
impacting the accuracy of the OCP measurement and to
smooth the voltage across R in the presence of
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VMON pin with the
reference that tracks with the margining circuitry to prevent
accidental tripping. UV and OV functionality is not enabled
until the end of soft-start.
HSOC
switching noise on the input bus.
Simple Low Side OCP Equation
(EQ. 2)
I
• r
OC_SOURCE
DS(ON)LowSide
--------------------------------------------------------------------------------------
=
R
LSOC
100μA
An OV event is detected asynchronously and causes the
high side MOSFET to turn off, the low side MOSFET to turn
on (effectively a 0% duty cycle), and PGOOD to pull low. The
regulator stays in this state and overrides sourcing and
sinking OCP protections until the OV event is cleared.
Detailed Low Side OCP Equations
ΔI
2
⎛
⎝
⎞
⎠
----
I
+
• r
OC_SOURCE
DS(ON),L
--------------------------------------------------------------------------------------
R
=
LSOC
V
I
• N
L
LSOC
An UV event is detected asynchronously and results in the
PGOOD pulling low.
- V
V
OUT
V
IN
IN
OUT
L
------------------------------- ---------------
ΔI =
•
(EQ. 3)
F
S
Overcurrent Protection
I
• N • R
LSOC
The ISL6540A monitors both the high side MOSFET and low
side MOSFET for overcurrent events. Dual sensing allows the
ISL6540A to detect overcurrent faults at the very low and very
high duty cycles that can result from the ISL6540A’s wide input
range. The OCP function is enabled with the drivers at startup
and detects the peak current during each sensing period. A
resistor and a capacitor between the LSOC pin and GND set
the low side source and sinking current limits. A 100µA current
source develops a voltage across the resistor which is then
compared with the voltage developed across the low side
MOSFET at conduction mode. The measurement comparator
uses offset correcting circuitry to provide precise current
measurements with roughly ±2mV of offset error. An ~120ns
blanking period, implemented on the upper and lower MOSFET
current sensing circuitries, is used to reduce the current
sampling error due to the leading-edge switching noise. An
additional 120ns low pass filter is used to further reduce
measurement error due to noise. In sourcing current
ΔI
2
LSOC
L
------------------------------------------------------- ----
I
=
–
OC_SINK
r
DS(ON),L
N
= Number of low side MOSFETs
L
Sourcing OCP faults cause the regulator to disable (Ugate and
Lgate drives pulled low, PGOOD pulled low, soft-start capacitor
discharged) itself for a fixed period of time after which a normal
soft-start sequence is initiated. The period of time the regulator
waits before attempting a soft-start sequence is set by three
charge and discharge cycles of the soft-start capacitor.
Simple High Side OCP Equation
I
• r
OC_SOURCE
DS(ON)HighSide
(EQ. 4)
----------------------------------------------------------------------------------------
=
R
HSOC
100μA
Detailed High Side OCP Equation
applications, the LSOC voltage is inverted and compared with
the voltage across the MOSFET while on. When this voltage
exceeds the LSOC set voltage, a sourcing OCP fault is
triggered. A 1000pF or greater filter capacitor should be used in
ΔI
2
⎛
⎝
⎞
⎠
----
I
+
• r
OC_SOURCE
DS(ON),U
---------------------------------------------------------------------------------------
(EQ. 5)
R
=
HSOC
I
• N
U
HSOC
parallel with R
impacting the accuracy of the OCP measurement.
to prevent on-chip parasitics from
N
= Number of high side MOSFETs
LSOC
U
Sinking OCP faults cause the low side MOSFET drive to be
disabled, effectively operating the ISL6540A in a
The ISL6540A’s sinking current limit is set to the same
voltage as its sourcing limit. In sinking applications, when the
voltage across the MOSFET is greater than the voltage
non-synchronous manner. The fault is maintained for three
clock cycles at which point it is cleared and normal operation
is restored. OVP fault implementation overrides sourcing
and sinking OCP events, immediately turning on the low side
MOSFET and turning off the high side MOSFET. The OC trip
developed across the resistor (R
) a sinking OCP event
LSOC
is triggered. To avoid non-synchronous operation at light
load, the peak-to-peak output inductor ripple current should
not be greater than twice of the sinking current limit.
FN6288.5
October 7, 2008
12
ISL6540A
point varies mainly due to the MOSFETs r
variations
DS(ON)
and system noise. To avoid overcurrent tripping in the
normal operating load range, find the R and/or R
80
60
HSOC
resistor from the previous detailed equations with:
LSOC
40
30
1. Maximum r
2. Minimum I
at the highest junction temperature.
DS(ON)
and/or I
from specification table on
HSOC
LSOC
page 8.
3. Determine the overcurrent trip point greater than the
maximum output continuous current at maximum
inductor ripple current.
20
10
Frequency Programming
By tying a resistor to GND from FS pin, the switching
frequency can be set between 250kHz and 2MHz.
7
5
200k
300k
400k
600k
800k 1M
2M
Oscillator/VFF
FREQUENCY (Hz)
The Oscillator is a triangle waveform, providing for leading
and falling edge modulation. The bottom of the oscillator
waveform is set at 1.0V. The ramp's peak-to-peak amplitude
is determined from the voltage on the VFF (Voltage
Feed-Forward) pin. See Equation 6:
FIGURE 4. R RESISTANCE vs FREQUENCY
FS
10
–0.973
(EQ. 7)
(R TO GND)
T
Fs[Hz] ≈ 1.178×10 • R [Ω]
T
(EQ. 6)
ΔVosc = 0.16 • VFF
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2Ω internal series
linear regulator, which is internally compensated. The
external series linear regulator option should be used for
applications requiring pass elements of less than 2Ω. When
using the internal regulator, the LIN_DRV pin should be
connected directly to GND. The PVCC and VIN pins should
have a bypass capacitor (at least 10µF on PVCC is required)
connected to PGND. For proper operation the PVCC
capacitor must be within 150 mils of the PVCC and the
PGND pins, and be connected to these pins with dedicated
traces. The internal series linear regulator’s input (VIN) can
range between 3.3V to 20V ±10%. The internal linear
regulator is to provide power for both the internal MOSFET
drivers through the PVCC pin and the analog circuitry
through the VCC pin. The VCC pin should be connected to
the PVCC pin with an RC filter to prevent high frequency
driver switching noise from entering the analog circuitry.
When VIN drops below 5.5V, the pass element will saturate;
PVCC will track VIN, minus the dropout of the linear
An internal RC filter of 233kΩ and 2pF (341kHz) provides
filtering of the VFF voltage. An external RC filter may be
required to augment this filter in the event that it is
insufficient to prevent noise injection or control loop
interactions. Voltages below 2.9V on the VFF pin may result
in undesirable operation due to extremely small peak to
peak oscillator waveforms. The oscillator waveform should
not exceed VCC -1.0V. For high VFF voltages the
internal/external 5.5V linear regulator should be used. 5.5V
on VCC provides sufficient headroom for 100% duty cycle
operation when using the maximum VFF voltage of 22V. In
the event of sustained 100% duty cycle operation, defined as
32-clock cycles where no LG pulse is detected, LG will be
pulsed on to refresh the design’s bootstrap capacitor.
regulator: PVCC = VIN-2xI
. When used with an external
VIN
5V supply, the VIN pin should be tied directly to PVCC.
At start-up (PVCC = 0V and VIN = 0V) the DV/DT on VIN
should be kept below 1V/µs to prevent electrical overstress
on PVCC. Care should be taken to keep the DV/DT on VIN
below 0.05V/µs if the initial steady state voltage on PVCC is
above 2.0V, as electrical overstress on PVCC is otherwise
possible.
External Series Linear Regulator
The LIN_DRV pin provides sinking drive capability for an
external pass element linear regulator controller. The
external linear options are especially useful when the
FN6288.5
October 7, 2008
13
ISL6540A
internal linear dropout is too large for a given application.
When using the external linear regulator option, the
example: V
Equation 8:
< VCC - 1.8V, as shown in
REF_MARG
LIN_DRV pin should be connected to the gate of a PMOS
device, and a resistor should be connected between its gate
and source. A resistor and a capacitor should be connected
from gate-to-source to compensate the control loop. A PNP
device can be used instead of a PMOS device in which case
the LIN_DRV pin should be connected to the base of the
PNP pass element. The sinking capability of the LIN_DRV
pin is 5mA, and should not be exceeded if using an external
resistor for a PMOS device. The designer should take care
in designing a stable system when using external pass
elements. The VCC pin should be connected to the PVCC
pin with an RC filter to prevent high frequency driver
switching noise from entering the analog circuitry.
V
R
MARG
REF
5
-------------- --------------------
V
=
•
MARG_UP
R
OFS+
(EQ. 8)
V
R
REF
MARG
-------------- --------------------
V
=
•
MARG_DOWN
5
R
OFS-
An alternative calculation provides for a desired percentage
change in the output voltage when using the internal 0.591V
reference:
R
R
MARG
MARG
--------------------
V
= 20 •
--------------------
V
= 20 •
pct_DOWN
PCT_UP
R
R
OFS-
OFS+
(EQ. 9)
High Speed MOSFET Gate Driver
When not used in a design OFS+, OFS-, and MARCTRL
should be left floating. To prevent damage to the part, OFS+
and OFS- should not be tied to VCC or PVCC.
The integrated driver has similar drive capability and
features to Intersil's ISL6605 stand alone gate driver. The
PWM tri-state feature helps prevent a negative transient on
the output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from
reversed-output-voltage damage. See the ISL6605
datasheet for specification parameters that are not defined in
the current ISL6540A “Electrical Specifications” table on
page 6.
Reference Output Buffer
The internal buffer’s output tracks the unmargined system
reference. It has a 19mA drive capability, with maximum and
minimum output voltage capabilities of VCC and GND
respectively. Its capacitive loading can range from 1µF to
above 17.6µF, which is designed for 1 to 8 DIMM systems in
DDR (Dual Data Rate) applications. 1µF of capacitance
should always be present on REFOUT. It is not designed to
drive a resistive load and any such load added to the system
should be kept above 300kΩ total impedance. The
A 1Ω to 2Ω resistor is recommended to be in series with the
bootstrap diode when using VCCs above 5.0V to prevent the
bootstrap capacitor from overcharging due to the negative
swing of the trailing edge of the phase node.
Reference Output Buffer should not be left floating.
Reference Input
Margining Control
The REFIN pin allows the user to bypass the internal 0.591V
reference with an external reference. Asynchronously, if
REFIN is NOT within ~1.8V of VCC, the external reference
pin is used as the control reference instead of the internal
0.591V reference. The minimum usable REFIN voltage is
When the MAR_CTRL is pulled high or low, the positive or
negative margining functionality is respectively enabled.
When MAR_CTRL is left floating, the function is disabled.
Upon UP margining, an internal buffer drives the OFS- pin
from VCC to maintain OFS+ at 0.591V. The resistor divider,
~68mV, while the maximum is VCC - 1.8V - V
present).
(if
MARG
R
and R
, causes the voltage at OFS- to be
MARG
OFS+
increased. Similarly, upon DOWN margining, an internal
buffer drives the OFS+ pin from VCC to maintain OFS- at
VCC
0.591V. The resistor divider, R
and R
, causes the
OFS-
REFERENCE
ISL6540A
STATE
MACHINE
MARG
V
= 0.591V
REF
voltage at OFS+ to be increased. In both modes, the voltage
difference between OFS+ and OFS- is then sensed with an
instrumentation amplifier and is converted to the desired
margining voltage by a 5:1 ratio. The maximum designed
margining range of the ISL6540A is ±200mV, this sets the
REFIN
800mV
MINIMUM value of R
or R at approximately 5.9k
OFS+
OFS-
REFOUT
for an R
of 10k for a MAXIMUM of 1V across R .
MARG
MARG
The OFS pins are completely independent and can be set to
different margining levels. The maximum usable reference
voltage for the ISL6540A is VCC-1.8V, and should not be
exceeded when using the margining functionality, for
V
REF_MARG
MARGINING
BLOCK
OTA
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
FN6288.5
October 7, 2008
14
ISL6540A
VSENSE-
(REMOTE)
VSENSE+
(REMOTE)
10Ω
10Ω
VOUT (LOCAL)
GND (LOCAL)
R
FB
R
OS
C
SEN
Z
Z
IN
FB
VSEN+
VCC
VSEN-
VMON
COMP
FB
OV/UV
COMP
ERROR AMP
1.8V
GAIN=1
V
SS
FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION
VMON is to be connected directly to FB instead of to VOUT
Internal Reference and System Accuracy
through a separate resistor divider network. This filter
prevents noise injection from disturbing the OV/UV/PGOOD
comparators on VMON. VMON may also be connected to
the SS pin, which completely bypasses the OV/UV/PGOOD
functionality.
The internal reference is trimmed to 0.591V. The total DC
system accuracy of the system is within ±0.68% over
commercial temperature range, and ±1.00% over industrial
temperature range. System accuracy includes error amplifier
offset, OTA error, and bandgap error. Differential remote
sense offset error is not included. As a result, if the
differential remote sense is used, then an extra 1.9mV of
offset error enters the system. The use of REFIN may add
up to 2.2mV of additional offset error.
Application Guidelines
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET is carrying the output inductor current.
During the turnoff, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide circuit traces minimize the magnitude of
voltage spikes.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an
instrumentation amplifier with unity gain. The offset is
trimmed to 1.5mV for high system accuracy. As with any
instrumentation amplifier, typically 6µA are sourced from the
VSEN- pin. The output of the remote sense buffer is
connected directly to the internal OV/UV comparator. As a
result, a resistor divider should be placed on the input of the
buffer for proper regulation, as shown in Figure 6. The
VMON pin should be connected to the FB pin by a standard
feed-back network. A small capacitor, C
in Figure 6, can
is chosen so the
SEN
be added to filter out noise, typically C
SEN
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator.
As some applications will not use the differential remote
sense, the output of the remote sense buffer can be disabled
(high impedance) by pulling VSEN- within 1.8V of VCC. As
the VMON pin is connected internally to the OV/UV/PGOOD
comparator, an external resistor divider must then be
connected to VMON to provide correct voltage information
for the OV/UV comparator. An RC filter should be used if
There are two sets of critical components in a DC/DC
converter using a ISL6540A controller. The power
components are the most critical because they switch large
currents and have the potential to create large voltage
spikes, as well as induce noise into sensitive, high
impedance adjacent nodes. Next are small signal
FN6288.5
October 7, 2008
15
ISL6540A
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
input power and output power nodes. Use copper-filled
polygons on the top and bottom circuit layers for large
current-carrying circuit nodes. Use the remaining printed
circuit layers for small signal wiring.
Equally important are the connections of the internal gate
drives (UGATE, LGATE, PHASE, PGND, BOOT): since they
drive the power train MOSFETs using short, high current
pulses, it is important to size them accordingly and reduce
their overall impedance. While not always esthetically
pleasing, straightest connections encircling the least area
result in the lowest parasitic inductance build-up, and,
consequentially, are the better choice.
Size the trace interconnects commensurate with the signals
they are carrying. Use narrow (0.004” to 0.008”) and short
traces for the high-impedance, small-signal connections, such
as the feedback, compensation, soft-start, frequency set,
reference input, offset, etc. The wiring traces from the IC to
the MOSFETs’ gates and sources should be wide (0.02” to
0.05”) and short, encircling the smallest area possible.
The power train components should be placed first. Locate
the input capacitors close to the power switches. Minimize
the length of the connections between the input capacitors,
The metal pad of the ISL6540A’s package should be
connected to the ground plane via 6 to 9 small vias evenly
placed in the bottom pad’s footprint. The GND and PGND
pins should be connected to this bottom pad to find a
convenient, low inductance path to the rest of the circuitry.
This recommended connection provides not only an
electrically low impedance path, but a low thermal path as
well, helping with the heat dissipation taking place in the
part.
C
, especially the high frequency decoupling, and the
IN
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate all
the high-frequency decoupling capacitors (ceramics) as
close as practicable to their decoupling target, making use of
the shortest connection paths to any internal planes, such as
vias to GND immediately next, or even onto the capacitor’s
grounded solder pad.
Compensating the Converter
The critical small signal components include the bypass
capacitors for VIN, VCC and PVCC. Locate the bypass
The ISL6540A single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 7).
capacitors, C , close to the device. It is especially
BP
important to locate the components associated with the
feedback circuit close to their respective controller pins,
since they belong to a high-impedance circuit loop, sensitive
to EMI pick-up. Place all the other highlighted components
close to the respective pins of the ISL6540A.
C
2
C
A multi-layer printed circuit board is recommended. Figure 8
shows the connections of the critical components of the
R
1
2
COMP
FB
converter. Note that capacitors C
and C could each
xxIN
xxOUT
C
3
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, to a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the PHASE island as
small as practicable, while still allowing for proper heat-sinking
of the lower MOSFET. The power plane should support the
R
1
ISL6540A
R
3
VMON
FIGURE 7. COMPENSATION CONFIGURATION FOR
ISL6540A WHEN USING DIFFERENTIAL REMOTE
SENSE
FN6288.5
October 7, 2008
16
ISL6540A
+3.3V TO +20V
L
IN
R
CC
(C
)
C
HFIN
BIN
D
R
BOOT
VIN
(C
)
(C
)
F2
F1
LOCATE NEAR SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
VCC
PVCC
VIN
INTERNAL BIAS
LINEAR REGULATOR
BOOT
HSOC
R
VFF
R
HSOC
VFF
(C
)
F3
C
C
VFF
BOOT
L
C
HSOC
UGATE
Q1
V
OUT
OUT
VCC
EN
PHASE
LGATE
REFIN
C
(C
)
BOUT
HFOUT
Q2
REFOUT
PG
R
LSOC
LSOC
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
C
PG_DLY
ISL6540A
PG_DLY
FS
C
R
LSOC
R
LS+
LS-
R
FS
COMP
C
2
C
R
3
3
C
1
MARCTRL
OFS+
R
2
R
1
R
FB
OFS+
VMON
R
R
MARG
FB
V
SENSE+
R
OFS-
VSEN+
OFS-
SS
C
R
SEN
OS
V
SENSE-
VSEN-
KEY
LINDRV
GND PGND
C
SS
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON/POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN6288.5
October 7, 2008
17
ISL6540A
frequency (F ; typically 0.1 to 0.3 of F ) and adequate
SW
phase margin (better than 45°). Phase margin is the
0
C
2
difference between the closed loop phase at F and 180°.
0dB
C
The equations that follow relate the compensation network’s
R
3
3
R
C
2
1
poles, zeros and gain to the components (R , R , R , C , C ,
COMP
1
2
3
1
2
and C ) in Figures 7 and 9. Use the following guidelines for
locating the poles and zeros of the compensation network:
3
-
R
FB
1
+
E/A
1. Select a value for R (1kΩ to 10kΩ, typically). Calculate
1
VREF
value for R for desired converter bandwidth (F ). If
2
0
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 9), in order
to compensate for the attenuation introduced by the
VMON
R
FB
-
VSEN-
VSEN+
C
SEN
R
OS
+
resistor divider, the below obtained R value needs be
2
V
OSCILLATOR
OUT
multiplied by a factor of (R +R )/R . The remainder
OS FB OS
V
IN
of the calculations remain unchanged, as long as the
V
OSC
compensated R value is used.
PWM
CIRCUIT
2
V
⋅ R ⋅ F
1 0
⋅ V ⋅ F
IN LC
OSC
L
(EQ. 11)
---------------------------------------------
=
R
DCR
C
UGATE
PHASE
2
d
MAX
HALF-BRIDGE
DRIVE
A small capacitor, CSEN in Figure 9, can be added to filter
out noise, typically CSEN is chosen so the corresponding
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
ESR
LGATE
frequency of the regulator. As the ISL6540A supports
100% duty cycle, d
equals 1. The ISL6540A also
uses feedforward compensation, as such V is equal
ISL6540A
EXTERNAL CIRCUIT
MAX
OSC
to 0.16 multiplied by the voltage at the VFF pin. When
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
tieing VFF to V , the Equation 12 simplifies to:
IN
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
0.16 ⋅ R ⋅ F
1
0
(EQ. 12)
----------------------------------
R
=
2
F
LC
(V
) is regulated to the reference voltage, VREF, level.
OUT
2. Calculate C such that F is placed at a fraction of the F
,
1
Z1 LC
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a
pulse-width modulated wave with an amplitude of V at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to
LC
desired number). The higher the quality factor of the output
IN
filter and/or the higher the ratio F /F , the lower the F
CE LC
Z1
frequency (to maximize phase boost at F ).
LC
1
(EQ. 13)
----------------------------------------------
C
=
1
2π ⋅ R ⋅ 0.5 ⋅ F
2
LC
The modulator transfer function is the small-signal transfer
function of V
DC gain, given by D
/V
. This function is dominated by a
V /V , and shaped by the
OUT COMP
3. Calculate C such that F is placed at F
.
2
P1 CE
MAX IN OSC
output filter, with a double pole break frequency at F and a
zero at F . For the purpose of this analysis C and ESR
CE
represent the total output capacitance and its equivalent
LC
C
1
(EQ. 14)
-------------------------------------------------------
=
C
2
2π ⋅ R ⋅ C ⋅ F – 1
CE
2
1
series resistance.
4. Calculate R such that F is placed at F . Calculate C
3
3
Z2
LC
1
1
(EQ. 10)
---------------------------
F
=
---------------------------------
such that F is placed below F
(typically, 0.5 to 1.0
F
=
P2 SW
LC
CE
2π ⋅ C ⋅ ESR
2π ⋅ L ⋅ C
times F ). F
represents the regulator’s switching
SW SW
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F lower in frequency
P2
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
The compensation network consists of the error amplifier
(internal to the ISL6540A) and the external R thru R , C thru
1
3
1
C components. The goal of the compensation network is to
3
provide a closed loop transfer function with high 0dB crossing
FN6288.5
October 7, 2008
18
ISL6540A
R
1
---------------------
MODULATOR GAIN
R
C
=
=
F
F
F
P1
F
Z1 Z2
P2
3
3
F
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
SW
------------
– 1
(EQ. 15)
F
LC
1
------------------------------------------------
2π ⋅ R ⋅ 0.7 ⋅ F
3
SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
R2
-------
⎛
⎝
⎞
⎠
20log
D
⋅ V
IN
R1
MAX
20log----------------------------------
V
0
OSC
G
frequency response of the modulator (G
), feedback
FB
MOD
G
CL
compensation (G ) and closed-loop response (G ):
FB
CL
D
⋅ V
1 + s(f) ⋅ ESR ⋅ C
MAX
V
IN
G
------------------------------ -----------------------------------------------------------------------------------------------------------
MOD
FREQUENCY
G
(f) =
⋅
MOD
2
OSC
1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C
1 + s(f) ⋅ R ⋅ C
LOG
F
F
F
0
LC
CE
2
1
----------------------------------------------------
G
(f) =
⋅
FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
s(f) ⋅ R ⋅ (C + C )
1
1
2
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
1 + s(f) ⋅ (R + R ) ⋅ C
3
1
3
-------------------------------------------------------------------------------------------------------------------------
C
⋅ C
⎛
⎛
⎜
⎝
⎞⎞
⎟⎟
⎠⎠
1
2
the switching frequency, F
.
--------------------
(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R ⋅
2
⎜
SW
3
3
C
+ C
2
⎝
1
G
(f) = G
(f) ⋅ G (f)
MOD FB
where, s(f) = 2π ⋅ f ⋅ j
(EQ. 16)
Component Selection Guidelines
CL
Output Capacitor Selection
As before when tieing VFF to VIN terms in the previous
equations can be simplified as shown in Equation 17:
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
D
⋅ V
1 ⋅ V
IN
MAX
V
IN
(EQ. 17)
------------------------------
--------------------------
=
= 6.25
0.16 ⋅ V
OSC
IN
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 10 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
compensation gain at F against the capabilities of the error
P2
amplifier. The closed loop gain, G , is constructed on the
CL
log-log graph of Figure 10 by adding the modulator gain,
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0µF
ceramic capacitors in the 1206 surface-mount package.
Follow on specifications have only increased the number
and quality of required ceramic decoupling capacitors.
G
(in dB), to the feedback compensation gain, G (in
MOD
FB
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
1
1
--------------------------------------------
F
=
------------------------------
F
=
P1
Z1
C
⋅ C
2
2π ⋅ R ⋅ C
1
2
1
--------------------
⋅
2π ⋅ R
2
C
+ C
2
1
1
1
-------------------------------------------------
2π ⋅ (R + R ) ⋅ C
------------------------------
2π ⋅ R ⋅ C
3
F
=
F
=
Z2
P2
1
3
3
3
(EQ. 18)
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
FN6288.5
October 7, 2008
19
ISL6540A
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
0.6
0.5
0.4
0.3
0.2
0.1
0.0
ΔI
= 0.5 x I
out
LOUT
ΔI
= 0.25 x I
LOUT out
ΔI
= 0
LOUT
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 19:
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE (D)
FIGURE 11. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
SINGLE-PHASE BUCK CONVERTER
V
- V
V
OUT
V
IN
IN
F
OUT
ΔV
= ΔI × ESR
------------------------------- ---------------
ΔI =
•
OUT
x L
to supply the current needed each time Q turns on. Place the
1
small ceramic capacitors physically close to the MOSFETs
S
(EQ. 19)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
and between the drain of Q and the source of Q .
1 2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25x greater than the maximum input
voltage and a voltage rating of 1.5x is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximated in Equation 21.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6540A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
V
2
O
ΔI
-------
2
2
----------
D =
I
=
I
(D – D ) +
D
IN, RMS
O
VIN
12
OR
I
The response time to a transient is different for the
application of load and the removal of load. Equation 20
gives the approximate response time interval for application
and removal of a transient load:
= K
• I
O
ICM
INRMS
(EQ. 21)
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. Figure 11 provides an easy
graphical approximation of the input RMS requirements for a
single-phase buck converter.
L
× I
L × I
O TRAN
O
TRAN
-------------------------------
------------------------------
t
=
t
=
FALL
(EQ. 20)
RISE
V
– V
V
IN
OUT
OUT
where: I
is the transient load current step, t
is the
TRAN
response time to the application of load, and t
RISE
is the
FALL
response time to the removal of load. With a lower input
source such as 1.8V or 3.3V, the worst case response time
can be either at the application or removal of load and
dependent upon the output voltage setting. Be sure to check
both of these equations at the minimum and maximum
output levels for the worst case response time.
MOSFET Selection/Considerations
The ISL6540A requires 2 N-Channel power MOSFETs.
These should be selected based upon r
, gate supply
DS(ON)
Input Capacitor Selection
requirements, and thermal management requirements.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
FN6288.5
October 7, 2008
20
ISL6540A
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). The
upper MOSFET exhibits turn-on and turn-off switching
losses as well as the reverse recover loss, while the
synchronous rectifier exhibits body-diode conduction losses
during the leading and trailing edge dead times.
where D is the duty cycle = V /VIN; Q is the reverse
rr
O
recover charge; t and t are leading and trailing edge
DL
DT
and t
dead time, and t
are the switching intervals.
OFF
ON
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
r
2
DS(ON),L
ΔI
2
⎛
⎝
⎞
⎠
---------------------------
P
P
=
I
+
•
• (1 – D) + P
-------
LOWER
O
DEAD
N
L
12
ΔI
ΔI
⎛
⎝
⎞
⎠
⎛
⎞
⎠
------
=
I
+
• V
• t
+ I
–
• V • t
• F
------
DEAD
O
DT DT
O
DL DL S
⎝
12
12
r
2
DS(ON),U
ΔI
2
⎛
⎞
⎠
---------------------------
P
P
=
I
+
•
• D + P
+ P
-------
UPPER
O
SW
Qrr
⎝
N
U
12
ΔI
12
ΔI
⎛
⎝
⎞
⎛
⎞
------
=
I
+
• t
+ I
–
• t
• VIN • F
S
------
SW
O
OFF
O
ON
⎠
⎝
⎠
12
P
= Q • VIN • F
rr S
Qrr
(EQ. 22)
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FN6288.5
October 7, 2008
21
ISL6540A
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X
3.0
5.00
0.50
24X
A
6
B
PIN #1 INDEX AREA
28
22
6
PIN 1
INDEX AREA
1
21
3 .10 ± 0 . 15
15
7
(4X)
0.15
8
14
0.10 M C A B
- 0.07
TOP VIEW
28X 0.55 ± 0.10
BOTTOM VIEW
4
28X 0.25
+ 0.05
SEE DETAIL "X"
C
0.10
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08
C
( 4. 65 TYP )
(
( 24X 0 . 50)
SIDE VIEW
3. 10)
(28X 0 . 25 )
( 28X 0 . 75)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6288.5
October 7, 2008
22
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