ISL6568CRZ-T_技术文档

DATASHEET

ISL6568

FN9187

Rev 5.00

Jan 12, 2012

Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9,

VRM10, and AMD Hammer Applications

The ISL6568 two-phase PWM control IC provides a precision

Features

voltage regulation system for advanced microprocessors. The

• Integrated Multi-Phase Power Conversion

- 1 or 2-Phase Operation

integration of power MOSFET drivers into the controller IC

marks a departure from the separate PWM controller and

driver configuration of previous multi-phase product families.

By reducing the number of external parts, this integration is

optimized for a cost and space saving power management

solution.

• Precision Core Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.5% System Accuracy Over Temperature

- Adjustable Reference-Voltage Offset

Outstanding features of this controller IC include

programmable VID codes compatible with Intel VRM9,VRM10,

as well as AMD Hammer microprocessors. A unity gain,

differential amplifier is provided for remote voltage sensing,

compensating for any potential difference between remote

and local grounds. The output voltage can also be positively or

negatively offset through the use of a single external resistor.

• Precision Channel Current Sharing

- Uses Loss-Less r

Current Sampling

DS(ON)

• Accurate Load Line Programming

- Uses Loss-Less Inductor DCR Current Sampling

• Variable Gate Drive Bias: 5V to 12V

A unique feature of the ISL6568 is the combined use of both

• Microprocessor Voltage Identification Inputs

- Up to a 6-Bit DAC

DCR and r

current sensing. Load line voltage positioning

DS(ON)

(droop) and overcurrent protection are accomplished through

continuous inductor DCR current sensing, while r current

- Selectable between Intel’s VRM9, VRM10, or AMD

Hammer DAC codes

DS(ON)

sensing is used for accurate channel-current balance. Using

both methods of current sampling utilizes the best advantages

of each technique.

- Dynamic VID-on-the-fly Technology

• Overcurrent Protection

Protection features of this controller IC include a set of

sophisticated overvoltage, undervoltage, and overcurrent

protection. Overvoltage results in the converter turning the

lower MOSFETs ON to clamp the rising output voltage and

protect the microprocessor. The overcurrent protection level is

set through a single external resistor. Furthermore, the

ISL6568 includes protection against an open circuit on the

remote sensing inputs. Combined, these features provide

advanced protection for the microprocessor and power system.

• Multi-tiered Overvoltage Protection

• Digital Soft-Start

• Selectable Operation Frequency up to 1.5MHz Per Phase

• Pb-Free (RoHS Compliant)

FN9187 Rev 5.00

Jan 12, 2012

Page 1 of 30

ISL6568

Pin Configuration

ISL6568

(32 LD QFN)

TOP VIEW

32 31 30 29 28 27 26 25

VID12.5

REF

1

2

3

4

5

6

7

8

24 BOOT1

23

22

PHASE1

VID4

OFS

VCC

21 VID3

20

19

18

COMP

FB

ENLL

PHASE2

BOOT2

VDIFF

RGND

17 UGATE2

9

10 11 12 13 14 15 16

Ordering Information

PART NUMBER

(Notes 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL6568CRZ

0 to +70

32 Ld 5x5 QFN

L32.5x5

ISL6568CRZ-T (Note 1)

ISL6568CRZR5184

ISL6568CRZ-TR5184 (Note 1)

ISL6568CRZAR5184

ISL6568CRZA-TR5184 (Note 1)

ISL6568IRZ

32 Ld 5x5 QFN, Tape and Reel

32 Ld 5x5 QFN

L32.5x5

ISL6568CRZ

ISL6568IRZ

0 to +70

32 Ld 5x5 QFN, Tape and Reel

32 Ld 5x5 QFN

0 to +70

32 Ld 5x5 QFN, Tape and Reel

32 Ld 5x5 QFN

-40 to +85

ISL6568IRZ-T (Note 1)

ISL6568IRZA

32 Ld 5x5 QFN, Tape and Reel

32 Ld 5x5 QFN

ISL6568IRZA-T (Note 1)

32 Ld 5x5 QFN, Tape and Reel

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6568. For more information on MSL please see tech brief TB363.

FN9187 Rev 5.00

Jan 12, 2012

Page 2 of 30

ISL6568

Block Diagram

ENLL

OCSET

PGOOD

ICOMP

100µA

ISEN AMP

ISUM

0.66V

VCC

POWER-ON

RESET

OC

IREF

PVCC

+1V

RGND

VSEN

BOOT1

SOFT START

AND

x1

FAULT LOGIC

UGATE1

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

VDIFF

PHASE1

LGATE1

FS

UVP

0.2V

OVP

CLOCK AND

SAWTOOTH

GENERATOR

OVP

V

PWM1



BOOT2

+150mV

x 0.82

UGATE2

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

PHASE2

LGATE2

PWM2



VID4

VID3

DYNAMIC

VID

D/A

VID2

VID1

VID0

PHASE 2

DETECT

VID12.5

CHANNEL

CURRENT

BALANCE

1

N

REF

FB

E/A

COMP

OFS



OFFSET

CHANNEL

CURRENT

SENSE

GND

ISEN1 ISEN2

FN9187 Rev 5.00

Jan 12, 2012

Page 3 of 30

ISL6568

Typical Application - ISL6568

FB

COMP

VDIFF

VSEN

RGND

+12V

+5V

PVCC1

VCC

BOOT1

UGATE1

OFS

PHASE1

ISEN1

FS

REF

LGATE1

VID4

VID3

ISL6568

+12V

VID2

PVCC2

VID1

LOAD

VID0

VID12.5

BOOT2

UGATE2

PGOOD

GND

PHASE2

ISEN2

+12V

LGATE2

ENLL

IREF

OCSET

ICOMP

ISUM

FN9187 Rev 5.00

Jan 12, 2012

Page 4 of 30

ISL6568

Typical Application - ISL6568 with NTC Thermal Compensation

FB

COMP

VDIFF

VSEN

RGND

+12V

+5V

PVCC1

VCC

BOOT1

UGATE1

OFS

PHASE1

ISEN1

FS

REF

LGATE1

VID4

VID3

ISL6568

+12V

VID2

PVCC2

VID1

LOAD

VID0

VID12.5

PLACE IN CLOSE

PROXIMITY

BOOT2

UGATE2

PGOOD

GND

PHASE2

ISEN2

NTC

+12V

LGATE2

ENLL

IREF

OCSET

ICOMP

ISUM

FN9187 Rev 5.00

Jan 12, 2012

Page 5 of 30

ISL6568

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V

Thermal Resistance

QFN Package (Notes 4, 5) . . . . . . . . . . . . . .



(°C/W)

35



(°C/W)

5

JA

JC

Absolute Boot Voltage, V

. . . . . . . . . . . . . . . . GND - 0.3V to GND + 36V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

BOOT

. . . . . . . . . . . . . . . . GND - 0.3V to 15V (PVCC = 12)

Phase Voltage, V

PHASE

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT-PHASE

Upper Gate Voltage, V

. . . . . . . . . . . . V

- 0.3V to V

PHASE

UGATE

- 3.5V (<100ns Pulse Width, 2µJ) to V

BOOT

V

PHASE

Lower Gate Voltage, V

. . . . . . . . . . . . . . . .GND - 0.3V to PVCC + 0.3V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Recommended Operating Conditions

Input, Output, or I/O Voltage. . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5%

Ambient Temperature

ISL6568CRZ, ISL6568CRZR5184 . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6568IRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Boldface limits apply over the operating

temperature ranges, 0°C to +70°C and -40°C to +85°C.

MIN

MAX

PARAMETER

BIAS SUPPLY AND INTERNAL OSCILLATOR

Input Bias Supply Current

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

I

; ENLL = high

-

15

20

-

mA

V

VCC

Gate Drive Bias Current

; ENLL = high

-

1.5

PVCC

VCC POR (Power-On Reset) Threshold

VCC Rising

VCC Falling

PVCC Rising

PVCC Falling

4.25

3.75

4.25

3.60

-

4.38

3.88

4.38

3.88

1.50

66.6

250

4.50

4.00

4.50

4.00

-

V

PVCC POR (Power-On Reset) Threshold

V

Oscillator Ramp Amplitude (Note 6)

Maximum Duty Cycle (Note 6)

V

P-P

-

%

Oscillator Frequency, F

R = 100k (±0.1%)

225

275

kHz

SW

T

CONTROL THRESHOLDS

ENLL Rising Threshold

-

0.66

100

0.3

-

V

mV

V

ENLL Hysteresis

COMP Shutdown Threshold

COMP Falling

0.2

0.4

REFERENCE AND DAC

System Accuracy (VID = 1.0V - 1.850V)

System Accuracy (VID = 0.8V - 1.0V)

DAC Input Low Voltage (VR9, VR10)

DAC Input High Voltage (VR9, VR10)

DAC Input Low Voltage (AMD)

DAC Input High Voltage (AMD)

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

-0.5

-0.8

-

0.5

0.8

0.4

-

%

V

-

0.8

-

V

-

0.6

-

V

1.0

47.5

-

V

R

= 30kfrom OFS to VCC

= 10kfrom OFS to GND

50.0

52.5

µA

OFS

FN9187 Rev 5.00

Jan 12, 2012

Page 6 of 30

ISL6568

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Boldface limits apply over the operating

temperature ranges, 0°C to +70°C and -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

ERROR AMPLIFIER

DC Gain (Note 6)

R

= 10k to ground

-

96

20

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product (Note 6)

Slew Rate (Note 6)

C = 100pF, R = 10k to ground

-

L

C

= 100pF, Load = ±400µA

-

3.90

-

8

-

L

Maximum Output Voltage

Minimum Output Voltage

OVERCURRENT PROTECTION

OCSET trip current

Load = 1mA

Load = -1mA

4.20

0.85

1.0

V

93

-5

100

0

107

5

µA

mV

OCSET Accuracy

OCSET and ISUM Difference

ICOMP Offset

-5

0

5

PROTECTION

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold while IC Disabled

VSEN falling

VSEN Rising

80

-

82

3

84

-

%VID

V , VRM9.0 Configuration

OVP

1.92

1.62

1.97

1.67

2.02

1.72

V

V , Hammer and VRM10.0 Configurations

OVP

Overvoltage Threshold

VSEN Rising

VID +

125mV

150mV

175mV

Overvoltage Hysteresis

VSEN Falling

-

50

-

mV

V

Open Sense-Line Protection Threshold

IREF Rising and Falling

VDIFF + VDIFF + VDIFF +

0.9V

1V

1.1V

SWITCHING TIME (Note 3)

UGATE Rise Time

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

-

26

18

12

10

-

ns

RUGATE; PVCC

LGATE Rise Time

V

RLGATE; PVCC

UGATE Fall Time

V

FUGATE; PVCC

LGATE Fall Time

V

FLGATE; PVCC

UGATE Turn-On Non-overlap

LGATE Turn-On Non-overlap

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

OVER-TEMPERATURE SHUTDOWN

Thermal Shutdown Setpoint (Note 6)

Thermal Recovery Setpoint (Note 6)

NOTE:

; V

= 12V, 3nF Load, Adaptive

PDHUGATE PVCC

; V

PDHLGATE PVCC

V

= 12V, 15mA Source Current

1.25

0.9

2.0

3.0



PVCC

= 12V, 15mA Sink Current

= 12V, 15mA Source Current

= 12V, 15mA Sink Current

1.65

1.25

0.80

0.85

0.60

2.2

1.35

-

+160

+100

-

°C

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

FN9187 Rev 5.00

Jan 12, 2012

Page 7 of 30

ISL6568

Timing Diagram

t

PDHUGATE

t

RUGATE

FUGATE

UGATE

LGATE

t

FLGATE

RLGATE

t

PDHLGATE

Simplified Power System

Diagram

+12V

IN

+5V

IN

Q1

CHANNEL1

Q2

5-6

VID

DAC

V

OUT

Q3

Q4

CHANNEL2

ISL6568

VID4, VID3, VID2, VID1, VID0, and VID12.5

Functional Pin Description

These are the inputs for the internal DAC that provides the

reference voltage for output regulation. These pins respond to

TTL logic thresholds. The ISL6568 decodes the VID inputs to

establish the output voltage; see VID Tables for

correspondence between DAC codes and output voltage

settings. These pins are internally pulled high, to

approximately 1.2V, by 40µA (typically) internal current

sources; the internal pull-up current decreases to 0 as the VID

voltage approaches the internal pull-up voltage. All VID pins

are compatible with external pull-up voltages not exceeding

the IC’s bias voltage (VCC).

VCC

VCC is the bias supply for the ICs small-signal circuitry. Connect

this pin to a +5V supply and locally decouple using a quality

1.0µF ceramic capacitor.

PVCC

This pin is the power supply pin for the MOSFET drivers. This

pin can be connected to any voltage from +5V to +12V,

depending on the desired MOSFET gate drive level.

GND

GND is the bias and reference ground for the IC.

The VID12.5 pin also serves as the internal DAC compliance

selector. The way this pin is connected selects which of the

three internal DAC codes will be used. For VRM10 codes this

pin must be less that 3V. To encode the DAC with Intel VRM9.0

codes, connect the VID12.5 pin to a +5V source through a

50k resistor. To encode the DAC with AMD Hammer VID

codes, connect this pin to a +5V source through a 5k resistor.

ENLL

This pin is a threshold-sensitive (approximately 0.66V) enable

input for the controller. Held low, this pin disables controller

operation. Pulled high, the pin enables the controller for

operation. ENLL has a internal 1.0µA pull-up to 5V.

FS

A resistor, placed from FS to ground, will set the switching

frequency. Refer to Equation 34 for proper resistor calculation.

FN9187 Rev 5.00

Jan 12, 2012

Page 8 of 30

ISL6568

VSEN and RGND

UGATE1 and UGATE2

VSEN and RGND are inputs to the precision differential

remote-sense amplifier and should be connected to the sense

pins of the remote load.

Connect these pins to the corresponding upper MOSFET gates.

These pins are used to control the upper MOSFETs and are

monitored for shoot-through prevention purposes. Maximum

individual channel duty cycle is limited to 66%.

ICOMP, ISUM, and IREF

BOOT1 and BOOT2

These pins provide the bias voltage for the corresponding

upper MOSFET drives. Connect these pins to

appropriately-chosen external bootstrap capacitors. Internal

bootstrap diodes connected to the PVCC pins provide the

necessary bootstrap charge.

ISUM, IREF, and ICOMP are the DCR current sense amplifier’s

negative input, positive input, and output respectively. For

accurate DCR current sensing, connect a resistor from each

channel’s phase node to ISUM and connect IREF to the

summing point of the output inductors, roughly V . A parallel

OUT

R-C feedback circuit connected between ISUM and ICOMP will

then create a voltage from IREF to ICOMP proportional to the

voltage drop across the inductor DCR. This voltage is referred to

as the droop voltage and is added to the differential

remote-sense amplifier output.

PHASE1 and PHASE2

Connect these pins to the sources of the upper MOSFETs.

These pins are the return path for the upper MOSFET drives.

Note: An optional 0.01µF ceramic capacitor can be placed

from the IREF pin to the ISUM pin to help reduce any noise

affects that may occur due to layout.

LGATE1 and LGATE2

These pins are used to control the lower MOSFETs. Connect

these pins to the corresponding lower MOSFETs’ gates.

VDIFF

PGOOD

VDIFF is the output of the differential remote-sense amplifier.

The voltage on this pin is equal to the difference between VSEN

and RGND added to the difference between IREF and ICOMP.

VDIFF therefore represents the output voltage plus the droop

voltage.

During normal operation PGOOD indicates whether the output

voltage is within specified overvoltage and undervoltage limits.

If the output voltage exceeds these limits or a reset event occurs

(such as an overcurrent event), PGOOD is pulled low. PGOOD is

always low prior to the end of soft-start.

FB and COMP

These pins are the internal error amplifier inverting input and

output respectively. FB, VDIFF, and COMP are tied together

through external R-C networks to compensate the regulator.

Operation

Multi-Phase Power Conversion

Microprocessor load current profiles have changed to the point

that the advantages of multi-phase power conversion are

impossible to ignore. The technical challenges associated with

producing a single-phase converter that is both cost-effective

and thermally viable have forced a change to the cost-saving

approach of multi-phase. The ISL6568 controller helps simplify

implementation by integrating vital functions and requiring

minimal external components. The “Block Diagram” on page 3

provides a top level view of multi-phase power conversion

using the ISL6568 controller.

REF

The REF input pin is the positive input of the error amplifier. It is

internally connected to the DAC output through a 1k resistor. A

capacitor is used between the REF pin and ground to smooth

the voltage transition during Dynamic VID operations.

OFS

The OFS pin provides a means to program a dc current for

generating an offset voltage across the resistor between FB and

VDIFF. The offset current is generated via an external resistor

and precision internal voltage references. The polarity of the

offset is selected by connecting the resistor to GND or VCC. For

no offset, the OFS pin should be left unconnected.

IL1 + IL2 + IL3, 7A/DIV

IL3, 7A/DIV

OCSET

This is the overcurrent set pin. Placing a resistor from OCSET to

ICOMP allows a 100A current to flow out this pin, producing a

voltage reference. Internal circuitry compares the voltage at

OCSET to the voltage at ISUM, and if ISUM ever exceeds OCSET,

the overcurrent protection activates.

PWM3, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

ISEN1 and ISEN2

IL1, 7A/DIV

These pins are used for balancing the channel currents by

sensing the current through each channel’s lower MOSFET

when it is conducting. Connect a resistor between the ISEN1

and ISEN2 pins and their respective phase node. This resistor

sets a current proportional to the current in the lower MOSFET

during its conduction interval.

PWM1, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR

3-PHASE CONVERTER

FN9187 Rev 5.00

Jan 12, 2012

Page 9 of 30

ISL6568

12V to 1.5V at 36A. The single-phase converter has 11.9A

RMS

Interleaving

input capacitor current. The single-phase converter must use an

input capacitor bank with twice the RMS current capacity as the

equivalent three-phase converter.

The switching of each channel in a multi-phase converter is

timed to be symmetrically out of phase with each of the other

channels. In a 3-phase converter, each channel switches 1/3

cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has a

combined ripple frequency three times greater than the ripple

frequency of any one phase. In addition, the peak-to-peak

amplitude of the combined inductor currents is reduced in

proportion to the number of phases (Equations 1 and 2).

Increased ripple frequency and lower ripple amplitude mean

that the designer can use less per-channel inductance and

lower total output capacitance for any performance

specification.

INPUT-CAPACITOR CURRENT, 10A/DIV

CHANNEL 3

INPUT CURRENT

10A/DIV

CHANNEL 2

INPUT CURRENT

10A/DIV

Figure 1 illustrates the multiplicative effect on output ripple

frequency. The three channel currents (IL1, IL2, and IL3)

combine to form the AC ripple current and the DC load current.

The ripple component has three times the ripple frequency of

each individual channel current. Each PWM pulse is terminated

1/3 of a cycle after the PWM pulse of the previous phase. The

peak-to-peak current for each phase is about 7A, and the DC

components of the inductor currents combine to feed the load.

CHANNEL 1

INPUT CURRENT

10A/DIV

1µs/DIV

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR

RMS CURRENT FOR 3-PHASE CONVERTER

To understand the reduction of ripple current amplitude in the

multi-phase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

Figures 22 and 23 in “Input Capacitor Selection” on page 25

can be used to determine the input-capacitor RMS current

based on load current, duty cycle, and the number of channels.

They are provided as aids in determining the optimal input

capacitor solution.

V – V

 V

OUT

IN

OUT

(EQ. 1)

I

= -----------------------------------------------------

P-P

Lf

V

S

IN

PWM Operation

In Equation 1, V and V

IN OUT

are the input and output voltages

The timing of each converter leg is set by the number of active

channels. The default channel setting for the ISL6568 is two.

One switching cycle is defined as the time between the

internal PWM1 pulse termination signals. The pulse

termination signal is the internally generated clock signal that

triggers the falling edge of PWM1. The cycle time of the pulse

termination signal is the inverse of the switching frequency set

by the resistor between the FS pin and ground. Each cycle

begins when the clock signal commands PWM1 to go low. The

PWM1 transition signals the internal channel-1 MOSFET driver

to turn off the channel-1 upper MOSFET and turn on the

channel-1 synchronous MOSFET. In the default channel

configuration, the PWM2 pulse terminates 1/2 of a cycle after

the PWM1 pulse.

respectively, L is the single-channel inductor value, and f is

the switching frequency.

S

The output capacitors conduct the ripple component of the

inductor current. In the case of multi-phase converters, the

capacitor current is the sum of the ripple currents from each of

the individual channels. Compare Equation 1 to the expression

for the peak-to-peak current after the summation of N

symmetrically phase-shifted inductor currents in Equation 2.

Peak-to-peak ripple current decreases by an amount

proportional to the number of channels. Output-voltage ripple

is a function of capacitance, capacitor equivalent series

resistance (ESR), and inductor ripple current. Reducing the

inductor ripple current allows the designer to use fewer or less

costly output capacitors.

If the BOOT2 and PHASE2 pins are both connected to +12V

single channel operation is selected.

V – N V

 V

OUT

IN

OUT

(EQ. 2)

I

= -----------------------------------------------------------

Once a PWM pulse transitions low, it is held low for a minimum

of 1/3 cycle. This forced off time is required to ensure an

accurate current sample. Current sensing is described in the

next section. After the forced off time expires, the PWM output

is enabled. The PWM output state is driven by the position of

CP-P

Lf

V

S

IN

Another benefit of interleaving is to reduce input ripple current.

Input capacitance is determined in part by the maximum input

ripple current. Multi-phase topologies can improve overall

system cost and size by lowering input ripple current and

allowing the designer to reduce the cost of input capacitance.

The example in Figure 2 illustrates input currents from a

three-phase converter combining to reduce the total input

ripple current.

the error amplifier output signal, V

, minus the current

COMP

correction signal relative to the sawtooth ramp as illustrated in

Figure 3. When the modified V voltage crosses the

COMP

sawtooth ramp, the PWM output transitions high. The internal

MOSFET driver detects the change in state of the PWM signal

and turns off the synchronous MOSFET and turns on the upper

MOSFET. The PWM signal will remain high until the pulse

termination signal marks the beginning of the next cycle by

triggering the PWM signal low.

The converter depicted in Figure 2 delivers 1.5V to a 36A load

from a 12V input. The RMS input capacitor current is 5.9A.

Compare this to a single-phase converter also stepping down

FN9187 Rev 5.00

Jan 12, 2012

Page 10 of 30

ISL6568

period sample. The sampled current is used only for

channel-current balance.

Channel-Current Balance

One important benefit of multi-phase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

I

L

PWM

In order to realize the thermal advantage, it is important that

each channel in a multi-phase converter be controlled to carry

about the same amount of current at any load level. To achieve

this, the currents through each channel must be sampled

SWITCHING PERIOD

I

SEN

every switching cycle. The sampled currents, I , from each

n

active channel are summed together and divided by the

number of active channels. The resulting cycle average

SAMPLING PERIOD

current, I

, provides a measure of the total load-current

AVG

demand on the converter during each switching cycle.

Channel-current balance is achieved by comparing the

sampled current of each channel to the cycle average current,

and making the proper adjustment to each channel pulse

width based on the error. Intersil’s patented current-balance

method is illustrated in Figure 3, with error correction for

channel 1 represented. In the figure, the cycle average current,

NEW SAMPLE

CURRENT

OLD SAMPLE

CURRENT

TIME

FIGURE 4. SAMPLE AND HOLD TIMING

The ISL6568 supports MOSFET r

current sensing to

sample each channel’s current for channel-current balance.

DS(ON)

I

, is compared with the channel 1 sample, I , to create an

AVG

1

error signal I

.

The internal circuitry, shown in Figure 5 represents channel n

of an N-channel converter. This circuitry is repeated for each

channel in the converter, but may not be active depending on

the status of the BOOT2 and PHASE2 pins, as described in

“PWM Operation” on page 10.

ER

The filtered error signal modifies the pulse width commanded

by V to correct any unbalance and force I toward zero.

COMP ER

The same method for error signal correction is applied to each

active channel.

V

IN

+

PWM1

V

COMP

TO GATE

CONTROL

LOGIC

+

-

r

CHANNEL N

UPPER MOSFET

DSON

I

= I -------------------------

-

SEN

L

R

ISEN

I

n

SAWTOOTH SIGNAL

FILTER f(s)

I

L

SAMPLE

&

HOLD

I

ER

+

I

ISEN(n)

AVG



N

I

2

-

R

ISEN

-

+

I

r

L

DSON

I

+

1

CHANNEL N

NOTE: Channel 2 is optional.

LOWER MOSFET

FIGURE3. CHANNEL-1PWMFUNCTIONANDCURRENT-BALANCE

ADJUSTMENT

ISL6565A INTERNAL CIRCUIT

EXTERNAL CIRCUIT

FIGURE 5. ISL6568 INTERNAL AND EXTERNAL

CURRENT-SENSING CIRCUITRY FOR CURRENT

BALANCE

Current Sampling

In order to realize proper current-balance, the currents in each

channel must be sampled every switching cycle. This sampling

occurs during the forced off-time, following a PWM transition

low. During this time the current-sense amplifier uses the ISEN

inputs to reproduce a signal proportional to the inductor

The ISL6568 senses the channel load current by sampling the

voltage across the lower MOSFET r

, as shown in

DS(ON)

Figure 5. A ground-referenced operational amplifier, internal to

the ISL6568, is connected to the PHASE node through a

resistor, R

. The voltage across R

is equivalent to the

ISEN

of the lower MOSFET while it is

current, I . This sensed current, I

, is simply a scaled version

L

SEN

voltage drop across the r

DS(ON)

conducting. The resulting current into the ISEN pin is

of the inductor current. The sample window opens exactly 1/6

of the switching period, t , after the PWM transitions low.

SW

The sample window then stays open the rest of the switching

cycle until PWM transitions high again, as illustrated in

Figure 4.

proportional to the channel current, I . The ISEN current is

L

sampled and held as described in the “Current Sampling” on

page 11. From Figure 5, Equation 3 for I is derived

n

The sampled current, at the end of the t

, is proportional

SAMPLE

to the inductor current and is held until the next switching

FN9187 Rev 5.00

Jan 12, 2012

Page 11 of 30

ISL6568

TABLE 2. AMD HAMMER VOLTAGE IDENTIFICATION

CODES (Continued)

r

DSON

I

= I ----------------------

(EQ. 3)

n

L

R

ISEN

VID4

1

0

VID3

1

0

1

0

VID2

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

where I is the channel current.

L

Output Voltage Setting

The ISL6568 uses a digital to analog converter (DAC) to

generate a reference voltage based on the logic signals at the

VID pins. The DAC decodes the 5 or 6-bit logic signals into one

of the discrete voltages shown in Tables 2, 3, and 4. Each VID

pin is pulled up to an internal 1.2V voltage by a weak current

source (40mA current), which decreases to 0 as the voltage at

the VID pin varies from 0 to the internal 1.2V pull-up voltage.

External pull-up resistors or active-high output stages can

augment the pull-up current sources, up to a voltage of 5V.

.

The ISL6568 accommodates three different DAC ranges: Intel

VRM9.0, AMD Hammer, or Intel VRM10.0. The state of the

VID12.5 pin decides which DAC version is active. Refer to

Table 1 for a description of how to select the desired DAC

version.

TABLE 1. ISL6568 DAC SELECT TABLE

DAC VERSION

VRM10.0

VID12.5 PIN CONDITION

Less than 3V

VRM9.0

50k resistor to +5V

5k resistor to +5V

AMD HAMMER

TABLE 2. AMD HAMMER VOLTAGE IDENTIFICATION

CODES

VID4

1

VID3

1

VID2

1

VID1

1

VID0

1

VDAC

Off

1

0

0.800

0.825

0.850

0.875

0.900

1

0

1

0

1

0

1

0

1

0

FN9187 Rev 5.00

Jan 12, 2012

Page 12 of 30

ISL6568

TABLE 3. VRM9 VOLTAGE IDENTIFICATION CODES

TABLE 4. VRM10 VOLTAGE IDENTIFICATION CODES

VID0 VID12.5

VID4

1

0

1

VID3

1

0

1

VID2

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

VDAC

VID4

1

0

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

1

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VDAC

Off

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Off

1

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

0

1

0

1

0

1

0

1

0

1

0

1

0

12.75

1

0

FN9187 Rev 5.00

Jan 12, 2012

Page 13 of 30

ISL6568

TABLE 4. VRM10 VOLTAGE IDENTIFICATION CODES (Continued)

EXTERNAL CIRCUIT

ISL6568 INTERNAL CIRCUIT

VID4

1

0

VID3

0

1

VID2

1

0

1

0

VID1

1

0

1

0

1

0

1

VID0 VID12.5

VDAC

R

C

COMP

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2750

1.2875

1.300

VID DAC

1k

REF

C

+

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

-

V

FB

COMP

ERROR AMPLIFIER

+

R

V

FB

OFS

I

OFS

-

VDIFF

VSEN

+

OUT

-

+

V

RGND

IREF

-

+

V

DROOP

-

ICOMP

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH

OFFSET ADJUSTMENT

The ISL6568 incorporates an internal differential

remote-sense amplifier in the feedback path. The amplifier

removes the voltage error encountered when measuring the

output voltage relative to the controller ground reference point,

resulting in a more accurate means of sensing output voltage.

Connect the microprocessor sense pins to the non-inverting

input, VSEN, and inverting input, RGND, of the remote-sense

amplifier. The droop voltage, V , also feeds into the

remote-sense amplifier. The remote-sense output, V , is

therefore equal to the sum of the output voltage, V , and the

droop voltage. V

DROOP

DIFF

OUT

is connected to the inverting input of the

DIFF

error amplifier through an external resistor.

The output of the error amplifier, V , is compared to the

COMP

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers and

regulate the converter output so that the voltage at FB is equal

to the voltage at REF. This will regulate the output voltage to be

equal to Equation 4. The internal and external circuitry that

controls voltage regulation is illustrated in Figure 6.

Voltage Regulation

In order to regulate the output voltage to a specified level, the

ISL6568 uses the integrating compensation network shown in

Figure 6. This compensation network insures that the

steady-state error in the output voltage is limited only to the

error in the reference voltage (output of the DAC) and offset

errors in the OFS current source, remote-sense and error

amplifiers. Intersil specifies the guaranteed tolerance of the

ISL6568 to include the combined tolerances of each of these

elements.

(EQ. 4)

V

= V

– V

OFS DROOP

OUT

REF

FN9187 Rev 5.00

Jan 12, 2012

Page 14 of 30

ISL6568

-

Load-Line (Droop) Regulation

V (s)

L

I

OUT

V

L

Some microprocessor manufacturers require a

precisely-controlled output impedance. This dependence of

output voltage on load current is often termed “droop” or “load

line” regulation.

DCR

PHASE1

PHASE2

INDUCTOR

OUT

I

L1

R

C

S

OUT

L

As shown in Figure 6, a voltage, V

, proportional to the

DROOP

DCR

total current in all active channels, I , feeds into the

OUT

INDUCTOR

L2

differential remote-sense amplifier. The resulting voltage at

the output of the remote-sense amplifier is the sum of the

output voltage and the droop voltage. Equation 4 shows that

feeding this voltage into the compensation network causes the

regulator to adjust the output voltage so it will be equal to the

reference voltage minus the droop voltage.

R

S

ISUM

The droop voltage, V

through the output inductors. This is accomplished by using a

continuous DCR current sensing method.

, is created by sensing the current

R

COMP

C

DROOP

COMP

ICOMP

-

V

DROOP

+

(optional)

Inductor windings have a characteristic distributed resistance

or DCR (Direct Current Resistance). For simplicity, the inductor

DCR is considered as a separate lumped quantity, as shown in

IREF

ISL6568

Figure 7. The channel current, I , flowing through the inductor,

L

passes through the DCR. Equation 5 shows the s-domain

FIGURE 7. DCR SENSING CONFIGURATION

equivalent voltage, V , across the inductor.

L

By simply adjusting the value of R , the load line can be set to

S

(EQ. 5)

V s = I  s  L + DCR

L

any level, giving the converter the right amount of droop at all

load currents. It may also be necessary to compensate for any

changes in DCR due to temperature. These changes cause the

load line to be skewed, and cause the R-C time constant to not

match the L/DCR time constant. If this becomes a problem a

simple negative temperature coefficient resistor network can

The inductor DCR is important because the voltage dropped

across it is proportional to the channel current. By using a

simple R-C network and a current sense amplifier, as shown in

Figure 7, the voltage drop across all of the inductors’ DCRs can

be extracted. The output of the current sense amplifier,

be used in the place of R

DCR due to temperature.

to compensate for the rise in

COMP

V

, can be shown to be proportional to the channel

DROOP

currents I and I , shown in Equation 6.

L1

L2

Note: An optional 10nF ceramic capacitor from the ISUM pin to

the IREF pin is recommended to help reduce any noise affects

on the current sense amplifier due to layout.

(EQ. 6)

s  L







------------- + 1

R



DCR

COMP

------------------------------------------------------------------------- -----------------------

V

s =



 I + I   DCR

L1 L2

DROOP

s  R

 C

+ 1

R

COMP

S

Output-Voltage Offset Programming

The ISL6568 allows the designer to accurately adjust the

If the R-C network components are selected such that the R-C

time constant matches the inductor L/DCR time constant,

offset voltage by connecting a resistor, R

, from the OFS pin

then V

is equal to the sum of the voltage drops across

OFS

DROOP

the individual DCRs, multiplied by a gain. As Equation 7 shows,

to VCC or GND. When R

is connected between OFS and

OFS

VCC, the voltage across it is regulated to 1.5V. This causes a

proportional current (I ) to flow into the OFS pin and out of

V

I

is therefore proportional to the total output current,

DROOP

.

OFS

is connected to ground, the voltage across it

OUT

the FB pin. If R

OFS

R

is regulated to 0.5V, and I

flows into the FB pin and out of

OFS

COMP

R

S

(EQ. 7)

--------------------

V

=

 I

 DCR

OUT

DROOP

the OFS pin. The offset current flowing through the resistor

between VDIFF and FB will generate the desired offset voltage

which is equal to the product (I

shown in Figures 8 and 9.

x R ). These functions are

OFS

FB

FN9187 Rev 5.00

Jan 12, 2012

Page 15 of 30

ISL6568

regulator to do this by making changes to the VID inputs. The

core-voltage regulator is required to monitor the DAC inputs and

respond to on-the-fly VID changes in a controlled manner,

supervising a safe output voltage transition without

discontinuity or disruption.

VDIFF

+

V

R

OFS

-

FB

VREF

E/A

The DAC mode the ISL6568 is operating in determines how the

controller responds to a dynamic VID change. When in VRM10

mode the ISL6568 checks the VID inputs six times every

switching cycle. If a new code is established and it stays the

same for 3 consecutive readings, the ISL6568 recognizes the

change and increments the reference. Specific to VRM10, the

processor controls the VID transitions and is responsible for

incrementing or decrementing one VID step at a time. In

VRM10 setting, the ISL6568 will immediately change the

reference to the new requested value as soon as the request is

validated; in cases where the reference step is too large, the

sudden change can trigger overcurrent or overvoltage events.

FB

OFS

I

-

1.5V

+

-

0.5V

OFS

ISL6568

R

OFS

In order to ensure the smooth transition of output voltage

during a VRM10 VID change, a VID step change smoothing

network is required for an ISL6568 based voltage regulator.

This network is composed of a 1k internal resistor between

GND

VCC

GND

FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE PROGRAMMING

the output of DAC and the capacitor C , between the REF pin

REF

VDIFF

and ground. The selection of C

is based on the time

REF

duration for 1-bit VID change and the allowable delay time.

-

Assuming the microprocessor controls the VID change at 1-bit

V

R

OFS

+

FB

VREF

every T , the relationship between C

VID

and T

is given by

(EQ. 10)

REF

VID

E/A

Equation 10.

FB

C

= 0.004X T

VID

REF

I

OFS

As an example, for a VID step change rate of 5µs per bit, the

value of C is 22nF based on Equation 10.

REF

When running in VRM9 or AMD Hammer operation, the ISL6568

responds slightly differently to a dynamic VID change than when

in VRM10 mode. In these modes the VID code can be changed

by more than a 1-bit step at a time. Once the controller receives

the new VID code it waits half of a phase cycle and then begins

slewing the DAC 12.5mV every phase cycle, until the VID and

DAC are equal. Thus, the total time required for a VID change,

VCC

-

R

OFS

1.5V

+

-

0.5V

OFS

ISL6568

t

, is dependent on the switching frequency (f ), the size of

DVID

S

the change (V ), and the time required to register the VID

VID

GND

VCC

change. The one-cycle addition in the t

DVID

equation is due to the

possibility that the VID code change may occur up to one full

switching cycle before being recognized. The approximate time

required for a ISL6568-based converter in AMD Hammer

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE PROGRAMMING

Once the desired output offset voltage has been determined,

use formulas in Equations 8 and 9 to set R

:

OFS

configuration running at f = 335kHz to make a 1.1V to 1.5V

S

reference voltage change is about 100µs, as calculated using

Equation 11.

For Positive Offset (connect R

to GND):

OFS

0.5  R

FB

V

(EQ. 8)

(EQ. 9)

R

= --------------------------

1

VID







OFS

(EQ. 11)

----

t

=

----------------- + 1.5

V

DVID

OFFSET



f

0.0125

S

For Negative Offset (connect R

to VCC):

OFS

Advanced Adaptive Zero Shoot-Through

Deadtime Control (Patent Pending)

1.5  R

FB

R

= --------------------------

OFS

V

OFFSET

The integrated drivers incorporate a unique adaptive deadtime

control technique to minimize deadtime, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFET body-diode conduction, and to prevent the upper and

lower MOSFETs from conducting simultaneously. This is

Dynamic VID

Modern microprocessors need to make changes to their core

voltage as part of normal operation. They direct the core-voltage

FN9187 Rev 5.00

Jan 12, 2012

Page 16 of 30

ISL6568

accomplished by ensuring either rising gate turns on its MOSFET

with minimum and sufficient delay after the other has turned off.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released to

rise. An auto-zero comparator is used to correct the r

drop

DS(ON)

in the phase voltage preventing false detection of the -0.3V phase

level during r conduction period. In the case of zero current,

DS(ON)

the UGATE is released after 35ns delay of the LGATE dropping

below 0.5V. During the phase detection, the disturbance of LGATE

falling transition on the PHASE node is blanked out to prevent

falsely tripping. Once the PHASE is high, the advanced adaptive

shoot-through circuitry monitors the PHASE and UGATE voltages

during a PWM falling edge and the subsequent UGATE turn-off. If

either the UGATE falls to less than 1.75V above the PHASE or the

PHASE falls to less than +0.8V, the LGATE is released to turn on.

Q

= 100nC

GATE

50nC

0.2

0.0

20nC

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

V (V)

BOOT_CAP

Internal Bootstrap Device

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE

Both integrated drivers feature an internal bootstrap Schottky

diode. Simply adding an external capacitor across the BOOT

and PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

PHASE node. This reduces voltage stress on the boot to phase

pins.

Gate Drive Voltage Versatility

The ISL6568 provides the user flexibility in choosing the gate

drive voltage for efficiency optimization. The controller ties the

upper and lower drive rails together. Simply applying a voltage

from 5V up to 12V on PVCC sets both gate drive rail voltages

simultaneously.

The bootstrap capacitor must have a maximum voltage rating

above PVCC + 5V and its capacitance value can be chosen

from Equation 12:

Initialization

Prior to initialization, proper conditions must exist on the ENLL,

VCC, PVCC and the VID pins. When the conditions are met, the

controller begins soft-start. Once the output voltage is within the

proper window of operation, the controller asserts PGOOD.

Q

GATE

-------------------------------------

C



BOOT_CAP

V

BOOT_CAP

(EQ. 12)

Q

 PVCC

G1

-----------------------------------

Q

=

 N

Q1

Enable and Disable

GATE

V

GS1

While in shutdown mode, the PWM outputs are held in a

high-impedance state. This forces the drivers to short

gate-to-source of the upper and lower MOSFET’s to assure the

MOSFETs remain off. The following input conditions must be

met before the ISL6566 is released from this shutdown mode.

where Q is the amount of gate charge per upper MOSFET at

G1

V

gate-source voltage and N is the number of control

GS1

MOSFETs. The V

Q1

term is defined as the allowable

BOOT_CAP

droop in the rail of the upper gate drive.

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this threshold

is reached, proper operation of all aspects of the ISL6568

is guaranteed. Hysteresis between the rising and falling

thresholds assure that once enabled, the ISL6568 will not

inadvertently turn off unless the bias voltage drops

substantially (see “Electrical Specifications” on page 6).

FN9187 Rev 5.00

Jan 12, 2012

Page 17 of 30

ISL6568

Thus, the soft-start period (not including the 16 PHASE clock

ISL6568 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

cycle delay) up to a given voltage, V

by Equation 13.

, can be approximated

DAC

V

 1280

DAC

(EQ. 13)

T

= ---------------------------------

SS

f

S

PVCC1

+12V

where V

is the DAC-set VID voltage, and f is the switching

S

DAC

frequency.

POR

CIRCUIT

ENABLE

10.7k

The ISL6568 also has the ability to start up into a pre-charged

output, without causing any unnecessary disturbance. The FB

pin is monitored during soft-start, and should it be higher than

the equivalent internal ramping reference voltage, the output

drives hold both MOSFETs off. Once the internal ramping

reference exceeds the FB pin potential, the output drives are

enabled, allowing the output to ramp from the pre-charged

level to the final level dictated by the DAC setting. Should the

output be pre-charged to a level exceeding the DAC setting, the

output drives are enabled at the end of the soft-start period,

leading to an abrupt correction in the output voltage down to

the DAC-set level.

COMPARATOR

ENLL

+

-

1.40k

0.66V

SOFT-START

AND

FAULT LOGIC

FIGURE 11. POWER SEQUENCING USING THRESHOLD-SENSITIVE

ENABLE (ENLL) FUNCTION

OUTPUT PRECHARGED

ABOVE DAC LEVEL

2. The voltage on ENLL must be above 0.66V. The EN input

allows for power sequencing between the controller bias

voltage and another voltage rail. The enable comparator

holds the ISL6568 in shutdown until the voltage at ENLL

rises above 0.66V. The enable comparator has 60mV of

hysteresis to prevent bounce.

OUTPUT PRECHARGED

BELOW DAC LEVEL

3. The driver bias voltage applied at the PVCC pin must reach

the internal power-on reset (POR) rising threshold.

Hysteresis between the rising and falling thresholds assure

that once enabled, the ISL6568 will not inadvertently turn

off unless the PVCC bias voltage drops substantially (see

“Electrical Specifications” on page 6).

V

(0.5V/DIV)

GND>

OUT

ENLL (5V/DIV)

T1 T2

T3

4. The VID code must not be 111111 or 111110 in VRM10

mode or 11111 in AMD Hammer or VRM9 modes. These

codes signal the controller that no load is present. The

controller will enter shut-down mode after receiving either

of these codes and will execute soft-start upon receiving

any other code. These codes can be used to enable or

disable the controller but it is not recommended. After

receiving one of these codes, the controller executes a

2-cycle delay before changing the overvoltage trip level to

the shut-down level and disabling PWM. Overvoltage

shutdown cannot be reset using one of these codes.

FIGURE 12. SOFT-START WAVEFORMS FOR ISL6568-BASED

MULTI-PHASE CONVERTER

Fault Monitoring and Protection

The ISL6568 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to a microprocessor load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 13 outlines

the interaction between the fault monitors and the power good

signal.

When each of these conditions is true, the controller

immediately begins the soft-start sequence.

SOFT-START

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. Following a delay of 16 PHASE clock cycles between

enabling the chip and the start of the ramp, the output voltage

progresses at a fixed rate of 12.5mV per each 16 PHASE clock

cycles.

FN9187 Rev 5.00

Jan 12, 2012

Page 18 of 30

ISL6568

voltage, V . The fixed voltage, V , is 1.67V when running in

OVP OVP

R

V

OCSET

AMD Hammer, or VRM10 modes, and 1.97V for VRM9 mode.

Upon successful soft-start, the overvoltage trip level is only DAC

plus 150mV. OVP releases 50mV below its trip point if it was

“DAC plus 150mV” that tripped it, and releases 100mV below its

OCSET

ICOMP

-

OCSET

+

IREF

ISUM

+

trip point if it was the fixed voltage, V , that tripped it. Actions

ISEN

OVP

-

are taken by the ISL6568 to protect the microprocessor load

when an overvoltage condition occurs, until the output voltage

falls back within set limits.

-

V

100uA

DROOP

+

At the inception of an overvoltage event, all LGATE signals are

commanded high, and the PGOOD signal is driven low. This

causes the controller to turn on the lower MOSFETs and pull

the output voltage below a level that might cause damage to

the load. The LGATE outputs remain high until VDIFF falls to

within the overvoltage limits explained above. The ISL6568 will

continue to protect the load in this fashion as long as the

overvoltage condition recurs.

OC

+

-

VDIFF

+1V

VID + 150mV

Once an overvoltage condition ends the ISL6568 continues

normal operation and PGOOD returns high.

SOFT-START, FAULT

AND CONTROL LOGIC

V

OVP

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the ISL6568

is designed to protect the load from any overvoltage events

that may occur. This is accomplished by means of an internal

10k resistor tied from PHASE to LGATE, which turns on the

lower MOSFET to control the output voltage until the

overvoltage event ceases or the input power supply cuts off.

For complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

-

OV

UV

VSEN

RGND

+

-

PGOOD

x1

-

+

0.82 x DAC

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from any

more pre-POR overvoltage events.

ISL6568 INTERNAL CIRCUITRY

FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY

Power-Good Signal

Open Sense Line Protection

The power good pin (PGOOD) is an open-drain logic output that

transitions high when the converter is operating after soft-

start. PGOOD pulls low during shutdown and releases high

after a successful soft-start. PGOOD transitions low when an

undervoltage, overvoltage, or overcurrent condition is detected

or when the controller is disabled by a reset from ENLL, POR,

or one of the no-CPU VID codes. If after an undervoltage or

overvoltage event occurs the output returns to within under

and overvoltage limits, PGOOD will return high.

In the case that either of the remote sense lines, VSEN or GND,

become open, the ISL6568 is designed to detect this and shut

down the controller. This event is detected by monitoring the

voltage on the IREF pin, which is a local version of V

at the outputs of the inductors.

sensed

OUT

If VSEN or RGND become opened, VDIFF falls, causing the duty

cycle to increase and the output voltage on IREF to increase. If

the voltage on IREF exceeds “VDIFF+1V”, the controller will

shut down. Once the voltage on IREF falls below “VDIFF+1V”,

the ISL6568 will restart at the beginning of soft-start.

Undervoltage Detection

The undervoltage threshold is set at 82% of the VID code.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, PGOOD gets pulled low. No other

action is taken by the controller. PGOOD will return high if the

output voltage rises above 85% of the VID code.

Overcurrent Protection

The ISL6568 detects overcurrent events by comparing the

droop voltage, V

, to the OCSET voltage, V , as

DROOP

OCSET

shown in Figure 13. The droop voltage, set by the external

current sensing circuitry, is proportional to the output current

as shown in Equation 7. A constant 100µA flows through

Overvoltage Protection

R

, creating the OCSET voltage. When the droop voltage

OCSET

The ISL6568 constantly monitors the difference between the

VSEN and RGND voltages to detect if an overvoltage event

occurs. During soft-start, while the DAC is ramping up, the

overvoltage trip level is the higher of DAC plus 150mV or a fixed

exceeds the OCSET voltage, the overcurrent protection circuitry

activates. Since the droop voltage is proportional to the output

current, the overcurrent trip level, I

, can be set by selecting

MAX

the proper value for R

, as shown in Equation 14.

OCSET

FN9187 Rev 5.00

Jan 12, 2012

Page 19 of 30

ISL6568

can be pushed as high as 40A per phase, but these designs

require heat sinks and forced air to cool the MOSFETs,

inductors and heat-dissipating surfaces.

I

 R

 DCR

COMP

MAX

(EQ. 14)

R

= ---------------------------------------------------------

OCSET

100  R

S

Once the output current exceeds the overcurrent trip level,

will exceed V , and a comparator will trigger the

MOSFETS

V

DROOP

OCSET

The choice of MOSFETs depends on the current each MOSFET

will be required to conduct, the switching frequency, the

capability of the MOSFETs to dissipate heat, and the availability

and nature of heat sinking and air flow.

converter to begin overcurrent protection procedures. At the

beginning of overcurrent shutdown, the controller turns off

both upper and lower MOSFETs. The system remains in this

state for a period of 4096 switching cycles. If the controller is

still enabled at the end of this wait period, it will attempt a

soft-start (as shown in Figure 14). If the fault remains, the trip-

retry cycles will continue indefinitely until either the controller

is disabled or the fault is cleared. Note that the energy

delivered during trip-retry cycling is much less than during

full-load operation, so there is no thermal hazard.

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is simple,

since virtually all of the loss in the lower MOSFET is due to

current conducted through the channel resistance (r ). In

Equation 15, I is the maximum continuous output current,

DS(ON)

M

I

is the peak-to-peak inductor current (see Equation 1 on

P-P

page 10), and d is the duty cycle (V

/V ).

OUT IN

2

I

1 – d













I

LP-P

(EQ. 15)

OUTPUT CURRENT, 50A/DIV

M

P

= r

1 – d + -----------------------------------

-----

LOW 1

DSON

12

N

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the diode

0A

forward voltage at I , V

the length of dead times, t and t , at the beginning and the

end of the lower-MOSFET conduction interval respectively.

, the switching frequency, f , and

M

D(ON)

S

OUTPUT VOLTAGE,

500mV/DIV

d1 d2









I

M

 N

I

(EQ. 16)









M

P-P

2

P-P

2 

P

= V

f

DON S

t

d2

+

----- + ----------

----- – ----------

LOW 2

d1

0V

N

2ms/DIV

FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE

The total maximum power dissipated in each lower MOSFET is

approximated by the summation of P and P

F

= 500kHz

SW

.

LOW,1 LOW,2

UPPER MOSFET POWER CALCULATION

In addition to r losses, a large portion of the upper-

General Design Guide

DS(ON)

MOSFET losses are due to currents conducted across the input

This design guide is intended to provide a high-level explanation of

the steps necessary to create a multi-phase power converter. It is

assumed that the reader is familiar with many of the basic skills

and techniques referenced below. In addition to this guide, Intersil

provides complete reference designs that include schematics, bill

of materials, and example board layouts for all common

microprocessor applications.

voltage (V ) during switching. Since a substantially higher

IN

portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

Upper MOSFET losses can be divided into separate

components involving the upper-MOSFET switching times, the

lower-MOSFET body-diode reverse-recovery charge, Q , and

rr

the upper MOSFET r

DS(ON)

conduction loss.

Power Stages

When the upper MOSFET turns off, the lower MOSFET does not

conduct any portion of the inductor current until the voltage at

the phase node falls below ground. Once the lower MOSFET

begins conducting, the current in the upper MOSFET falls to

zero as the current in the lower MOSFET ramps up to assume

the full inductor current. In Equation 17, the required time for

The first step in designing a multi-phase converter is to

determine the number of phases. This determination depends

heavily on the cost analysis which in turn depends on system

constraints that differ from one design to the next. Principally,

the designer will be concerned with whether components can

be mounted on both sides of the circuit board, whether

through-hole components are permitted, the total board space

available for power-supply circuitry, and the maximum amount

of load current. Generally speaking, the most economical

solutions are those in which each phase handles between 25A

and 30A. All surface-mount designs will tend toward the lower

end of this current range. If through-hole MOSFETs and

inductors can be used, higher per-phase currents are possible.

In cases where board space is the limiting constraint, current

this commutation is t and the approximated associated

1

power loss is P

.

UP,1

t

I













1

M

P-P

2







(EQ. 17)

P

 V

f

S

----

----- + ----------

UP1

IN



2

N

FN9187 Rev 5.00

Jan 12, 2012

Page 20 of 30

ISL6568

At turn-on, the upper MOSFET begins to conduct and this

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of +125°C. The maximum allowable IC power

dissipation for the 5x5 QFN package is approximately 4W at

room temperature. See “Layout Considerations” on page 26

for thermal transfer improvement suggestions.

transition occurs over a time t . In Equation 18, the

2

UP,2

approximate power loss is P

.

t

I













I

2

M

P-P

2







(EQ. 18)

P

 V

f

S

----

----- – ----------

UP2

IN



2

N

A third component involves the lower MOSFET reverse-recovery

charge, Q . Since the inductor current has fully commutated to

rr

When designing the ISL6568 into an application, it is

recommended that the following calculation is used to ensure

safe operation at the desired frequency for the selected

the upper MOSFET before the lower-MOSFET body diode can

recover all of Q , it is conducted through the upper MOSFET

rr

across VIN. The power dissipated as a result is P

.

UP,3

MOSFETs. The total gate drive power losses, P

, due to

Qg_TOT

(EQ. 19)

the gate charge of MOSFETs and the integrated driver’s

internal circuitry and their corresponding average driver

current can be estimated with Equations 21 and 22,

respectively.

P

= V

Q f

UP3

IN rr S

Finally, the resistive part of the upper MOSFET is given in

Equation 20 as P

.

UP(4)

P

= P

+ P

+ I  VCC

Qg_Q2 Q

(EQ. 21)

Qg_TOT

Qg_Q1

2









I

P-P

I

M

(EQ. 20)

P

 r

d +





----------

12

-----

UP4

DSON

N

3

2

--

P

=

 Q

 PVCC  F

 N

Q2



 N

Q1 PHASE

Qg_Q1

Qg_Q2

G1

SW

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 17, 18, 19 and 20. Since the power equations

depend on MOSFET parameters, choosing the correct

MOSFETs can be an iterative process involving repetitive

solutions to the loss equations for different MOSFETs and

different switching frequencies.

P

I

= Q

 PVCC  F

 N

PHASE

G2

SW

(EQ. 22)

3

2



--

=

 Q

 N

+ Q

 N

 F

+ I

SW

DR

G1

G2

Q2



PHASE

Q



Q1

Package Power Dissipation

In Equations 21 and 22, P

power loss and P

Qg_Q2

is the total upper gate drive

is the total lower gate drive power loss;

Qg_Q1

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of two drivers

in the controller package, the total power dissipated by both

drivers must be less than the maximum allowable power

dissipation for the QFN package.

the gate charge (Q and Q ) is defined at the particular gate to

G1 G2

source drive voltage PVCC in the corresponding MOSFET data

sheet; I is the driver total quiescent current with no load at both

Q

drive outputs; N and N are the number of upper and lower

Q1

Q2

MOSFETs per phase, respectively; N

is the number of active

PHASE

phases. The I VCC product is the quiescent power of the

Q*

controller without capacitive load and is typically 75mW at

300kHz.

PVCC

BOOT

D

C

GD

R

HI1

G

UGATE

C

DS

R

LO1

R

GI1

C

G1

GS

Q1

S

PHASE

FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FN9187 Rev 5.00

Jan 12, 2012

Page 21 of 30

ISL6568

PVCC

V

IN

D

CHANNEL N

UPPER MOSFET

C

GD

I

L

R

HI2

G

LGATE

C

DS

ISEN(n)

R

LO2

R

GI2

C

G2

GS

R

ISEN

Q2

S

-

ISL6568

I

r

L

DSON

+

CHANNEL N

FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

LOWER MOSFET

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in the

controller itself is the power dissipated in the upper drive path

FIGURE 17. ISL6568 INTERNAL AND EXTERNAL

CURRENT-SENSING CIRCUITRY

Select values for these resistors based on the room

temperature r

of the lower MOSFETs; the full-load

DS(ON)

resistance, P

, the lower drive path resistance, P , and

DR_UP

operating current, I ; and the number of phases, N using

FL

in the boot strap diode, P

. The rest of the power will be

BOOT

Equation 24.

dissipated by the external gate resistors (R and R ) and the

G1 G2

r

I

DSON FL

(EQ. 24)

internal gate resistors (R and R ) of the MOSFETs. Figures 15

GI1 GI2

R

= ----------------------- -------

–

ISEN

6

N

50 10

and 16 show the typical upper and lower gate drives’ turn-on

transition path. The total power dissipation in the controller itself,

In certain circumstances, it may be necessary to adjust the

value of one or more ISEN resistors. When the components of

one or more channels are inhibited from effectively dissipating

their heat so that the affected channels run hotter than desired,

P

, can be roughly estimated as Equation 23:

DR

P

= P

+ P

+ I  VCC

(EQ. 23)

DR

DR_UP

P

DR_LOW

BOOT

Q

choose new, smaller values of R

for the affected phases

ISEN

Qg_Q1

(see the section entitled “Channel-Current Balance” on

page 11). Choose R in proportion to the desired decrease

P

= ---------------------

BOOT

3

ISEN,2

in temperature rise in order to cause proportionally less current

to flow in the hotter phase.

P

R













Qg_Q1

3

HI1

LO1

---------------------

P

=

-------------------------------------- + ---------------------------------------





DR_UP

R

+ R

R

+ R

EXT1

HI1

EXT1

LO1

T

2

(EQ. 25)

R

= R

----------

ISEN,2

ISEN

T

P

R







1

Qg_Q2

2

HI2

LO2

---------------------

P

R

=

-------------------------------------- + ---------------------------------------

HI2







DR_LOW

R

+ R

R

+ R

LO2 EXT2

EXT2

In Equation 25, make sure that T is the desired temperature

2

rise above the ambient temperature, and T is the measured

1

R

GI1

GI2

temperature rise above the ambient temperature. While a

single adjustment according to Equation 25 is usually sufficient,

= R

+ -------------

R

= R

+ -------------

EXT1

G1

EXT2

G2

N

Q1

Q2

it may occasionally be necessary to adjust R

ISEN

times to achieve optimal thermal balance between all channels.

two or more

Current Balancing Component Selection

The ISL6568 senses the channel load current by sampling the

Load Line Regulation Component Selection

(DCR Current Sensing)

voltage across the lower MOSFET r

, as shown in

DS(ON)

Figure 17. The ISEN pins are denoted ISEN1 and ISEN2. The

resistors connected between these pins and the respective

phase nodes determine the gains in the channel-current

balance loop.

For accurate load line regulation, the ISL6568 senses the total

output current by detecting the voltage across the output

inductor DCR of each channel (see “Load-Line (Droop)

Regulation” on page 15). Figure 18 illustrates that an R-C

network is required to accurately sense the inductor DCR

voltage and convert this information into a “droop” voltage,

which is proportional to the total output current.

FN9187 Rev 5.00

Jan 12, 2012

Page 22 of 30

ISL6568

Choosing the components for this current sense network is a

Due to errors in the inductance or DCR it may be necessary to

adjust the value of R to match the time constants

two step process. First, R

that the time constant of this R

and C

must be chosen so

network matches

COMP

-C

COMP

correctly. The effects of time constant mismatch can be seen

in the form of droop overshoot or undershoot during the initial

load transient spike, as shown in Figure 19. Follow the steps

below to ensure the R-C and inductor L/DCR time constants

are matched accurately.

COMP COMP

the time constant of the inductor L/DCR. Then the resistor R

must be chosen to set the current sense network gain,

S

obtaining the desired full load droop voltage. Follow the steps

below to choose the component values for this R-C network.

1. Choose an arbitrary value for C

. The recommended

COMP

1. Capture a transient event with the oscilloscope set to about

L/DCR/2 (sec/div). For example, with L = 1H and DCR =

1m, set the oscilloscope to 500s/div.

value is 0.01µF.

2. Plug the inductor L and DCR component values, and the

values for C chosen in steps 1, into Equation 26 to

2. Record V1 and V2 as shown in Figure 19.

COMP

calculate the value for R

.

COMP

3. Select a new value, R

, for the time constant resistor

COMP,2

based on the original value, R

equation.

, using the following

COMP,1

L

(EQ. 26)

---------------------------------------

R

=

COMP

DCR  C

COMP

V

1

(EQ. 28)

----------

R

= R



COMP 1

3. Use the new value for R

COMP

obtained from Equation 26,

COMP 2

V

2

as well as the desired full load current, I , full load droop

FL

voltage, V

, and inductor DCR in Equation 27 to

DROOP

4. Replace R

with the new value and check to see that

COMP

calculate the value for R .

S

the error is corrected. Repeat the procedure if necessary.

I

FL

After choosing a new value for R , it will most likely be

(EQ. 27)

COMP

------------------------

R

=

 R

 DCR

COMP

S

V

necessary to adjust the value of R to obtain the desired full

DROOP

S

load droop voltage. Use Equation 27 to obtain the new value

-

for R .

S

V (s)

L

I

OUT

L

DCR

PHASE1

PHASE2

V

INDUCTOR

OUT

I

L1

R

C

S

OUT

V

2

L

V

1

DCR

INDUCTOR

L2

V

OUT

R

S

ISUM

I

TRAN

I

R

C

COMP

ICOMP

-

V

DROOP

+

(optional)

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

IREF

Compensation

The two opposing goals of compensating the voltage regulator

are stability and speed.

ISL6568

FIGURE 18. DCR SENSING CONFIGURATION

The load-line regulated converter behaves in a similar manner

to a peak current mode controller because the two poles at the

output filter L-C resonant frequency split with the introduction

of current information into the control loop. The final location

of these poles is determined by the system function, the gain

of the current signal, and the value of the compensation

components, R and C .

C

FN9187 Rev 5.00

Jan 12, 2012

Page 23 of 30

ISL6568

In Equation 29, L is the per-channel filter inductance divided by

the number of active channels; C is the sum total of all output

capacitors; ESR is the equivalent series resistance of the bulk

C

(OPTIONAL)

2

output filter capacitance; and V

sawtooth signal amplitude as described in the “Electrical

Specifications” on page 6.

is the peak-to-peak

C

P-P

C

R

C

COMP

FB

Once selected, the compensation values in Equations 29

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

ISL6568

R

improved by making adjustments to R . Slowly increase the

FB

C

value of R while observing the transient performance on an

C

VDIFF

oscilloscope until no further improvement is noted. Normally,

C will not need adjustment. Keep the value of C from

C

Equations 29 unless some performance issue is noted.

FIGURE 20. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6568 CIRCUIT

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (See Figure 20). Keep a

Since the system poles and zero are affected by the values of

the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C poles

and the ESR zero of the voltage mode approximation, yields a

solution that is always stable with very close to ideal transient

performance.

position available for C , and be prepared to install a

high-frequency capacitor of between 22pF and 150pF in case

any leading edge jitter problem is noted.

2

Output Filter Design

The output inductors and the output capacitor bank together to

form a low-pass filter responsible for smoothing the pulsating

voltage at the phase nodes. The output filter also must provide

the transient energy until the regulator can respond. Because

it has a low bandwidth compared to the switching frequency,

the output filter limits the system transient response. The

output capacitors must supply or sink load current while the

current in the output inductors increases or decreases to meet

the demand.

Select a target bandwidth for the compensated system, f . The

0

target bandwidth must be large enough to assure adequate

transient performance, but smaller than 1/3 of the per-

channel switching frequency. The values of the compensation

components depend on the relationships of f to the L-C pole

0

frequency and the ESR zero frequency. For each of the

following three, there is a separate set of equations for the

compensation components.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit. Output

filter design begins with minimizing the cost of this part of the

circuit. The critical load parameters in choosing the output

capacitors are the maximum size of the load step, I, the

load-current slew rate, di/dt, and the maximum allowable

1

------------------- > f

Case 1:

0

2 LC

2f V

LC

pp

0

output-voltage deviation under transient loading, V

.

R

C

= R -----------------------------------

MAX

C

FB

0.66V

IN

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

0.66V

IN

= ------------------------------------

2V

R

f

PP FB 0

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the voltage

drop across the ESR increases linearly until the load current

reaches its final value. The capacitors selected must have

sufficiently low ESL and ESR so that the total output-voltage

deviation is less than the allowable maximum. Neglecting the

contribution of inductor current and regulator response, the

output voltage initially deviates by an amount as shown by

Equation 30.

1

-------------------

 f < -----------------------------

0

2CESR

Case 2:

2 LC

2

V

2

f

LC

0

PP

R

C

= R --------------------------------------------

(EQ. 29)

C

FB

0.66 V

IN

0.66V

IN

= ------------------------------------------------------------

2

2

f

V

R

LC

0

PP FB

1

Case 3:

f

> -----------------------------

0

2CESR

di

dt

(EQ. 30)

V  ESL ---- + ESR I

2 f V

L

pp

0

R

= R

-----------------------------------------

FB

C

0.66 V ESR

IN

The filter capacitor must have sufficiently low ESL and ESR so

that V < V

.

0.66V ESR

C

MAX

IN

C

= -------------------------------------------------

2V

R

f

L

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination with

PP FB 0

FN9187 Rev 5.00

Jan 12, 2012

Page 24 of 30

ISL6568

bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

1000

100

10

The ESR of the bulk capacitors also creates the majority of the

output-voltage ripple. As the bulk capacitors sink and source

the inductor ac ripple current (See “Interleaving” and

Equation 2 on page 10), a voltage develops across the bulk

capacitor ESR equal to I

(ESR). Thus, once the output

C(P-P)

capacitors are selected, the maximum allowable ripple

voltage, V , determines the lower limit on the

P-P(MAX)

inductance as shown by Equation 31.

10

100

1000

10000

SWITCHINGFREQUENCY (kHz)







V

– N V

IN

OUT



(EQ. 31)

FIGURE 21. R vs SWITCHING FREQUENCY

T

L

ESR



-----------------------------------------------------------

f V

V

IN P-PMAX

S

Input Capacitor Selection

Since the capacitors are supplying a decreasing portion of the

load current while the regulator recovers from the transient,

the capacitor voltage becomes slightly depleted. The output

inductors must be capable of assuming the entire load current

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the ac component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

before the output voltage decreases more than V

. This

MAX

places an upper limit on inductance.

0.3

0.2

0.1

Equation 32 gives the upper limit on L for the cases when the

trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 33

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually less

than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of the

two results. In each equation, L is the per-channel inductance,

C is the total output capacitance, and N is the number of active

channels.

I

= 0

2  N  C  V

O

L(P-P)

(EQ. 32)

L  --------------------------------- V

– I  ESR

MAX

2

= 0.5 I





I

O

= 0.75 I

O

0





1.25  N  C

(EQ. 33)







– V

O

0

0.2

0.4

0.6

0.8

1.0

L  --------------------------------- V

– I  ESR

V

IN

2







I

DUTY CYCLE (V

V

)

O

IN/

FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR

2-PHASE CONVERTER

Switching Frequency

There are a number of variables to consider when choosing the

switching frequency, as there are considerable effects on the

upper MOSFET loss calculation. These effects are outlined in

“MOSFETs” on page 20, and they establish the upper limit for

the switching frequency. The lower limit is established by the

requirement for fast transient response and small

output-voltage ripple as outlined in “Output Filter Design” on

page 24. Choose the lowest switching frequency that allows

the regulator to meet the transient-response requirements.

For a two-phase design, use Figure 22 to determine the

input-capacitor RMS current requirement set by the duty cycle,

maximum sustained output current (I ), and the ratio of the

O

peak-to-peak inductor current (I

) to I . Select a bulk

O

L(P-P)

capacitor with a ripple current rating which will minimize the

total number of input capacitors required to support the RMS

current calculated. The voltage rating of the capacitors should

also be at least 1.25x greater than the maximum input

voltage. Figure 23 provides the same input RMS current

information for single-phase designs. Use the same approach

for selecting the bulk capacitor type and number.

Switching frequency is determined by the selection of the

frequency-setting resistor, R . Figure 21 and Equation 34 are

T

provided to assist in selecting the correct value for R .

T

(EQ. 34)







10.61 – 1.035logf

S

R

= 10

T

FN9187 Rev 5.00

Jan 12, 2012

Page 25 of 30

ISL6568

When placing the MOSFETs try to keep the source of the upper

FETs and the drain of the lower FETs as close as thermally possible.

Input Bulk capacitors should be placed close to the drain of the

upper FETs and the source of the lower FETs. Locate the output

inductors and output capacitors between the MOSFETs and the load.

The high-frequency input and output decoupling capacitors

(ceramic) should be placed as close as practicable to the decoupling

target, making use of the shortest connection paths to any internal

planes, such as vias to GND next or on the capacitor solder pad.

0.6

0.4

0.2

The critical small components include the bypass capacitors for

VCC and PVCC, and many of the components surrounding the

controller including the feedback network and current sense

components. Locate the VCC/PVCC bypass capacitors as close to

the ISL6566 as possible. It is especially important to locate the

components associated with the feedback circuit close to their

respective controller pins, since they belong to a high-impedance

circuit loop, sensitive to EMI pick-up. It is also important to place

the current sense components close to their respective pins on

I

= 0

L(P-P)

= 0.5 I

O

= 0.75 I

O

0

0.2

0.4

0.6

IN

0.8

1.0

DUTY CYCLE (V /V

)

O

FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR

SINGLE-PHASE CONVERTER

the ISL6566, including R

, R , R

, and C .

ISEN

S

COMP

A multi-layer printed circuit board is recommended. Figure 24 shows

the connections of the critical components for the converter. Note

Low capacitance, high-frequency ceramic capacitors are needed in

addition to the input bulk capacitors to suppress leading and

falling edge voltage spikes. The spikes result from the high current

slew rate produced by the upper MOSFET turn on and off. Select

low ESL ceramic capacitors and place one as close as possible to

each upper MOSFET drain to minimize board parasitics and

maximize suppression.

that capacitors C

and C could each represent numerous

xxIN

xxOUT

physical capacitors. Dedicate one solid layer, usually the one

underneath the component side of the board, for a ground plane

and make all critical component ground connections with vias to

this layer. Dedicate another solid layer as a power plane and break

this plane into smaller islands of common voltage levels. Keep the

metal runs from the PHASE terminal to output inductors short. The

power plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom circuit

layers for the phase nodes. Use the remaining printed circuit layers

for small signal wiring.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which

the current transitions from one device to another causes voltage

spikes across the interconnecting impedances and parasitic

circuit elements. These voltage spikes can degrade efficiency,

radiate noise into the circuit and lead to device overvoltage

stress. Careful component selection, layout, and placement

minimizes these voltage spikes. Consider, as an example, the

turnoff transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the turnoff,

current stops flowing in the upper MOSFET and is picked up by

the lower MOSFET. Any inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

magnitude of voltage spikes.

Routing UGATE, LGATE, and PHASE Traces

Great attention should be paid to routing the UGATE, LGATE, and

PHASE traces since they drive the power train MOSFETs using

short, high current pulses. It is important to size them as large and

as short as possible to reduce their overall impedance and

inductance. They should be sized to carry at least one ampere of

current (0.02” to 0.05”). Going between layers with vias should also

be avoided, but if so, use two vias for interconnection when possible.

Extra care should be given to the LGATE traces in particular since

keeping their impedance and inductance low helps to significantly

reduce the possibility of shoot-through. It is also important to route

each channels UGATE and PHASE traces in as close proximity as

possible to reduce their inductances.

There are two sets of critical components in a DC/DC converter

using a ISL6566 controller. The power components are the most

critical because they switch large amounts of energy. Next, are

small signal components that connect to sensitive nodes or

supply critical bypassing current and signal coupling.

Thermal Management

For maximum thermal performance in high current, high

switching frequency applications, connecting the thermal GND

pad of the ISL6566 to the ground plane with multiple vias is

recommended. This heat spreading allows the part to achieve

its full thermal potential. It is also recommended that the

controller be placed in a direct path of airflow if possible to help

thermally manage the part.

The power components should be placed first, which include the

MOSFETs, input and output capacitors, and the inductors. It is

important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each.

Symmetrical layout allows heat to be dissipated equally across all

three power trains. Equidistant placement of the controller to the

three power trains also helps keep the gate drive traces equally

short, resulting in equal trace impedances and similar drive

capability of all sets of MOSFETs.

FN9187 Rev 5.00

Jan 12, 2012

Page 26 of 30

ISL6568

Suppressing MOSFET Gate Leakage

With VCC at ground potential, UGATE is high impedance. In this

state, any stray leakage has the potential to deliver charge to the

gate of the upper MOSFET. If UGATE receives sufficient charge to

bias the device on, a low impedance path will be connected

between the upper MOSFET drain and PHASE. If this occurs and

the input power supply is present and active, the system could

see potentially damaging current. Worst-case leakage currents

are on the order of pico-amps; therefore, a 10k resistor,

connected from UGATE to PHASE, is more than sufficient to bleed

off any stray leakage current. This resistor will not affect the

normal performance of the driver or reduce its efficiency.

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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

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FN9187 Rev 5.00

Jan 12, 2012

Page 27 of 30

ISL6568

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN9187.5

CHANGE

January 3, 2012

Updated to new Intersil format including Intersil standards.

New part numbers added to “Ordering Information” on page 2 (ISL6568CRZ, ISL6568CRZ-T)

Four obsolete part numbers removed from “Ordering Information” on page 2 (ISL6568IR, ISL6568IR-T,

ISL6568CRR5184, ISL6568CR-TR5184)

Updated POD L32.5x5 to latest revision with the following changes:

Corrected Note 4 from:"Dimension b applies to..." to:

"Dimension applies to.." ("b" leftover from when dimensions were in table format)

Enclosed Note #'s 4, 5 and 6 in a triangle

March 9, 2006

July 25, 2005

FN9187.4

FN9187.3

Changed the Ordering Information on the front page to reflect the new ISL6568 part numbers. Set Customer

Portal attributes for Apple

1) Rewrote the Layout Considerations Section to flow better and provide a better explanation of proper layout

guidelines.

2) Added a "Thermal Management" section to the Layout Considerations section

3) Added a "Suppressing MOSFET Gate Leakage" section to the Layout Considerations section

July 11, 2005

FN9187.2

1) Changed Multiple "Gate Drive Resistance" specs on Page 6

2) All "Gate Drive Resistance" specs are now marked "Parameter magnitude guaranteed by design. Not 100%

tested."

3) Added a spec to page 5 for "Oscillator Frequency" tolerance

4) Added "DAC Input Low and High" specs for AMD mode to page 5

5) Made a change to the Block Diagram on Page 2: added resistors between the LGATE and PHASE pins

6) Made a change to the Application Diagrams on pages 3 and 4: added a capacitors from the IREF pin to ground

7) Made a slight change to the "Pre-POR Overvoltage Protection" section description

October 28, 2004

October 22, 2004

FN9187.1

FN9187.0

Change OFST to OFS throughout

Initial release

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