ISL6615AIBZ-T13 [RENESAS]
AND GATE BASED MOSFET DRIVER;
| 型号： | ISL6615AIBZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | AND GATE BASED MOSFET DRIVER 驱动 接口集成电路 |
| 文件： | 总12页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Frequency 6A Sink Synchronous MOSFET Drivers
with Protection Features
ISL6615A
Features
The ISL6615A is a high-speed MOSFET driver optimized to drive
upper and lower power N-Channel MOSFETs in a synchronous
rectified buck converter topology. This driver, combined with an
Intersil Digital or Analog multiphase PWM controller, forms a
complete high frequency and high efficiency voltage regulator.
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- LGATE Detection
- Auto-zero of r
DS(ON)
Conduction Offset Effect
The ISL6615A drives both upper and lower gates over a range of
4.5V to 13.2V. This drive-voltage provides the flexibility necessary
to optimize applications involving trade-offs between gate charge
and conduction losses.
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
The ISL6615A features 6A typical sink current for the low-side
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power loss
caused by the self turn-on of the lower MOSFET due to the high
dV/dt of the switching node.
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 5V PWM Input Logic
An advanced adaptive zero shoot-through protection is integrated
to prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead-time. The ISL6615A
includes an overvoltage protection feature operational before
VCC exceeds its turn-on threshold, at which the PHASE node is
connected to the gate of the low side MOSFET (LGATE). The
output voltage of the converter is then limited by the threshold of
the low side MOSFET, which provides some protection to the load
if the upper MOSFET(s) is shorted.
• Tri-State PWM Input for Safe Output Stage Shutdown
• Tri-State PWM Input Hysteresis for Applications with Power
Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB Efficiency
and Thinner in Profile
The ISL6615A also features an input that recognizes a
high-impedance state, working together with Intersil multiphase
PWM controllers to prevent negative transients on the controlled
output voltage when operation is suspended. This feature
eliminates the need for the Schottky diode that may be utilized in
a power system to protect the load from negative output voltage
damage.
• Pb-free (RoHS compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power Supplies
Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing
Moisture Sensitive Surface Mount Devices (SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and Surface
Mount Guidelines for QFN Packages”
April 13, 2012
FN6608.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010, 2012. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6615A
Block Diagram
ISL6615A
(UVCC)
BOOT
VCC
UGATE
PRE-POR OVP
FEATURES
+5V
PHASE
PVCC
SHOOT-
(LVCC)
THROUGH
10k
PROTECTION
UVCC = PVCC
POR/
CONTROL
LOGIC
PWM
LGATE
GND
8k
SUBSTRATE RESISTANCE
FOR DFN DEVICES, THE PAD ON THE BOTTOM SIDE OF
PAD
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
Typical Application - 2 Channel Converter
V
IN
+7V TO +13.2V
+5V
BOOT
PVCC
VCC
+5V
FB
COMP
VCC
UGATE
VSEN
PWM
PWM1
PWM2
ISL6615A
GND
PHASE
LGATE
PGOOD
PWM
CONTROL
(ISL63xx
OR ISL65xx)
ISEN1
ISEN2
VID
(OPTIONAL)
+V
CORE
+7V TO +13.2V
V
IN
PVCC
VCC
BOOT
FS/EN
GND
UGATE
PWM
ISL6615A
PHASE
LGATE
GND
THE ISL6615A CAN SUPPORT 5V PWM INPUT
FN6608.2
April 13, 2012
2
ISL6615A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6615ACBZ
ISL6615ACRZ
ISL6615AIBZ
ISL6615AIRZ
ISL6615AFRZ
NOTES:
6615A CBZ
615A
0 to +70
0 to +70
8 Ld SOIC
M8.15
10 Ld 3x3 DFN
8 Ld SOIC
L10.3x3
M8.15
6615A IBZ
15AI
-40 to +85
-40 to +85
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
15AF
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6615A. For more information on MSL please see techbrief TB363.
Pin Configurations
ISL6615A
(8 LD SOIC)
TOP VIEW
ISL6615A
(10 LD 3x3 DFN)
TOP VIEW
UGATE
BOOT
PWM
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
PHASE
PVCC
1
2
3
4
5
10
9
UGATE
BOOT
N/C
GND
8
N/C
GND
LGATE
VCC
7
PWM
GND
6
LGATE
*RECOMMEND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Functional Pin Descriptions
PACKAGE PIN #
PIN
SOIC
1
DFN
1
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device “TIMING DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
-
3, 8
4
N/C
No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the
“TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of the
controller.
4
5
6
7
5
6
7
9
GND
LGATE
VCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
PVCC
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high quality
low ESR ceramic capacitor from this pin to GND.
8
9
10
11
PHASE
PAD
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return
path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
FN6608.2
April 13, 2012
3
ISL6615A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . .VPHASE - 0.3VDC to VBOOT + 0.3V
. . . . . . . . . . . .VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
. . . . . . . . . . . . . . . . .GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to
Thermal Resistance
θ
(°C/W)
θ
(°C/W)
JC
JA
SOIC Package (Notes 4, 5) . . . . . . . . . . . . . 98
DFN Package (Notes 6, 7) . . . . . . . . . . . . . 47
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
56
5
Recommended Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V (<200ns, VBOOT-GND < 36V))
ESD Ratings
HBM (Tested per JESD22-A114E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
MM (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
CDM (Tested per JESD22-C101C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Latchup . . . . . . . . . . . . . . . . . . . . . . Tested per JESD78A, Class II at +85°C
Ambient Temperature Range
ISL6615ACRZ, ISL6615ACBZ . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6615AIRZ, ISL6615AIBZ . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6615AFRZ (Note 8). . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . .+125°C
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8V to 13.2V
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V to 12V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air.
JA
5. For θ , the “case temp” location is taken at the package top center.
JC
6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
7. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
8. When using ISL6615AFRZ, care should be taken to minimize power dissipation.
Electrical Specifications Recommended Operating Conditions; Boldface limits apply over the operating temperature ranges.
MIN
MAX
PARAMETER
VCC SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNITS
Bias Supply Current
I
f
f
= 300kHz, V
= 300kHz, V
= 12V
-
-
4.5
8
-
-
mA
mA
VCC
PWM
VCC
Gate Drive Bias Current
POWER-ON RESET AND ENABLE
VCC Rising Threshold
I
= 12V
PVCC
PVCC
PWM
6.1
4.7
6.4
5.0
6.7
5.3
V
V
VCC Falling Threshold
PWM INPUT (See “TIMING DIAGRAM” on page 6)
Input Current
I
V
V
= 5V
= 0V
-
510
-475
3.00
2.00
-
-
µA
µA
V
PWM
PWM
PWM
-
-
PWM Rising Threshold (Note 10)
PWM Falling Threshold (Note 10)
Typical Tri-State Shutdown Window
Tri-State Lower Gate Falling Threshold
Tri-State Lower Gate Rising Threshold
Tri-State Upper Gate Rising Threshold
Tri-State Upper Gate Falling Threshold
Shutdown Holdoff Time
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
-
-
-
-
V
1.80
2.40
V
-
-
-
-
-
-
-
1.50
1.00
3.20
2.70
55
-
-
-
-
-
-
-
V
V
V
V
t
ns
ns
ns
TSSHD
UGATE Rise Time (Note 10)
t
V
V
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
13
RU
PVCC
PVCC
LGATE Rise Time (Note 10)
t
10
RL
FN6608.2
April 13, 2012
4
ISL6615A
Electrical Specifications Recommended Operating Conditions; Boldface limits apply over the operating temperature ranges. (Continued)
MIN
MAX
PARAMETER
UGATE Fall Time (Note 10)
LGATE Fall Time (Note 10)
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
10
(Note 9)
UNITS
ns
t
V
V
V
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
-
-
-
-
-
-
FU
PVCC
PVCC
PVCC
t
10
ns
FL
UGATE Turn-On Propagation Delay
(Note 10)
t
30
ns
PDHU
LGATE Turn-On Propagation Delay
(Note 10)
t
V
V
V
V
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
-
-
-
-
20
10
20
20
-
-
-
-
ns
ns
ns
ns
PDHL
PVCC
PVCC
PVCC
PVCC
UGATE Turn-Off Propagation Delay
(Note 10)
t
PDLU
LGATE Turn-Off Propagation Delay
(Note 10)
t
= 12V, 3nF Load
PDLL
PDTS
LG/UG Tri-State Propagation Delay
(Note 10)
t
= 12V, 3nF Load
OUTPUT (Note 10)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
NOTES:
I
V
= 12V, 3nF Load
-
-
-
-
-
-
-
-
2.5
1
-
-
-
-
-
-
-
-
A
Ω
A
U_SOURCE
PVCC
R
150mA Source Current
= 12V, 3nF Load
U_SOURCE
I
V
4
U_SINK
PVCC
150mA Sink Current
V = 12V, 3nF Load
R
0.8
4
Ω
A
U_SINK
I
L_SOURCE
PVCC
150mA Source Current
V = 12V, 3nF Load
R
0.7
6
Ω
A
L_SOURCE
I
L_SINK
PVCC
150mA Sink Current
R
0.45
Ω
L_SINK
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Limits established by characterization and are not production tested.
FN6608.2
April 13, 2012
5
ISL6615A
Description
1.18V < PWM < 2.36V
0.76V < PWM < 1.96V
PWM
t
t
PDLU
PDHU
t
TSSHD
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
t
FL
RL
t
t
TSSHD
PDLL
t
PDHL
FIGURE 1. TIMING DIAGRAM
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring the rising gate turns on its MOSFET
with minimum and sufficient delay after the other has turned off.
Operation
Designed for versatility and speed, the ISL6615A MOSFET driver
controls both high-side and low-side N-Channel FETs of a half-
bridge power train from one externally provided PWM signal.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it drops below 1.75V. Prior to reaching this level,
there is a 25ns blanking period to protect against sudden dips in
the LGATE voltage. Once 1.75V is reached, the UGATE is released
to rise after 20ns of propagation delay. Once the PHASE is high,
the adaptive shoot-through circuitry monitors the PHASE and
UGATE voltages during PWM falling edge and subsequent UGATE
turn-off. If PHASE falls to less than +0.8V, the LGATE is released
to turn on after 10ns of propagation delay. If the UGATE-PHASE
falls to less than 1.75V and after 40ns of propagation delay,
LGATE is released to rise.
Prior to VCC exceeding its POR level, the Pre-POR overvoltage
protection function is activated during initial start-up; the upper
gate (UGATE) is held low and the lower gate (LGATE), controlled
by the Pre-POR overvoltage protection circuits, is connected to
the PHASE. Once the VCC voltage surpasses the VCC Rising
Threshold (see “Electrical Specifications” on page 4) the PWM
signal takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see “TIMING
DIAGRAM” on page 6). After a short propagation delay [t
the lower gate begins to fall. Typical fall times [t ] are provided
],
PDLL
FL
in the “Electrical Specifications” on page 4. Adaptive shoot-
through circuitry monitors the LGATE voltage and determines the
Tri-state PWM Input
A unique feature of these drivers and other Intersil drivers is the
addition of a shutdown window to the PWM input. If the PWM
signal enters and remains within the shutdown window for a set
holdoff time, the driver outputs are disabled and both MOSFET
gates are pulled and held low. The shutdown state is removed
when the PWM signal moves outside the shutdown window.
Otherwise, the PWM rising and falling thresholds outlined in
“Electrical Specifications” on page 4, determine when the lower
and upper gates are enabled.
upper gate delay time [t
]. This prevents both the lower and
upper MOSFETs from conducting simultaneously. Once this delay
PDHU
period is complete, the upper gate drive begins to rise [t ] and
RU
the upper MOSFET turns on.
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
] is encountered before the upper gate
PDLU
begins to fall [t ]. Again, the adaptive shoot-through circuitry
FU
determines the lower gate delay time, t
. The PHASE voltage
PDHL
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the Schottky
diode that is used in some systems for protecting the load from
reversed output voltage events.
and the UGATE voltage are monitored, and the lower gate is
allowed to rise after PHASE drops below a level or the voltage of
UGATE to PHASE reaches a level depending upon the current
direction (See the following section titled “Advanced Adaptive
Zero Shoot-Through Dead-Time Control” for details). The lower
In addition, more than 400mV hysteresis also incorporates into
the Tri-State shutdown window to eliminate PWM input
oscillations due to the capacitive load seen by the PWM input
through the body diode of the controller’s PWM output when the
power-up and/or power-down sequence of bias supplies of the
driver and PWM controller are required.
gate then rises [t ], turning on the lower MOSFET.
RL
Advanced Adaptive Zero Shoot-Through
Dead-time Control
The ISL6615A driver incorporates a unique adaptive dead-time
control technique to minimize dead-time, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFETs’ body-diode conduction, and to prevent the upper and
FN6608.2
April 13, 2012
6
ISL6615A
Power-On Reset (POR) Function
1.6
1.4
1.2
1.0
0.8
0.6
0.4
During initial start-up, the VCC voltage rise is monitored. Once the
rising VCC voltage exceeds 6.4V (typically), operation of the driver
is enabled and the PWM input signal takes control of the gate
drives. If VCC drops below the falling threshold of 5.0V (typically),
operation of the driver is disabled.
Pre-POR Overvoltage Protection
Prior to VCC exceeding its POR level, the upper gate is held low
and the lower gate is controlled by the overvoltage protection
circuits. The upper gate driver is powered from PVCC and will be
held low when a voltage of 2.75V or higher is present on PVCC as
VCC surpasses its POR threshold. The PHASE is connected to the
gate of the low side MOSFET (LGATE), which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during start-up, normal, or shutdown conditions. For
complete protection, the low side MOSFET should have a gate
threshold well below the maximum voltage rating of the
load/microprocessor.
Q
= 100nC
GATE
50nC
0.2
0.0
20nC
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Internal Bootstrap Device
Gate Drive Voltage Versatility
Both drivers feature an internal bootstrap Schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit. The bootstrap function is also
designed to prevent the bootstrap capacitor from overcharging
due to the large negative swing at the trailing-edge of the PHASE
node. This reduces voltage stress on the boot to phase pins.
The ISL6615A provides the user with flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6615A ties
the upper and lower drive rails together. Simply applying a
voltage from +4.5V up to 13.2V on PVCC sets both gate drive rail
voltages simultaneously, while VCC’s operating range is from
+6.8V up to 13.2V.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 5V and its capacitance value can be chosen from
Equation 1:
Power Dissipation
Package power dissipation is mainly a function of the switching
Q
frequency (F ), the output drive impedance, the external gate
GATE
SW
---------------------------------
C
≥
BOOT_CAP
resistance and the selected MOSFET’s internal gate resistance and
total gate charge. Calculating the power dissipation in the driver for
a desired application is critical to ensure safe operation. Exceeding
the maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package (with an exposed heat escape pad) is more than 1.5W. The
DFN package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal transfer
ΔV
BOOT_CAP
(EQ. 1)
Q
• PVCC
G1
V
-------------------------------
Q
=
• N
GATE
Q1
GS1
where Q is the amount of gate charge per upper MOSFET at
G1
V
gate-source voltage and N is the number of control
GS1
MOSFETs. The ΔV
Q1
term is defined as the allowable
BOOT_CAP
droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as the
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation is used
to ensure safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses due to the gate charge
of MOSFETs and the driver’s internal circuitry and their
upper MOSFETs. The gate charge, Q , from the data sheet is
G
10nC at 4.5V (V ) gate-source voltage. Then the Q
is
GS GATE
calculated to be 53nC for PVCC = 12V. We will assume a 200mV
droop in drive voltage over the PWM cycle. We find that a
bootstrap capacitance of at least 0.267µF is required. The next
larger standard value capacitance is 0.33µF. A good quality
ceramic capacitor is recommended.
corresponding average driver current can be estimated with
Equations 2 and 3, respectively:
(EQ. 2)
P
= P
+ P
+ I • VCC
Q
Qg_TOT
Qg_Q1
Qg_Q2
2
Q
• PVCC
G1
----------------------------------
P
=
• F
• N
• N
Qg_Q1
SW
Q1
V
GS1
2
Q
• PVCC
G2
----------------------------------
P
=
• F
Qg_Q2
SW
Q2
V
GS2
Q
• PVCC • N
Q
• PVCC • N
G2 Q2
⎛
⎜
⎝
⎞
⎟
⎠
G1
Q1
------------------------------------------------ ------------------------------------------------
I
=
+
• F
+ I
SW Q
(EQ. 3)
DR
V
V
GS2
GS1
FN6608.2
April 13, 2012
7
ISL6615A
where the gate charge (Q and Q ) is defined at a particular
G1
G2
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power devices’
packaging (both upper and lower MOSFETs) can cause serious
ringing, exceeding the absolute maximum ratings of the devices.
A good layout helps reduce the ringing on the switching node
(PHASE) and significantly lowers the stress applied to the output
drives. The following advice is meant to lead to an optimized
layout and performance:
gate to source voltage (V
and V
) in the corresponding
GS1
GS2
MOSFET datasheet; I is the driver’s total quiescent current with
Q
no load at both drive outputs; N and N are the number of
Q1 Q2
upper and lower MOSFETs, respectively; PVCC is the drive voltage
for both upper and lower FETs. The I *VCC product is the
Q
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz and VCC = PVCC = 12V.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses; the rest will be dissipated by the external gate resistors
• Keep decoupling loops (VCC-GND, PVCC-GND and BOOT-PHASE)
short and wide (at least 25 mils). Avoid using vias on decoupling
components other than their ground terminals, which should be
on a copper plane with at least two vias.
(R and R ) and the internal gate resistors (R
and R ) of
G1 G2 GI1
GI2
MOSFETs. Figures 3 and 4 show the typical upper and lower gate
drives turn-on transition path. The power dissipation on the driver
can be roughly estimated, as shown in Equation 4.
• Minimize trace inductance, especially on low-impedance lines.
All power traces (UGATE, PHASE, LGATE, GND, PVCC, VCC,
GND) should be short and wide (at least 25 mils). Try to place
power traces on a single layer, otherwise, two vias on
interconnection are preferred where possible. For no
connection (NC) pins on the QFN part, connecting them to the
adjacent net (LGATE2/PHASE2) can reduce trace inductance.
P
P
= P
+ P
+ I • VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
P
R
R
⎛
⎞
Qg_Q1
HI1
LO1
+ R
EXT1
----------------------------------- ------------------------------------ -------------------
=
+
•
⎜
⎝
⎟
DR_UP
R
+ R
R
2
⎠
HI1
EXT1
LO1
• Shorten all gate drive loops (UGATE-PHASE and LGATE-GND)
and route them closely spaced.
P
R
R
⎛
⎜
⎝
⎞
Qg_Q2
HI2
LO2
----------------------------------- ------------------------------------ -------------------
P
R
=
+
•
⎟
DR_LOW
R
+ R
R
+ R
EXT2
2
⎠
HI2
EXT2
LO2
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET should
be as close as thermally allowable.
R
R
GI1
GI2
------------
------------
= R
+
R
= R
+
EXT1
G1
EXT2
G2
N
N
Q1
Q2
• Minimize the current loop of the output and input power trains.
Short the source connection of the lower MOSFET to ground as
close to the transistor pin as feasible. Input capacitors
(especially ceramic decoupling) should be placed as close to
the drain of upper and source of lower MOSFETs as possible.
PVCC
BOOT
D
C
GD
R
HI1
G
• Avoid routing relatively high impedance nodes (such as PWM
and ENABLE lines) close to high dV/dt UGATE and PHASE
nodes.
C
DS
R
R
GI1
LO1
R
G1
C
GS
Q1
In addition, for heat spreading, place copper underneath the IC
whether it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or connected to
buried power ground plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended copper
plane, and buried planes for heat spreading allows the IC to
achieve its full thermal potential.
S
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Upper MOSFET Self Turn-On Effects at
Start-up
PVCC
D
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high dV/dt
rate while the driver outputs are floating due to the self-coupling
C
GD
R
HI2
G
C
DS
via the internal C of the MOSFET, the UGATE could
GD
R
R
GI2
LO2
R
G2
momentarily rise up to a level greater than the threshold voltage
of the MOSFET. This could potentially turn on the upper switch
and result in damaging inrush energy. Therefore, if such a
situation (when input bus powered up before the bias of the
controller and driver is ready) could conceivably be encountered,
C
GS
Q2
S
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
it is a common practice to place a resistor (R
) across the
UGPH
gate and source of the upper MOSFET to suppress the Miller
coupling effect. The value of the resistor depends mainly on the
input voltage’s rate of rise, the C /C ratio, as well as the
GD GS
FN6608.2
April 13, 2012
8
ISL6615A
gate-source threshold of the upper MOSFET. A higher dV/dt, a
lower C /C ratio, and a lower gate-source threshold upper
PVCC
VIN
BOOT
DS GS
FET will require a smaller resistor to diminish the effect of the
internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
D
C
BOOT
C
GD
DU
DL
UGATE G
C
DS
R
The coupling effect can be roughly estimated with the formulas
in Equation 5, which assume a fixed linear input ramp and
neglect the clamping effect of the body diode of the upper drive
and the bootstrap capacitor. Other parasitic components such as
lead inductances and PCB capacitances are also not taken into
account. These equations are provided for guidance purpose
only. Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to ensure
a safe design margin.
GI
C
Q
GS
UPPER
S
PHASE
FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE UPPER
MOSFET MILLER COUPLING
–V
DS
⎛
⎜
⎜
⎜
⎜
⎝
⎞
⎟
-------------------------------
dV
------
⋅ R ⋅ C
dV
dt
iss
dt
⎟
⎟
⎟
⎠
------
V
=
⋅ R ⋅ C
1 – e
(EQ. 5)
GS_MILLER
rss
C
= C + C
GD GS
C
= C
R = R
+ R
GI
iss
rss
GD
UGPH
FN6608.2
April 13, 2012
9
ISL6615A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN6608.2
CHANGE
5/16/11
Converted to new template
Added Tjc and applicable note to “Thermal Information” on page 4 for SOIC package.
Updated “Package Outline Drawing” on page 12 (M8.15) to new POD format by removing table and moving
dimensions onto drawing and adding land pattern
7/21/10
4/20/10
Added “ESD Ratings” and “Latchup Tested per JESD78A, Class II at +85°C” to page 4.
FN6608.1
Electrical Specifications Table changes:
PWM Input - Shutdown Holdoff Time - Typ from “65” to “55”
UGATE Turn-On Propagation Delay (Note 10) tPDHU VPVCC = 12V, 3nF Load, Adaptive - from “10” to “30” - ns
LGATE Turn-On Propagation Delay (Note 10) tPDHL VPVCC = 12V, 3nF Load, Adaptive - from “10” to “20” - ns
LGATE Turn-Off Propagation Delay (Note 10) tPDLL VPVCC = 12V, 3nF Load, Adaptive - from “10” to “20” - ns
LG/UG Tri-State Propagation Delay (Note 10) tPDTS VPVCC = 12V, 3nF Load, Adaptive - from “10” to “20” - ns
2/24/10
Converted to New Intersil Template.
Updated Ordering Information Industrial parts Temp Range from "-40C to +70C" to "-40C to +85C".
Added MSL Note to Ordering Information.
Updated Thermal Information Tja and Tjc for SOIC - from "100, N/A" to "98, N/A" DFN - "48, 7" to "47, 5".
Moved over-temp note from conditions of Electrical Specifications table to end of table as "Note".
Added Bold text to conditions of Electrical Specifications table indicating over-temp.
Added note to Min and Max columns of Electrical Specifications table.
Changed layout to meet new standard flow.
Added part # ISL6615AFRZ with temp range of -40°C to +125°C to Ordering Information, Recommended
Operating Conditions and Note 8 reference.
Updated POD L10.3x3 to latest revision.
POD changes are as follows:
Changed Note 4 from "Dimension b applies..." to "Lead width applies..."
Changed Note callout in Detail X from 4 to 5
Changed height in side view from 0.90 MAX to 1.00 MAX
Added Note 4 callout next to lead width in Bottom View
In Land Pattern, corrected lead shape for 4 corner pins to "L" shape (was rectangular and did not match bottom
view).
04/30/08
FN6608.0
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL6615A
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6608.2
April 13, 2012
10
ISL6615A
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
1
2
6
PIN 1
INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
10x 0.35
4
TOP VIEW
BOTTOM VIEW
C A B
M
0.10
(4X)
0.415
0.23
PACKAGE
OUTLINE
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
5
0.20 REF
0.05
C
1.60
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6608.2
April 13, 2012
11
ISL6615A
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6608.2
April 13, 2012
12
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