ISL78610ANZ-T_技术文档

DATASHEET

ISL78610

Multi-Cell Li-Ion Battery Manager

FN8830

Rev 3.00

May 10, 2018

The automotive grade ISL78610 12-cell battery pack monitor

can be used as a stand-alone battery monitor or as a

redundant back-up device in an ASIL compliant system. It

supervises up to 12 series connected cells and features cell

voltage and temperature monitoring along with system

diagnostics.

Features

• Up to 12-cell voltage monitors with support for Li-ion CoO ,

2

Li-ion Mn O , and Li-ion FePO chemistries

2

4

• Cell voltage measurement accuracy of ±10mV

• 13-bit cell voltage measurement

The ISL78610 communicates to a host microcontroller with an

SPI interface and to other ISL78610 devices using a robust,

proprietary, two-wire daisy chain system.

• 14-bit pack voltage and temperature measurements

• Cell voltage scan rate of 19.5µs per cell (234µs to scan

12 cells)

The ISL78610 is offered in a 64 Ld TQFP package and is

specified for operation at a temperature range of -40°C to

+105°C.

• Internal and external temperature monitoring

• Up to four external temperature inputs

• Robust daisy chain communications system

• Integrated system diagnostics for all key internal functions

Applications

• Hybrid Electric Vehicle (HEV), Plug-in Hybrid Electric Vehicle

(PHEV) and Electric Vehicle (EV) battery packs

• Integrated watchdog shuts down device if communication is

lost

• Electric motorcycle battery packs

• 2Mbps SPI

• Backup battery and energy storage systems requiring high

accuracy management and monitoring

• AEC-Q100 qualified

• Portable and semiportable equipment

Related Literature

For a full list of related documents, visit our website

• ISL78610 product page

TO OTHER DEVICES (OPTIONAL)

ISL78610

VG1 VG1

VG2 VG2

DHi2

DLo2

DHi2

DLo2

DHi1

DLo1

SCLK

DOUT

DIN

HOST

CS

MICRO

DATA READY

FAULT

EN

VG1

VG2

MONITOR BOARD (Daisy Chain - Optional)

MONITOR BOARD (Master or Stand-Alone)

FIGURE 1. TYPICAL APPLICATION

FN8830 Rev 3.00

May 10, 2018

Page 1 of 100

ISL78610

Table of Contents

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Cell/V

Reading Error - 3 Sigma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reading Error - 5 Sigma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

BAT

Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Device Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

System Hardware Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Battery and Cell Balance Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Supplies and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Communications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Daisy Chain Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

External Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Typical Applications Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Operating with Reduced Cell Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Notes on Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Board Level Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Device Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Address All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Read and Write Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Scan Voltages Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Scan Temperatures Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Scan Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Scan Wires Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Scan All Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Scan Continuous Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Scan Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Measure Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Scan Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Temperature Monitoring Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Sleep Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Wake-Up Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Balance Enable Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Balance Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Manual Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Timed Balance Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Auto Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Daisy Chain Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Identify Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

ACK (Acknowledge) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

NAK (Not Acknowledge) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Non-Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FN8830 Rev 3.00

May 10, 2018

Page 2 of 100

ISL78610

Daisy Chain Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Communication Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Measurement Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Response Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

System Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Command Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Measurement Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Response Timing Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

System Diagnostics Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Hardware Fault Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

System Out of Limit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Diagnostic Activity Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Memory Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Communication Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Communication Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Daisy Chain Communications Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Loss of Signal from Host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Alarm Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Fault Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Worked Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Voltage Reference Check Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Cell Balancing – Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Cell Balancing – Timed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Cell Balancing – Auto Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Cell Voltage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Temperature Data, Secondary Voltage Reference Data, Scan Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Set-Up Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Cell Balance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Reference Coefficient Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Cells In Balance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Nonvolatile Memory (EEPROM) Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

FN8830 Rev 3.00

May 10, 2018

Page 3 of 100

ISL78610

Ordering Information

PACKAGE

(RoHS

COMPLIANT)

PART NUMBER

(Notes 2, 3)

PART

MARKING

TRIM VOLTAGE, V

(V)

TEMP. RANGE

(°C)

TAPE AND REEL

(UNITS) (Note 1)

PKG.

DWG. #

NOM

ISL78610ANZ

Evaluation Kit

3.3

-40 to +105

-

64 Ld TQFP

Q64.10x10D

ISL78610ANZ-T

ISL78610EVKIT1Z

NOTES:

1k

1. Refer to TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the ISL78610 product information page. For more information about handling and processing moisture

sensitive devices, see TB363.

TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS

INITIAL CELL MONITOR VOLTAGE ERROR

PART NUMBER

(mV) (Note 4)

ISL78610

ISL78600

NOTE:

10.0 (maximum)

2.0 (maximum)

4. Conditions: Temperature = -20°C to +60°C, V

= 2.6V to 4.0V, limits applied to a ±3 sigma distribution.

CELL

FN8830 Rev 3.00

May 10, 2018

Page 4 of 100

ISL78610

Pin Configuration

ISL78610

(64 LD 10x10 TQFP)

TOP VIEW

1

CB10

VC9

CB9

VC8

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB4

VC3

CB3

VC2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DNC

2

EN

3

DATA READY

FAULT

4

5

DGND

6

COMMS RATE 0

COMMS RATE 1

COMMS SELECT 1

COMMS SELECT 2

DNC

7

8

9

10

11

12

13

14

15

16

BASE

DNC

V3P3

V2P5

VCC

REF

Pin Descriptions

SYMBOL

PIN NUMBER

DESCRIPTION

VC0, VC1, VC2, VC3, VC4, 2, 4, 6, 8, 10, Battery cell voltage inputs. VCn connects to the positive terminal of CELLn and the negative terminal of

VC5, VC6, VC7, VC8, VC9,

VC10, VC11, VC12

12, 14, 16, CELLn+1 (VC12 connects only to the positive terminal of CELL12 and VC0 connects only to the negative

18, 20, 60, terminal of CELL1).

62, 64

CB1, CB2, CB3, CB4, CB5, 1, 3, 5, 7, 9, Cell balancing FET control outputs. Each output controls an external FET, which provides a current path

CB6, CB7, CB8, CB9, CB10, 11, 13, 15, around the cell for balancing.

CB11, CB12

17, 19, 61, 63

VBAT

VSS

58, 59

Main IC supply pins. Connect to the most positive terminal in the battery string.

Ground. Connect to the most negative terminal in the battery string.

21, 22

ExT1, ExT2, ExT3, ExT4

24, 26, 28, 30 External temperature monitor or general purpose inputs. The temperature inputs are intended for use with

external resistor networks using NTC type thermistor sense elements but can also be used as general

purpose analog inputs at the user’s discretion. 0V to 2.5V input range.

TEMPREG

29

Temperature monitor voltage regulator output. This switched 2.5V output supplies a reference voltage to

external NTC thermistor circuits to provide ratiometric ADC inputs for temperature measurement.

FN8830 Rev 3.00

May 10, 2018

Page 5 of 100

ISL78610

Pin Descriptions(Continued)

SYMBOL

PIN NUMBER

DESCRIPTION

VDDEXT

32

External V3P3 supply input/output. This pin is connected to the V3P3 pin by a switch, and can power

external circuits from the V3P3 supply. The switch is open when the ISL78610 is placed in Sleep mode.

REF

33

2.5V voltage reference decoupling pin. Connect a 2.0µF to 2.5µF X7R capacitor to VSS. Do not connect any

additional external load to this pin.

VCC

34

35

36

Analog supply voltage input. Connect to V3P3 with a 33Ω resistor. Connect a 1µF capacitor to ground.

V2P5

V3P3

Internal 2.5V digital supply decoupling pin. Connect a 1µF capacitor to DGND.

3.3V digital supply voltage input. Connect the emitter of the external NPN regulator transistor to this pin.

Connect a 1µF capacitor to DGND.

BASE

DNC

38

Regulator control pin. Connect the external NPN transistor’s base. Do not let this pin float.

37, 39, 48 Do not connect. Leave pins floating.

COMMS SELECT 1

41

Communications Port 1 mode select pin. Connect to V3P3 using a 1kΩ resistor for daisy chain

communications on Port 1 or to DGND for SPI operation on Port 1.

COMMS SELECT 2

40

Communications Port 2 mode select pin. Connect to V3P3 using a 1kΩ resistor to enable Port 2 or to DGND

to disable this port.

COMMS RATE 0,

COMMS RATE 1

43, 42

Daisy chain communications data rate setting. Connect to DGND (0) using a 1kΩ resistor or to V3P3 (1) to

select between various communication data rates.

DGND

FAULT

44

45

46

47

49

50

52

53

56

55

Digital Ground.

Logic fault output. Asserted low if a fault condition exists.

SPI data ready. Asserted low when the device is ready to transmit data to the host microcontroller.

Enable input. Tie to V3P3 to enable the part. Tie to DGND to disable (all IC functions are turned off).

Serial data output (SPI) or NC (daisy chain). 0V to 3.3V push-pull output.

Serial data input (SPI) or NC (daisy chain). 0V to 3.3V input.

Chip-select, active low 3.3V input (SPI) or daisy chain Port 1 Low connection.

Serial-Clock Input (SPI) or daisy chain Port 1 High connection.

Daisy chain Port 2 High connection.

DATA READY

EN

DOUT/NC

DIN/NC

CS/DLo1

SCLK/DHi1

DHi2

DLo2

Daisy chain Port 2 Low connection.

NC

23, 25, 27, No internal connection.

31, 51, 54, 57

FN8830 Rev 3.00

May 10, 2018

Page 6 of 100

ISL78610

Block Diagram

DHi 2

DLo 2

VBAT

SCLK/DHi 1

CS/DLo 1

DIN

DAISY

CHAIN

AND

VC12

CB12

DOUT

SPI

COMMS

DATA READY

COMMS RATE 1

COMMS RATE 0

COMMS SELECT 2

COMMS SELECT 1

DGND

VC11

CB11

VC10

CB10

FAULT

EN

VC9

CB9

VC8

CB8

BASE

V3P3

VREG

V2P5

VC7

CB7

VDDEXT

V2P5

VCC

VC6

CB6

VC5

CB5

VREF

REF

VC4

CB4

VC3

CB3

ADC

TEMPREG

VC2

CB2

TEMP MUX

VC1

CB1

ExT1

ExT2

ExT3

ExT4

VC0

VSS

FIGURE 2. BLOCK DIAGRAM

FN8830 Rev 3.00

May 10, 2018

Page 7 of 100

ISL78610

Absolute Maximum Ratings Unless otherwise

Thermal Information

specified. With respect to VSS.

BASE, DIN, SCLK, CS, DOUT, DATA READY, COMMS SELECT n,

TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n,

Thermal Resistance (Typical)

64 Ld TQFP Package (Notes 5, 6) . . . . . . .

θ

(C/W)

42

θ

(C/W)

9

JA

JC

EN, VDDEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 5.5V

ExTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2V to 4.1V

V2P5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 2.9V

VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 63V

Maximum Continuous Package Power Dissipation . . . . . . . . . . . . .400mW

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . .+125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

Dhi1, DLo1, DHi2, DLo2 . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V

+ 0.5V)

BAT

VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +9.0V

VC1, VC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +18V

VC3, VC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +27V

VC5, VC6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +36V

VC7, VC8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +45V

VC9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +54V

VC10, VC11, VC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +63V

VCn (for n = 0 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V

CBn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VBAT +0.5V

CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . V(VCn-1) -0.5V to V(VCn-1) +9V

CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn) +0.5V

Current into VCn, VBAT, VSS (Latch-Up Test) . . . . . . . . . . . . . . . . . . ±100mA

ESD Rating

Recommended Operating Conditions

T , Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

A

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 60V

(Daisy Chain Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V to 60V

BAT

V

VCn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 5V

VC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V

CBn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V(VCn-1) to V(VCn-1) + 9V

CBn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V(VCn) -9V to V(VCn)

DIN, SCLK, CS, COMMS SELECT 1, COMMS SELECT 2, V3P3, VCC,

COMMS RATE 0, COMMS RATE 1, EN. . . . . . . . . . . . . . . . . . . . . . .0V to 3.6V

ExT1, ExT2, ExT3, ExT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 2.5V

Human Body Model (Tested per AECQ100-002) . . . . . . . . . . . . . . . . 2kV

Charged Device Model (Tested per AECQ100-011) . . . . . . . . . . . . . . 2kV

Latch-Up (Tested per AEC-Q100-004; Class 2, Level A) . . . . . . . . . . 100mA

NOTE: DOUT, DATA READY and FAULT are digital outputs and should not

be driven from external sources. V2P5, REF, TEMPREG and BASE are

analog outputs and should not be driven from external sources.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5.  is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.

JA

6. For  , the “case temp” location is taken at the package top center.

JC

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent.

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 7)

TYP

(Note 7)

UNIT

MEASUREMENT SPECIFICATIONS

Cell Voltage Input Measurement

Range

V

VC(N) - VC(N-1). For design reference

0

5

V

CELL

Cell Monitor Voltage Resolution

V

[VC(N) - VC(N-1)] LSB step size (13-bit signed number),

5V full scale value

0.61

mV

CELLRES

ISL78610 Cell Monitor Voltage Error

(Absolute)

For Performance Characteristics, see

“Performance Characteristics” on

page 15

V

CELLA

Cell Measurement Error

(Cell measurement error compared with applied

voltage with 1k series resistance in line to cell input)

Temperature = +25°C, V

Temperature = +85°C, V

= 3.3V

-6.5

-25.0

-2.0

-3.0

-0.8

0.5

6.5

25.0

-0.5

-0.9

0.9

mV

µA

CELL

Cell Input Current

I

VC0 input, V

CELL

= 0.5V to 4.95V

-1

-2

0

VCELL

VC1, VC2, VC3 inputs, V

CELL

Note: Cell accuracy figures assume a

fixed 1kΩ resistor is placed in series

with each VCn pin (n = 0 to 12)

VC4 input, V

CELL

VC5, VC6, VC7, VC8, VC9, VC10, VC11 inputs,

= 0.5V to 4.95V

2

3.2

V

CELL

VC12 input, V

= 0.5V to 4.95V

0.4

1

2.0

µA

CELL

FN8830 Rev 3.00

May 10, 2018

Page 8 of 100

ISL78610

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent. (Continued)

MIN

MAX

PARAMETER

SYMBOL

VBAT

TEST CONDITIONS

(Note 7)

TYP

(Note 7)

UNIT

mV

V

Monitor Voltage Resolution

ADC resolution referred to input (V ) level. 14b

BAT

4.863

BAT

RES

unsigned number. Full scale value = 79.67V.

Monitor Voltage Error

V

BAT

Temperature = +25°C,

-120

-320

120

320

mV

V

BAT

Measured at V

BAT

= 39.6V

Temperature = +85°C,

Measured at V = 39.6V

BAT

External Temperature Monitoring

Regulator

V

Voltage on TEMPREG output (0 to 2mA load)

2.475

2.500

0.1

2.525

TEMP

External Temperature Output

Impedance

R

Output impedance at TEMPREG pin

Ω

TEMP

External Temperature Input Range

External Temperature Input Pull-Up

V

ExTn input voltage range. For design reference

0

2344

mV

EXT

R

Pull-up resistor to V

applied to each input

10

MΩ

EXTTEMP

TEMPREG

during measurement

External Temperature Input Offset

External Temperature Input INL

V

= 39.6V

-12

12

mV

EXTOFF

BAT

V

±0.3

±8

EXTINL

External Temperature Input Gain Error

Internal Temperature Monitor Error

V

18.5

mV

EXTG

V

±10

31.9

°C

INTMON

Internal Temperature Monitor

Resolution

T

Output resolution (LSB/°C). 14b number

Output count at +25°C

LSB/°C

INTRES

Internal Temperature Monitor Output

Power-Up Specifications

T

9180

Decimal

INT25

Power-Up Condition Threshold

Power-Up Condition Hysteresis

Initial Power-Up Delay

V

voltage (rising)

4.8

5.1

5.6

V

POR

BAT

V

400

mV

ms

PORhys

t

Time after VPOR condition

from 0V to 0.95 x V

27.125

POR

V

(nom) (EN tied to V3P3)

REF

Device can now communicate

Enable Pin Power-Up Delay

t

Delay after EN = 1 to V from

27.125

ms

PUD

REF

(nom)

0V to 0.95 x V

REF

= 39.6V) - Device can now communicate

(V

BAT

FN8830 Rev 3.00

May 10, 2018

Page 9 of 100

ISL78610

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 7)

TYP

(Note 7)

UNIT

Supply Current Specifications

V

BAT

Supply Current

I

Non-daisy chain configuration. Device

enabled. No communications, ADC,

measurement, or open-wire detection activity

6V

39.6V

60V

35

64

µA

mA

µA

mA

µA

mA

µA

VBAT

10

73

96

I

Daisy chain configuration – master device.

Enabled. No communications, ADC,

measurement, or open-wire detection activity

6V

530

680

750

18

VBATMASTER

39.6V

60V

550

1000

Peak current when daisy chain transmitting

I

Daisy chain configuration – mid stack device.

Enabled. No communications, ADC,

measurement, or open-wire detection activity

6V

39.6V

60V

1020

1250

1400

18

VBATMID

1000

1700

Peak current when daisy chain transmitting

I

Daisy chain configuration – top device.

Enabled. No communications, ADC,

measurement, or open-wire detection activity

6V

39.6V

60V

530

680

750

18

VBATTOP

550

1000

Peak current when daisy chain transmitting

I

Sleep mode

(EN = 1, daisy chain configuration)

20

13

6

35

50

VBATSLEEP1

I

Sleep mode

(EN = 1, stand-alone, non-daisy chain)

20

15

µA

VBATSLEEP2

I

Shutdown. device “off” (EN = 0)

(Daisy chain and non-daisy chain configurations)

54

VBATSHDN

V

BAT

Supply Current Tracking. Sleep

I

EN = 1, daisy chain Sleep mode configuration.

0

10.5

VBATΔSLEEP

Mode

V

current difference between any two devices

BAT

operating at the same temperature and supply voltage

V3P3 Regulator Voltage (Normal)

V3P3 Regulator Voltage (Sleep)

V3P3 Supply Current

V

EN = 1, Load current range 0 to 5 mA

3.2

0.7

3.35

2.7

1

3.5

1.3

V

3P3N

V

= 39.6V

BAT

EN = 1, Load current range, no load, (SLEEP)

= 39.6V

V

3P3S

V

BAT

I

Device Enabled

mA

V3P3

No measurement activity, normal mode

V

Reference Voltage

V

EN = 1, no load, normal mode

2.5

12

V

Ω

REF

VDDEXT Switch Resistance

VCC Supply Current

R

Switch “On” resistance, V = 39.6V

BAT

VDDEXT

I

Device enabled (EN = 1). Stand-alone or daisy

configuration. No ADC or daisy chain communications

active

2.00

3.25

5.00

mA

VCC

I

Device enabled (EN = 1). Stand-alone or daisy

configuration. Average current during 16ms Scan

6.0

mA

VCCACTIVE1

Continuous operation. V

= 39.6V

BAT

I

Device enabled (EN = 1). Sleep mode. V

BAT

= 39.6V

2.4

1.2

µA

VCCSLEEP

I

Device disabled (EN = 0). Shutdown mode

0

9.0

VCCSHDN

FN8830 Rev 3.00

May 10, 2018

Page 10 of 100

ISL78610

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 7)

TYP

150

(Note 7)

UNIT

Over-Temperature Protection Specifications

Internal Temperature Limit Threshold

T

Balance stops and auto scan stops.

Temperature rising or falling

°C

INTSD

External Temperature Limit Threshold

T

Corresponding to 0V (minimum) and V

(maximum)

0

16383

Decimal

XT

TEMPREG

External temperature input voltages higher than

15/16 V are registered as open input faults

TEMPREG

Fault Detection System Specifications

Undervoltage Threshold

V

Programmable. Corresponding to 0V (minimum) and

5V (maximum)

0

8191

Decimal

UV

Overvoltage Threshold

V

Programmable. Corresponding to 0V (minimum) and

5V (maximum)

Decimal

OV

V3P3 Power-Good Window

V

3.3V power-good window high threshold.

3.90

2.65

2.7

V

3PH

V

= 39.6V

BAT

3.3V power-good window low threshold.

= 39.6V

V

3PL

V

BAT

2.5V power-good window high threshold.

= 39.6V

V2P5 Power-Good Window

VCC Power-Good Window

V

2PH

V

BAT

V

2.5V power-good window low threshold.

2.0

2PL

V

= 39.6V

BAT

V

power-good window high threshold.

3.75

2.7

VCCH

CC

= 39.6V

BAT

V

VCC power-good window low threshold.

VCCL

V

= 39.6V

BAT

V

Power-Good Window

V

power-good window high threshold.

= 39.6V

2.7

REF

RPH

REF

BAT

V

power-good window low threshold.

= 39.6V

2.30

2.500

RPL

REF

BAT

Reference Accuracy Test

V

value calculated using stored coefficients.

= 39.6V

RACC

REF

BAT

(See “Voltage Reference Check Calculation” on

page 80)

Voltage Reference Check Timeout

Oscillator Check Timeout

t

Time to check voltage reference value from

power-on, enable, or wake-up

20

ms

VREF

t

Time to check main oscillator frequency from

power-on, enable, or wake-up

OSC

Oscillator Check Filter Time

Fast Oscillator

t

Minimum duration of fault required for detection

Oscillator frequency

100

4

ms

MHz

kHz

OSCF

3.4

4.6

Slow Oscillator

Oscillator frequency

27.2

32

36.8

Cell Open-Wire Detection (See “Scan Wires Command” on page 41 and “Open-wire Test” on page 74)

Open-Wire Current

I

ISCN bit = 0; V

ISCN bit = 1; V

= 39.6V

0.125

0.85

0.150

1.00

4.6

0.185

1.15

mA

ms

V

OW

BAT

Open-Wire Detection Time

t

Open-wire current source “on” time

OW

Open VC0 Detection Threshold

V

CELL1 negative terminal (with respect to VSS)

1.2

1.5

1.8

VC0

V

= 39.6V (Note 8)

BAT

FN8830 Rev 3.00

May 10, 2018

Page 11 of 100

ISL78610

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 7)

TYP

0.7

(Note 7)

UNIT

V

Open VC1 Detection Threshold

V

CELL1 positive terminal (with respect to VSS)

0.6

0.8

0

VC1

V

= 39.6V (Note 8)

BAT

V(VC(n - 1)) - V(VCn), n = 2 to 12

= 39.6V (Note 8)

Primary Detection Threshold, VC2 to

VC12

V

-2

-1.5

-30

V

VC2_12P

V

BAT

Via ADC. VC2 to VC12 only

= 39.6V (Note 8)

Secondary Detection Threshold, VC2 to

VC12

V

-100

50

mV

VC2_12S

V

BAT

Open V

BAT

Fault Detection Threshold

V

VC12 - V

200

250

mV

VBO

BAT

Open VSS Fault Detection Threshold

Cell Balance Output Specifications

Cell Balance Pin Output Impedance

V

VSS - VC0

VSSO

R

CBn output off impedance

2

4

5

MΩ

CBL

between CB(n) to VC(n-1): Cells 1 to 9 and

between CB(n) to VC(n): Cells 10 to 12

Cell Balance Output Current

I

CBn output on. (CB1 - CB9); V

device sinking current

= 39.6V;

BAT

-28

21

-25

25

-21

28

μA

nA

V

CBH1

I

CBn output on. (CB10 - CB12); V

device sourcing current

= 39.6V;

BAT

CBH2

Cell Balance Output Leakage in

Shutdown

I

EN = GND. V

BAT

= 39.6V

-500

7.04

10

700

8.96

CBSD

External Cell Balance FET Gate Voltage

VGS

CBn Output on;

8.00

External 320kΩ between VCn and CBn

(n = 10 to 12) and between CBn and VCn-1

(n = 1 to 9)

Internal Cell Balance Output Clamp

Logic Inputs: SCLK, CS, DIN

Low Level Input Voltage

High Level Input Voltage

Input Hysteresis

VCBCL

I

= 100µA

8.94

V

CB

V

0.8

V

IL

V

1.75

-1

IH

V

250

mV

µA

pF

HYS

Input Current

I

0V < V < V3P3

IN

1

IN

Input Capacitance (Note 8)

C

10

IN

Logic Inputs: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1

Low Level Input Voltage

High Level Input Voltage

Input Hysteresis

V

0.3*V3P3

V

IL

V

0.7*V3P3

0.05*V3P3

-1

IH

V

(Note 8)

V

HYS

Input Current

I

0V < V < V3P3

IN

1

µA

pF

IN

Input Capacitance (Note 8)

Logic Outputs: DOUT, FAULT, DATA READY

Low Level Output Voltage

C

10

IN

V

At 3mA sink current

At 6mA sink current

At 3mA source current

At 6mA source current

0

0.4

0.6

V

OL1

V

0

OL2

High Level Output Voltage

V

V3P3 – 0.4

V3P3 – 0.6

V3P3

OH1

V

OH2

SPI Interface Timing See Figures 3 and 4

SCLK Clock Frequency

f

2

MHz

SCLK

FN8830 Rev 3.00

May 10, 2018

Page 12 of 100

ISL78610

Electrical Specifications

V

= 6 to 60V, T = -20°C to +85°C, unless otherwise specified. Biasing setup as in

A

BAT

Figure 45 on page 26 or equivalent. (Continued)

MIN

MAX

PARAMETER

Pulse Width of Input Spikes Suppressed

Enable Lead Time

SYMBOL

TEST CONDITIONS

(Note 7)

TYP

(Note 7)

UNIT

ns

t

50

200

IN1

t

Chip select low to ready to receive clock data

200

LEAD

Clock High Time

t

200

HIGH

Clock Low Time

t

200

LOW

Enable Lag Time

t

Last data read clock edge to Chip Select high

Chip Select low to DOUT active

250

LAG

Slave Access Time

t

200

350

A

Data Valid Time

t

Clock low to DOUT valid

V

Data Output Hold Time

DOUT Disable Time

Data Setup Time

t

Data hold time after falling edge of SCLK

DOUT disabled following rising edge of CS

Data input valid prior to rising edge of SCLK

0

HO

t

240

DIS

t

100

80

SU

Data Input Hold Time

t

Data input to remain valid following rising edge of

SCLK

HI

Data Ready Start Delay Time

Data Ready Stop Delay Time

Data Ready High Time

t

Minimum chip select high to Data Ready low

Maximum chip select high to Data Ready high

Minimum time between bytes

100

750

1.0

ns

µs

ns

µs

DR:ST

t

DR:SP

t

DR:WAIT

Chip Select High Time

t

Minimum high time for CS between bytes

200

100

CS:WAIT

SPI Communications Timeout

t

Maximum time the CS remains high before SPI

communications time out - requiring the start of a new

command

SPI:TO

DOUT Rise Time

DOUT Fall Time

t

Up to 50pF load

30

ns

R

t

F

Daisy Chain Communications Interface: DHi1, DLo1, DHi2, DLo2

Daisy Chain Clock Frequency

Comms Rate (0, 1) = 11

450

225

500

250

125

62.5

550

275

kHz

V

Comms Rate (0, 1) = 10

Comms Rate (0, 1) = 01

Comms Rate (0, 1) = 00

112.5

56.25

137.5

68.75

Common-Mode Reference Voltage

NOTES:

V

/2

BAT

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. Limits are 100% tested, unless

declared otherwise.

8. These MIN and/or MAX values are based on characterization data and are not 100% tested.

9. Stresses may be induced in the ISL78610 during soldering or other high temperature events that affect measurement accuracy. Initial accuracy does

not include effects due to this. See Figure 8 on page 16 for cell reading accuracy obtained after soldering to Renesas evaluation boards. When

soldering the ISL78610 to a customized circuit board with a layout or construction significantly differing from the Renesas evaluation board, design

verification tests should be applied to determine drift due to soldering and over lifetime.

FN8830 Rev 3.00

May 10, 2018

Page 13 of 100

ISL78610

Timing Diagrams

CS

(FROM µC)

t

SPI:TO

t

CS:WAIT

t

LOW

t

LEAD

HIGH

LAG

SCLK

(FROM µC)

t

DIS

HO

F

t

A

V

DOUT

(TO µC)

t

R

t

HI

SU

DIN

(FROM µC)

CLOCK DATA INTO

ISL78610

CLOCK DATA OUT OF

ISL78610

FIGURE 3. SPI FULL DUPLEX (4-WIRE) INTERFACE TIMING

t

CS:WAIT

CS

(FROM µC)

t

SPI:TO

t

DR:WAIT

DR:SP

DATA READY

(TO µC)

SCLK

(FROM µC)

t

A

DIS

DOUT

(TO µC)

CLOCK DATA OUT OF

ISL78610

SIGNALS ON DIN IGNORED

WHILE DATA READY IS LOW

DIN

(FROM µC)

CLOCK DATA INTO

ISL78610

FIGURE 4. SPI HALF DUPLEX (3-WIRE) INTERFACE TIMING

FN8830 Rev 3.00

May 10, 2018

Page 14 of 100

ISL78610

Performance Characteristics

Cell/V

Reading Error - 3 Sigma

BAT

-3 SIGMA

(Note 10)

+3 SIGMA

(Note 10)

PARAMETER

SYMBOL

TEST CONDITIONS

Temperature = +25°C

TYP

UNIT

mV

ISL78610 Initial Cell Reading V

Error (Absolute)

CELLA

V

= 3.3V

-3.2

-10

3.2

10

CELL

Limits applied to a ±3 sigma distribution

Temperature = -20°C to +60°C

V

= 2.6V to 4.0V

mV

CELL

Limits applied to a ±3 sigma distribution

Temperature = -40°C to -20°C

V

= 2.6V to 4.0V

-15

15

CELL

Limits applied to a ±3 sigma distribution

Temperature = +60°C to +85°C

V

= 2.6V to 4.0V

-15

15

CELL

Limits applied to a ±3 sigma distribution

ISL78610InitialV

Error (Absolute)

Reading

V

BAT

Temperature = -20°C to +60°C

BAT

V

= 31.2V to 48V

-175

-300

175

300

BAT

Limits applied to a ±3 sigma distribution

Temperature = -40°C to +105°C

V

= 31.2V to 48V

BAT

Limits applied to a ±3 sigma distribution

Voltage Reference Long Term

Drift

-0.31

TYP

mV/

log (days)

Cell/V

Reading Error - 5 Sigma

BAT

-5 SIGMA

(Note 10)

+5 SIGMA

(Note 10)

PARAMETER

SYMBOL

V

TEST CONDITIONS

Temperature = +25°C

UNIT

mV

ISL78610 Initial Cell Monitor

Voltage Error (Absolute)

CELLA

V

= 3.3V

-5

5

CELL

Limits applied to a ±5 sigma distribution

Temperature = -20°C to +60°C

V

= 2.6V to 4.0V

-12

12

mV

CELL

Limits applied to a ±5 sigma distribution

Temperature = -40°C to -20°C

V

= 2.6V to 4.0V

-20

20

CELL

Limits applied to a ±5 sigma distribution

Temperature = +60°C to +85°C

V

= 2.6V to 4.0V

-25

25

CELL

Limits applied to a ±5 sigma distribution

Temperature = +85°C to +105°C

V

= 2.6V to 4.0V

-45

45

CELL

Limits applied to a ±5 sigma distribution

ISL78610InitialV

Error (Absolute)

Reading

V

BAT

Temperature = -20°C to +60°C

V

Limits applied to a ±5 sigma distribution

BAT

= 31.2V to 48V

-250

-425

250

425

BAT

Temperature = -40°C to +105°C

V

= 31.2V to 48V

BAT

Limits applied to a ±5 sigma distribution

NOTE:

10. These distribution values are based on characterization of devices mounted on evaluation boards and are not 100% tested.

FN8830 Rev 3.00

May 10, 2018

Page 15 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards.

20

15

10

5

50

40

30

20

10

0

-10

-20

-30

-40

-50

-5

-10

-15

-20

0.5

2.6

3

3.3

3.6

4

4.5

-40

-20

0

20

40

60

80

100

120

CELL VOLTAGE (V)

TEMPERATURE (^oC)

FIGURE 5. CELL VOLTAGE READING ERROR FROM -20°C TO +60°C

FIGURE 6. CELL VOLTAGE READING ERROR 3.0V TO 3.6V PER CELL

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

35

30

25

20

15

10

5

0.0

0

-1.5 -1 -0.5

0

0.5

1

1.5

2

2.5

3

3.5

-4 -3 -2 -1

0

1

2

3

4

5

6

7

8

9

10

READING ERROR (mV)

FIGURE 7. INITIAL CELL VOLTAGE ACCURACY FROM EVALUATION

BOARDS AT 3.3V, +25°C HISTOGRAM

FIGURE 8. CELL READING ERROR FROM EVALUATION BOARDS AT

CELL VOLTAGE FROM 2.6V TO 4.0V, AND -20°C TO

+60°C HISTOGRAM

300

180

160

140

120

100

80

101

104

107

110

102

105

108

103

106

109

250

200

150

100

50

60

40

20

0

6V

31.2V

39.6V

48V

0

-20

-40

-60

-50

-100

-150

36V

43.2V

54V

-40

10

60

TEMPERATURE (^oC)

110

160

0

5

10 15 20 25 30 35 40 45 50 55 60

PACK VOLTAGE (V)

FIGURE 10. AVERAGE PACK VOLTAGE READING ERROR AT 6V TO 54V

PACK VOLTAGE

FIGURE 9. PACK VOLTAGE READING ERROR AT +25°C

(MULTIPLE BOARDS)

FN8830 Rev 3.00

May 10, 2018

Page 16 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued)

30.0

25.0

20.0

15.0

10.0

5.0

5.00

4.00

3.00

2.00

1.00

0.00

-1.00

-2.00

-3.00

-4.00

-5.00

6V

31.2V

39.6V

48V

36V

43.2V

54V

0.0

-140 -100 -60

-20

20

60

100

140

180

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (^oC)

READING ERROR (mV)

FIGURE 11. INITIAL PACK VOLTAGE ACCURACY 31.2V TO 48V,

-20°C TO +60°C HISTOGRAM

FIGURE 12. IC TEMPERATURE READING ERROR vs TEMPERATURE

0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

5.00

6V

31.2V

39.6V

48V

4.00

3.00

36V

43.2V

54V

2.00

1.00

0.00

-1.00

-2.00

-3.00

-4.00

-5.00

0.001

0.01

0.1

1.0

10.0

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (^oC)

YEARS

FIGURE 13. VOLTAGE REFERENCE CHECK VOLTAGE ERROR OVER

VBAT = 6V TO 54V AND TEMPERATURE

FIGURE 14. LONG TERM DRIFT

25.60

25.55

25.50

25.45

25.40

25.6

V

= 3.3V

CELL

25.4

25.2

25.0

24.8

24.6

24.4

24.2

0

10

20

30

40

50

60

-40

-20

0

20

40

60

80

100

PACK VOLTAGE (V)

TEMPERATURE (°C)

FIGURE 15. BALANCE CURRENT vs PACK VOLTAGE

FIGURE 16. BALANCE CURRENT vs TEMPERATURE

FN8830 Rev 3.00

May 10, 2018

Page 17 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued)

975

970

965

960

955

950

1000

980

960

940

920

900

880

860

840

820

800

TEMPERATURE = +25°C

V

= 3.3V

CELL

-40

-20

0

20

40

60

80

100

120

0

10

20

30

40

50

60

TEMPERATURE ( ^oC )

PACK VOLTAGE (V)

FIGURE 17. OPEN-WIRE TEST CURRENT vs TEMPERATURE

(1mA SETTING)

FIGURE 18. OPEN-WIRE TEST CURRENT vs PACK VOLTAGE

(1mA SETTING)

160

159

158.6

158.4

TEMPERATURE = +25°C

V

= 3.3V

CELL

158

157

156

155

154

153

152

158.2

158

157.8

157.6

157.4

157.2

157

-40

-20

0

20

40

60

80

100

120

0

10

20

30

40

50

60

TEMPERATURE ( ^oC )

PACK VOLTAGE (V)

FIGURE 19. OPEN-WIRE TEST CURRENT vs TEMPERATURE

(150µA SETTING)

FIGURE 20. OPEN-WIRE TEST CURRENT vs PACK VOLTAGE

(150µA SETTING)

4.05

4.045

4.040

V

= 39.6V

BAT

4.00

3.95

3.90

3.85

3.80

3.75

3.70

V

= 39.6V

BAT

4.035

4.030

4.025

4.020

4.015

4.010

4.005

4.000

-40

-20

0

20

40

60

80

100

120

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

TEMPERATURE ( ^oC )

VCC (V)

FIGURE 21. 4MHz OSCILLATOR FREQUENCY vs TEMPERATURE

FIGURE 22. 4MHz OSCILLATOR FREQUENCY vs V

CC

FN8830 Rev 3.00

May 10, 2018

Page 18 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued)

31.60

31.40

31.20

31.00

30.80

30.60

30.40

30.20

30.00

29.80

31.35

31.30

31.25

31.20

31.15

31.10

31.05

31.00

V

= 39.6V

BAT

V

= 39.6V

BAT

-40

-20

0

20

40

60

80

100

120

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

TEMPERATURE ( ^oC )

VCC (V)

FIGURE 23. 32kHz OSCILLATOR FREQUENCY vs TEMPERATURE

FIGURE 24. 32kHz OSCILLATOR FREQUENCY vs V

CC

60

80

70

60

50

40

30

20

10

0

50

40

30

20

10

0

V

= 60V

BAT

V

= 60V

BAT

V

= 39.6V

BAT

V

= 39.6V

BAT

V

= 6V

BAT

80

V

= 6V

80

BAT

-40

-20

0

20

40

60

100

120

-40

-20

0

20

40

60

100

120

TEMPERATURE (^oC )

TEMPERATURE ( ^oC )

FIGURE 25. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (STAND-ALONE MODE)

FIGURE 26. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN MASTER)

80

70

60

80

70

60

V

= 60V

BAT

V

= 60V

BAT

50

40

30

20

10

0

50

40

30

20

10

0

V

= 39.6V

BAT

V

= 39.6V

BAT

V

= 6V

BAT

V

= 6V

BAT

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (^oC )

FIGURE 27. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN MIDDLE)

FIGURE 28. PACK VOLTAGE SLEEP CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN TOP)

FN8830 Rev 3.00

May 10, 2018

Page 19 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued)

750

700

650

600

550

500

450

100

95

90

85

80

75

70

65

60

55

50

V

= 60V

BAT

V

= 60V

V

= 39.6V

BAT

V

= 6V

BAT

V

= 6V

BAT

V

0

= 39.6V

20

BAT

-40

-20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (^oC )

FIGURE 30. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN MASTER)

FIGURE 29. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (STAND-ALONE MODE)

1450

750

V

= 60V

BAT

V

= 60V

BAT

1350

1250

1150

1050

950

700

650

600

550

500

450

V

= 39.6V

BAT

V

= 39.6V

BAT

V

= 6V

80

BAT

V

= 6V

80

BAT

850

-40

-20

0

20

40

60

100

120

-40

-20

0

20

40

60

100

120

TEMPERATURE (^oC )

FIGURE 31. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN MIDDLE)

FIGURE 32. PACK VOLTAGE SUPPLY CURRENT vs TEMPERATURE AT

6V, 39.6V, 60V (DAISY CHAIN TOP)

3.45

3.40

3.35

3.25

3.20

3.15

3.10

3.05

3.00

2.95

2.90

60

50

40

30

V

= 60V

V

= 39.6V

BAT

20

10

0

V

= 6V

80

BAT

-60

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

100

120

TEMPERATURE (^oC )

TEMPERATURE (°C)

FIGURE 33. PACK VOLTAGE SHUTDOWN CURRENT vs TEMPERATURE

(EN = 0) AT 6V, 39.6V, 60V

FIGURE 34. V SUPPLY CURRENT vs TEMPERATURE AT

CC

6V, 39.6V, 60V

FN8830 Rev 3.00

May 10, 2018

Page 20 of 100

ISL78610

Performance Curves These performance curves are based on characterization of devices mounted on evaluation boards. (Continued)

2.5

2.0

1.5

1.0

0.5

0

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

V

= 3.3V

VC5

VC8

CELL

VC6

VC11

VC10

VC7

VC9

VC12

VC4

VC0

39.6V

60V

-0.5

-1.0

-1.5

-2.0

-2.5

6V

VC3

-20

VC2

0

VC1

-40

-20

0

20

40

60

80

100

-40

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 35. V3P3 SUPPLY CURRENT vs TEMPERATURE

FIGURE 36. CELL INPUT CURRENT vs TEMPERATURE

2.5

VC11

2.0

VC10

VC9

1.5

1.0

VC8

VC7

VC6

VC5

VC12

0.5

VC4

VC0

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

VC3

VC2

VC1

0

10

20

30

40

50

60

PACK VOLTAGE (V)

FIGURE 37. CELL INPUT CURRENT vs PACK VOLTAGE (+25°C)

FN8830 Rev 3.00

May 10, 2018

Page 21 of 100

ISL78610

The ISL78610 incorporates extensive fault diagnostics functions

including cell overvoltage and undervoltage, regulator and

oscillator operation, open cell input detection, and

communication faults. The current status of most faults is

accessible using the ISL78610 registers. Some communication

faults are reported by special responses to system commands

and some as “unprompted” responses from the device detecting

the fault to the host microcontroller through the daisy chain.

Device Description and

Operation

The ISL78610 is a Li-ion battery manager IC that supervises up

to 12 series connected cells. Up to 14 ISL78610 devices can be

connected in series to support systems with up to 168 cells. The

ISL78610 provides accurate monitoring, cell balance control,

and diagnostic functions. The ISL78610 includes a voltage

reference, 14-bit A/D converter, and registers for control and

data.

To conserve power, the ISL78610 has three main power modes:

Normal mode, Sleep mode, and “off” (Shutdown mode).

When multiple ISL78610 devices are connected to a series of

cells, their power supply domains are normally non-overlapping.

The lower (VSS) supply of each ISL78610 nominally connects to

The devices enters Sleep mode in response to a Sleep command

or after a watchdog timeout (see “Watchdog Function” on

page 76). Only the communications input circuits, low speed

oscillator, and internal registers are active in Sleep mode,

allowing the part to perform timed scan and balancing activity

and to wake up in response to communications.

the same potential as the upper (V ) supply of the ISL78610

BAT

device below.

Within each device, the cell voltage monitoring system has two

basic elements: a level shift to eliminate the cell common-mode

voltage and an analog-to-digital conversion of the cell voltage.

The device is in Shutdown mode when the Enable pin is low. In

this mode, the internal bias for most of the IC is powered down

except digital core, Sleep mode regulators, and digital input

buffers. When exiting, the device powers up and does not reload

the factory programmed configuration data from the EEPROM.

Each ISL78610 is calibrated at a specific cell input voltage value,

V

. Cell voltage measurement error data is given in

NOM

“MEASUREMENT SPECIFICATIONS” on page 8 for various voltage

and temperature ranges with voltage ranges defined with

Normal mode consists of an Active state and a Standby state. In

the Standby state, all systems are powered and the device is

ready to perform an operation in response to commands from

the host microcontroller. In the Active state, the device is

performing an operation, such as ADC conversion, open-wire

detection, etc.

respect to V

. Plots showing the typical error distribution over

NOM

the full input range are included in the “Performance Curves”

section beginning on page 16.

To collect cell voltage and temperature measurements, the

ISL78610 provides two multiple parameter measurement

“scanning” modes in addition to single parameter direct

measurement capability. The scanning modes provide pseudo

simultaneous measurement of all cell voltages in the stack.

System Hardware Connection

Battery and Cell Balance Connection

The first consideration in designing a battery system around the

ISL78610 is the connection of the cells to the IC.

The ISL78610 does not measure current. The system does this

separately using other measurement systems.

The only filtering applied to the ADC measurements is that

resulting from external protection circuits and the limited

bandwidth of the measurement path. No additional filtering is

performed within the part. This arrangement is typically needed

to maintain timing integrity between the cell voltage and pack

current measurements. However, the ISL78610 does apply

filtering to the fault detection systems.

The battery connection elements are split between the cell

monitor connections (VCn) and the cell balance connections

(CBn).

BATTERY CONNECTION

All inputs to the ISL78610 VCn pins are protected against battery

voltage transients by external RC filters. The basic input filter

structure, with capacitors to the local ground, provides protection

against transients and EMI for the cell inputs. They carry the loop

currents produced by EMI and should be placed as close to the

battery connector as possible. The ground terminals of the

capacitors must be connected directly to a solid ground plane. Do

not use vias to connect these capacitors to the input signal path

or to ground. Any vias should be placed in line to the signal inputs

so that the inductance of these forms a low pass filter with the

grounded capacitors.

Cell balancing is an important function in a battery pack

consisting of a stack of multiple Li-ion cells. As the cells charge

and discharge, differences in each cell’s ability to take on and

give up charge typically leads to cells with different states of

charge. The problem with a stack of cells having different states

of charge is that Li-ion cells have a maximum voltage above

which it should not be charged, and a minimum voltage below

which it should not be discharged. Extreme cases, in which one

cell in the stack is at the maximum voltage and one cell is at the

minimum voltage, result in a nonfunctional battery stack,

because the battery stack cannot be charged or discharged.

The resistors on the input filter provide a current limit function

during hot plug events. The ISL78610 is calibrated for use with 1kΩ

series protection resistors at the VCn inputs. The VBAT connection

uses a lower value input resistor to accommodate the supply current

of the ISL78610. As much as possible, the time constant produced

by the filtering applied to VBAT should be matched to that applied to

the VCn monitoring inputs. See Figure 38.

The ISL78610 provides multiple cell balance modes: Manual

Balance mode, Timed Balance mode, and Auto Balance mode.

These modes are described in more detail in “Alarm Response”

on page 76.

FN8830 Rev 3.00

May 10, 2018

Page 22 of 100

ISL78610

might affect the accuracy of the cell voltage readings. Second, if

the single wire breaks, it is very difficult for the system to tell

specifically what happened through normal diagnostic methods.

LOCATE CLOSE

TO INPUT CONNECTOR

ISL78610

VBAT

27

B14b

C

58V*

VSS

1

An alternative circuit in Figure 40 shows the connection of one

(or two) wires with additional Schottky diodes to provide supply

current paths to allow the device to detect a connection fault and

to minimize the effects on cell voltage measurements when

there is an open connection to the battery.

*EXAMPLE DIODE:

PTVS58VS1UTR

180

820

B12

VC12

22nF

180

820

B11

B10

VC11

VC10

ISL78610

100

820

22nF

820

VC2

VSS2

820

22nF

VC1

22nF

820

180

820

VC9

B9

VSS2

22nF

VC0

22nF

VSS2

820

22nF

820

180

B3

B2

VC3

VC2

ISL78610

VBAT

27

C

1

VSS

100

VSS

22nF

820

VC12

180

820

VC1

B1

22nF

820

22nF

100

VC11

VSS

820

B0

VC0

VSS

22nF

B0b

= “QUIET” GROUND

= “NOISY” GROUND

FIGURE 39. BATTERY CONNECTION BETWEEN STACKED DEVICES

(OPTION 1)

CELL BALANCE CIRCUITS NOT SHOWN IN THIS FIGURE

ISL78610

FIGURE 38. TYPICAL INPUT FILTER CIRCUITS

180

820

22nF

VC2

The filtered battery voltage connects to the internal cell voltage

monitoring system. The monitoring system comprises three basic

elements; a level shifter to eliminate the cell common-mode

voltage, a multiplexer to select a specific input, and an

analog-to-digital conversion of the cell voltage.

VSS2

820

VC1

22nF

820

VSS2

VC0

Each ISL78610 is calibrated at a specific cell input voltage value,

22nF

V

with an expected input series resistance of 1kΩ. Cell voltage

VSS2

NOM

measurement error data is given in “MEASUREMENT

SPECIFICATIONS” on page 8 for various voltage and temperature

ISL78610

ISL78714

VBAT

27

C

ranges with voltage ranges defined with respect to V

. Plots

1

NOM

VSS

180

showing the typical error distribution over the full input range are

included in the “Performance Curves” section beginning on

page 16.

VSS

820

VC12

VC11

22nF

Another important consideration is the connection of cells in a

stacked (non-overlapping) configuration. This mainly involves

connecting the supply and ground pins at the junction of two

devices. The diagram in Figure 39 shows the recommended

minimum connection to the pack. Renesas recommends using

four connection wires at the intersection of two devices, but this

does pose a cost constraint. To minimize the connections, the

power and monitor pins are connected separately, as shown in

Figure 39. Do not connect all four wires together with a single

wire to the pack - first, the power supply current for the devices

VSS

180

820

22nF

FIGURE 40. BATTERY CONNECTION BETWEEN STACKED DEVICES

(OPTION 2)

FN8830 Rev 3.00

May 10, 2018

Page 23 of 100

ISL78610

Figures 41 and 42 show the circuit detail for the recommended

balancing and cell voltage monitoring system. In this

CELL BALANCE CONNECTION

The ISL78610 uses external MOSFETs for cell balancing. The gate

drive for these is derived from on-chip current sources on the

ISL78610, which are 25µA nominally. The current sources are

turned on and off as needed to control the external MOSFET

devices. The current sources are turned off when the device is in

Shutdown mode or Sleep mode. The ISL78610 uses a mix of

N-channel and P-channel MOSFETs for the external balancing

function. The top three cell locations, Cells 10, 11, and 12 are

configured to use P-channel MOSFETs, while the remaining cell

locations, Cells 1 through 9, use N-channel MOSFETs. The mix of

N-channel and P-channel devices are used for the external FETs

in order to remove the need for a charge pump, while providing a

balance FET gate voltage that is sufficient to drive the FET on,

regardless of the cell voltages.

configuration, the cell voltage is monitored after the cell balance

resistor. This allows the system to monitor the operation of the

external balance circuits and is part of the fault detection

system. However, this connection prevents monitoring the cell

voltage while cell balance is enabled for that cell.

Figure 41 shows the connection for VC12 to VC9. This connection

for the upper three cells uses P-channel FETs, while VC9 and

below use N-channel FETs. Similarly, Figure 42 shows the

connection for VC1 to VC3 using an N-channel FETs. The

connections for VC3 through VC9 are similar. See Figure 51 on

page 31 for a more complete example.

R2

R5

VC12

22nF

C3

R5

R3

4MΩ

C1

C2

R1

9V

VC3

CB3

100Ω

22nF

C3

C2

C1

Q1

CB12

10kΩ

R3

25µA

100Ω

R5

Q2

VC11

10kΩ

R1

22nF

C3

4MΩ

C1

C2

R1

9V

R5

R3

Q1

100Ω

CB11

10kΩ

R3

VC2

CB2

25µA

100Ω

22nF

C3

R5

C2

C1

VC10

25µA

22nF

C3

4MΩ

Q2

10kΩ

R1

C1

C2

R1

9V

Q1

100Ω

4MΩ

CB10

10kΩ

25µA

9V

R3

R4

R6

R5

VC9

VC1

CB1

100Ω

22nF

C3

C2

C1

100Ω

Q2

R4

25µA

C2

C1

22nF

C3

25µA

Q2

CB9

10kΩ

R1

R2

4MΩ

9V

R5

4MΩ

9V

VC0

VSS

22nF

R3

R5

VC8

100Ω

22nF

ISL78610

FIGURE 41. CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT

(VC8 TO VC12)

FIGURE 42. CELL MONITOR AND BALANCE CIRCUIT ARRANGEMENT

(VC0 TO VC3)

TABLE 2. ISL78610 INPUT FILTER COMPONENT OPTIONS

Q1 (P-channel)

with examples

Q2 (N-channel)

with examples

C1

C2

C3

R1

R2

R3

R4

R5

R6

30V

60V

A&O Semi AO3401

Fairchild FDN5618

30V

60V

A&O Semi AO3402

Diodes DMN6140L-7

1nF

10nF Not populated 100k 820 720 1.54k 180 360

10nF 100nF 100k 100 910 1900

0

Not needed 10nF Not populated 330k 820 720 1.54k 180 360

Not needed 10nF 100nF 330k 100 910 1900

0

Note: Q1 and Q2 should have low RdsON specifications (<100mOhm) to function properly in this fault diagnostic configuration.

FN8830 Rev 3.00

May 10, 2018

Page 24 of 100

ISL78610

Figures 43 and 44 show an alternative balancing and cell voltage

monitoring arrangement. The diagram in Figure 43 shows the

connection for VC9 through VC12, using P-channel FETs for the

upper three inputs. Figure 44 shows the connection for VC1

through VC3 using N-channel FETs. With this alternative circuit it

is possible to monitor the cell voltages during cell balancing

(even though the voltage will likely drop a little when measuring

a cell that is being balanced). However, this circuit connection

does not allow the system to check for all potential external

component failures. See Figure 54 on page 34 for a more

complete example.

capacitances. These momentarily turn on the FET in the event of

a large transient, thus limiting the Vgs values to reasonable

levels. A 10nF capacitor is included between the MOSFET gate

and source terminals to protect against EMI effects. This

capacitor provides a low impedance path to ground at high

frequencies and prevents the MOSFET turning on in response to

high frequency interference.

The 10k and 330k resistors prevent the 9V clamp at the output

from the ISL78610 from activating.

Reduced cell counts for fewer than 12 cells are accommodated

by removing connections to the cells in the middle of the stack

first. The top and bottom cell locations are always occupied. See

“Operating with Reduced Cell Counts” on page 30 for suggested

cell configurations when using fewer than 12 cells.

The gate of the N-channel MOSFET (cell locations 1 through 9)

and P-channel MOSFETs (Cells 10 through 12) are normally

protected against excessive voltages during cell voltage

transients by the action of the parasitic Cgs and Cgd

R2

R5

VC12

22nF

C3

4MΩ

C1

R1

R5

9V

VC3

R4

Q1

100Ω

22nF

CB12

10kΩ

R2

100Ω

C2

25µA

C2

C1

C3

R5

CB3

VC11

Q2

10kΩ

R1

22nF

C3

4MΩ

R1

C1

C2

4MΩ

9V

R5

Q1

100Ω

CB12

10kΩ

R2

VC2

CB2

R4

22nF

C3

25µA

100Ω

C2

C1

R5

VC10

25µA

22nF

C3

Q2

4MΩ

10kΩ

R1

9V

C1

C2

R1

4MΩ

Q1

100Ω

9V

R5

CB12

10kΩ

R2

25µA

C2

VC1

R5

R4

VC9

CB9

22nF

C3

100Ω

25µA

22nF

C3

100Ω

CB1

25µA

Q2

10kΩ

Q2

C1

R1

R3

4MΩ

10kΩ

9V

4MΩ

R5

C1

R1

R2

9V

R5

VC0

VSS

22nF

VC8

22nF

ISL78600

FIGURE 44. ALTERNATE CELL MONITOR AND BALANCE CIRCUIT

ARRANGEMENT (VC1 TO VC3)

FIGURE 43. ALTERNATE CELL MONITOR AND BALANCE CIRCUIT

ARRANGEMENT (VC8 to VC12)

TABLE 3. ISL78610 INPUT FILTER COMPONENT OPTIONS

Q1 (P-channel)

with examples

Q2 (N-channel)

with examples

C1

C2

C3

R1

R2

R3

R4

R5

R6

30V

60V

Diodes DMP32D4S-13

Fairchild NDS0605

30V

60V

Diodes DMN63D8L-7

Fairchild NDS7002

10nF

1nF

Not populated 100k 820 720 1.54k 180 360

100nF 100k 100 910 1900

0

10nF Not needed Not populated 330k 820 720 1.54k 180 360

10nF Not needed 100nF 330k 100 910 1900

0

Note: Q1 and Q2 RdsON specification is not critical, since fault diagnostics are not performed in this configuration.

FN8830 Rev 3.00

May 10, 2018

Page 25 of 100

ISL78610

CELL VOLTAGE MEASUREMENTS DURING BALANCING

Power Supplies and Reference

The standard cell balancing circuit (Figures 41 and 42 on

page 24 and Figure 51 on page 31) is configured so the cell

measurement is taken from the drain connection of the

balancing MOSFET. When balancing is enabled for a cell, the

resulting cell measurement is then the voltage across the

balancing MOSFET (VGS voltage). This system provides a

diagnostic function for the cell balancing circuit. The input

voltage of the cell adjacent to the MOSFET drain connection is

also affected by this mechanism: the input voltage for this cell

increases by the same amount that the voltage of the balance

cell decreases.

VOLTAGE REGULATORS

The two VBAT pins, along with V3P3, VCC, and VDDEXT, supply

power to the ISL78610. The VBAT pins provide power for the high

voltage circuits and Sleep mode internal regulators. V3P3

supplies the logic circuits and VCC similarly supplies the low

voltage analog circuits. The V3P3 and VCC pins must not be

connected to external circuits other than those associated with

the ISL78610 main voltage regulator. The VDDEXT pin is

provided for use with external circuits.

The ISL78610 main low voltage regulator uses an external NPN

pass transistor to supply 3.3V power for the V3P3 and VCC pins.

This regulator is enabled whenever the ISL78610 is in Normal

mode and can also power external circuits through the VDDEXT

pin. An internal switch connects the VDDEXT pin to the V3P3 pin.

Both the main regulator and the switch are off when the part is

placed in Sleep mode or Shutdown mode (EN pin LOW.) The pass

transistor’s base is connected to the ISL78610 BASE pin. A

suitable configuration for the external components associated

with the V3P3, VCC, and VDDEXT pins is shown in Figure 45 on

page 26.

For example, if Cells 2 and 3 are both at 3.6V and balancing is

enabled for Cell 2, the voltage across the balancing MOSFET may

be only 50mV. In this case, the input voltage on the VC2 pin

would be VC1 + 50mV and Cell 3 would be VC2 + 7.15V. The VC3

value in this case is outside the measurement range of the cell

input. VC3 would then read full scale voltage, which is 4.9994V.

This full scale voltage reading will occur if the sum of the

voltages on the two adjacent cells is greater than the total of 5V

plus the “balancing on” voltage of the balanced cell. Table 4

shows the cell affected when each cell is balanced.

The cell voltage measurement is affected by impedances in the

cell connectors and any associated wiring. The balance current

passes through the connections at the top and bottom of the

balanced cell. This effect further reduces the voltage measured

on the balanced cell and increases the voltage measured on cells

above and below the balanced cell. For example, if Cell 4 is

balanced with 100mA, and the total impedance of the connector

and wiring for each cell connection is 0.1Ω, then Cell 4 would

read low by an additional 20mV (10mV due to each pin) while

Cells 3 and 5 would both read high by 10mV.

The external pass transistor is required. Do not allow the BASE

pin to float.

VOLTAGE REFERENCE

A bypass capacitor is required between REF (pin 33) and the

analog ground VSS. The total value of this capacitor should be in

the range of 2.0µF to 2.5µF. Use X7R type dielectric capacitors

for this function. The ISL78610 continuously performs a

power-good check on the REF pin voltage starting 20ms after a

power-up, Enable, or Wake-up condition. If the REF capacitor is

too large, then the reference voltage may not reach its target

voltage range before the power-good check starts and result in a

REF fault. If the capacitor is too small, then it may lead to

inaccurate voltage readings.

TABLE 4. CELL READINGS DURING BALANCING

CELL WITH LOW

CELL BALANCED

READING

CELL WITH HIGH READING

1

2

1

2

3

PACK

VOLTAGE

ISL78610

R

1

3

4

VBAT

4

5

R

3

Q

1

C

1

BASE

V3P3

5

6

7

D

1

C

7

8

R

2

VCC

8

9

C

2

9

9*

10*

11

12

10*

9*

10

11

VREF

10

11

12

C

6

V2P5

C

5

NOTE: *Cells 9 and 10 produce a different result from the other cells.

Cell 9 uses an N-channel MOSFET while Cell 10 uses a P-channel MOSFET.

The circuit arrangement used with these devices produces approximately

half the normal cell voltage when balancing is enabled. The adjacent cell

then sees an increase of half the voltage of the balanced cell.

VSS

VDDEXT

TO EXTERNAL

CIRCUITS

C

4

FIGURE 45. ISL78610 REGULATOR AND EXTERNAL CIRCUIT

SUPPLY ARRANGEMENT

FN8830 Rev 3.00

May 10, 2018

Page 26 of 100

ISL78610

specifies the use of SPI or daisy chain on the communication

ports.

TABLE 5. COMPONENT SELECTION FOR CRICUIT IN Figure 45

COMPONENT

VALUE

R

Sized to pass the maximum supply current at the

minimum specified battery pack voltage.

TABLE 6. COMMUNICATIONS MODE CONTROL

1

COMMS COMMS

SELECT 1 SELECT 2

PORT 1

COMM

PORT 2

COMM

COMMUNICATIONS

CONFIGURATION

R

C

33Ω

27Ω

2

3

1

0

1

0

1

0

1

SPI

(Full Duplex)

Disabled Stand-alone

Selected to produce a time constant with R of a few

1

milliseconds. C and R provide transient protection for

1

SPI

(Half Duplex)

Enabled

Daisy chain,

the collector of Q . Obtain component values and voltage

1

master device setting

ratings by simulating measurement of the worst case

transient expected on VBAT.

Daisy Chain Disabled Daisy chain,

top device setting

C , C , C , C 1μF

2

3

4

5

C

2.2μF

6

7

Daisy Chain Enabled

Daisy chain

C

220nF/100V

PTVS54VS1UTR

middle device setting

D

Q

1

Selected for power dissipation at the maximum specified

battery voltage and load current. The load current includes

ISL78610

the V

and V currents for the ISL78610 and the

3P3

CC

maximum current drawn by external circuits supplied

through VDDEXT. The voltage rating should be determined

by the worst case transient expected on VBAT.

COMMS SELECT2

COMMS SELECT1

SPI

VSS

Communications Circuits

FIGURE 46. NON-DAISY CHAIN COMMUNICATIONS CONNECTIONS

AND SELECTION

The ISL78610 operates as a stand-alone monitor for up to 12

series connected cells or in a daisy chain configuration for

multiple series connected ISL78610 monitoring devices. For

stand-alone (non-daisy chain) systems, only a synchronous SPI is

needed for communications between a host microcontroller and

the ISL78610.

.

V3P3

ISL78610

Both the SPI port and daisy chain ports are needed for

communication in systems with more than one ISL78610.

DAISY DOWN

COMMS SELECT2

COMMS SELECT1

A daisy chain consists of a bottom device, a top device, and up to

12 middle devices. The ISL78610 device located at the bottom of

the stack is called the master and communicates to the host

microcontroller using SPI communications and to other

ISL78610 devices using the daisy chain port. Each middle device

provides two daisy chain ports: one is connected to the ISL78610

above in the stack and the other to the ISL78610 below.

Communications between the SPI and daisy chain interfaces are

buffered by the master device to accommodate timing

differences between the two systems.

VSS

V3P3

ISL78610

DAISY UP

DAISY DOWN

COMMS SELECT2

COMMS SELECT1

VSS

The daisy chain ports are fully differential, DC balanced,

bidirectional, and AC coupled to provide maximum immunity to

EMI and other system transients while requiring only two wires

for each port.

V3P3

ISL78610

DAISY UP

COMMS SELECT2

COMMS SELECT1

SPI

The addressed device, the top device, and the bottom device act

as master devices for controlling command and response

communications. All other devices are repeaters, passing data

up or down the chain.

VSS

FIGURE 47. DAISY CHAIN COMMUNICATIONS CONNECTIONS AND

SELECTION

The communications setup is controlled by the COMMS SELECT 1

and COMMS SELECT 2 pins on each device. These pins specify

whether the ISL78610 is a stand-alone device, the daisy chain

master, the daisy chain top, or a middle position in the daisy

chain. See Figures 46 and 47 and Table 6. This configuration also

FN8830 Rev 3.00

May 10, 2018

Page 27 of 100

ISL78610

Four daisy chain data rates are available and are configurable by

pin selection using the COMMS RATE 0 and COMMS RATE 1 pins

(see Table 7).

The daisy chain operates with standard unshielded twisted pair

wiring. The component values given in Table 8 accommodate

cable capacitance values from 0pF to 50pF when operating at

the 500kHz data rate. Higher cable capacitance values can be

TABLE 7. DAISY CHAIN COMMUNICATIONS DATA RATE SELECTION

accommodated by either reducing the value of C or operating at

2

lower data rates.

DATA RATE

COMMS RATE 0

COMMS RATE 1

(kHz)

62

The values of components in Figure 48 are given in Table 8 for

various daisy chain operating data rates.

0

1

0

1

0

1

125

250

500

The circuit and component values of Figure 48 and Table 8 will

accommodate cables with differential capacitance values in the

ranges given. This allows a range of cable lengths to be

accommodated through careful selection of cable properties.

The circuit of Figure 48 provides full isolation when used with off

board wiring. The daisy chain external circuit can be simplified in

cases in which the daisy chain system is contained within a

single board. Figure 49 on page 29 and Table 9 on page 29 show

the circuit arrangement and component values for single board

Daisy Chain Circuits

The ISL78610 daisy chain communications system external

circuit arrangement is symmetrical to provide the bidirectional

communications function. The performance of the system under

transient voltage and EMI conditions is enhanced by the use of a

capacitive load. A schematic of the daisy chain circuit for board

to board connection is shown in Figure 48.

use. In this case, the AC coupling capacitors C need to be rated

1

only for the maximum transient voltage expected from device to

device.

The basic circuit elements are the series resistor and capacitor

The value for C2 in Table 8 is ideally 220pF. This creates a 3:1

ratio in the transmit vs. received signal. However, additional

capacitance on the board due to device pin, board layout, and

connector capacitance forces the use of a lower value capacitor.

In practical terms, using the “ideal” capacitor and ignoring real

additional capacitance on the board reduces the signal level at

the receiver. Renesas recommends that the board layout

minimize distance on daisy chain traces and to isolate them as

much as possible from each other and from ground planes.

Expect at least 50pF to 90pF of additional board capacitance,

depending on the layout and connectors

elements R and C , which provide the transient current limit

1

and AC coupling functions, and the line termination components

C , which provide the capacitive load. Capacitors C and C

2

1

2

should be located as closely as possible to the board connector.

The AC coupling capacitors C need to be rated for the maximum

1

voltage, including transients, that will be applied to the interface.

Specific component values are needed for correct operation with

each daisy chain data rate and are given in Table 8 on page 28.

CONNECTOR

ISL78610

R

C

R

1

ISL78610

2

1

C

2

DGND1

DGND2

C

2

R

2

1

C

1

FIGURE 48. ISL78610 DAISY CHAIN CIRCUIT IMPLEMENTATION

TABLE 8. COMPONENT VALUES IN FIGURE 48 FOR VARIOUS DAISY CHAIN DATA RATES

DAISY CHAIN CLOCK RATES

COMPONENT

500kHz

250kHz

220pF

125kHz

470pF

400pF

62.5kHz

1nF

COMMENTS

2.2nF

C

4

1

150pF

(Note)

960pF

2nF

2

R

4

470Ω

100Ω

470Ω

100Ω

470Ω

100Ω

470Ω

100Ω

1

2

Cable Capacitance Range

N/A

0 to 50pF

0 to 100pF

0 to 200pF

0 to 400pF

NOTE: Can be accommodated using two 100pF capacitors in parallel.

FN8830 Rev 3.00

May 10, 2018

Page 28 of 100

ISL78610

.

TEMPREG

VCC

R

1

C

1

VREF

C

2

R

1

2

10M

R

10k

1

10k

R

1

ISL78610

DGND1

DGND2

ADC

EXT4

C

1

10nF

ISOLATED GROUND PLANES ON THE SAME PCB

FIGURE 49. ISL78610 DAISY CHAIN – BOARD LEVEL IMPLEMENTATION

CIRCUIT

RT

ISL78610

TABLE 9. DAISY CHAIN COMPONENT VALUES FOR BOARD LEVEL

IMPLEMENTATION

FIGURE 50. CONNECTION OF NTC THERMISTOR TO INPUT EXT4

DAISY CHAIN DATA RATE (kHz)

QUANTITY

COMPONENT

(ea.)

TOLERANCE 500

250

125

62.5

TABLE 10. COMPONENT FUNCTIONS AND DIAGNOSTIC RESULTS FOR

CIRCUIT OF FIGURE 50

C

2

5%

100pF 220pF 470pF 1nF

150pF 400pF 960pF 2nF

1

4

2

COMPONENT

FUNCTION

DIAGNOSTIC RESULT

R

2

1kΩ

1kΩ

1

R

Protection from wiring

shorts to external HV

connections.

Open: Open-wire detection

Short: No diagnostic result

1

2

External Inputs

The ISL78610 provides four external inputs for use either as

general purpose analog inputs or for NTC type thermistors.

Measurement high-side Open: Low input level

resistor (over-temperature indication)

Short: High input level

(open-wire indication).

The arrangement of the external inputs is shown in Figure 50

using the ExT4 input as an example. It is important that the

components are connected in the sequence shown in Figure 50.

Thermistor

Open: High input level

(open-wire indication).

Short: Low input level

For example, C must be connected so the trace from this

1

capacitor’s positive terminal connects to R before connecting to

2

(over-temperature indication)

R . This guarantees the correct operation of the various fault

1

detection functions.

C

Noise Filter. Connects to Open: No diagnostic result.

1

measurement ground

VSS.

Short: Low input level

(over-temperature indication)

Each of the external inputs has an internal pull-up resistor, which

is connected by a switch to the VCC pin whenever the TEMPREG

output is active. This arrangement results in an open input being

pulled up to the V voltage.

CC

Inputs above 15/16 of full scale are registered as open inputs

and cause the relevant bit in the Over-Temperature Fault register

and the OT bit in the Fault Status register to be set on condition

of the respective temperature test enable bit in the Fault Setup

register. The user must then read the register value associated

with the faulty input to determine if the fault was due to an open

input (value above 15/16 full scale) or an over-temperature

condition (value below the External Temperature Limit setting).

The function of each of the components in Figure 50 is listed in

Table 10 with the diagnostic result of an open or short fault in

each component.

FN8830 Rev 3.00

May 10, 2018

Page 29 of 100

ISL78610

Typical Applications Circuits

Operating with Reduced Cell Counts

Typical applications circuits are shown in Figures 51 to 57.

Table 11 on page 38 contains recommended component values.

All external (off-board) inputs to the ISL78610 are protected

against battery voltage transients by RC filters. They also provide

a current limit function during hot plug events. The ISL78610 is

calibrated for use with 1kΩ series protection resistors at the cell

When using the ISL78610 with fewer than 12 cells, ensure that

each used cell has a normal input circuit connection to the top

and bottom monitoring inputs for that cell. The simplest way to

use the ISL78610 with any number of cells is to always use the

full input circuit arrangement for all inputs and short together the

unused inputs at the battery terminal. In this way, each cell input

sees a normal source impedance independent of whether or not

it is monitoring a cell.

inputs. V

uses a lower value resistor to accommodate the

supply current of the ISL78610. A value of 27Ω is used for

BAT

V

BAT

this component. As much as possible, the time constant

produced by the filtering applied to V should be matched to

The cell balancing components associated with unconnected cell

inputs are not required and can be removed. Unused cell balance

outputs should be tied to the adjacent cell voltage monitoring

pin.

BAT

that applied to the Cell 12 monitoring input. Component values

given in Table 11 produce the required matching characteristics.

The input circuit component count can be reduced in cases

where fewer than 10 cells are being monitored. It is important

that cell inputs that are being used are not connected to other

(unused) cell inputs as this would affect measurement accuracy.

Figures 55, 56, and 57 (starting on page 35) show examples of

systems with 10 cells, 8 cells, and 6 cells, respectively.

Figure 51 on page 31 shows the standard arrangement for

connecting the ISL78610 to a stack of 12 cells. The cell input

filter is designed to maximize EMI suppression. These

components should be placed close to the connector with a well

controlled ground to minimize noise for the measurement inputs.

The balance circuits shown in Figure 51 provide normal cell

monitoring when the balance circuit is turned off and a near zero

cell voltage reading when the balance circuit is turned on. This is

part of the diagnostic function of the ISL78610.

The component notations and values used in Figures 56 and 57

are the same as those used in Figures 51 to 54.

In Figure 57 the resistor associated with the input filter on VC9 is

noted as R , rather than R . This value change is needed to

maintain the correct input network impedance in the absence of

the Cell 9 balance circuits.

5

5U

Figure 52 on page 32 shows connections for the daisy chain

system, setup pins, power supply, and external voltage inputs for

daisy chain devices other than the master (stack bottom) device.

Figure 53 on page 33 shows the daisy chain system, setup pins,

microcontroller interface, power supply, and external voltage

inputs for the daisy chain master device. Figure 53 is also

applicable to stand-alone (non-daisy chain) devices, although in

this case, the daisy chain components connected to DHi2 and

DLo2 are omitted.

Figure 54 on page 34 shows an alternate arrangement for the

battery connections in which the cell input circuits are connected

directly to the battery terminal and not through the balance

resistor. In this condition, the balance diagnostic function

capability is removed.

FN8830 Rev 3.00

May 10, 2018

Page 30 of 100

ISL78610

PLACE THESE

COMPONENTS

PACK

CLOSE TO CONNECTOR

VOLTAGE

R

B12b

B12

C

D

58

59

60

61

1

ISL78610

VBAT

VC12

CB12

R

C

2

2A

3A

4A

2

3

4

R

28

Q

1

C

R

27

R

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

29

C

62

3

VC11

R

63

64

31

Q

CB11

VC10

2

C

R

28

30

R

4

32

R

Q

1

2

3

34

3

CB10

VC9

R

C

R

35

29

33

5U

R

5AU

R

5L

C

5L

36

R

C

30

37

5AL

5U

Q

CB9

4

R

38

R

C

4

5

6

6A

7A

8A

9A

6

7

8

9

VC8

CB8

R

39

Q

R

C

R

41

31

40

5

R

6

7

VC7

CB7

42

Q

R

32

43

44

8

R

8

9

8

VC6

CB6

45

Q

C

R

33

34

35

36

37

46

49

52

55

58

47

8

R

10

11

9

VC5

CB5

48

Q

R

50

8

R

C

12

13

10

10A

11A

12A

13A

71A

10

VC4

CB4

51

Q

53

9

R

C

14

15

11

VC3

CB3

54

56

Q

10

R

16

17

12

13

39

VC2

CB2

R

57

Q11

59

R

18

13

VC1

R

60

C

R

19

20

38

61

62

Q

CB1

VC0

12

B0

71

B0b

21

22

VSS

FIGURE 51. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS

FN8830 Rev 3.00

May 10, 2018

Page 31 of 100

ISL78610

PLACE THESE

COMPONENTS

CLOSE TO DEVICE

PLACE THESE

COMPONENTS

CLOSE TO CONNECTOR

C

R

44

65

DAISY UP HI

63

56

DHi2

C

ISL78610

42

C

R

45

51

43

66

DAISY UP LO

DAISY DN HI

64

55

53

DLo2

DHi1

69

67

C

49

R

C

R

70

52

DAISY DN LO

68

50

52

DLo1

43

42

41

40

COMMS RATE 0

COMMS RATE 1

Connect Pins 40 to 43 to V3P3 or VSS

depending on comms selection

and daisy chain clock speed

COMMS SELECT 1

COMMS SELECT 2

Connect Pin 47 to V3P3 to Enable

Connect Pin 47 to VSS to Disable

47

EN

PACK

VOLTAGE

44

35

DGND

V2P5

R

81

C

53

V3P3

C

55

38

36

Q

BASE

V3P3

13

R

34

33

82

VCC

REF

C

54

C

56

C

57

R

R R

83

84 85 86

29

TEMPREG

R

EXT IN 4

EXT IN 3

EXT IN 2

EXT IN 1

87

90

93

96

30

28

26

24

EXT4

EXT3

EXT2

EXT1

R

C

C C

58

59 60 61

FIGURE 52. TYPICAL APPLICATIONS CIRCUIT – NON BATTERY CONNECTIONS, MIDDLE AND TOP DAISY CHAIN DEVICES

FN8830 Rev 3.00

May 10, 2018

Page 32 of 100

ISL78610

PLACE THESE

COMPONENTS

CLOSE TO DEVICE

PLACE THESE

COMPONENTS

CLOSE TO CONNECTOR

C

R

44

DAISY UP HI

DAISY UP LO

63

65

56

55

DHi2

DLo2

ISL78610

C

42

R

45

64

66

C

43

42

41

40

COMMS RATE 0

COMMS RATE 1

Connect Pins 40 to 43 to V3P3 or VSS

depending on comms selection

and daisy chain clock speed

COMMS SELECT 1

COMMS SELECT 2

Connect Pin 47 to V3P3 to Enable

Connect Pin 47 to VSS to Disable

53

52

50

49

47

46

45

SCLK

CS

DIN

MICROCONTROLLER

INTERFACE

DOUT

EN

DATA READY

FAULT

PACK

VOLTAGE

44

35

DGND

V2P5

R

81

C

53

V3P3

C

Q

55

38

36

BASE

V3P3

13

R

82

34

33

VCC

REF

C

54

C

56

C

57

R

R R

83

84 85 86

29

TEMPREG

R

EXT IN 4

EXT IN 3

EXT IN 2

EXT IN 1

87

90

93

96

30

28

26

24

EXT4

EXT3

EXT2

EXT1

R

C

C C

58

59 60 61

FIGURE 53. TYPICAL APPLICATIONS CIRCUIT – NON BATTERY CONNECTIONS, MASTER DAISY CHAIN DEVICE

FN8830 Rev 3.00

May 10, 2018

Page 33 of 100

ISL78610

PLACE THESE

COMPONENTS

PACK

VOLTAGE

CLOSE TO CONNECTOR

R

1

B12b

B12

C

D

58

59

60

61

1

ISL78610

VBAT

VC12

CB12

C

R

27

2

2A

3A

4A

5A

6A

7A

8A

9A

C

2

R

28

Q

1

R

29

C

R

28

30

3

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C

62

63

3

VC11

CB11

R

31

Q

2

R

C

R

32

29

33

4

64

1

4

VC10

CB10

R

34

Q

3

R

35

5

2

5

VC9

R

36

C

R

30

31

32

33

34

35

36

37

38

37

40

43

46

49

52

55

58

61

38

3

4

Q

CB9

VC8

4

R

6

R

39

41

5

6

Q

CB8

VC7

5

R

7

42

44

7

8

Q

CB7

VC6

6

R

8

45

47

9

Q

CB6

VC5

7

R 9

9

10

9

48

R

50

11

12

Q

CB5

VC4

8

R

10A

10

C

10

11

12

13

39

51

R

53

13

14

Q

CB4

VC3

9

11

11A

12A

13A

R

Q

54

R

56

15

16

CB3

VC2

10

12

R

57

R

59

17

18

Q

CB2

VC1

11

13

R

Q

60

R

62

19

20

CB1

VC0

12

71A

71

B0

21

22

B0b

VSS

FIGURE 54. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS ALTERNATIVE CONFIGURATION

FN8830 Rev 3.00

May 10, 2018

Page 34 of 100

ISL78610

PLACE THESE

COMPONENTS

PACK

VOLTAGE

CLOSE TO CONNECTOR

R

B12b

B12

C

D

58

59

60

61

1

ISL78610

VBAT

VC12

CB12

R

C

2

2A

3A

4A

2

3

4

R

28

Q

1

C

R

27

R

29

R

B11

B10

B9

C

62

3

VC11

63

64

31

Q

CB11

VC10

2

C

R

28

30

R

4

32

R

Q

1

2

3

34

3

CB10

VC9

R

C

R

35

R

29

33

37

5U

R

5AU

R

C

5L

36

Q

5U

5L

C

R

30

5AL

CB9

4

R

38

R

B8

4

5

6

6A

6

7

8

9

VC8

CB8

R

39

Q

R

C

R

41

31

40

5

R

C

6

7

7A

7

8

9

VC7

CB7

R

8A

8

9

VC6

CB6

R

9A

B5

B4

B3

B2

B1

10

11

VC5

CB5

R

48

Q

C

R

34

35

36

37

49

52

55

58

50

8

R

12

13

10

10A

11A

12A

13A

71A

10

VC4

CB4

51

Q

53

9

R

C

R

14

15

11

VC3

CB3

54

56

Q

10

R

16

17

12

13

39

VC2

CB2

R

57

Q11

59

R

18

13

VC1

R

60

C

R

19

20

38

61

62

Q

CB1

VC0

12

B0

71

B0b

21

22

VSS

FIGURE 55. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 10 CELLS

FN8830 Rev 3.00

May 10, 2018

Page 35 of 100

ISL78610

PLACE THESE

COMPONENTS

CLOSE TO CONNECTOR

V

BAT

R

C

D

1

B12b

B12

58

59

60

61

1

ISL78610

VBAT

VC12

CB12

R

2A

3A

4A

2

C

2

3

4

R

28

Q

1

C

R

27

R

29

B11

B10

B9

3

C

62

VC11

31

63

64

Q

CB11

VC10

2

C

R

30

28

R

32

4

R

Q

34

1

2

3

CB10

VC9

R

35

36

Q

C

R

29

33

5U

5L C

R

5AU

C

5L

5U

R

30

37

5AL

CB9

4

R

38

6

R

6A

C

4

5

6

VC8

CB8

6

7

VC7

CB7

8

9

VC6

CB6

R

9A

9

C

10

11

9

VC5

CB5

R

C

10A

11A

12A

13A

71A

B4

B3

B2

B1

10

12

13

10

11

12

13

39

VC4

CB4

R

51

Q

C

R

53

35

36

37

52

55

58

9

R

11

14

15

VC3

CB3

54

56

Q

10

R

12

16

17

VC2

CB2

R

57

59

Q

11

R

13

18

VC1

R

60

R

C

R

62

19

20

38

61

Q

CB1

VC0

12

B0

71

21

22

B0b

VSS

FIGURE 56. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 8 CELLS

FN8830 Rev 3.00

May 10, 2018

Page 36 of 100

ISL78610

PLACE THESE

COMPONENTS

PACK

VOLTAGE

CLOSE TO CONNECTOR

R

C

D

1

B12b

B12

58

59

60

61

ISL78610

1

VBAT

VC12

CB12

R

2

C

2A

3A

4A

5A

2

3

4

5

R

28

Q

1

C

R

27

R

3

B11

B10

29

62

VC11

R

31

63

64

Q

CB11

VC10

2

C

R

28

30

R

4

32

R

34

Q

1

2

3

CB10

VC9

35

29

33

R

5

CB9

4

5

VC8

CB8

6

7

VC7

CB7

8

9

VC6

CB6

10

11

VC5

CB5

R

C

10A

11A

12A

13A

71A

12

13

10

11

12

13

39

VC4

CB4

R

C

B3

B2

B1

11

14

15

VC3

CB3

R

54

R

C

56

55

36

Q

10

R

12

16

17

VC2

CB2

R

57

59

58

37

Q

11

R

18

13

VC1

R

60

R

C

19

20

62

61

38

Q

CB1

VC0

12

B0

71

B0b

21

22

VSS

FIGURE 57. TYPICAL APPLICATIONS CIRCUIT – BATTERY CONNECTION CIRCUITS, SYSTEM WITH 6 CELLS

FN8830 Rev 3.00

May 10, 2018

Page 37 of 100

ISL78610

TABLE 11. RECOMMENDED COMPONENT VALUES FOR FIGURES (Figures 51 through 57)

COMPONENTS

VALUE

RESISTORS

0

R

101

1

27

33

82

820

R , R

2

71

R , R , R , R , R , R , R , R , R , R

10 11 12 13

720

Figure 51 on page 31,

Figure 55 on page 35,

Figure 56 on page 36

3

4

6

7

8

9

1.54k

180

R

, R

5U 5L

, R , R , R , R , R , R , R

, R

2A 3A 4A 6A 7A 8A 9A 10A 11A 12A 13A

360

, R

5AU 5AL

910

Figure 54 on page 34

1/2W (or larger)

R , R , R , R , R , R , R , R , R , R , R

10 11 12 13

3

4

5

6

7

8

9

180

R

, R , R , R , R , R , R , R , R

, R

2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A

100

, R , R , R , R , R , R , R , R , R , R , R

29 32 35 36 39 42 45 48 51 54 57 60

1.3k

(assumes minimum pack voltage of 12V and maximum supply current of 6.5mA. Higher current or

81

lower minimum pack voltage requires the use of a smaller resistor)

100

1.4k

470

10k

R

, R , R , R

63 64 67 68

, R

5U 5L

, R , R , R

65 66 69 70

R

, R , R , R , R , R , R , R , R , R , R , R , R , R , R , R , R , R , R , R ,

28 31 34 38 41 44 47 50 53 56 59 62 83 84 85 86 87 90 93 96

, R , R , R

100a 100b 100c 100d

330k

CAPACITORS

VALUE

200p

R

, R , R , R , R , R , R , R , R , R , R , R

27 30 33 37 40 43 46 49 52 55 58 61

VOLTAGE

100

500

50

COMPONENTS

C

, C , C , C

42 43 49 50

220p

, C , C , C

44 45 51 52

10n

, C , C , C , C , C , C , C , C , C , C , C , C , C , C , C

27 28 29 30 31 32 33 34 35 36 37 38 58 59 60 61

22n

100

10

C , C , C , C , C , C , C , C , C , C , C , C , C

2

1

3

4

5

6

7

8

9

10 11 12 13 39

220n

C

1µ

, C , C

53 54 56

1µ

100

10

55

57

2.2µ

ZENER DIODES

VALUE

54V

EXAMPLE

COMPONENTS

- DIODE-TVS, SMD, 2P, SOD-123W, 54VWM, 87.1VC

PTVS54VS1UTR

D

1

FN8830 Rev 3.00

May 10, 2018

Page 38 of 100

ISL78610

A dual point failure in the balancing resistor (R , R , R , etc.)

29 32 35

Notes on Board Layout

Referring to Figure 51 on page 31 (battery connection circuits),

the basic input filter structure is composed of resistors R to R

of Figure 51 on page 31 and associated balancing MOSFET (Q

1

to Q ) can also cause a shorted cell condition. Renesas

12

,

2

13

recommends replacing the balancing resistor with two resistors

in series.

R

, and capacitors C to C and C . These components

71

2

13 39

provide protection against transients and EMI for the cell inputs.

They carry the loop currents produced by EMI and should be

placed as close to the connector as possible. The ground

terminals of the capacitors must be connected directly to a solid

ground plane. Do not use vias to connect these capacitors to the

input signal path or to ground. Place any vias in line to the signal

inputs so that the inductance of these forms a low pass filter with

the grounded capacitors.

Board Level Calibration

For best accuracy, the ISL78610 can be recalibrated after soldering

to a board using a simple resistor trim. The adjustment method

involves obtaining the average cell reading error for the cell inputs at

a single temperature and cell voltage value and applying a

select-on-test resistor to zero the average cell reading error.

The adjustment system uses a resistor placed either between

Referring to Figure 52 on page 32, the daisy chain components

are shown to the top right of the drawing. These are split into two

sections. Components to the right of this section should be

placed close to the board connector with the ground terminals of

capacitors connected directly to a solid ground plane. This is the

same ground plane that serves the cell inputs. Components to

the left of this section should be placed as close to the device as

possible.

VDDEXT and V

or V , and VSS as shown in Figure 58. The

REF

value of resistor R or R is then selected based on the average

1

2

error measured on all cells at 3.3V per cell and room

temperature; for example, with 3.3V on each cell input, scan the

voltage values using the ISL78610 and record the average

reading error (ISL78610 reading – cell voltage value). Table 12

shows the value of R and R required for various measured

1

2

errors.

The battery connector and daisy chain connectors should be

placed closely to each other on the same edge of the board to

minimize any loop current area.

To use Table 12, find the measured error value closest to the

result obtained with measurements using the ISL78610 and

select the corresponding resistor value. For finer adjustment

resolution, this value can be obtained by interpolation using

Table 12.

Two grounds are identified on the circuit diagram. These are

nominally referred to as noisy and quiet grounds. The noisy ground,

denoted by an “earth” symbol, carries the EMI loop currents and

digital ground currents. The quiet ground defines the decoupling

voltage for voltage reference and the analog power supply rail. Join

the quiet and noisy grounds at the VSS pin. Keep the quiet ground

area as small as possible.

VDDEXT

R

1

2

The circuits shown to the bottom right of Figure 52 on page 32

provide signal conditioning and EMI protection for the external

temperature inputs. These inputs are designed to operate with

external NTC thermistors.

VREF

VSS

R

C

1

Each of the external inputs has an internal pull-up resistor, which

is connected by a switch to the VCC pin whenever the TEMPREG

output is active. This arrangement results in an open input being

ISL78610

FIGURE 58. CELL READING ACCURACY ADJUSTMENT SYSTEM

pulled up to the V voltage.

CC

Component Selection

TABLE 12. COMPONENT VALUES FOR ACCURACY CALIBRATION

ADJUSTMENT OF FIGURE 58

Certain failures associated with external components can lead to

unsafe conditions in electronic modules. A good example of this

is a component that is connected between high energy signal

sources failing short. Such a condition can easily lead to the

component overheating and damaging the board and other

components in its proximity.

MEASURED ERROR AT VC = 3.3V

R

2

1

V

- V

(mV)

(kΩ)

205

274

(kΩ)

DNP

2550

1270

866

78610 CELL

4

3

2

412

825

DNP

One area to consider with the external circuits on the ISL78610 is

the capacitors connected to the cell monitoring inputs. These

capacitors are normally protected by the series protection

resistors but can be a safety hazard in the event of a dual point

fault in which both the capacitor and associated series resistor

fail short. Also, a short in one of these capacitors would dissipate

the charge in the battery cell if left uncorrected for an extended

1

0

-1

-2

-3

-4

649

period of time. Renesas recommends selecting capacitors C to

1

C

to be “fail safe” or “open mode” types. An alternative

DNP = Do Not Populate

13

strategy is to replace each of these capacitors with two devices in

series, each with double the value of the single capacitor.

FN8830 Rev 3.00

May 10, 2018

Page 39 of 100

ISL78610

The host microcontroller should build in handlers for commands

that might be delayed within the communication structure and

look for a Communications Failure response if the wait time

expires. For more detail, see “Communication Faults” on page 75.

System Commands

The ISL78610 has a series of commands available to the host

microcontroller to control operation of the ISL78610 system, to

read and write data to any individual device, and to check system

status. These following sections describe each commands, along

with the commands’ characteristics.

An Acknowledge (ACK) response indicates that the command

was successfully received by the target device. A Not

Acknowledged (NAK) indicates an error in decoding the

command.

The attributes associated with each command are: the device

response, whether the command can address all devices with a

single command, and whether there is a response from the

target device.

Address All

Address All is used only in a daisy chain configuration. To address

a particular device, the host microcontroller specifies the address

of that device (1 through 14) for each of the maximum of

14 devices. To address all devices in a daisy chain stack, the host

microcontroller uses an address of 15 (Hex ‘1111’) to cause all

stack devices to perform functions simultaneously. Only some

commands recognize Address All.

Device Response

In a stand-alone configuration, the host should only expect a

response when reading data from a register. In all other cases,

no response is expected.

In a daisy chain configuration, all commands except any Scan,

Measure, Sleep, Wake, and Reset commands require a response

from either the stack top device or the target device (see

Table 13). Each device in the stack waits for a response from the

stack device above. Correct receipt of a command is indicated by

the correct response. Failure to receive a response within a

timeout period indicates a communications fault. The timeout

value is stack position dependent. The device that detects the

fault then transmits the Communications Failure response,

which includes its stack address.

Read and Write Commands

Read and Write commands are the primary communication

mechanisms in the ISL78610 system. All commands use the

read and write operations. Refer to “Communications” on

page 52 for a detailed description of these operations’ protocols,

timing, and interactions.

Table 13 describes the commands and how they control the

system.

TABLE 13. COMMAND ATTRIBUTES

NORMAL DEVICE RESPONSE

VALID IN

DEVICEWAITSFORA “ADDRESS ALL”

RESPONSE? COMPATIBLE

(Daisy Chain Only) (Daisy Chain Only)

STAND-ALONE OR

DAISY CHAIN

COMMAND

STAND-ALONE

TOP

ACK

-

TARGET

Read

Both

Data

ACK

-

Yes

No

Write

-

No

Scan Voltages

Both

Yes

Scan Temperatures

Scan Mixed

Both

-

No

Yes

Both

-

No

Yes

Scan Wires

Both

-

No

Yes

Scan All

Both

-

No

Yes

Scan Continuous

Scan Inhibit

Both

ACK

-

ACK

NAK

ACK

-

Yes

No

Yes

Both

Yes

Sleep

Both

Yes

Wake-up

Both

No

Yes

Balance Enable

Balance Inhibit

Measure

Both

Yes

No

Yes

Both

Yes

Both

No

Identify (special command)

NAK

Daisy chain only

Both

ACK

-

NAK

ACK

-

No

Special address

Yes

No

ACK

Reset

Calculate Register Checksum

Check Register Checksum

Both

ACK

Yes

Both

FN8830 Rev 3.00

May 10, 2018

Page 40 of 100

ISL78610

Scan Voltages Command

Scan Mixed Command

When a device receives the Scan Voltages command to its stack

address (or an Address All stack address), it increments the scan

counter (see “Scan Counter” on page 43) and begins a scan of

the cell voltage inputs. It sequences through the cell voltage

inputs in order from Cell 12 (top) to Cell 1 (bottom). This

operation is followed by a scan of the Pack Voltage.

When a device receives the Scan Mixed command to its stack

address (or an Address All stack address), it increments the Scan

counter (see “Scan Counter” on page 43) and begins a Scan

Mixed operation.

The Scan Mixed command causes the addressed device (or all

devices with an Address All stack address) to scan through the

cell voltage inputs in order from Cell 12 (top) to Cell 7. Then the

external input ExT1 is measured, followed by a scan of Cell 6 to

Cell 1. These operations are followed by a scan of the Pack

Voltage and the IC temperature. The IC temperature is recorded

for use with the internal calibration routines.

The scan operation forces a sample and hold on each input, an

analog-to-digital conversion of the voltage, and the storage of the

value in its appropriate register. The IC temperature is also

recorded for use with the internal calibration routines.

The Scan Voltages command performs cell overvoltage and

undervoltage comparisons on each cell input and checks the

VBAT and VSS connections for open-wire at the end of the scan. If

a fault condition is present (see “Fault Diagnostics” on page 77

for what constitutes a fault condition), the device sets the

specific fault bit, sets the device FAULT pin active, and sends an

“unprompted fault response” to the host down the daisy chain

communication link (a stand-alone device sets the FAULT pin

only). The Unprompted Response is identical to a “Read Status

Register” command.

The Scan Mixed command also performs cell overvoltage and

undervoltage comparisons on each cell voltage sampled. The

VBAT and VSS pins are also checked for open conditions at the

end of the scan.

ExT1 is sampled in the middle of the cell voltage scan so that half

the cells are sampled before ExT1 and half after ExT1. This mode

allows ExT1 to be used for an external voltage measurement,

such as a current sensing, so it is performed with the cell voltage

measurements, reducing the latency between measurements.

Devices revert to the Standby state on completion of the scan

activity.

The Scan Mixed command is intended for use in stand-alone

systems, or by the master device in stacked applications, and

typically measures a single system parameter, such as battery

current or Pack voltage.

Cell voltage, Pack voltage data, and any fault conditions are

stored in local memory ready for reading by the system host

microcontroller.

Cell voltage, Pack voltage, ExT1 data, and any fault conditions are

stored in local memory ready for reading by the system host

microcontroller. Access the data from the ExT1 measurement by a

direct Read ET1 Voltage command or by the All Temperatures

read command.

Scan Temperatures Command

When a device receives the Scan Temperatures command to its

stack address (or an Address All stack address), it increments

the scan counter (see “Scan Counter” on page 43) and begins a

scan of the temperature inputs.

If a fault condition is present, (see “Fault Diagnostics” on

page 77 for what constitutes a fault condition), the device sets

the FAULT pin active and sends an “unprompted fault response”

to the host down the daisy chain communication link on

completion of a scan (a stand-alone device sets the FAULT pin

only). The unprompted response is identical to a “Read Status

Register” command.

The Scan Temperatures command causes the addressed device

(or all devices with an Address All stack address) to scan through

the internal and four external temperature signals followed by

multiplexer loopback and reference measurements. The

loopback and reference measurements are part of the internal

diagnostics function. Over-temperature compares are performed

on each temperature measurement depending on the condition

of the appropriate bit in the Fault Setup register.

Devices revert to the Standby state on completion of the scan

activity.

Temperature data and any fault conditions are stored in local

memory ready for reading by the system host microcontroller. If

is a fault condition is present, the device sets its FAULT pin active

and sends an “unprompted fault response” to the host down the

daisy chain communication link on completion of a scan (a

stand-alone device sets the FAULT pin only). The Unprompted

Response is identical to a “Read Status Register” command.

Scan Wires Command

When a device receives the Scan Wires command to its stack

address (or an Address All stack address), it increments the Scan

counter (see “Scan Counter” on page 43) and begins a Scan

Wires operation.

The Scan Wires command causes the addressed device (or all

devices with an Address All stack address) to measure all the

VCn pin voltages while applying load currents to each input pin in

turn. This is part of the fault detection system.

Devices revert to the Standby state on completion of the scan

activity.

See “Temperature Monitoring Operation” on page 43 for more

information.

If is a fault condition is present, the device sets the FAULT pin and

returns a fault signal (sent down the stack) on completion of a

scan.

No cell voltage data is sent as a result of the Scan Wires

command. Devices revert to the standby state on completion of

this activity.

FN8830 Rev 3.00

May 10, 2018

Page 41 of 100

ISL78610

scan rate for voltage scan intervals above 512ms. The wire scan

is performed at a fixed 512ms rate at and below this value.

Table 14 shows the various scan rate combinations available.

Scan All Command

When a device receives the Scan All command to its stack

address (or an Address All stack address), it increments the Scan

counter (see “Scan Counter” on page 43) and begins a Scan All

operation.

Data is not automatically returned while devices are in Scan

Continuous mode except when a fault condition is detected. The

results of voltage and temperature scans are stored in local

volatile memory and can be accessed at any time by the system

host microcontroller. However, because the scan continuous

operation is running asynchronously to any communications,

Renesas recommends stopping the continuous scan before

reading the registers.

The Scan All command causes the addressed device (or all

devices with an Address All stack address) to execute the Scan

Voltages, Scan Wires, and Scan Temperatures commands in

sequence one time (see Figure 59 on page 44 for example timing).

Scan Continuous Command

Devices can be operated in Scan Continuous mode while in

Normal mode or in Sleep mode. Devices revert to Sleep mode or

remain in Normal mode as applicable on completion of each

scan.

Scan Continuous mode is used primarily for fault monitoring and

incorporates the Scan Voltages, Scan Temperatures, and Scan

Wires commands. See “Temperature Monitoring Operation” on

page 43 for more information.

The response to a detected fault condition is to send the Fault

signal, either immediately in the case of stand-alone devices or

daisy chain devices in Normal mode, or following transmission of

the Wake-up signal if the device is being used in a daisy chain

configuration and is in Sleep mode.

The Scan Continuous command causes the addressed device (or

all devices with an Address All stack address) to set the SCAN bit

in the Device Setup register and performs a succession of scans

at a predetermined scan rate. Each device operates

asynchronously on its own clock. This is similar to the Scan All

command except that the scans are repeated at intervals

determined by the SCN0-3 bits in the Fault Setup register.

To operate the “Scan Continuous” function in Sleep mode, the

host microcontroller configures the ISL78610, starts Scan

Continuous mode, and sends the Sleep command. The ISL78610

then wakes itself up each time a scan is required. Note that for

the fastest scan settings (scan interval codes 0000, 0001, and

0010) the main measurement functions do not power down

between scans because the ISL78610 remains in Normal mode.

The ISL78610 provides an option that pauses cell balancing

activity while measuring cell voltages in Scan Continuous mode.

This is controlled by the BDDS bit in the Device Setup register. If

BDDS is set, cell balancing is inhibited during cell voltage

measurement and for 10ms before the cell voltages are

scanned. Balancing is re-enabled at the end of the scan to allow

balancing to continue. This function applies during the Scan

Continuous and while either the Timed or Auto Balance functions

are active. This “BDDS” action allows the implementation of a

circuit arrangement that can be used to diagnose the condition

of external balancing components. See “Cell Voltage

TABLE 14. SCAN CONTINUOUS TIMING MODES

WIRE

SCAN

WIRE

SCAN

INTERVAL

SCN3:0

SCAN

INTERVAL

(ms)

TEMP

SCAN

(ms)

WSCN = 0 WSCN = 1

(ms)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

16

32

512

Measurements during Balancing” on page 26. During Manual

Balance this external circuit arrangement does not allow Scan

Continuous without generating a fault condition. It is up to the

host microcontroller to stop balancing functions when

performing a Scan or Measure command, as BDDS only works in

conjunction with Scan Continuous.

512

64

512

128

512

256

1024

2048

4096

8192

16384

32768

65536

131072

262144

512

1024

2048

4096

8192

16384

32768

65536

131072

262144

The Scan Continuous scan interval is set using the SCN3:0 bits

(lower nibble of the Fault Setup register.) The temperature and

wire scans occur at slower rates and depend on the value of the

scan interval selected. The scan system is synchronized so that

the wire and temperature scans always follow a voltage scan.

The three scan sequences, depending on the scans required at a

particular instance, are as follows:

512

1024

2048

4096

8192

16384

32768

65536

1024

2048

4096

8192

16384

32768

65536

• Scan Voltages

• Scan Voltages, Scan Wires

• Scan Voltages, Scan Wires, Scan Temperatures

The temperature and wire scans occur at 1/5 the voltage scan

rate for voltage scan intervals above 128ms. Below this value,

the temperature scan interval is fixed at 512ms.

The behavior of the wire scan interval is determined by the WSCN

bit in the Fault Setup register. A bit value of ‘1’ causes the wire

scan to be performed at the same rate as the temperature scan.

A bit value of ‘0’ causes the wire scan rate to track the voltage

FN8830 Rev 3.00

May 10, 2018

Page 42 of 100

ISL78610

located in the Scan Count register (Page 1, address 6’h16)

increments each time a Scan or Measure command is received.

This allows the host microcontroller to compare the counter

value before and after the Scan or Measure command was sent

to verify receipt. The counter wraps to zero when overflowed.

Scan Inhibit Command

The Scan Inhibit command stops a Continuous scan (that is,

receipt of the command by the target device resets the SCAN bit

and stops the Scan Continuous function).

Measure Command

When a device receives the Measure command to its stack

address, it increments the scan counter (see “Scan Counter” on

page 43) and begins a Measure operation.

The scan counter increments whenever the ISL78610 receives a

Scan or Measure command. The ISL78610 does not perform a

requested Scan or Measure function if a Scan or Measure

function is already in progress, but it still increments the scan

counter.

This command initiates the voltage measurement of a single cell

voltage, internal temperature, any of the four external

temperature inputs, or the secondary voltage reference. The

command incorporates a 6-bit suffix that contains the address of

the required measurement element. See Table 15 on page 43

and Figure 64B on page 55.

Temperature Monitoring Operation

One internal and four external temperature inputs are provided

together with a switched bias voltage output (TEMPREG, pin 29).

The voltage at the TEMPREG output is nominally equal to the

ADC reference voltage so that the external voltage

measurements are ratiometric to the ADC reference (see

Figure 50 on page 29).

The device matching the target address responds by conducting

the single measurement and loading the result to local memory.

The host microcontroller then reads from the target device to

obtain the measurement result. All devices revert to the Standby

state on completion of this activity.

The temperature inputs are intended for use with external

resistor networks using NTC type thermistor sense elements but

can also be used as general purpose analog inputs. Each

temperature input is applied to the ADC through a multiplexer.

The ISL78610 converts the voltage at each input and loads the

14-bit result to the appropriate register.

TABLE 15. MEASURE COMMAND TARGET ELEMENT ADDRESSES

MEASURE COMMAND

(SUFFIX)

6’h00

6’h01

6’h02

6’h03

6’h04

6’h05

6’h06

6’h07

6’h08

6’h09

6’h0A

6’h0B

6’h0C

6’h10

6’h11

6’h12

6’h13

6’h14

6’h15

DESCRIPTION

The TEMPREG output is turned “on” in response to a Scan

Temperatures or Measure Temperature command. A dwell time

of 2.5ms is provided to allow external circuits to settle, after

which the ADC measures each external input in turn. The

TEMPREG output turns “off” after measurements are completed.

V

Voltage

BAT

Cell 1 Voltage

Cell 2 Voltage

Cell 3 Voltage

Cell 4 Voltage

Cell 5 Voltage

Cell 6 Voltage

Cell 7 Voltage

Cell 8 Voltage

Cell 9 Voltage

Cell 10 Voltage

Cell 11 Voltage

Cell 12 Voltage

Figure 59 on page 44 shows an example temperature scan with

the ISL78610 operating in Scan Continuous mode with a scan

interval of 512ms. The preceding voltage and wire scans are

shown for comparison.

The external temperature inputs are designed so that an open

connection results in the input being pulled up to the full scale

input level. This function is provided by a switched 10MΩ pull-up

from each input to VCC. This feature is part of the fault detection

system and is used to detect open pins.

The internal IC temperature, Auxiliary Reference Voltage, and

multiplexer loopback signals are sampled in sequence with the

external signals using the Scan Temperatures command.

The converted value from each temperature input is also

compared to the external over-temperature limit and open

connection threshold values on condition of the [TST4:1] bits in

the Fault Setup register (see “Fault Setup:” on page 86.) If a TSTn

bit is set to “1”, the temperature value is compared to the

External Temperature threshold and a Fault occurs if the

measured value is lower than the threshold value. If a TSTn bit is

set to “0”, then the temperature measurement is not compared

to the threshold value and no fault occurs. The [TST4:1] bits are

“0” by default.

Internal temperature reading

External temperature Input 1 reading

External temperature Input 2 reading

External temperature Input 3 reading

External temperature Input 4 reading

Reference voltage (raw ADC) value. Use this

value to calculate corrected reference voltage

using reference coefficient data

Scan Counter

Because the Scan and Measure commands do not have a

response, the scan counter is provided to allow confirmation of

receipt of the Scan and Measure commands. This 4-bit counter

FN8830 Rev 3.00

May 10, 2018

Page 43 of 100

ISL78610

512ms

VOLTAGE SCAN

765µs

WIRE SCAN

59.4ms

TEMPERATURE SCAN

2.69ms

2.5ms

2.5V

TEMPREG PIN

Hi-Z

ADC SAMPLING

FIGURE 59. SCAN TIMING EXAMPLE DURING SCAN CONTINUOUS MODE AND SCAN ALL MODE

TABLE 16. MAXIMUM WAIT TIME FOR DEVICES ENTERING SLEEP MODE

Sleep Command

Sleep mode is entered in response to a Sleep command. Only the

communications input circuits, low speed oscillator, and internal

registers are active in Sleep mode, allowing the part to perform

timed scan and balancing activity and to wake up in response to

communications.

MAXIMUM WAIT TIME FROM

TRANSMISSION OF SLEEP COMMAND

(DAISY CHAIN ONLY)

DAISY CHAIN DATA RATE (kHz)

Time to Enter Sleep mode (µs)

500

250

125

62.5

1000

2000

4000

Using a Sleep command does not require that the devices in a

daisy chain stack be identified first. They do not need to know

their position in the stack.

Wake-Up Command

The communications pins are monitored when the device is in

Sleep mode, allowing the part to respond to communications.

In a daisy chain system, the Sleep command must be written

using the Address All stack address. The command is not

recognized if sent with an individual device address and causes

the addressed device to respond NAK. The top stack device

responds ACK on receiving a valid Sleep command.

The host microcontroller wakes up a sleeping device, or a stack

of sleeping devices, by sending the Wake-up command to a

stand-alone or a master stack device. In a daisy chain

configuration, the Wake-up command must be written using the

Address All stack address. The command is not recognized if

sent with an individual device address and causes the master

device to respond NAK.

After receiving a valid Sleep command, the devices wait before

entering Sleep mode. This is to allow time for the top stack

device in a daisy chain to respond ACK, or for all devices that do

not recognize the command to respond NAK, and for the host

microcontroller to respond with another command. Receipt of

any valid communications on Port 1 of the ISL78610 before the

wait period expires cancels the Sleep command. Receipt of

another Sleep command restarts the wait timers. Table 16

provides the maximum wait time for various daisy chain data

rates. The communications fault checking timeout is not applied

to the Sleep command. A problem with the communications is

indicated by a lack of response to the host microcontroller. The

host microcontroller may choose to do nothing if no response is

received, in which case devices that received the Sleep

command go to sleep when the wait time expires. Devices that

do not receive the message go to sleep when their watchdog

timer expires (if this is enabled).

Using a Wake-up command does not require that the devices in a

stack be identified first. They do not need to know their position

in the stack.

The master exits Sleep mode on receipt of a valid Wake-up

command and transmits the Wake-up signal to the next device in

the stack. The Wake-up signal is a few cycles of a 4kHz clock. Each

device in the chain wakes up on receipt of the Wake-up signal and

sends the signal to the next device.

Any communications received on Port 1 by a device that is

transmitting the Wake-up signal on Port 2 are ignored.

The top stack device, after waking up, waits for some time before

sending an ACK response to the master. This wait time is

necessary to allow receipt of the Wake-up signal being originated

by a stack device other than the master. See “Fault Response in

Sleep Mode” on page 77 for more information.

Devices exit Sleep mode on receipt of a valid Wake-up command.

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ISL78610

The master device passes the ACK on to the host microcontroller

to complete the Wake-up sequence. The total time required to

wake up a complete stack of devices is dependent on the

number of devices in the stack. Table 17 gives the maximum

time from Wake-up command transmission to receipt of ACK

response (DATA READY asserted low) for stacks of 8 and

14 devices at various daisy chain data rates (interpolate linearly

for different number of devices).

CELL BALANCING FUNCTIONS

Cell balancing is performed using external MOSFETs and external

current balancing resistors (see Figure 51 on page 31). Each

MOSFET is controlled independently by the CB1 to CB12 pins of

the ISL78610. The CB1 to CB12 outputs are controlled either

directly, or indirectly by an external microcontroller through bits

in various control registers.

The three cell balance modes are Manual, Timed, and Auto.

TABLE 18. REGISTERS CONTROLLING BALANCE

TABLE 17. MAXIMUM WAKE-UP TIMES FOR STACKS OF 8 DEVICES

AND 14 DEVICES (WAKE-UP COMMAND TO ACK

RESPONSE)

REGISTER

Balance Setup

Balance Status

BALANCE MODE

REFERENCE

MAXIMUM WAKE-UP TIMES

Manual, Timed, Auto Table 19 on page 46

DAISY CHAIN DATA RATE (kHz)

Stack of 8 Devices (ms)

500

63

250

63

125

63

62.5

63

Watchdog/Balance Time Timed, Auto

Table 21 on page 47

Stack of 14 Devices (ms)

100

Device Setup

Timed, Auto

“Set-UpRegisters”on

page 88

There is no additional checking for communications faults while

devices are waking up. A communications fault is indicated by

the host microcontroller not receiving an ACK response within

the expected time.

Balance Value

Auto only

Table 22 on page 49

BALANCE MODE

Set the Balance mode with the BMD1 and BMD0 bits in the

Balance Setup Register (see Table 19).

Reset Command

All digital registers can be reset to their power-up condition using

the Reset Command.

In Manual mode, the host microcontroller directly controls the

state of each MOSFET output.

Daisy chain devices must be reset in sequence from the stack

top device to the stack bottom (master) device. Sending the

Reset command to all devices using the Address All stack

address has no effect. There is no response from the stack when

sending a Reset command.

In Timed mode, the host microcontroller programs a balance

duration value and selects which cells are to be balanced, then

starts the balance operation. The ISL78610 turns all the FETs off

when the balance duration has been reached.

In Auto Balance mode, the host microcontroller programs the

ISL78610 to control the balance MOSFETs to remove a

programmed “charge delta” value from each cell. The ISL78610

does this by controlling the amount of charge removed from each

cell over a number of cycles, rather than trying to balance all

cells to a specific voltage.

All stack address and stack size information is set to zero in

response to a Reset command. When all devices have been reset

it is necessary to reprogram the stack address and stack size

information using the Identify command.

A Reset command should be issued following a “hard reset” in

which the EN pin is toggled.

BALANCE WAIT TIME

The balance wait time is the interval between balancing

operations in Auto Balance mode (see Table 19).

Balance Enable Command

The Balance Enable command sets the BEN bit, which starts the

balancing operation. However, before this command becomes

operational and before balancing can commence, the balance

operation needs to be specified. See “Cell Balancing Functions”.

BALANCE ENABLE

When all of the other balance control bits are properly set,

setting the balance Enable bit to “1” starts the balance

operation. The BEN bit can be set by writing directly to the

Balance Setup register or by sending a Balance Enable

command. See Table 19.

The Balance Enable command can be sent to all devices with one

command using Address All addressing.

Balance Inhibit Command

The Balance Inhibit command clears the BEN bit, which stops the

balancing operation. The Balance Inhibit command can be sent

to all devices with one command using Address All addressing.

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ISL78610

TABLE 19. BALANCE SETUP REGISTER

REGISTER BITS

9

8

7

6

5

4

3

2

1

0

SECONDS

BETWEENBALANCE

BWT2 BWT1 BWT0 CYCLES

BALANCE

BMD1 BMD0 MODE

BEN BALANCE BSP3 BSP2 BSP1 BSP0

POINT TO REGISTER

0

1

Off

0

Balance Status 0

0

Off

9 8 7 6 5 4 3 2 1

Set bit to 1 to enable

balance

On

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Balance Status 1

Balance Status 2

Balance Status 3

Balance Status 4

Balance Status 5

Balance Status 6

Balance Status 7

Balance Status 8

Balance Status 9

Balance Status 10

Balance Status 11

Balance Status 12

0

1

0

1

0

1

0

1

0

1

0

1

2

0

1

0

1

Manual

Timed

Auto

4

8

16

32

64

bit 11 [BAL12] controls the FET for Cell 12. Bits are set to ‘1’ to

enable the balancing for that cell and cleared to ‘0’ to disable

balancing.

BALANCE STATUS POINTER

The Balance Status register is a “multiple instance” register (see

“Balance Status Register” on page 46. There are 13 locations

within this register and only one location can be accessed at a

time. The Balance Status Pointer points to one of these 13

locations (see Table 19).

Manual Balance Mode

In Manual Balance mode, the host microcontroller specifies

which cell is balanced and controls when balancing starts and

stops.

Manual Balance mode and Timed Balance mode requires a

balance status pointer value of ‘0’. In this case, the bits in the

Balance Status Register directly select the cells to be balanced.

To manually control the cells to be balanced:

• Set the Balance Mode bits to ‘01’ for “Manual”

• Set the balance status pointer to zero

The Auto Balance mode uses Balance Status register locations 1

to 12 (see Table 19). In Auto Balance mode, the ISL78610

increments the Balance Status pointer on each auto balance

cycle to step through Balance Status register locations 1 to 12.

This allows the programming of up to twelve different balance

profiles for each Auto Balance operation. When the operation

encounters a zero value at a pointer location, the auto balance

operation returns to the pattern at location 1 and resumes

balancing with that pattern.

• Set bits in the Balance Status register to program the cells to

be balanced (e.g., to balance Cell 5, set the BAL5 bit to 1)

• Enable balancing, either by setting the BEN bit in the Balance

Setup register or by sending a Balance Enable command

• Disable balancing either by resetting the BEN bit or by sending

a Balance Inhibit command

The Balance Enable and Balance Inhibit commands can be used

with the “Address All” device address to control all devices in a

stack simultaneously.

More information about the Auto Balance mode is provided in

“Auto Balance Mode” on page 47. Example balancing setup

information is provided in “Auto Balance Mode Cell Balancing

Example” on page 81.

Manual Balance mode cannot operate while the ISL78610 is in

Sleep mode. If the watchdog timer is off and the Sleep command

is received during Manual balance, balancing stops immediately

and the device goes into Sleep mode.

BALANCE STATUS REGISTER

The Balance Status register contents control which external

balance FET is turned on during a balance event. Each of the 12

bits in the Balance Status register controls one external

balancing FET, such that bit 0 [BAL1] controls the Cell 1 FET and

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ISL78610

TABLE 20. BALANCE, SLEEP, WAKE, WATCHDOG TIMER OPERATION

RECEIVE SLEEP COMMAND

ALL BALANCE MODES

Stop balancing

WATCHDOG TIMES OUT

ALL BALANCE MODES

RECEIVE WAKE COMMAND

MANUAL BALANCE TIMED BALANCE AUTO BALANCE

N/A

OPERATING WATCHDOG

IN

TIMER

Normal

Mode

Off

N/A

Device enters the Sleep mode.

On

Stop balancing.

N/A

Device enters the Sleep mode. Device enters the Sleep mode.

Set the WDTM bit when the

watchdog timer expires.

Set the WDTM bit.

Sleep Mode

N/A

Resume Balancing ResumeBalancing, Resume Balancing

Balance time

reduced by the

with Auto Balance

settings suspended

time spent in Sleep during Sleep

If the watchdog timer is active during manual balance and the

device receives the Sleep command, balancing stops

immediately and the device goes into Sleep mode, but the WDTM

bit is set when the watchdog timer expires (see Table 20).

TABLE 21. WATCHDOG/BALANCE TIME REGISTER

REGISTER BITS

13

12

11

10

9

8

7

BALANCE TIME

(MINUTES)

The ISL78610 has a watchdog timer function that protects the

battery from excess discharge due to balancing. If

communications are lost, the watchdog begins a count down. If

the timeout value is exceeded while the part is in Manual

Balance mode, all balancing ceases and the device goes into

Sleep mode. See Table 20.

BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 BTM0

0

1

0

1

0

1

Disabled

0.33

0

0.67

If the device was performing a manual balance operation before

a Sleep command, receiving a Wake command resumes

balancing.

0

1.00

-

•••

1

0

1

0

1

41.67

42.00

42.33

Timed Balance Mode

1

In Timed Balance mode, the host microcontroller specifies which

cell is balanced and sets a balance time-out period. Balancing

starts by control of the microcontroller and stops at the end of a

time-out period (or by a command from the microcontroller.)

1

Timed Balance mode cannot operate while the ISL78610 is in

Sleep mode. If the watchdog timer is off and the Sleep command

is received during Manual balance, then balancing stops

immediately and the device goes into Sleep mode.

To set up a timed balance operation:

• Set the Balance mode bits to ‘10’ for “Timed”

• Set the Balance Status Pointer to zero

If the watchdog timer is active during Timed balance and the

device receives the Sleep command, balancing stops

• Set bits in the Balance Status register to program the cells to

be balanced (for example to balance Cells 7 and 10, set the

BAL7 and BAL10 bits to 1)

immediately and the device goes into Sleep mode, but the WDTM

bit is set when the watchdog timer expires (see Table 20).

If the watchdog timeout value is exceeded while the part is in

Manual Balance mode, all balancing ceases and the device goes

into Sleep mode (see Table 20).

• Set the balance on time. The balance on time is

programmable in 20 second intervals from 20 seconds to

42.5 minutes using the BTM[6:0] bits. See Table 21

If the device was performing a Timed balance operation before a

Sleep command, receiving a Wake command resumes

balancing. However, the balance timer continues during the

Sleep mode, so if the Balance timer expires before a Wake

command, then Balance will not resume until the host

microcontroller starts another balance cycle.

• Enable balancing, either by setting the BEN bit in the Balance

Setup register or by sending a Balance Enable command.

When BEN is reasserted, or when a new Balance Enable

command is received, balancing resumes, using the full time

specified by the BTM[6:0] bits

• Disable balancing either by resetting the BEN bit or by sending

a Balance Inhibit command. Resetting BEN stops the

balancing functions and resets the timer values.

Auto Balance Mode

In Auto Balance mode, the host microcontroller specifies an

amount of charge to be removed from each cell to be balanced.

Balancing starts by control of the microcontroller and stops when

all cells have had the specified charge removed (or by command

from the microcontroller.)

• When the balance timeout period is met, the End Of Balance

(EOB) bit in the Device Setup register is set and BEN is reset.

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ISL78610

Auto Balance mode performs balancing autonomously and in an

intelligent manner. Thermal issues are accommodated by the

provision of auto balance sequencing (see “Auto Balance

Sequencing” on page 48), a multiple instance Balance Status

register, and a balance wait time.

Balance Status register instance at balance status pointer

location 1.

For example, using two Balance Status registers, the ISL78610

can balance odd numbered cells during the first cycle and even

numbered cells on the second cycle.

During Auto Balance mode the ISL78610 cycles through each

Balance Status register instance, which turns on the balancing

outputs corresponding to the bits set in each Balance Status

register instance. While each cell is being balanced, the amount

of charge withdrawn is calculated. Balancing stops for a cell

when the specified amount of charge has been removed. See

“Auto Balance SOC Adjustment value” on page 48.

There is a delay time between each cycle. This delay is set by the

balance wait time bits (see Table 19 on page 46)

Cells are balanced with periodic measurements performed

during the balance time interval (see Table 21). These

measurements are used to calculate the reduction in State of

Charge (SOC) with each balancing cycle.

When Auto Balancing is complete, the End Of Balance (EOB) bit

in the Device Setup register is set and BEN bit is reset.

As individual cells reach their programmed SOC adjustment, that

cell balance terminates, but the balance operation continues

cycling through all instances until all cells reach their SOC

adjustment value.

To set up an auto balance operation:

• Set the Balance Mode bits to ‘11’ for Auto

• Set the Balance Status Pointer to ‘1’

AUTO BALANCE SOC ADJUSTMENT VALUE

The balance value (delta SOC) is the difference between the

present charge in a cell and the desired charge for that cell.

• Set the bits in the Balance Status register to program the cells

to be balanced in the first cycle (for example, to balance odd

cells, set Bits 1, 3, 5, 7, 9, and 11)

The method for calculating the state of charge for a cell is left to

the system designer. Typically, determining the state of charge is

dependent on the chosen cell type and manufacturer, and is

dependent on cell voltage, charge and discharge rates,

temperature, age of the cell, number of cycles, and other factors.

Tables for determining SOC are often available from the battery

cell manufacturer.

• Set the Balance Status Pointer to ‘2’

• Set bits in the Balance Status register to program the cells to

be balanced in the second cycle (for example, to balance even

cells, set Bits 2, 4, 6, 8, 10, and 12)

• Set the Balance Status Pointer to ‘3’

• Set the bits in the Balance Status register at this location to

zero to terminate the sequence. The next cycle will go back to

balance at status pointer = 1.

The balance value itself is a function of the current SOC, required

SOC, balancing leg impedance, and sample interval. This value is

calculated by the host microcontroller for each cell. The

balancing leg impedance is made up of the external balance FET

and balancing resistor. The sample interval is equal to the

balance cycle on-time period (for example, each cell voltage is

sampled at the end of the balance on-time).

• Write the B values into the Balance Value Registers for each

cell to be balanced.

• Enable balancing, either by setting the BEN bit in the Balance

Setup register or by sending a Balance Enable command.

When enabled, the ISL78610 cycles through each instance of

the Balance Status register for the duration given by the

balance timeout. Between each Balance Status register

instance, the device does a Scan All operation and inserts a

delay equal to the balance wait time. The process continues

with the balance status pointer wrapping back to 1, until all

the Balance Value registers equal zero. If one cell Balance

Value register reaches zero before the others, balancing for

that cell stops, but the others continue.

The balancing value B for each cell is calculated using the

formula shown in Equation 1 (see also “Balance Value

Calculation Example” on page 81):

8191

5

Z

dt

------------

----

B =

 CurrentSOC – TargetSOC 

(EQ. 1)

where:

B = The balance register value

CurrentSOC = The present SOC of the cell (Coulombs)

TargetSOC = The required SOC value (Coulombs)

Z = The balancing leg impedance (Ω)

• Disable balancing either by resetting the BEN bit or by sending

a Balance Inhibit command. Resetting BEN, either directly or

by using the Balance Inhibit command, stops the balancing

functions but maintains the current Balance Value register

contents. Auto Balancing continues from Balance Status

register location 1 when BEN is reasserted.

dt = The sampling time interval (Balance cycle on time in seconds)

8191/5 = A voltage to Hex conversion value

The balancing leg impedance is normally the sum of the balance

FET r

and the balance resistor.

DS(ON)

AUTO BALANCE SEQUENCING

The first cycle of the auto balance operation begins with the

balance status pointer at location 1, specifying the first Balance

Status register instance. For the next auto balance cycle, the

balance status pointer increments to location 2. For each

subsequent cycle, the pointer increments to the next Balance

Status register instance, until a zero value instance is

encountered. At this point the sequence repeats from the

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ISL78610

The balancing value (B) can also be defined as in the set of

equations following. Auto balance is guided by Equations 2

and 3:

by the BDDS bit in the Device Setup register. If BDDS is set, cell

balancing is inhibited during cell voltage measurements and for

10ms before the cell voltage scan to allow the balance devices to

turn off. Balancing is re-enabled automatically at the end of the

scan. The Scan Continuous and BDDS function are available

during both Timed and Auto Balance modes, but not during

Manual Balance.

V

(EQ. 2)

(EQ. 3)

---

SOC = I  t =  t

Z

dt

V

Z

dt

V

dt

----

---

----

B = SOC 

=

 t 

=

 t

MONITORING CELL BALANCE

where:

To facilitate system monitoring of the cell balance operation, the

ISL78610 has a Cells Balanced Enabled register that shows the

present state of the balance drivers. A “1” bit indicates that the

CBn output is enabled. A “0” indicates that the CBn output is

disabled. This register is valid only in a Stand-Alone

configuration. Reading this register in any other mode results in a

NAK response.

dt = Balance cycle on time

t = Total balance time

Equations 2 and 3 show that the impedance drops out of the

equation, leaving only the voltage and time elements. So, B

becomes a collection of voltages that integrates during the

balance cycle on time, and accumulates over the total balance

time period to equal the programmed delta capacity.

TABLE 23. CELLS BEING BALANCED REGISTER

11 10

9

8

7

6

5

4

3

2

1

0

Twelve 28-bit registers are provided for the balance value for

each cell. The balance values are programmed for all cells as

needed using Balance Value registers 6’h20 to 6’h37 (see

Table 22 for the contents of the Cell 1 and Cell 2 Balance Values

registers).

TABLE 22. BALANCE VALUES REGISTER CELL1 AND CELL2

Daisy Chain Commands

ADDR 13 12 11 10

6’20

9

8

7

6

5

4

3

2

1

0

Daisy chain devices require some special commands that are not

needed by a stand-alone device. These commands are Identify,

ACK, and NAK. Identify is needed to enumerate the devices in the

stack. ACK is used as a command to check the communications

hardware and to indicate proper communications status. A NAK

response indicates a problem with the addressed device

recognizing the command.

Cell 1 Balance Value Bits [13:0]

6’21

6’22

6’23

Cell 1 Balance Value Bits [27:14]

Cell 2 Balance Value Bits [13:0]

Cell 2 Balance Value Bits [27:14]

At the end of each balance cycle on time interval the ISL78610

measures the voltage on each of the cells that were balanced

during that interval. The measured values are then subtracted

from the balance values for those cells. This process continues

until the balance value for each cell is zero, at which time the

auto balancing process is complete.

Identify Command

Identify mode is a special case mode that must be executed

before any other communications to daisy chained devices,

except for the Sleep command and Wake-up command. The

Identify command initiates address assignments to the devices

in the daisy chain stack.

Auto Balance mode cannot operate while the ISL78610 is in

Sleep mode. If the Sleep command is received while the device is

auto balancing (and the watchdog timer is off), balancing

continues until it is finished and the device enters Sleep mode. If

the watchdog timer is active during the Auto Balance mode and

the device receives the Sleep command, balancing stops

immediately and the device enters Sleep mode immediately. The

WDTM bit is set when the watchdog timer expires (see Table 20).

Devices determine their stack position while in Identify mode.

Identify mode is entered on receipt of the “base” Identify

command (this is the Identify command with the device address

set to 6’h00). The top stack device responds ACK after receiving

the base Identify command and enters the Identify mode. Other

stack devices wait to allow the ACK response to be relayed to the

host microcontroller, then enter Identify mode. When in Identify

mode, all stack devices except the master load address 4’h0 to

their stack address register. The master (identified by the state of

the Comms Select pins = 2’b01) loads 4’h1 to its stack address.

If the device was performing an Auto balance operation before a

Sleep Command, receiving a Wake command resumes

balancing with the same SOC calculations that were in place

when the device entered Sleep Mode.

After receiving the ACK response the host microcontroller sends

the Identify command with stack address 6’h2 (that is, 24’h0000

0011 0010 0100 0010 0110; the stack address is bolded). The

last four bits are the corresponding CRC value. The master

passes the command onto the stack. The device at stack

position 2 responds by setting the stack address bits (ADDR[3:0])

and stack size bits (SIZE[3:0]) in the Comms Setup register to

4’h2 and returns the Identify response with CRC and an address

of 6’h32 (that is, 32’b0000 0011 0010 0111 0010 0000 0000

1111; the address bits are bolded). The address bits contains the

BALANCING IN SCAN CONTINUOUS MODE

Cell balancing may be active while the ISL78610 is operating in

Scan Continuous mode. In Scan Continuous mode the ISL78610

scans cell voltages, temperatures, and open-wire conditions at a

rate determined by the Scan Interval bits in the Fault Setup

register (see Table 14 on page 42). The behavior of the balancing

functions while operating in Scan Continuous mode is controlled

FN8830 Rev 3.00

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ISL78610

normal stack address (2’h0010) and the state of the Comms

Select pins (2’b11). Note that the in an Identify response, the

data LSBs are always zero.

loads the stack address and stack size information and returns

the Identify response with address 6’h2x, where x corresponds to

the stack position of the top device. The host microcontroller

recognizes the top stack response and loads the total number of

stack devices to local memory. The host microcontroller then

sends the Identify command with data set to 6’h3F. Devices exit

Identify mode on receipt of this command. The stack top device

responds ACK. An example Identify transmit and receive

The host microcontroller then sends the Identify command with

stack address 6’h3. Device 3 responds by setting its stack

address and stack size information to 4’h3 and returning the

Identify response with address 6’h33. Devices 1 and 2 set their

stack size information to 4’h3.

sequence for a stack of three devices is shown in Figure 60.

The process continues with the host microcontroller

When in Normal mode, only the base Identify command is

recognized by devices. Any other Identify command variant or an

Identify command sent with a nonzero stack address causes a

NAK response from the addressed device(s).

incrementing the stack address until all devices in the stack

receive their stack address. Identified devices update their stack

size information with each new transmission. The stack top

device (identified by the state of the Comms Select pins = 10)

0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0

Send Identify Command

Tx

03 24 04

Rx

03 30 00 0C

0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0

Send Identify Device 2

Send Identify Device 3

Send Identify Complete

Tx

Rx

Tx

03 24 26

03 27 20 0F

03 24 37

0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 1

0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0

Rx

Tx

Rx

03 26 30 05

03 27 FE

0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

33 30 00 01

FIGURE 60. IDENTIFY EXAMPLE, STACK OF 3 DEVICES

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ISL78610

receiving the daisy response, the master sends the response to

the host through the SPI port.

IDENTIFY TIMING

Refer to Table 24 to determine the time required to complete an

Identify operation. The table’s two SPI Command columns show

the time required to send the Identify command and receive the

response (with a 1MHz SPI clock). The master has no daisy chain

clocks, so all three bytes of the send and four bytes of the receive

are accumulated. For the daisy chain devices, the daisy

communication overlaps with two of the SPI send bytes and with

three of the SPI receive bytes, so no extra time is needed for

these bits.

The “Time for Each Device” column shows the time for the

Identify commands to be sent and propagate through each

numbered device. The “Identify Total Time” column shows the

total accumulated time required for Identify commands to be

sent and propagate through all devices in the battery stack

configuration. The “Identify + Identify Complete Time”

columnadds the identify complete timing to the total. The

Identify Complete command takes the same number of clock

cycles as the last Identify command.

When the device receives the Identify command, it adds a Delay

time before sending the response back to the master. After

.

TABLE 24. IDENTIFY TIMING WITH DAISY CHAIN OPERATING AT 500kHz

NUMBER OF SPI COMMAND

DAISY

TRANSMIT TIME

(μs)

RESPONSE

DELAY

(µs)

DAISY

TIME FOR

IDENTIFY IDENTIFY + IDENTIFY

DEVICES

SEND TIME

RECEIVE TIME SPI COMMAND EACH DEVICE TOTAL TIME

COMPLETE TIME

(µs)

(2 MINIMUM)

(μs)

(µs)

0

RECEIVE TIME (µs)

(µs)

56

(µs)

56

1 (Master)

24

8

0

32

8

56

2

3

50

52

54

56

58

60

62

64

66

68

70

72

74

18

66

68

70

72

74

76

78

80

82

84

86

88

90

150

154

158

162

166

170

174

178

182

186

190

194

198

206

356

360

514

4

518

676

5

680

842

6

846

1012

1186

1364

1546

1732

1922

2116

2314

2516

7

1016

1190

1368

1550

1736

1926

2120

2318

8

9

10

11

12

13

14

.

TABLE 25. IDENTIFY TIMING WITH DAISY CHAIN OPERATING AT 250kHz

NUMBER OF SPI COMMAND

DAISY

TRANSMIT TIME

(μs)

RESPONSE

DELAY

(μs)

DAISY

TIME FOR

IDENTIFY

DEVICES

SEND TIME

(µs)

RECEIVE TIME SPI COMMAND EACH DEVICE TOTAL TIME IDENTIFY + IDENTIFY

(2 MINIMUM)

(µs)

RECEIVE TIME (µs)

(µs)

COMPLETE TIME (µs)

1 (Master)

24

8

0

32

8

56

2

3

100

104

108

112

116

120

124

128

132

136

140

144

148

34

132

136

140

144

148

152

156

160

164

168

172

176

180

282

290

298

306

314

322

330

338

346

354

362

370

378

338

620

628

918

4

926

1224

1538

1860

2190

2528

2874

3228

3590

3960

4338

4724

5

1232

1546

1868

2198

2536

2882

3236

3598

3968

4346

6

7

8

9

10

11

12

13

14

FN8830 Rev 3.00

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Page 51 of 100

ISL78610

formulated. An incorrect formulation, (for example, a read bit

instead of a write bit), causes the port to lose synchronization.

ACK (Acknowledge) Command

The daisy chain devices use the ACK command to acknowledge

receipt of a valid command. ACK is also useful as a

communications test command: the stack top device returns

ACK in response to successful receipt of the ACK command. No

other action is performed in response to an ACK.

A timeout period associated with the CS inactive (high) condition

resets all the communications counters. This effectively resets

the SPI port to a known starting condition. If CS stays high for

more than 100µs, the SPI state machine resets.

A pending device response from a previous command is sent by

the ISL78610 during the first two bytes of the 3-byte Write

transaction. The third byte from the ISL78610 is then discarded

by the host microcontroller. This maintains sequencing during

3-byte (Write) transactions.

NAK (Not Acknowledge) Command

Receipt of an unrecognized command by either the target device

or the top stack device results in a NAK being returned by that

device. If a command addressed to all devices using the Address

All stack address 1111 or the identify stack address 0000 is not

recognized by any devices, then all devices not recognizing the

command respond NAK. In this case, the host microcontroller

receives the NAK response from the lowest stack device that

failed to recognize the command. An incomplete command (for

example, one that is less than the length required) also causes a

NAK to be returned.

Figure 3 on page 14 shows interface timing for full duplex SPI

transfers.

HALF DUPLEX (DAISY CHAIN) OPERATION

The SPI operates in half duplex mode when configured as a daisy

chain application (see Table 6 on page 27). Data flow is controlled

by a handshake system using the DATA READY and CS signals.

DATA READY is controlled by the ISL78610. CS is controlled by

the host microcontroller. This handshake accommodates the

delay between command receipt and device response due to the

latency of the daisy chain communications system.

Communications

All communications are conducted through the SPI port in single

8-bit byte increments. The MSB is transmitted first and the LSB is

transmitted last.

A timeout period associated with the CS inactive (high) condition

resets all the communications counters. This effectively resets

the SPI port to a known starting condition. If CS stays high for

more than 100µs, the SPI state machine resets.

Maximum operating data rates are 2Mbps for the SPI interface.

When using the daisy chain communications system it is

recommended that the synchronous communications data rate

be at least twice that of the daisy chain system (see Table 7).

Responses from stack devices are received by the stack master

(stack bottom device). The stack master then asserts its DATA

READY output when the first full data byte is available. The host

microcontroller responds by asserting CS and clocking the data

out of the DOUT port. The DATA READY line is then cleared and

DOUT is tri-stated in response to CS being taken high. The DIN

and DOUT lines can be connected externally in this mode.

In stand-alone applications (non-daisy chain) data is sent without

additional address information. This maximizes the throughput

for full duplex SPI operation.

In daisy chain applications all measurement data is sent with the

corresponding device stack address (the position within the daisy

chain), parameter identifier, and data address. Daisy chain

communication throughput is maximized by allowing streamed

data (accessed by a “read all data” address).

Half duplex communications are conducted using the DATA

READY/CS handshake as follows:

1. The host microcontroller sends a command to the ISL78610

using the CS line to select the ISL78610 and clocking data

into the ISL78610 DIN pin.

SPI Interface

The ISL78610 operates as an SPI slave capable of bus speeds up

to 2Mbps. Four lines make up the SPI interface: SCLK, DIN, DOUT,

and CS. The SPI interface operates in either full duplex or half

duplex mode depending on the daisy chain status of the part.

2. The ISL78610 asserts DATA READY low when it is ready to

send data to the host microcontroller. When DATA READY is

low, the ISL78610 is in transmit mode and will ignore any

data on DIN.

The DOUT line is normally tri-stated (high impedance) to allow

use in a multidrop bus. DOUT is active only when CS is low.

3. The host microcontroller asserts CS low and clocks 8 bits of

data out of DOUT using SCLK.

An additional output DATA READY is used in the daisy chain

configuration to notify the host microcontroller that responses

have been received from a device in the chain.

4. The host microcontroller then raises CS. The ISL78610

responds by raising DATA READY and tri-stating DOUT.

5. The ISL78610 reasserts DATA READY for the next byte, and so

on.

FULL DUPLEX (STAND-ALONE) SPI OPERATION

In non-daisy chain applications, the SPI bus operates as a

standard, full duplex SPI port. Read and write commands are

sent to the ISL78610 in 8-bit blocks. CS is taken high between

each block.

Data flow is controlled by interpreting the first bit of each

transaction and counting the requisite number of bytes. The host

microcontroller ensures that commands are correctly

FN8830 Rev 3.00

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ISL78610

The host microcontroller must service the ISL78610 if DATA

READY is low before sending further commands. The ISL78610

ignores any data sent to DIN while DATA READY is low.

are then loaded to the shift register when CS goes low and are

shifted out on the DOUT line on the falling edges of SCLK. This

sequence continues until all the requested data has been sent.

The ISL78610 DATA READY output is not asserted if CS is already

asserted. It is possible for the microcontroller to interrupt a

sequential data transfer by asserting CS before the ISL78610

asserts DATA READY. This causes a conflict with the

communications and is not recommended. A conflict created in

this manner would be recognized by the microcontroller either

not receiving the expected response or receiving a

Commands and data are memory mapped to 14-bit data

locations. The memory map is arranged in pages. Pages 1 and 2

are used for volatile data. Page 3 contains the action and

communications administration commands. Page 4 accesses

nonvolatile memory. Page 5 is used for factory test.

Action commands, such as scan and communications

administration operations are treated as reads.

communications failure notification.

Non-daisy chain devices do not generate a response to write or

system level commands. Data integrity can be verified by reading

register contents after writing. The ISL78610 does nothing in

response to a write or administration command that is not

recognized. An unrecognized read command returns 16’h0000.

An incomplete command, such as may occur if communications

are interrupted, is registered as an unrecognized command

either when CS is taken high or after a timeout period. The

communications interface is reset after the timeout period.

Figure 4 on page 14 shows interface timing for half duplex SPI

transfers.

Non-Daisy Chain Communications

In non-daisy chain (Stand-Alone) systems, all communications

sent from the master are 2 or 3 bytes in length. Data read and

action commands are 2 bytes. Data writes are 3 bytes. Device

responses are 2 bytes in length and contain data only.

Write commands in non-daisy chain systems consist of a

read/write bit, page address (3 bits), data address (6 bits), and

data (14 bits) - three bytes.

Non-daisy chain communications are conducted without CRC

(Cyclical Redundancy Check) error detection. The following

commands have no meaning in non-daisy chain systems:

Identify, ACK, and NAK.

Read commands in non-daisy chain systems are composed of a

read/write bit, page address (3 bits), data address (6 bits), fill

(6 bits), and 16 bits of returned data (ignore the first most

significant bits of data returned) - four bytes.

The rules for non-daisy chain installations are shown in Table 26.

Examples of full duplex SPI read and write sequences are shown

in Figures 61, 62, and 63. An example Device Read (Cell 7), with

response, is shown in Figure 63.

The ISL78610 responds to read commands by loading the

requested data to its output buffer. The output buffer contents

TABLE 26. ISL78610 DATA INTERPRETATION RULES FOR NON-DAISY CHAIN INSTALLATIONS

DATA

FIRST BIT IN PAGE

SEQUENCE ADDR ADDRESS

INTERPRETATION

0

1

011

Any

001000 Measure command. The last six bits of the transmission contain the element address.

All other Device read or action command. The last six bits of the transmission are zero.

Any

Device write command.

CS

SCLK

DOUT

DIN

Note 11

MSB

Note 11

HIGH IMPEDANCE

NOT DETERMINED

ACTIVE

1

0

1

0

1

0

R

W

PAGE

ADDR

DATA

FILL WITH 0

ADDRESS

FIGURE 61. SPI FULL DUPLEX (STAND-ALONE) MEASURE COMMAND EXAMPLE: EXT4 VOLTAGE

FN8830 Rev 3.00

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ISL78610

CS

SCLK

DOUT

DIN

Note 11

Note 12

LSB

0

MSB

1

0

1

0

1

0

1

0

1

0

1

0

1

R

W

HIGH IMPEDANCE

NOT DETERMINED

ACTIVE

PAGE

ADDR

DATA

ADDRESS

CELL UNDERVOLTAGE THRESHOLD DATA

NOTES:

11. Last data byte pair from previous command.

12. Not defined.

FIGURE 62. SPI FULL DUPLEX (STAND-ALONE) WRITE COMMAND EXAMPLE: WRITE UNDERVOLTAGE THRESHOLD DATA

CS

SCLK

DOUT

Note 13

0

1

0

1

0

1 0 1 0

MSB

0

LEADING

ZEROS

CELL7 DATA

RESPONSE

COMMAND

Note 14

DIN

0

1

0

1

0

0 0 0 0

R

W

PAGE

ADDR

DATA

ADDRESS

HIGH IMPEDANCE

NOT DETERMINED

ACTIVE

NOTES:

13. Last data byte pair from previous command.

14. Next command (or 8’h00 if no command).

FIGURE 63. SPI FULL DUPLEX (STAND-ALONE) READ COMMAND EXAMPLE: READ CELL 7 DATA

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ISL78610

EXAMPLE NON-DAISY COMMUNICATIONS

Daisy Chain Communications

Examples of the various command structures for non-daisy chain

installations are shown in Figures 64A through 64E.

Commands in daisy chain systems are transmitted and received

through the SPI port and are composed of a device address

(4 bits), a read/write bit, page address (3 bits), data address

(6 bits), data (6 bits), and CRC (4 bits).

DATA

ADDRESS

(11, 6)

TRAILING

ZEROS

(5, 0)

PAGE

(14, 12)

Device commands and data are memory mapped to 14-bit data

locations. The memory map is arranged in pages. Pages 1 and 2

are used for volatile data. Page 3 contains the action and

communications administration commands. Page 4 accesses

nonvolatile memory. Page 5 is used for factory test.

0

1

0

1

0

1

0

MSB

BYTE 1

BYTE 0

LSB

FIGURE 64A. DEVICE LEVEL COMMAND: SLEEP

The daisy chain communication is intended for use with large

stacks of battery cells with many ISL78610 devices.

DATA

ADDRESS

(11, 6)

TRAILING

ZEROS

(5, 0)

Communications Protocol

PAGE

(14, 12)

All daisy chain communications are passed from device to device

so that all devices in the stack receive the same information.

Each device then decodes the message and responds as needed.

The originating device (master in the case of commands,

addressed device or top stack device in the case of responses)

generates the system clock and data stream. Each device delays

the data stream by one clock cycle. Each device knows its stack

location (see the Identify command on page 49) and the total

number of devices in the stack. Each originating device adds a

number of clock pulses to the daisy chain data stream to allow

transmission through the stack.

0

1

0

1

0

MSB

BYTE 1

BYTE 0

LSB

FIGURE 64B. DEVICE LEVEL COMMAND: WAKE-UP

DATA

ADDRESS

(11, 6)

TRAILING

ZEROS

(5, 0)

PAGE

(14, 12)

0

1

0

1

0

All communications from the host microcontroller are passed

from device to device to the last device in the chain (top device).

The top device responds to read and write messages with an

“ACK” (or with the requested data if this is the addressed device

and the message was a read command). The addressed device

then waits to receive the “ACK” before responding, either with

data, in the case of a read, or with an “ACK” in the case of a write.

Action commands such as the Scan commands do not require a

response.

MSB

BYTE 1

BYTE 0

LSB

FIGURE 64C. DEVICE LEVEL COMMAND: SCAN VOLTAGES

DATA

ADDRESS

(11, 6)

ELEMENT

ADDRESS

(5, 0)

PAGE

(14, 12)

0

1

0

1

0

1

0

1

A read or write communications transmission is only considered to

be complete following receipt of a response from the target device

or the identification of a communications fault condition. The host

microcontroller should not transmit further data until either a

response has been received from the target stack device or a

communications fault condition has been identified. Figure 65 on

page 56 shows a typical communication sequence to “Read

Device 4, Cell 7” data from a stack of 10 devices. The maximum

response time (the time from the rising edge of CS at the end of

the first byte of a read/write command, sent by the host

MSB

BYTE 1

BYTE 0

LSB

FIGURE 64D. DEVICE LEVEL COMMAND: MEASURE CELL 5 VOLTAGE

DATA

ADDRESS

(19, 14)

DATA

(13, 0)

PAGE

(22, 20)

1

0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

MSB

BYTE 2

BYTE 1

BYTE 0

LSB

microcontroller, to the assertion of DATA READY by the master

device) is given in Table 27 for various daisy chain data rates.

FIGURE 64E. DEVICE WRITE: WRITE EXTERNAL TEMPERATURE

LIMIT = 14’h0FFF

TABLE 27. MAXIMUM RESPONSE TIMES FOR DAISY CHAIN READ AND

WRITE COMMANDS. STACK OF 10 DEVICES

FIGURE 64. NON-DAISY CHAIN DEVICE COMMAND AND WRITE

EXAMPLES

MAXIMUM TIME TO ASSERTION

OF DATA READY

DAISY CHAIN DATA RATE (kHz) 500

Response time 240

250

480

125

960

62.5

UNIT

µs

1920

FN8830 Rev 3.00

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ISL78610

SCLK

DIN

A

DOUT

B

SPI

CS

DATA READY

10 EXTRA

CLOCKS

PACKET A

MASTER Tx

MASTER Rx

DEVICE 4 Tx

DEVICE 4 Rx

NO EXTRA

CLOCKS

PACKET B

4 EXTRA

CLOCKS

4 DAISY CLOCK PULSES

PACKET A

PACKET B

6 EXTRA

CLOCKS

DAISY

CHAIN

ACK

5 EXTRA

CLOCKS

10 EXTRA

CLOCKS

DEVICE 10 Tx

DEVICE 10 Rx

ACK

PACKET A

NO EXTRA CLOCKS

10 DAISY CLOCK PULSES

• Host microcontroller sends “Read Device 4, Cell 7” = Packet A

• Device 4 receives and decodes ACK.

• Master begins relaying Packet A following receipt of the first byte of

A. Master adds 10 extra clock cycles to allow all stack devices to relay

the message.

• Device 4 transmits the Cell 7 data = Packet B. Device 4 subtracts one

clock cycle to synchronize timing for lower stack devices to relay the

message.

• Device 4 receives and decodes “Read Device 4, Cell 7” and waits for a

response from top stack device.

• Master asserts DATA READY after receiving the first byte of Packet B.

• Host responds by asserting CS and clocking out 8 bits of data from

DOUT. CS is taken high following the 8th bit. The master responds by

taking DATA READY high and tri-stating DOUT. Master asserts

DATA READY after receiving the next byte and so on.

• Top of stack (device 10) receives and decodes Packet A.

• Device 10 responds “ACK”. Device 10 adds 10 clock cycles to allow

all stack devices to relay the message.

FIGURE 65. DAISY CHAIN READ EXAMPLE “READ DEVICE 4, CELL 7”. STACK OF 10 DEVICES

TABLE 28. ISL78610 DATA INTERPRETATION RULES FOR DAISY CHAIN INSTALLATIONS

TH

5

BIT

FIRST 4 BITS IN SEQUENCE

Stack address [3:0] (nonzero)

0000

(R/W)

PAGE

011

Any

DATA ADDRESS

001000

001001

All other

Any

INTERPRETATION

0

1

Measure command. Data address is followed by 6-bit element address.

Identify command. Data address is followed by device count data.

Device Read command. Data address is followed by 6 zeros.

Device Write command.

Stack address [3:0] (nonzero)

Any

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ISL78610

DAISY CHAIN RECEIVE BUFFER

DIN

CS

RECEIVE IDENTIFY RESPONSE

≤ 31.5 t

SCK

≤ 31.5 t

D

DATA READY

Daisy Clocks

MASTER

DAISY PORT

DHI2/DLO2

8* t

D

Extra Bytes during “Read All” responses, fault responses, and first Identify response.

A fault response may precede command response increasing number of returned bytes.

The First Identify Response has 14 extra clocks because the stack size is not yet known.

The SPI must clock out 4 bytes before the Daisy can clock in 4 bytes to prevent buffer overflow.

FIGURE 66. EXAMPLE WORST CASE TIMING TO AVOID DAISY BUFFER OVERFLOW

commands, are treated as reads. Daisy chain communications

employ a 4-bit CRC (Cyclic Redundancy Check) using a

polynomial of the form 1 + X + X . The first four bits of each daisy

chain transmission contain the stack address, which can be any

number from 0001 to 1110. All devices respond to the Address

All (1111) and Identify (0000) stack addresses. The fifth bit is set

to ‘1’ for write and ‘0’ for read. The rules for daisy chain

installations are shown in Table 28 on page 56.

A 4-byte data buffer is provided between the Daisy Chain and SPI

communications. This accommodates all single transaction

responses. Multiple byte responses, such as Identify, Read All

Voltages, Read All Temperatures, Read All Faults, and responses

that may include a fault response from a device detecting an

error, would overflow this buffer. Therefore, it is important that

the host microcontroller completes a read of the first byte of data

before a fifth byte arrives on the Master device’s daisy chain port

and to clock data out from the SPI port faster than data is

clocked in through the Daisy port to prevent data loss.

4

CRC Calculation

Daisy chain communications use a 4-bit CRC with a polynomial

4

of the form 1 + X + X . The polynomial is implemented as a

For example, when performing the first step in an IDENTIFY

operation (see “Identify Command” on page 49) the daisy chain

top device returns a 4-byte response plus 14 extra zeros (because

it does not yet know how many devices are in the stack.) If the

Host does not read the first byte from the Master before the 32nd

daisy clock, the extra zeros will overwrite the first byte of the

response. In another example, a “Read All Faults” returns 22

bytes. It is important for the Host to read data from the ISL78610

faster than 4 bytes every 31.5 Daisy clocks (see Figure 66).

4-stage internal XOR standard linear feedback shift register as

shown in Figure 67. The CRC value is calculated using the base

command data only. The CRC value is not included in the

calculation.

The host microcontroller calculates the CRC when sending

commands or writing data. The calculation is repeated in the

ISL78610 and checked for compliance. The ISL78610 calculates

the CRC when responding with data (device reads). The host

microcontroller then repeats the calculation and checks for

compliance.

COMMUNICATION SEQUENCES

All daisy chain device responses are 4-byte sequences, except for

the responses to the Read All command. All responses start with

the device stack address and use a 4-bit CRC. The response to

the “Read All Commands” is to send a normal 4-byte data

response for the first data segment and continue sending the

remaining data segments in 3-byte sections composed of the data

address, data, and CRC. This creates an anomaly with the normal

CRC usage in that the first four bytes have a 4-bit CRC at the end

(operating on 3.5 bytes of data) while the remaining bytes have a

CRC which only operates on 2.5 bytes. The host microcontroller,

having requested the data, must be prepared for this.

DIN

+

FF0

FF1

FF2

FF3

FIGURE 67. 4-BIT CRC CALCULATION

Daisy chain devices require device stack address information to

be added to the basic command set. Daisy chain writes are

4-byte sequences. Daisy chain reads are 3 bytes. Action

commands, such as scan and communications administration

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ISL78610

Attribute VB_Name = "isl78610evb_crc4_lib"

' File - isl78610evb_crc4_lib.bas

' -----------------------------------------------------------------------------

Option Explicit

'***********************************************************

' CRC4 Routines

'initialize bits

bit0 = False

bit1 = False

bit2 = False

bit3 = False

'***********************************************************

Public Function CheckCRC4(myArray() As Byte) As Boolean

'returns True if CRC4 checksum (low nibble of last byte in myarray)

'is good. Array can be any length

'simple implementation of CRC4 (using polynomial 1 + X + X^4)

For i = LBound(arraycopy) To UBound(arraycopy)

'last nibble is ignored for CRC4 calculations

If i = UBound(arraycopy) Then

Dim crc4 As Byte

Dim lastnibble As Byte

k = 4

Else

k = 8

lastnibble = myArray(UBound(myArray)) And &HF

crc4 = CalculateCRC4(myArray)

End If

For j = 1 To k

If lastnibble = crc4 Then

CheckCRC4 = True

Else

'shift left one bit

carry = (arraycopy(i) And &H80) > 0

arraycopy(i) = (arraycopy(i) And &H7F) * 2

CheckCRC4 = False

End If

'see ISL78610 datasheet, Fig 11: 4-bit CRC calculation

ff0 = carry Xor bit3

ff1 = bit0 Xor bit3

ff2 = bit1

End Function

Public Sub AddCRC4(myArray() As Byte)

'adds CRC4 checksum (low nibble in last byte in array)

'array can be any length

ff3 = bit2

bit0 = ff0

bit1 = ff1

bit2 = ff2

Dim crc4 As Byte

bit3 = ff3

Next j

crc4 = CalculateCRC4(myArray)

Next i

myArray(UBound(myArray)) = (myArray(UBound(myArray)) And &HF0) Or

crc4

'combine bits to obtain CRC4 result

result = 0

End Sub

If bit0 Then

result = result + 1

End If

If bit1 Then

result = result + 2

End If

Public Function CalculateCRC4(ByRef myArray() As Byte) As Byte

'calculates/returns the CRC4 checksum of array contents excluding

'last low nibble. Array can be any length

Dim size As Integer

If bit2 Then

Dim i As Integer

Dim j As Integer

result = result + 4

End If

Dim k As Integer

If bit3 Then

Dim bit0 As Boolean, bit1 As Boolean, bit2 As Boolean, bit3 As Boolean

Dim ff0 As Boolean, ff1 As Boolean, ff2 As Boolean, ff3 As Boolean

Dim carry As Boolean

result = result + 8

End If

Dim arraycopy() As Byte

CalculateCRC4 = result

Dim result As Byte

End Function

'copy data so we do not clobber source array

ReDim arraycopy(LBound(myArray) To UBound(myArray)) As Byte

For i = LBound(myArray) To UBound(myArray)

arraycopy(i) = myArray(i)

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ISL78610

The state of the COMMS SELECT 1, COMMS SELECT 2, COMMS

RATE 0, and COMMS RATE 1 pins can be checked by reading the

CSEL[2:1] and CRAT[1:0] bits in the Comms Setup register (see

Table 29). The SIZE[3:0] bits show the number of devices in the

daisy chain and the ADDR[3:0] bits indicate the location of a

device within the daisy chain.

Daisy Chain Addressing

When used in a daisy chain system, each individual device

dynamically assigns itself a unique address (see “Identify

Command” on page 49). In addition, all daisy chain devices

respond to a common address, allowing them to be controlled

simultaneously (for example, when using the Scan Voltages and

Balance Enable commands). See “Communication Timing” on

page 61.

Examples of the various read and write command structures for

daisy chain installations are shown in Figures 70C to 70G. The

MSB is transmitted first and the LSB is transmitted last.

TABLE 29. COMMS SETUP REGISTER (ADDRESS 6’h18)

11

10

9

8

7

6

5

4

3

2

1

0

CRAT1

CRAT0

CSEL2

CSEL1

SIZE3

SIZE2

SIZE1

SIZE0

ADDR3

ADDR2

ADDR1

ADDR0

These bits show the status These bits show the status These bits show the daisy chain stack size These bits show this devices position within

of the COMMS RATE 1 and of the COMMS SEL 2 and

(that is, the total number of stacked devices) the daisy chain stack

COMMS RATE 0 pins

COMMS SEL 1 pins

CS

SCLK

DOUT

DIN

TRI-STATE

COMMAND

0

1

0 1 0

1

0

1

0

1

0

1

0

1

0

0 0 0 0

R

/W

DATA TO WRITE

DEVICE

ADDR

PAGE

ADDR

DATA

ADDRESS

CRC

FIGURE 69. SPI HALF DUPLEX (DAISY CHAIN) WRITE REGISTER COMMAND EXAMPLE: WRITE DEVICE 1, DEVICE SETUP REGISTER

DEVICE

ADDRESS

(23, 20)

DATA

ADDRESS

(15, 10)

CRC

(3, 0)

ZERO

(9, 4)

PAGE

(18, 16)

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 2

BYTE 1

BYTE 0

FIGURE 70A. DEVICE LEVEL COMMAND: SLEEP

DATA

DEVICE

ADDRESS

(23, 20)

ZERO

(9, 4)

ADDRESS

(15, 10)

CRC

(3, 0)

PAGE

(18, 16)

1

0

1

0

1

0

1

LSB

MSB

BYTE 2

BYTE 1

BYTE 0

FIGURE 70B. DEVICE LEVEL COMMAND: WAKE-UP

FN8830 Rev 3.00

May 10, 2018

Page 59 of 100

ISL78610

DEVICE

ADDRESS

(23, 20)

DATA

ADDRESS

(15, 10)

ZERO

(9, 4)

CRC

(3, 0)

PAGE

(18, 16)

1

0

1

0

1

0

1

0

1

LSB

MSB

BYTE 2

BYTE 1

BYTE 0

FIGURE 70C. DEVICE LEVEL COMMAND: DEVICE 9, SCAN VOLTAGES

DEVICE

ADDRESS

(23, 20)

DATA

ADDRESS

(15, 10)

CRC

(3, 0)

ZERO

(9, 4)

PAGE

(18, 16)

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 2

BYTE 1

BYTE 0

FIGURE 70D. DEVICE READ: DEVICE 9, GET CELL 7 DATA

DEVICE

ADDRESS

(23, 20)

DATA

ADDRESS

(15, 10)

ELEMENT

ADDRESS

(9, 4)

CRC

(3, 0)

PAGE

(18, 16)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSB

MSB

BYTE 2

BYTE 1

BYTE 0

FIGURE 70E. ELEMENT LEVEL COMMAND: DEVICE 4, MEASURE CELL 5 VOLTAGE

DEVICE

ADDRESS

(23, 20)

DATA

ADDRESS

(15, 10)

DEVICE

COUNT

(9, 4)

CRC

(3, 0)

PAGE

(18, 16)

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 2

BYTE 1

FIGURE 70F. IDENTIFY COMMAND

BYTE 0

DEVICE

ADDRESS

(31, 28)

DATA

ADDRESS

(23, 18)

DATA

(17, 4)

CRC

(3, 0)

PAGE

(26, 24)

0

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 3

BYTE 2

BYTE 1

BYTE 0

FIGURE 70G. DEVICE WRITE: DEVICE 7, WRITE EXTERNAL TEMPERATURE LIMIT = 14’h0FFF

FIGURE 70. DAISY CHAIN DEVICE READ AND WRITE EXAMPLES

FN8830 Rev 3.00

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ISL78610

Response examples are shown in Figures 71A to 71D.

DEVICE

ADDRESS

(31, 28)

DATA

ADDRESS

(23, 18)

PAGE

DATA

(17, 4)

CRC

(3, 0)

(26, 24)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 3

BYTE 2

BYTE 1

BYTE 0

FIGURE 71A. DEVICE DATA RESPONSE: DEVICE 9, CELL 7 VOLTAGE = 14’h170A (3.6V)

DEVICE

ADDRESS

(31, 28)

DATA

PAGE

ADDRESS

(23, 18)

ZEROS

(17, 4)

CRC

(3, 0)

(26, 24)

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 3

BYTE 2

BYTE 1

BYTE 0

FIGURE 71B. DEVICE COMMUNICATIONS ADMINISTRATION RESPONSE: DEVICE 10, ACK

DEVICE

ADDRESS

(31, 28)

DATA

ADDRESS

(23, 18)

DEVICE TYPE/

ADDRESS

(17, 4)

PAGE

CRC

(3, 0)

(26, 24)

0

1

0

1

0

1

0

1

0

1

0

1

0

LSB

MSB

BYTE 3

BYTE 2

BYTE 1

BYTE 0

FIGURE 71C. DEVICE COMMUNICATIONS ADMINISTRATION RESPONSE: IDENTIFY, DEVICE 4, MIDDLE STACK DEVICE

CELL 12

DATA

(305, 292)

DATA

ADDRESS 0BH

(287, 282)

DEVICE

ADDRESS

(319,316)

DATA

ADDRESS 0CH

(311, 306)

PAGE

(314,

312)

CELL 11 DATA

(281, 268)

CRC

(287, 264)

CRC

(291,288)

1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1

0

0 0 1 0 1 0 0 1 1 0

0

0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1

MSB

BYTE 39

BYTE 38

BYTE 37 BYTE 36

BYTE 35

BYTE 34

BYTE 33

DATA

ADDRESS 00H

(23, 18)

DATA

ADDRESS 0AH

(263, 258)

CELL 10

DATA

(257, 244)

CRC

(3, 0)

CRC

(243, 240)

PACK VOLTAGE DATA

(17, 4)

0

0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1

0 0 0 0 0 0 0 1 0 0 1

0

1

0 0 0 1 1 1 1 0 0 0

1

LSB

BYTE 32 BYTE 31 BYTE 30

BYTE 2 BYTE 1

BYTE 0

FIGURE 71D. DEVICE DATA RESPONSE: DEVICE 9, READ ALL CELL VOLTAGE DATA

FIGURE 71. DAISY CHAIN DEVICE RESPONSE EXAMPLES

Actual measurement operations occur within the device and

start with the last bit of the command byte and end with data

being placed in a register. Measurement times are dependent on

the ISL78610 internal clock. This clock has the same variations

(and is related to) the daisy chain clock.

Communication Timing

Collecting voltage and temperature data from daisy chained

ISL78610 devices consists of three separate types of operations:

A command to initiate measurement, the measurement itself,

and a command and response to retrieve data.

Responses have different timing calculations, based on the

position of the addressed device in the daisy chain stack and the

daisy chain and SPI clock rates.

Commands are the same for all types of operations, but the

timing is dependent on the number of devices in the stack, the

daisy chain clock rate, and the SPI clock rate.

FN8830 Rev 3.00

May 10, 2018

Page 61 of 100

ISL78610

port at the end of the first byte of data. Then, for each device,

there is an additional delay of one daisy chain clock cycle.

Measurement Timing Diagrams

All measurement timing is derived from the ISL78610’s internal

oscillators. The following typical figures are those obtained with

the oscillators operating at their nominal frequencies and with

any synchronization timing also at nominal value. Maximum

figures are those obtained with the oscillators operating at their

minimum frequencies and with the maximum time for any

synchronization timing.

After receiving the Start Scan signal, the device initializes

measurement circuits and performs the requested

measurement(s). When the measurements are made, some

devices perform additional operations, such as checking for

overvoltage conditions. The measurement command ends when

the registers are updated. At this time, the registers can be read

using a separate command. A detailed timing breakdown is

provided for each measurement type below.

Measurement timing begins with a Start Scan signal. This signal

is generated internally by the ISL78610 at the last clock falling

edge of the Scan or Measure command (this is the last falling

edge of the SPI clock in the case of a stand-alone or master

device, or the last falling edge of the daisy chain clock, in the

case of a daisy chain device). Daisy chain middle or top devices

impose additional synchronization delays. Communications sent

on the SPI port are passed on to the master device’s daisy chain

See Figure 72 for the measurement timing for a Stand-Alone

device. See Figure 73 for the measurement timing for daisy

chain devices.

Tables 33 through 38 starting on page 68 give the typical and

maximum timing for the critical elements of measurement

process. Each table shows the timing from the last edge of the

Scan command clock.

SCAN COMMAND

READ REGISTER COMMAND

DIN

SCK

DOUT

DIN

INTERNAL SCAN

MEASURE

INTERNAL OPERATION

UPDATE REGISTERS

See Tables 33 through 38

FIGURE 72. SCAN/MEASURE COMMAND TIMING WITH RESPONSE (STAND-ALONE)

SPI SCAN COMMAND

DIN

SCK

SCAN/MEASURE

INTERNAL

OPERATION (MASTER)

UPDATE REGISTERS

See Tables 33 through 38

See Figure 74 on page 63, Table 30 and Table 31 on page 67

DAISY CHAIN SCAN COMMAND

UNIT 2

UNIT 6

4 DAISY CHAIN CLOCKS

SCAN/MEASURE

INTERNAL OPERATION

(DAISY CHAIN UNIT 6)

UPDATE REGISTERS

See Tables 33 through 38

FIGURE 73. MEASUREMENT TIMING (6 DEVICE DAISY CHAIN)

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May 10, 2018

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ISL78610

Command Timing Diagram

SPI COMMAND

DOUT

t

CS:WAIT

CS

SCK

LEAD

t

LAG

t

SPI

t

D

t1A

DAISY CLOCK

(P2 TRANSMIT)

8* t

12 * t

D

(Note 15) (Note 16)

2 * t

D

8* t

D

12 * t

(P1 RECEIVE)

D

SCAN

2µs

2 * t

D

4 * t

D

8* t

D

8 * t

(P1 RECEIVE)

D

(FROM DEVICE 5)

SCAN

2µs

2 * t

D

8 * t

D

(P1 RECEIVE)

(FROM DEVICE 13)

8* t

D

SCAN

2µs

2 * t

D

t1B

t1C

To Start of Scan (master)

COMMANDS:

t1A = t

 8 + t

+ t

 3 + 2  t

LAG CSWAIT

• Scan Voltages

• Scan Temperatures

• Scan Mixed

• Scan Wires

• Scan All

SPI

LEAD

To Start of Scan (top/middle)

t1B = t

 8 + t

+ t

+ t  28 + n – 2 + 2s

SPI

LEAD

LAG

D

To End of command

t1C = t

 8 + t

+ t

+ t  34 + N – 2

• Measure

SPI

LEAD

D

• Read

where:

• Write

t

= SPI clock period

= Daisy chain clock period

SPI

• Scan Continuous

• Scan Inhibit

• Sleep

D

= CS High time

CS:WAIT

= CS Low to first SPI Clock

LEAD

= Last SPI Clock CS High

LAG

n = stack position of target device

N = stack position of TOP device

NOTES:

15. Master adds extra byte of zeros as part of daisy protocol.

16. Master adds N-2 clocks to allow communication to the end of the chain.

FIGURE 74. COMMAND TIMING

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ISL78610

Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in

Figures 75, 76, and 77.

DIN

CS

SCK

t

LAG

t

LEAD

t

CS

DR:SP

DATA READY

(P2 RECEIVE)

t

DR:WAIT

2µs

8* t

D

8* t

D

8* t

(P1 TRANSMIT)

D

4 * t

D

4*t

D

8* t

D

(P1 TRANSMIT)

2*t

8 * t

D

8* t

12 * t

D

DAISY CHAIN ACK RESPONSE

8 * t

D

2µs

t2

t2 = 8  t

+ t

  D – t

+ t  42 + N – 2 + 8 + 4s

DRSP D

SPI

DRSP

DRWAIT

CS

LEAD

LAG

where:

t

= SPI clock period

= Daisy chain clock period

= Host delay from DATA READY Low to the CS Low

SPI

D

CS

= CS High to DATA READY High

DRSP

DRWAIT

= DATA READY High time

= CS Low to first SPI Clock

LEAD

= Last SPI clock CS High

LAG

N = Stack position of top device

D = Number of data bytes

D = 4 for one register read (or ACK/NAK response)

D = 40 for read all voltages

D = 22 for read all temperatures

D = 22 for read all faults

D = 43 for read all setup

FIGURE 75. RESPONSE TIMING (MASTER DEVICE)

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ISL78610

Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in

Figures 75, 76, and 77. (Continued)

t

CS

DIN

CS

t

LEAD

t

LAG

SCK

t

DR:SP

DATA READY

2µs

8* t

2µs

8* t

(P2 RECEIVE)

(P1 TRANSMIT)

8* t

D

8* t

D

4* t

D

4*t

8* t

D

Note 17

DAISY CHAIN READ DATA RESPONSE

n

2µs

8* t

D

(P2 RECEIVE)

(FROM DEVICE 7)

8* t

D

2*t

7*t (= N - n - 1)

D

8* t

7* t

D

(P1 TRANSMIT)

COMMAND

D

N

8 * t

D

DAISY CHAIN ACK RESPONSE

Note 18

2µs

RESPONSE

t3

t4

t3 = t  50 + N – n – 1 + 4s

D

t4 = t

 8 + t

+ t

+ t  D  8 + n – 2 + 2s

SPI

CS

LEAD

LAG

DRSP

D

where:

t

= Daisy chain clock period

D

= SPI Clock Period

SPI

N = Stack position of top device

n = Stack position of middle stack device

= Delay imposed by host from DATA READY to the first SPI clock cycle

t

CS

D = Number of bytes in the middle stack device response e.g. read all cell data = 40 bytes, Register or ACK response = 4 bytes.

NOTES:

17. Top device adds (N - n - 1) daisy clocks to allow communications to the targeted middle stack device.

18. Middle stack device adds (n - 2) daisy clocks to allow communications to the master device.

FIGURE 76. RESPONSE TIMING (MIDDLE STACK DEVICE)

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ISL78610

Response Timing Diagrams Responses are different for master, middle, and top devices. The response timings are shown in

Figures 75, 76, and 77. (Continued)

t

CS

DIN

CS

t

LEAD

t

LAG

SCK

DR:SP

DATA READY

2µs

8* t

2µs

8* t

(P2 RECEIVE)

8* t

D

8* t

(P1 TRANSMIT)

D

4 * t

D

4*t

D

8* t

D

(P1 TRANSMIT)

2*t

8 * t

D

8* t

12 * t

D

8 * t

DAISY CHAIN DATA RESPONSE

t5

D

2µs

t5 = t

 8 + t

+ t

+ t  D  8 + 10 + N – 2 + 4s

SPI

LEAD

LAG

DRSP

CS

D

where:

t

= SPI clock period

= Daisy chain clock period

= Host delay from DATA READY to the first SPI clock

SPI

D

CS

= CS High to DATA READY High

= CS Low to first SPI Clock

DRSP

LEAD

= Last SPI Clock CS High

LAG

N = Stack position of top device

D = Number of bytes in response

FIGURE 77. RESPONSE TIMING (TOP DEVICE)

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ISL78610

TABLE 31. COMMAND TIMING

System Timing Tables

Command Timing Tables

TIME TO END OF COMMAND FOR NUMBER OF DEVICES

(µs)

The command timing (Table 30) includes the time from the start

of the command to the start of an internal operation for each

device in a stack. Table 31 shows the time required for the

command to complete. For a stand-alone device, the two values

are the same, because the internal operation starts at the end of

the command. For a daisy chain operation, the internal operation

begins before the end of the command.

SPI CLOCK = 2MHz

NUMBER

OF DEVICES

DAISY CLOCK = 500kHz

DAISY CLOCK = 250kHz

17.5

1

2

17.5

82.0

84.2

86.5

88.7

90.9

93.1

95.3

97.6

157.6

3

162.0

4

166.5

When calculating overall timing for a command, start with the

time from the start of the command to the start of the internal

operation for the target device. Add to this the time for the

internal operation (see “Measurement Timing Tables” on

page 68). Add to this the time it takes to read back the data. See

times shown in “Response Timing Tables” on page 69. Also

needed is a wait time between sending each command (see

Table 32).

5

170.9

6

175.3

7

179.8

8

184.2

9

188.7

When using the Address All option, the command timing for the

top device in the stack determines when the command ends, but

use the Time to Start of Scan for each device to determine when

that device begins its internal operation. For example, in a stack

of six devices, the command takes 90.9µs to complete, but

internal operations start at 13.8µs for the master, 68.7µs for

device 2, 70.9µs for device 3, etc.

10

11

12

13

14

99.8

102.0

104.2

106.5

108.7

193.1

197.6

202.0

206.5

210.9

In Tables 30 and 31, the calculation assumes a daisy chain (and

internal) clock that is 10% slower than the nominal and an SPI

clock that is running at the nominal speed (because the SPI clock

is normally crystal controlled). For the 500kHz daisy setting,

timing assumes a 450kHz clock.

SEQUENTIAL DAISY CHAIN COMMUNICATIONS

When sending a sequence of commands to the master device,

the host must allow time after each response and before sending

the next command for the daisy chain ports of all stack devices

(other than the master) to switch to receive mode. This wait time

is equal to eight daisy chain clock cycles and is imposed from the

time of the last edge on the master’s input daisy chain port to the

last edge of the first byte of the subsequent command on the SPI

(see Figure 78). Table 32 shows the minimum recommended

wait time between the host receiving the last edge of a response

and sending the first edge of the next command for the various

daisy chain data rates.

TABLE 30. TIME TO START OF INTERNAL OPERATION

TIME TO START OF INTERNAL OPERATION FOR TARGET DEVICE

(µs)

SPI CLOCK = 2MHz

TARGET

DEVICE

DAISY CLOCK = 500kHz

DAISY CLOCK = 250kHz

1

2

17.5

68.7

70.9

73.2

75.4

77.6

79.8

82.1

84.3

86.5

88.7

90.9

93.2

95.4

17.5

TABLE 32. MINIMUM RECOMMENDED COMMUNICATIONS WAIT TIME

130.9

MAXIMUM TIME FOR DAISY CHAIN

3

135.4

PORTS TO CLEAR

UNIT

kHz

µs

4

139.8

DAISY CHAIN DATA RATE

500

18

250

36

125

72

62.5

144

5

144.3

Communications Wait Time

6

148.7

7

153.2

8

157.6

9

162.1

10

11

12

13

14

166.5

170.9

175.4

179.8

184.3

FN8830 Rev 3.00

May 10, 2018

Page 67 of 100

ISL78610

SPI

NEXT SPI

SPI RESPONSE

COMMAND

DIN

SCK

DATA READY

Minimum Wait time

between commands.

See Table 32

UNIT 2

UNIT n

FIGURE 78. MINIMUM WAIT BETWEEN COMMANDS (DAISY CHAIN RESPONSE - TOP DEVICE)

SCAN TEMPERATURES

Measurement Timing Tables

The Scan Temperatures command turns on the TEMPREG output

and samples the ExT1 to ExT4 inputs after a 2.5ms settling

interval. TEMPREG turns off at completion of the ExT4

measurement. The Reference voltage, IC Temperature, and

Multiplexer loopback function are also measured. The sequence

is completed with respective registers being loaded.

SCAN VOLTAGES

The Scan Voltages command initiates a sequence of

measurements starting with a scan of each cell input from

Cell 12 to Cell 1, followed by a measurement of pack voltage.

Additional measurements are then performed for the internal

temperature and to check the connection integrity test of the VSS

and VBAT inputs. The process completes with the application of

calibration parameters and the loading of registers. Table 33

shows the times after the start of scan that the cell voltage

inputs are sampled. The voltages are held until the ADC

completes its conversion.

TABLE 34. SCAN TEMPERATURES FUNCTION TIMING – DAISY CHAIN

MASTER OR STAND-ALONE DEVICE

ELAPSED TIME (µs)

EVENT

Turn On TEMPREG

Sample ExT1

TYP

2

MAX

2

TABLE 33. SCAN VOLTAGES FUNCTION TIMING - DAISY CHAIN MASTER

OR STAND-ALONE DEVICE

2518

2770

~

EVENT

TYP (µs)

17

MAX (µs)

19

Sample ExT4

2564

2584

2689

2820

2842

2958

Sample Cell 12

Sample Cell 11

Sample Cell 10

Sample Cell 9

Sample Cell 8

Sample Cell 7

Sample Cell 6

Sample Cell 5

Sample Cell 4

Sample Cell 3

Sample Cell 2

Sample Cell 1

Sample Reference

Measure Internal Temperature

Load Registers

38

42

59

65

81

89

102

123

144

166

187

208

229

251

304

112

135

159

182

206

229

252

276

334

Complete Cell Voltage Capture (ADC

complete) Sample VBAT

Complete VBAT Voltage Capture

Measure Internal Temperature

Complete VSS Test

318

423

550

726

766

349

465

605

799

842

Complete V

Test

BAT

Load Registers

FN8830 Rev 3.00

May 10, 2018

Page 68 of 100

ISL78610

SCAN MIXED

SCAN ALL

The Scan Mixed command performs all the functions of the Scan

Voltages command but interposes a measurement of the ExT1

input between the Cell 7 and Cell 6 measurements.

The Scan All command combines the Scan Voltages, Scan Wires,

and Scan Temperatures commands into a single scan function.

TABLE 37. SCAN ALL FUNCTION TIMING – DAISY CHAIN MASTER OR

STAND-ALONE DEVICE

TABLE 35. SCAN MIXED FUNCTION TIMING – DAISY CHAIN MASTER

OR STAND-ALONE DEVICE

ELAPSED TIME (ms)

EVENT

TYP (µs)

17

MAX (µs)

19

EVENT

Start Scan Voltages

TYP

0

MAX

0

Sample Cell 12

Sample Cell 11

Sample Cell 10

Sample Cell 9

Sample Cell 8

Sample Cell 7

38

42

Start Scan Wires

0.8

0.9

59

65

Start Scan Temperatures

Complete Sequence

60.1

62.8

66.2

69.1

80

88

101

122

176

111

134

194

MEASURE COMMAND

Single parameter measurements of the cell voltages, pack

voltage, ExT1 to ExT4 inputs, IC temperature and reference

voltage are performed using the Measure command.

Complete Cell Voltage Capture 12-7

Sample Ext1

Complete Ext1 Capture

Sample Cell 6

192

207

228

249

270

291

312

367

211

228

251

274

297

321

344

404

TABLE 38. VARIOUS MEASURE FUNCTION TIMINGS – DAISY CHAIN

MASTER OR STAND-ALONE DEVICE

Sample Cell 5

ELAPSED TIME (µs)

Sample Cell 4

EVENT

Measure Cell Voltage

Measure Pack Voltage

Measure ExT input

TYP

178

122

2517

106

MAX

196

134

2768

116

Sample Cell 3

Sample Cell 2

Sample Cell 1

Complete Cell Voltage Capture 6-1

Measure IC Temperature

Measure Reference Voltage

Sample V

BAT

Complete V

Voltage Capture

381

829

419

911

BAT

Load Registers

Response Timing Tables

Response timing depends on the number of devices in the stack,

the position of the device in the stack, and how many bytes are

read back. There are four “sizes” of read responses. The four

types of responses are:

SCAN WIRES

The Scan Wires command initiates a sequence in which each

input is loaded in turn with a test current for a duration of 4.5ms

(default). At the end of this time the input voltage is checked and

the test current is turned off. The result of each test is recorded

and the Open-wire Fault and Fault Status registers are updated

(data latched) at the conclusion of the tests.

1. Single register read or ACK/NAK responses, where four bytes

are returned by the Read Command

2. Read All Voltage response, which returns 40 bytes

3. Read all Temps or Read All Faults responses, which returns

22 bytes

TABLE 36. SCAN WIRES FUNCTION TIMING – DAISY CHAIN MASTER

OR STAND-ALONE DEVICE

4. Read All Setup Registers response, which returns 43 bytes

ELAPSED TIME (ms)

In Tables 39 through 44, the master, middle, and top device

response times for any number of daisy chain devices are

included with the command timing for that configuration. The

right hand column shows the total time to complete the read

operation. This is calculated as follows:

EVENT

Turn On VC0 Current

Test VC0

TYP

0.03

4.5

MAX

0.05

5.0

Turn On Vc1 Current

Test VC1

4.6

5.1

(EQ. 4)

N  T

 + N – 2  T

 + T

+ T

TOP MASTER

COMMAND

MID

9.1

10.0

where N = Number of devices in the stack.

~

In the following tables, internal and daisy clocks are assumed to

be slow by 10% and the SPI clock is assumed to be at the stated

speed.

Turn On VC12 Current

Test VC12

54.9

59.4

60.3

65.3

Load Registers

FN8830 Rev 3.00

May 10, 2018

Page 69 of 100

ISL78610

For example, consider a stack of six devices. To get the full scan

time with a daisy clock of 500kHz and SPI clock of 2MHz, it takes

77.6µs from the start of the Scan All command to the start of the

internal scan of the top device (see Table 30), 842µs to complete

an internal scan of all voltages (see Table 33 on page 68),

5.337ms to read all cell voltages from all devices (see Table 41

on page 71), and 18µs delay before issuing another command.

In this case, all cell voltages in the host controller can be updated

every 6.28ms.

4-BYTE RESPONSE

Tables 39 and 40 show the calculated timing for read operations

for 4-byte responses. This is the timing for an ACK or NAK, as well

as a Read Register command.

TABLE 39. READ TIMING (MAX): 4-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

MIDDLE DEVICE

TOP DEVICE

ALL DEVICES

DEVICE

(µs)

2

3

80

139

142

144

146

148

151

153

155

157

159

162

164

166

110

113

115

117

119

121

124

126

128

130

133

135

137

250

455

410

82

201

203

206

208

210

212

215

217

219

221

223

226

702

4

85

666

1004

1314

1633

1961

2298

2643

2998

3361

3734

4115

4505

5

87

880

6

89

1099

1323

1550

1783

2020

2261

2506

2757

3011

7

91

8

93

9

96

10

11

12

13

14

98

100

102

105

107

TABLE 40. READ TIMING (MAX): 4-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

(µs)

MIDDLE DEVICE

(µs)

TOP DEVICE

(µs)

ALL DEVICES

(µs)

DEVICE

(µs)

156

160

165

169

173

178

182

187

191

196

200

205

209

(µs)

2

3

228

233

237

242

246

251

255

259

264

268

273

277

282

204

208

213

217

221

226

230

235

239

244

248

253

257

432

824

743

383

388

392

397

401

406

410

415

419

423

428

432

1304

1884

2480

3095

3727

4378

5045

5731

6435

7156

7895

8652

4

1226

1636

2055

2483

2919

3365

3820

4283

4755

5237

5727

5

6

7

8

9

10

11

12

13

14

FN8830 Rev 3.00

May 10, 2018

Page 70 of 100

ISL78610

40-BYTE RESPONSE

Tables 41 and 42 show the calculated timing for read operations

for 40-byte responses. Specifically, this is the timing for a Read

All Voltages command.

TABLE 41. READ TIMING (MAX): 40-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

(µs)

MIDDLE DEVICE

(µs)

TOP DEVICE

(µs)

ALL DEVICES

(µs)

DEVICE

(µs)

2

3

80

643

646

648

650

652

655

657

659

661

663

666

668

670

750

753

755

757

759

761

764

766

768

770

773

775

777

1394

2239

3090

3944

4803

5667

6534

7407

1554

2486

3428

4378

5337

6305

7282

8267

9262

10265

11278

12299

13329

82

841

843

846

848

850

852

855

857

859

861

863

866

4

85

5

87

6

89

7

91

8

93

9

96

10

11

12

13

14

98

8284

9165

10050

10941

11835

100

102

105

107

TABLE 42. READ TIMING (MAX): 40-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

(µs)

MIDDLE DEVICE

(µs)

TOP DEVICE

(µs)

ALL DEVICES

(µs)

DEVICE

(µs)

156

160

165

169

173

178

182

187

191

196

200

205

209

(µs)

2

3

732

737

741

746

750

755

759

763

768

772

777

781

786

1484

1488

1493

1497

1501

1506

1510

1515

1519

1524

1528

1533

1537

2216

3888

2527

4368

1663

1668

1672

1677

1681

1686

1690

1695

1699

1703

1708

1712

4

5570

6228

5

7260

8104

6

8959

9999

7

10667

12383

14109

15844

17587

19339

21101

22871

11911

13842

15789

17755

19739

21740

23759

25796

8

9

10

11

12

13

14

FN8830 Rev 3.00

May 10, 2018

Page 71 of 100

ISL78610

22-BYTE RESPONSE

Tables 43 and 44 show the calculated timing of read operations

for 22-byte responses. This is the timing for Read All

Temperature or Read All Faults command.

TABLE 43. READ TIMING (MAX): 22-BYTE RESPONSE, DAISY CLOCK = 500kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

MIDDLE DEVICE

TOP DEVICE

ALL DEVICES

DEVICE

(µs)

2

3

80

391

394

396

398

400

403

405

407

409

411

414

416

418

430

433

435

437

439

441

444

446

448

450

453

455

457

822

982

82

521

523

526

528

530

532

535

537

539

541

543

546

1347

1878

2412

2951

3495

4042

4595

5152

5713

6278

6849

7423

1594

2216

2846

3485

4133

4790

5455

6130

6813

7506

8207

8917

4

85

5

87

6

89

7

91

8

93

9

96

10

11

12

13

14

98

100

102

105

107

TABLE 44. READ TIMING (MAX): 22-BYTE RESPONSE, DAISY CLOCK = 250kHz, SPI CLOCK = 2MHz

COMMAND TIME TO

START OF RESPONSE

STACK (EACH DAISY DEVICE)

TIME TO COMPLETE RESPONSE (DAISY CHAIN)

COMMAND +

RESPONSE ALL

DEVICES

TOP

MASTER DEVICE

(µs)

MIDDLE DEVICE

(µs)

TOP DEVICE

(µs)

ALL DEVICES

(µs)

DEVICE

(µs)

156

160

165

169

173

178

182

187

191

196

200

205

209

(µs)

2

3

480

485

489

494

498

503

507

511

516

520

525

529

534

844

848

853

857

861

866

870

875

879

884

888

893

897

1324

2356

3398

4448

5507

6575

7651

1635

2836

1023

1028

1032

1037

1041

1046

1050

1055

1059

1063

1068

1072

4

4056

5

5292

6

6547

7

7819

8

9110

9

8737

10417

11743

13087

14448

15827

17224

10

11

12

13

14

9832

10935

12047

13169

14299

FN8830 Rev 3.00

May 10, 2018

Page 72 of 100

ISL78610

The Overvoltage, undervoltage, over-temperature, and open-wire

conditions have individual fault bits for each cell input. These bits

are OR’d and reflected to bits in the Fault Status register (one bit

per data register). The Open VBAT and Open VSS have one bit

each in the Fault Status register.

System Diagnostics Functions

The system uses the following four types of faults to determine

the overall health of the system:

1. Automatic Fault detection within the IC.

These conditions are not detected unless the host initiates a scan

2. Fault detection that is automatic, but requires the host

microcontroller to initiate an operation.

operation. The cell overvoltage, cell undervoltage, V

open, and

open faults are sampled at the same time at the end of a

BAT

V

SS

3. Faults that are detected by the host microcontroller during

normal communication. This includes lack of response or

responses that indicate a fault condition.

Scan Voltages command. The cell undervoltage and cell

overvoltage signals are also checked following a Measure Cell

Voltage command. These conditions are also checked during a

Scan Continuous operation. If the host initiates a Scan

Continuous operation, the status is checked automatically every

scan cycle, without further host involvement. For any other Scan

command, the host needs to periodically send the command to

perform another check of the system.

4. Faults that are detected by the host microcontroller following

a series of commands and responses that check various

internal and external circuits.

Hardware Fault Detection

The ISL78610 is always checking the internal V3P3, V2P5, and

VREF power supplies using window comparators. If any of these

voltages exceed a programmed limit (either too high or too low),

a REG fault occurs. This immediately starts an alarm response.

See “Alarm Response” on page 76.

FAULT SIGNAL FILTERING

Filtering is provided for the cell overvoltage, cell undervoltage,

V

open, and V open tests. These fault signals use a

BAT

SS

totalizing method in which an unbroken sequence of positive

results is required to validate a fault condition. The sequence

length (number of sequential positive samples) is set by the

[TOT2:0] bits in the Fault Setup register. See Table 46 on

page 74.

The ISL78610 also checks the two oscillators continually. The

high speed and low speed oscillators are compared against

limits and against each other. If there is a deviation greater than

programmed, then an OSC fault exists. This immediately starts

an alarm response. See “Alarm Response” on page 76.

If the host sends a Scan Continuous command, the Scan Interval

and the Totalizer value set the Fault Detection time. See

Table 45.

System Out of Limit Detection

Bits are set in the fault data registers for detection of:

Each cell input, VBAT, and VSS open circuit has separate filter

functions. The filter is reset whenever a test results in a negative

result (no fault). All filters are reset when the Fault Status register

bits are changed. When a fault is detected, the bits must be

rewritten.

• Overvoltage

• Undervoltage

• Open-wires

• Over-temperature

• Open VBAT

Any out of limit condition generates an Alarm response. See

“Alarm Response” on page 76.

• Open VSS

TABLE 45. FAULT DETECTION TIME AS A FUNCTION OF SCAN INTERVAL AND NUMBER OF TOTALIZED SAMPLES

FAULT DETECTION TIME

SCAN

INTERVAL INTERVAL

SCAN

000

1

001

2

010

4

011

8

100

16

101

32

110

64

111

128

FAULT SETUP REGISTER

TOTALIZER VALUE

CODE

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

(ms)

16

32

64

128

256

512

1024

2048

32

64

128

256

512

1024

2048

4096

64

128

256

512

1024

2048

4096

8192

128

256

512

1024

2048

4096

8192

16384

32768

65536

131072

262144

524288

2048

4096

8192

16384

32768

65536

131072

262144

524288

1048576

2097152

4194304

8388608

256

512

1024

2048

4096

8192

16384

32768

65536

131072

262144

4096

8192

16384

32768

65536

131072

262144

524288

1048576

2097152

4194304

512

1024

2048

4096

8192

16384

32768

65536

131072

8192

16384

32768

65536

131072

262144

524288

1048576

2097152

1024

2048

4096

8192

16384

32768

65536

1024

2048

4096

8192

16384

32768

65536

16384

32768

65536

131072

262144

524288

1048576

FN8830 Rev 3.00

May 10, 2018

Page 73 of 100

ISL78610

TABLE 46. FAULT SETUP REGISTER

REGISTER BITS

12

11

10

9

8

7

6

5

4

3

2

1

0

SCAN

INTERNAL

TEMP

TOTALIZER

TOT2 TOT1 TOT0 COUNT WSCN

INTERVAL

SCN1 SCN0 SCN1 SCN0 TIME (ms)

TST4 TST3 TST2 TST1 ENABLE TST0

SCAN WIRES

Track Voltage Scan

Track Temp Scan

0

x

0

x

0

x

0

1

x

None

ExT1

ExT2

ExT3

ExT4

0

1

Disable

Enable

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16

32

x

1

x

4

64

x

1

x

8

128

1

x

16

32

64

128

256

512

1024

2048

4096

8192

16384

32768

65536

The turn-off time is a function of the MOSFET gate charge and

the VGS connected resistor and capacitor values (for example,

Diagnostic Activity Settling Time

The majority of diagnostic functions within the ISL78610 do not

affect other system activity and there is no requirement to wait

before conducting further measurements. The exceptions to this

are the open-wire test and cell balancing functions.

R

and C in Figure 51 on page 31) and is generally longer

27

than the turn-on time. As with the turn-on case, the turn-off time

needs to be determined for the particular components used.

Turn-off settling times in the range 10ms to 15ms are typical for

settling to within 0.1mV of final value.

OPEN-WIRE TEST

The open-wire test loads each VCn pin in turn with 150µA or 1mA

current. This disturbs the cell voltage measurement while the

test is being applied. For example, a 1mA test current applied

with an input path resistance of 1kΩ reduces the pin voltage by

1V. The time required for the cell voltage to settle following the

open-wire test is dependent on the time constant of components

used in the cell input circuit. The standard input circuit (Figure 51

on page 31) with the components given in Table 11 on page 38

provide settling to within 0.1mV in approximately 2.8ms. This

time should be added at the end of each open-wire scan to allow

the cell voltages to settle.

Memory Checksum

Two checksum operations are available to the host

microcontroller for checking memory integrity - one for the

EEPROM and one for the Page 2 registers.

Two registers are provided to verify the contents of EEPROM

memory. The first (Page 4, address 6’h3F) contains the correct

checksum value, which is calculated during factory testing at

Renesas. The other (Page 5, address 6’h00) contains the

checksum value calculated each time the nonvolatile memory is

loaded to shadow registers, either after a power cycle or after a

device reset. An inequality between these two numbers indicates

corruption of the shadow register contents (and possible

corruption of EEPROM data). The external microcontroller needs

to compare the two registers because it is not automatic.

Resetting the device (using the Reset command) reloads the

shadow registers. A persistent difference between these two

register values indicates EEPROM corruption.

CELL BALANCING

The standard applications circuit (Figure 51 on page 31)

configures the balancing circuits so that the cell input

measurement reads close to 0V when balancing is activated.

There are time constants associated with the turn-on and turn-off

characteristics of the cell balancing system that must be allowed

for when conducting cell voltage measurements.

All Page 2 registers (device configuration registers) are subject to

a checksum calculation. A Calculate Register Checksum

command calculates the Page 2 checksum and saves the value

internally (it is not accessible). The Calculate Register Checksum

command can be run any time, but should be sent whenever a

Page 2 register is changed.

The turn-on time of the balancing circuit is primarily a function of

the 25µA drive current of the cell balancing output and the gate

charge characteristic of the MOSFET and needs to be determined

for a particular setup. Turn-on settling times to within 2mV of

final “on” value are typically less than 5ms.

FN8830 Rev 3.00

May 10, 2018

Page 74 of 100

ISL78610

A Check Register Checksum command recalculates the Page 2

checksum and compares it to the internal value. The occurrence

of a Page 2 checksum error sets the PAR bit in the Fault Status

register and causes a Fault response accordingly. The normal

response to a PAR error is for the host microcontroller to rewrite

the Page 2 register contents. A PAR fault also causes the device

to cease any scanning or cell balancing activity.

each communication. An external event has the potential to “flip”

the input so that the port settles in the inverse state.

A flipped input condition recovers during the normal course of

communications. If a flipped input is suspected, having received

notification of a communications fault condition for example, the

user can send a sequence of all 1s (for example, FF FF FF FF) to

clear the fault. Wait for the resulting NAK response, then send an

ACK to the device that reported the fault. The “all 1” sequence

allows a device to correct a flipped condition through the normal

end of the communication process. The command FB FF FF FF

also works and contains the correct CRC value (should this be a

consideration in the way the control software is set up).

See items 42 through 49 in Table 50 on page 77.

Communication Faults

There is no specific flag to indicate a communications fault. A

fault is indicated by receiving an abnormal communications

response or by an absence of all communications.

If the process above results in a communications failure

response, the next step is for the host microcontroller to send a

Sleep command, wait for all stack devices to go to sleep, then

send a Wake-up command. If successful, the host

microcontroller receives an ACK when all devices are awake. If a

single stack device is asleep, the devices above the sleeping

device do not receive the Sleep command and respond to the

Wake-up sequence with a NAK due to incomplete

communications. The host microcontroller then sends a

command (for example, ACK) to check that all devices are

awake. This process can be repeated as often as needed to wake

up sleeping devices.

Non-daisy chain device commands and responses use CRC

(Cyclical Redundancy Check) error detection (stand-alone

systems do not use the CRC). If a CRC is not recognized by a

target device, a command includes an Address All when it is not

allowed, or if there are too few bits in the sequence there is a

NAK response. The host can tell where this fault occurred by

reading the Device address.

No response indicates a communications failure.

Communication Failure

All commands except the Scan, Measure, and Reset commands

require a response from either the stack top device or the target

device (see Table 13 on page 40). Each device in the stack waits

for a response from the stack device above. Correct receipt of a

command is indicated by the correct response. Failure to receive

a response within a timeout period indicates a communications

failure. The timeout value is stack position dependent. The

device that detects the fault, then transmits the communications

failure response which includes its stack address.

If the Wake-up command does not generate a response, this

likely indicates that the communications have been

compromised. The host microcontroller may send a Sleep

command to all units. If the communications watchdog is

enabled, all parts go to Sleep mode automatically when the

watchdog period expires as long as there is no valid

communications activity. Table 13 on page 40 provides a

summary of the normal responses and an indication if the device

waits for a response from the various communications

commands.

If the target device receives a communications failure response

from the device above, the target device relays the

Daisy Chain Communications Conflicts

communications failure followed by the requested data (in the

case of a read) or simply relays the communications failure only

(in the case of a Write, Balance command, etc). The maximum

time required to return the communications failure response to

the host microcontroller (the time from the falling edge of the

24th clock pulse of an SPI command to receiving a DATA READY

low signal) is given for various data rates in Table 47.

Conflicts in the daisy chain system can occur if both a stack

device and the host microcontroller are transmitting at the same

time, or if more than one stack device transmits at the same

time. Conflicts caused by a stack device transmitting at the same

time as the host microcontroller are recognized by the absence

of the required response (for example, an ACK response to a

write command), or by the scan counter not being incremented in

the case of Scan and Measure commands.

TABLE 47. MAXIMUM TIME TO COMMUNICATIONS FAILURE RESPONSE

MAXIMUM TIME TO

Conflicts that arise from more than one device transmitting

simultaneously can occur if two devices detect faults at the same

time. This can occur when the stack is operating normally (for

example, if two devices register an undervoltage fault in

response to a Scan Voltages command sent to all devices). It is

recommended that the host microcontroller checks the Fault

Status register contents of all devices whenever a Fault response

is received from one device.

ASSERTION OF DATA READY

DAISY CHAIN DATA RATE (kHz)

500

250

125 62.5 UNIT

Communications Failure Response 5.8

11.6 23.2 46.4 ms

A communications fault can be caused by one of three

circumstances:

1. The communications system has been compromised

2. The device causing the fault is in Sleep mode

3. A daisy chain input port is in the wrong idle state

This latter condition is unlikely but could arise in response to

external influence, such as a large transient event. The daisy

chain ports are forced to the correct idle condition at the end of

FN8830 Rev 3.00

May 10, 2018

Page 75 of 100

ISL78610

of the Device Setup register must be set to 6’h3A (111010) to

allow the watchdog to be set to zero. The watchdog is disabled by

first writing the password to the Device Setup register (see “Set-

Up Registers” on page 88) and then writing zero to the lower bits

of the Watchdog/Balance time register. The password function

does not prevent changing the watchdog timeout setting to a

different nonzero value.

Loss of Signal from Host

A watchdog timer is provided as part of the daisy chain

communications fault detection system. The watchdog has no

effect in non-daisy chain systems.

Each device must receive a valid communications sequence

before its watchdog timeout period is exceeded. A valid

communications sequence requires an action or response from

the device. Address All commands, such as the Scan and

Balance commands, provide a simple way to reset the watchdog

timers on all devices with a single communication. Single device

communications (for example, ACK) must be sent individually to

each device to reset the watchdog timer in that device. A read of

the Fault Status register of each device is also a good way to

reset the watchdog timer on each device. This functionality

guards against situations in which a runaway host

The watchdog continues to function when the ISL78610 is in

Sleep mode. Parts in Sleep mode assert the FAULT output when

the watchdog timer expires.

WATCHDOG PASSWORD

Before writing a zero to the watchdog timer, which turns off the

timer, write a password to the [WP5:0] bits. The password value

is 6’h3A.

microcontroller might continually send data.

Alarm Response

Failure to receive valid communications within the required time

causes the WDGF bit to be set in the Fault Status register and the

device to be placed in Sleep mode, with all measurement and

balancing functions disabled. Daisy chain devices assert the

FAULT output in response to a watchdog fault and maintain this

asserted state while in Sleep mode. Note that no watchdog fault

response is automatically sent on the daisy chain interface.

If any of the fault bits are set, the FAULT logic output is asserted

low in response to the fault condition. The output then remains

low until the bits of the Fault Status register are reset. Individual

bits in the fault data registers must be cleared before the

associated bits in the Fault Status register can be cleared.

If the device is in a daisy chain, the Fault logic also sends an

“unprompted” response down the daisy chain to the master,

which notifies the host microcontroller that a problem exists.

WATCHDOG FUNCTION

The watchdog timeout is settable in two ranges using the lower

seven bits of the Watchdog/Balance time register (see Table 48).

The low range (7’b0000001 to 7’b0111111) provides timeout

settings in 1 second increments from 1 second to 63 seconds.

The high range (7’b1000000 to 7’b1111111) provides timeout

settings in 2 minute intervals from 2 minutes to 128 minutes

(see Table 48 for details).

The daisy chain fault response is immediate as long as there is

no communications activity on the device ports, and comprises

the normal Fault Status register read response. As such, it

includes the contents of the Status Register and includes the

device address that is reporting the fault.

The Fault response is sent only for the first fault occurrence.

Subsequent faults do not activate the Fault response until after

the Fault Status register has been cleared. If multiple devices

report a fault, the response shows the results from the lowest

stack device.

TABLE 48. WATCHDOG/BALANCE TIME REGISTER

REGISTER BITS

6

5

4

3

2

1

0

If a fault occurs while the device ports are active, the device waits

until communications activity ceases before sending the Fault

response. The host microcontroller has the option to wait for this

response before sending the next message. Alternately, the host

microcontroller can send the next message immediately (after

allowing the daisy chain ports to clear – see “Sequential Daisy

Chain communications” on page 67). Any conflicts resulting from

additional transmissions from the stack are recognized by the

lack of response from the stack.

WATCHDOG

TIMEOUT

WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0

0

1

0

1

0

Disabled

1s

0

2s

• • •

-

0

1

0

1

0

1

0

1

0

1

0

1

62s

Table 49 provides the maximum time from DATA READY going

low for the last byte of the normal response to DATA READY going

low for the first byte of the Fault response when a Fault response

is delayed by active communications.

1

63s

0

2min

4min

-

0

• • •

1

TABLE 49. MAXIMUM TIME BETWEEN DATA READY SIGNALS –

DELAYED FAULT RESPONSE

MAXIMUM TIME BETWEEN

DATA READY ASSERTIONS

1

0

1

126min

128min

1

DAISY CHAIN DATA RATE (kHz) 500

Fault Response 68

250

136

125

272

62.5

544

UNIT

µs

A zero setting (7’b0000000) disables the watchdog function. A

watchdog password function is provided to guard against

accidental disabling of the watchdog function. The upper six bits

FN8830 Rev 3.00

May 10, 2018

Page 76 of 100

ISL78610

Further read communications to the device return the Fault

response followed by the requested data. Write communications

return only the Fault response. Action commands return nothing.

The host microcontroller resets the register bits corresponding to

the fault by writing 14’h0000 to the Fault Status register, having

first cleared the bits in the Fault Data register(s) if these are set.

The device then responds ACK as with a normal write response

because the fault status bits are now cleared. This also prevents

further Fault responses unless the fault reappears, in which case

the Fault response is repeated.

Daisy chain devices registering a fault in Sleep mode wake up

the other devices in the stack (for example, middle devices send

the Wake-up signal on both ports). Any communications received

by a device on one port while it is transmitting the Wake-up

signal on its other port are ignored. After receiving the Wake-up

signal, the top stack device waits before sending an ACK

response on Port 1. This is to allow other stack devices to wake

up. The total wait time is dependent on the number of devices in

the stack. The time from a device detecting a fault to receipt of

the ACK response is also dependent on the stack position of the

device. See Table 17 for maximum response times for stacks of

8 and 14 devices.

Additionally, the fault status of each part can be obtained at any

time by reading the Fault Status register.

The normal host microcontroller response to receiving an ACK

while the stack is in Sleep mode is to read the Fault Status

register contents of each device in the stack to determine which

device (or devices) has a fault.

The FAULT logic output is asserted in Sleep mode if a fault has

been detected and has not been cleared.

FAULT RESPONSE IN SLEEP MODE

When a stand-alone device is in Sleep mode, the device may still

detect faults if operating in Scan Continuous mode. If an error

occurs, the FAULT output pin is asserted low.

Fault Diagnostics

Table 50 shows a summary of commands and responses for the

various fault diagnostics functions.

Devices may detect faults if operating in Scan Continuous mode

while also in Sleep mode.

TABLE 50. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES

DIAGNOSTIC

FUNCTION

ITEM

1

ACTION REQUIRED

REGISTER READ/WRITE

COMMENTS

Static fault

detection

functions

Check Fault Status (or look Read Fault Status register The main internal functions of the ISL78610 are monitored

for normal fault response)

continuously. Bits are set in the Fault Status register in response to

faults being detected in these functions.

2

Oscillator check Check for device in Sleep

Oscillator faults are detected as part of the Static Fault detection

functions. The response to an oscillator fault detection is to set the OSC

bit in the Fault Status register and to enter Sleep mode. A sleeping

device does not respond to normal communications, producing a

Communications Failure notification from the next device down the

stack. The normal recovery procedure is to send repeated Sleep and

Wake-up commands to ensure all devices are awake.

function

mode if stack returns a

Communications Failure

response

3

4

5

Cell overvoltage Set cell overvoltage limit

Write Overvoltage Limit Full scale value 14'h1FFF = 5V

register

Set fault filter sample value Write TOT bits in Fault

Setup register

Default is 3'b011 (eight samples) - (see “Fault Setup:” on page 86)

Identify which inputs have Write Cell Setup register A '0' bit value indicates the cell is connected. A '1' bit value indicates no

cells connected

cell is connected to this input. The overvoltage test is not applied to

unconnected cells.

6

7

Scan cell voltages

Send Scan Voltages

command

A cell overvoltage condition is flagged after a number of sequential

overvoltage conditions are recorded for a single cell. The number is

programmed in item 4.

Check fault status

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

8

9

Check overvoltage fault

register

Read Overvoltage Fault

register

Required only if the Fault Status register returns a fault condition.

Reset fault bits

Reset the bits in Overvoltage Fault register followed by the bits in Fault

Status register.

10

Reset fault filter

Change the value of the [TOT2:0] bits in the Fault Setup register, then

change back to the required value. This resets the filter. The filter is also

reset if a false overvoltage test is encountered.

FN8830 Rev 3.00

May 10, 2018

Page 77 of 100

ISL78610

TABLE 50. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES (Continued)

DIAGNOSTIC

FUNCTION

ITEM

ACTION REQUIRED

REGISTER READ/WRITE

COMMENTS

11 Cell

Undervoltage

Set cell undervoltage limit Write Undervoltage Limit Full scale value 14'h1FFF = 5V

register

12

Set fault filter sample value Write TOT Bits in Fault

Setup register

Default is 3'b011 (eight samples)

13

Identify which inputs have Write Cell Setup register A '0' bit value indicates the cell is connected. A '1' bit value indicates no

cells connected

cell is connected to this input. The undervoltage test is not applied to

unconnected cells.

14

15

Scan cell voltages

Send Scan Voltages

command

A cell undervoltage condition is flagged after a number of sequential

undervoltage conditions are recorded for a single cell. The number is

programmed in item 12.

Check fault status

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

16

17

18

Check undervoltage fault

register

Read Undervoltage Fault Required only if the Fault Status register returns a fault condition.

register

Reset fault bits

Reset the bits in Undervoltage Fault register followed by the bits in Fault

Status register.

Reset fault filter

Change the value of the [TOT2:0] bits in the Fault Setup register, then

change back to the required value. This resets the filter. The filter is also

reset if a false undervoltage test is encountered.

19

20

V

or VSS

Set fault filter sample value Write TOT bits in Fault

Setup register

Default is 3'b011 (eight samples)

BAT

Connection Test

Scan cell voltages

Send Scan Voltages

command

A open condition on V

or VSS is flagged after a number of sequential

BAT

open conditions are recorded for a single cell. The number is

programmed in item 19.

21

Check Fault Status

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

22

23

Reset fault bits

Reset fault filter

Reset bits in the Fault Status register.

Change the value of the [TOT2:0] bits in the Fault Setup register, then

change back to the required value. This resets the filter. The filter is also

reset if a false open test is encountered.

24 Open-Wire Test Set Scan current value

Write Device Setup

register: ISCN = 1 or 0

Sets scan current to 1mA (recommended) by setting ISCN = 1. Or, set

the scan current to 150µA by setting ISCN = 0.

25

Identify which inputs have Write Cell Setup register A '0' bit value indicates the cell is connected. A '1' bit value indicates no

cells connected

cell is connected to this input. Cell inputs VC2 to VC12: the open-wire

detection system is disabled for cell inputs with a '1' setting in the Cell

Setup register. Cell inputs VC0 and VC1 are not affected by the Cell

Setup register.

26

27

Activate Scan Wires function Send Scan Wires

command

Wait for Scan Wires to complete.

Check Fault Status

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

28

Check Open-Wire Fault

register

Read Open-Wire Fault

register

Required only if the Fault Status register returns a fault condition.

29

Reset fault bits

Reset the bits in Open-Wire Fault register followed by the bits in Fault

Status register.

30 Over-

Set external temperature

limit

Write External Temp Limit Full scale value 14'h3FFF = 2.5V

register

Temperature

Indication

FN8830 Rev 3.00

May 10, 2018

Page 78 of 100

ISL78610

TABLE 50. SUMMARY OF FAULT DIAGNOSTICS COMMANDS AND RESPONSES (Continued)

DIAGNOSTIC

FUNCTION

ITEM

31

ACTION REQUIRED

REGISTER READ/WRITE

COMMENTS

Identify which inputs are

required to be tested

Write Fault Setup register A '1' bit value indicates the input is tested. A '0' bit value indicates the

Bits TST1 to TST4 input is not tested.

32

33

Scan temperature inputs

Send Scan Temperatures An over-temperature condition is flagged immediately if the input

command voltage is below the limit value.

Check Fault Status

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

34

35

Check Over-temperature

Fault register

Read Over-temperature Required only if the Fault Status register returns a fault condition.

Fault register

Reset fault bits

Reset the bits in Over-temperature Fault register followed by the bits in

Fault Status register.

36 Reference

Check Function

Read reference coefficient A Read Reference

Coefficient A register

37

38

39

40

41

Read reference coefficient B Read Reference

Coefficient B register

Read reference coefficient C Read Reference

Coefficient C register

Scan temperature inputs

Send Scan Temperatures

command

Read reference voltage

value

Read Reference Voltage

register

Calculate voltage reference

value

See Voltage Reference Check Calculation in the Worked Examples

section of this datasheet (see “Voltage Reference Check Calculation”

on page 80).

42 Register

Checksum

Calculateregisterchecksum Send Calculate Register Causes the ISL78610 to calculate a checksum based on the current

value

Checksum command

contents of the Page 2 registers. This action must be performed each

time a change is made to the register contents. The checksum value is

stored for later comparison.

43

44

45

46

Check register checksum

value

Send Check Register

Checksum command

The checksum value is recalculated and compared to the value stored

by the previous Calculate Register Checksum command. The PAR bit in

the Fault Status register is set if these two numbers are not the same.

Check Fault Status

Re-write registers

Reset fault bits

Read Fault Status register The device sends the Fault Status register contents automatically if a

fault is detected and if the register value is zero before the fault is

detected.

Load all Page 2 registers This is required only if a PAR fault is registered. It is recommended that

with their correct values. the host reads back the register contents to verify values prior to

sending a Calc Register Checksum command.

Reset the bits in the Fault Status register.

47 EEPROM MISR Read checksum value

Read the EEPROM MISR

Register

Checksum

stored in EEPROM

48

49

Read checksum value

calculated by ISL78610

Read the MISR

Checksum register

The checksum value is calculated each time the EEPROM contents are

loaded to registers, either following the application of power, cycling

the EN pin followed by a host initiated Reset command, or simply the

host issuing a Reset command.

Compare checksum values

Correct function is indicated by the two values being equal. Memory

corruption is indicated by an unequal comparison. In this event the host

should send a Reset command and repeat the check process.

FN8830 Rev 3.00

May 10, 2018

Page 79 of 100

ISL78610

Cell Balancing – Manual Mode

Refer to “Manual Balance Mode” on page 46.

Worked Examples

The following worked examples are provided to assist with the

setup and calculations associated with various functions.

EXAMPLE: ACTIVATE BALANCING ON CELLS 1, 5, 7

AND 11

Voltage Reference Check Calculation

Step 1. Write the Balance Setup register: Set Manual Balance

mode, Balance Status pointer, and turn off balance.

TABLE 51. EXAMPLE REGISTER DATA

VALUE

(HEX)

BMD = 01 (Manual Balance mode)

BWT = XXX

BSP = 0000 (Balance Status Pointer location 0)

BEN = 0 (Balancing disabled)

R/W PAGE ADDRESS

PARAMETER

IC Temperature

Reference Voltage

Coefficient C

DECIMAL

9253

8359

164

0

001

010

010000

010101

111000

111001

111010

14’h2425

14’h20A7

14’h00A4

14’h3FCD

9’h006

Note: Blue text indicates a register change.

TABLE 52. BALANCE SETUP REGISTER

Coefficient B

-51

R/W PAGE

010

ADDRESS

010011

DATA

Coefficient A

6

1

XX XX00 000X XX01

Coefficients A, B, and C are two’s complement numbers. B and C

have a range +8191 to -8192. A has a range +255 to -256.

“X” values can be set to any number.

Coefficient B above is a negative number (Hex value > 1FFF).

The value for B is 14’h3FCD - 14h3FFF- 1 or

Step 2. Write the Balance Status register: Set Bits 0, 4, 6, and 10.

BAL12:1 = 0100 0101 0001

(16333 - 16383 - 1) = -51.

10 10

TABLE 53. BALANCE STATUS REGISTER

Coefficient A occupies the upper nine bits of register 6’b111010

(6'h3A). One way to extract the coefficient data from this register

is to divide the complete register value by 32 and round the

result down to the nearest integer. With 9'h006 in the upper nine

bits, and assuming the lower five bits are 0, the complete register

value will be 14'h0C0 = 192 decimal. Divide this by 32 to

obtain 6.

R/W

1

PAGE

010

ADDRESS

010100

DATA

XX 0100 0101 0001

Step 3. Enable balancing using the Balance Enable command.

TABLE 54. BALANCE ENABLE COMMAND

Coefficients A, B, and C are used with the IC temperature reading

to calibrate the Reference Voltage reading. The calibration is

applied by subtracting an adjustment of the form from the

reference voltage reading:

R/W

0

PAGE

011

ADDRESS

010000

DATA

00 0000

or enable balancing by setting BEN directly in the Balance Setup

register:

2

A

B

8192

-----------------------------

------------

Adjustment =

 dT

+

 dT + C

(EQ. 5)

256  8192

BEN = 1

An example calculation using the data of Table 51 is given in

Equation 6.

TABLE 55. BALANCE SETUP REGISTER

9253 – 9180

--------------------------------

dT =

= 36.5

(EQ. 6)

R/W

1

PAGE

010

ADDRESS

010011

DATA

2

XX XX1X XXXX XXXX

where 9180 is the internal temperature monitor reading at +25°C

(see the ““MEASUREMENT SPECIFICATIONS” on page 8).

The balance FETs attached to Cells 1, 5, 7, and 11 turn on.

2

6

51

8192

-----------------------------

------------

 36.5 + 164 = 163.8

Adjustment =

 36.5

–

256  8192

(EQ. 7)

Turn balancing off by resetting BEN or by sending the Balance

Inhibit command (Page 3, address 6’h11).

Corrected V

= 8359 – 163.8 = 8195.2

(EQ. 8)

(EQ. 9)

REF

8195.2

-----------------

 5 = 2.5010

V

value =

REF

16384

FN8830 Rev 3.00

May 10, 2018

Page 80 of 100

ISL78610

Cell Balancing – Timed Mode

Cell Balancing – Auto Mode

Refer to “Timed Balance Mode” on page 47.

Refer to “Auto Balance Mode” on page 47.

EXAMPLE: ACTIVATE BALANCING ON CELLS 2 AND 8

FOR 1 MINUTE.

BALANCE VALUE CALCULATION EXAMPLE

This example is based on a cell State of Charge (SOC) of 9360

coulombs, a target SOC of 8890 coulombs, a balancing leg

impedance of 31Ω (30Ω resistor plus 1Ω FET on resistance), and

a sampling time interval of 5 minutes (300 seconds).

Step 1. Write the Balance Setup register: Set Timed Balance

mode, Balance Status pointer, and turn off balance.

BMD = 10 (Timed Balance mode)

BWT = XXX

The Balance Value is calculated using Equation 10.

BSP = 0000 (Balance Status Pointer location 0)

BEN = 0 (BALANCING disabled)

8191

5

31

300

------------

---------

= 79562 = 28h00136CA

B =

 9360 – 8890 

(EQ. 10)

The value 8191/5 is the scaling factor of the cell voltage

measurement.

TABLE 56. BALANCE SETUP REGISTER

R/W

1

PAGE

010

ADDRESS

010011

DATA

The value of 28’h00136CA is loaded to the required Cell Balance

Register and the value 7’b0001111 (5 minutes) is loaded to the

Balance Time bits in the Watchdog/Balance time register.

XX XX00 000X XX10

“X” values can be set to any number.

In this example, the total coulomb difference to be balanced is:

470 coulomb (9360 - 8890). At 3.3V/31Ω * 300s = 31.9

coulomb per cycle, it takes about 15 cycles for the balancing to

terminate.

Step 2. Write the Balance Status register: Set Bits 1 and 7.

BAL12:1 = 0000 1000 0010

TABLE 57. BALANCE STATUS REGISTER

AUTO BALANCE MODE CELL BALANCING EXAMPLE

R/W

1

PAGE

010

ADDRESS

010100

DATA

The following describes a simple setup to demonstrate the Auto

Balance mode cell balancing function of the ISL78610. Note that

this balancing setup is not related to the balance value

calculation in Equation 10.

XX 0000 1000 0010

Step 3. Write the balance timeout setting to the

Watchdog/Balance Time register (Page 2, address 6’h15, Bits

[13:7]).

Auto balance cells using the following criteria:

• Balance time = 20 seconds

BTM6:1 = 0000011 (1 minute)

• Balance wait time (dead time between balancing

cycles) = 8 seconds

TABLE 58. WATCHDOG/BALANCE TIME REGISTER

R/W

1

PAGE

010

ADDRESS

010101

DATA

• Balancing disabled during cell measurements

• Balance Values: See Table 61

00 0001 1XXX XXXX

“X” values can be set to any number – the lower bits are the watchdog

timeout value and should be set to a time longer than the balance time.

A value of 111 1111 is suggested.

TABLE 61. CELL BALANCE VALUES (HEX) FOR EACH CELL

CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL

1

2

3

4

5

6

7

8

9

10

11 12

28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h 28’h

Step 4. Enable balancing using the Balance Enable command.

TABLE 59. BALANCE ENABLE COMMAND

406 3E4

0

292 3E0

0

290 3D0

0

151 502 6D6

E

A

D

F

0

3

6

R/W

0

PAGE

011

ADDRESS

010000

DATA

• Balance Status Register: Set up balance:

Cells 1, 4, 7, and 10 on first cycle

Cells 3, 6, 9, and 12 on second cycle

Cells 2, 5, 8, and 11 on third cycle

(See Table 62)

00 0000

or enable balancing by setting BEN directly in the Balance Setup

register:

BEN = 1

TABLE 62. BALANCE STATUS SETUP

CELL

TABLE 60. BALANCE SETUP REGISTER

BPS

R/W

1

PAGE

010

ADDRESS

010011

DATA

[3:0]

1

2

3

4

5

6

7

8

9

10 11 12

XX XX1X XXXX XXXX

0000 Reserved for Manual Balance mode and Timed Balance mode

0001

0010

0011

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

The balance FETs attached to Cells 2 and 8 turn on. The FETs turn

off after 1 minute. Balancing can be stopped by resetting BEN or

by sending the Balance Inhibit command.

FN8830 Rev 3.00

May 10, 2018

Page 81 of 100

ISL78610

Step 1. Write the Balance Value registers .

TABLE 63. BALANCE VALUE REGISTERS

TABLE 65. DEVICE SETUP REGISTER

R/W

1

PAGE

010

ADDRESS

011001

DATA

R/W

1

PAGE

010

ADDRESS

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

DATA (HEX)

14’h006A

14’h0001

14’h3E4D

14’h0000

14’h292F

14’h0000

14’h3E00

14’h0000

14’h2903

14’h0000

14’h3D06

14’h0000

14’h151E

14’h0000

14’h0502

14’h0000

14’h06D6

14’h0000

CELL

1

XX XXXX 1XXX XXXX

X = don’t care

Step 3. Write the balance timeout setting to the

Watchdog/Balance Time register: Balance timeout code =

0000001 (20 seconds).

2

3

BTM6:0 = 000 0001

TABLE 66. BALANCE TIMEOUT REGISTER

4

R/W

1

PAGE

010

ADDRESS

010101

DATA

00 0000 1XXX XXXX

5

“X” values can be set to any number – the lower bits are the watchdog

timeout value and should be set to a time longer than the balance time.

A value 111 1111 is suggested.

6

Step 4. Set up the Balance Status register (from Table 62 on

page 81).

7

Step 4A. Write the Balance Setup register: Set Auto Balance

mode, set the 8 second Balance wait time, and set balance off:

8

BMD = 11 (Auto Balance mode)

BWT = 100 (8 seconds)

BEN = 0 (Balancing disabled)

9

TABLE 67. BALANCE SETUP REGISTER

10

11

12

R/W

1

PAGE

010

ADDRESS

010011

DATA

XX XX0X XXX1 0011

“X” values can be set to any number.

Step 4B. Write the Balance Setup register: Set Balance Status

Pointer = 1.

BSP = 0001 (Balance status pointer = 1)

TABLE 68. BALANCE SETUP REGISTER

TABLE 64. BALANCE VALUE REGISTERS (CELL1) - VALUE 28’h406A

6’20 B0107 B0106 B0105 B0104 B0103 B0102 B0101 B0100

R/W

1

PAGE

010

ADDRESS

010011

DATA

0

1

0

1

0

1

0

XX XXX0 001X XXXX

B0113 B0112 B1011 B0110 B0109 B0108

“X” values can be set to any number.

0

Step 4C. Write the Balance Status register: Set Bits 1, 4, 7, and

10.

6’21 B0121 B0120 B0119 B0118 B0117 B0116 B0115 B0114

0

1

BAL12:1 = 0010 0100 1001

B0127 B0126 B0125 B0124 B0123 B0122

TABLE 69. BALANCE STATUS REGISTER

0

R/W

1

PAGE

010

ADDRESS

010100

DATA

Step 2. Write the BDDS bit in Device Setup register (turn

balancing functions off during measurement).

XX 0010 0100 1001

BDDS = 1

FN8830 Rev 3.00

May 10, 2018

Page 82 of 100

ISL78610

Step 4D. Write the Balance Setup register: Set the Balance

Status Pointer = 2.

Step 5. Enable balancing using the Balance Enable command.

TABLE 76. BALANCE ENABLE COMMAND

BSP = 0010 (Balance status pointer = 2)

TABLE 70. BALANCE SETUP REGISTER

R/W

0

PAGE

011

ADDRESS

010000

DATA

00 0000

R/W

1

PAGE

010

ADDRESS

010011

DATA

Or enable balancing by setting BEN directly in the Balance Setup

register:

XX XXX0 010X XXXX

“X” values can be set to any number

BEN = 1

Step 4E. Write the Balance Status register: Set Bits 3, 6, 9, and

12.

TABLE 77. BALANCE SETUP REGISTER

R/W

1

PAGE

010

ADDRESS

010011

DATA

BAL12:1 = 1001 0010 0100

XX XX1X XXXX XXXX

TABLE 71. BALANCE STATUS REGISTER

The balance FETs cycle through each instance of the Balance

Status register in a loop, interposing the balance wait time

between each instance. The measured voltage of each cell being

balanced is subtracted from the balance value for that cell at the

end of each Balance Status instance. The process continues until

the Balance Value register for each cell contains zero.

R/W

1

PAGE

010

ADDRESS

010100

DATA

XX 1001 0010 0100

Step 4F. Write the Balance Setup register: Set Balance Status

Pointer = 3.

BSP = 0011 (Balance status pointer = 3)

TABLE 72. BALANCE SETUP REGISTER

System Registers

System registers contain 14 bits each. All register locations are

memory mapped using a 9-bit address. The MSBs of the address

form a 3-bit page address. Page 1 (3’b001) registers are the

measurement result registers for cell voltages and temperatures.

Page 3 (3’b011) is used for commands. Pages 1 and 3 are not

subject to the checksum calculations. Page addresses 4 and 5

(3’b100 and 3b’101), with the exception of the EEPROM

checksum registers, are reserved for internal functions.

R/W

1

PAGE

010

ADDRESS

010011

DATA

XX XXX0 011X XXXX

“X” values can be set to any number

Step 4G. Write the Balance Status register: Set Bits 2, 5, 8, and

11.

BAL12:1 = 0100 1001 0010

All Page 2 registers (device configuration registers) and EEPROM

checksum registers are subject to a checksum calculation. The

checksum is calculated in response to the Calculate Register

Checksum command using a Multiple Input Shift Register (MISR)

error detection technique. The checksum is tested in response to

a Check Register Checksum command. The occurrence of a

checksum error sets the PAR bit in the Fault Status register and

causes a Fault response accordingly. The normal response to a

PAR error is for the host microcontroller to rewrite the Page 2

register contents. A PAR fault also causes the device to cease

any scanning or cell balancing activity.

TABLE 73. BALANCE STATUS REGISTER

R/W

1

PAGE

010

ADDRESS

010100

DATA

XX 0100 1001 0010

Step 4H. Write the Balance Setup register: Set the Balance

Status Pointer = 4.

BSP = 0100 (Balance status pointer = 4)

TABLE 74. BALANCE SETUP REGISTER

A description of each register is included in “Register

Descriptions” and includes a depiction of the register with bit

names and initialization values at power up, when the EN pin is

toggled and the device receives a Reset Command, or when the

device is reset. Bits that reflect the state of external pins are

notated “Pin” in the initialization space. Bits which reflect the

state of nonvolatile memory bits (EEPROM) are notated “NV” in

the initialization space. Initialization values are shown below

each bit name.

R/W

1

PAGE

010

ADDRESS

010011

DATA

XX XXX0 100X XXXX

“X” values can be set to any number

Step 4I. Write the Balance Status register: Set bits to all zero to

set the end point for the instances.

BAL12:1 = 0000 0000 0000

Reserved bits (indicated by gray areas) should be ignored when

reading and should be set to “0” when writing to them.

TABLE 75. BALANCE STATUS REGISTER

R/W

1

PAGE

010

ADDRESS

010100

DATA

XX 0000 0000 0000

FN8830 Rev 3.00

May 10, 2018

Page 83 of 100

ISL78610

Register Descriptions

Cell Voltage Data

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b001

Read Only 6’h00 - 6’h0C Measured cell voltage and pack voltage values. Address 001111 accesses all cell and Pack Voltage data with

th

and 6’h0F one read operation. See Figure 71D on page 61. Cell values are output as 13-bit signed integers with the 14

bit (MSB) denoting the sign, (for example, positive full scale is 14’h1FFF, 8191 decimal, negative full scale is

14’h2000, 8192 decimal). V

is a 14-bit unsigned integer.

BAT

PAGE

ADDR

REGISTER

ADDRESS

ACCESS

DESCRIPTION

Read Only 3’b001

6’h00

6’h01

6’h02

6’h03

6’h04

6’h05

6’h06

6’h07

6’h08

6’h09

6’h0A

6’h0B

6’h0C

6’h0F

V

Voltage

BAT

HEXvalue – 16384  2  2.5

10

Cell 1 Voltage

Cell 2 Voltage

Cell 3 Voltage

Cell 4 Voltage

Cell 5 Voltage

Cell 6 Voltage

Cell 7 Voltage

Cell 8 Voltage

Cell 9 Voltage

Cell 10 Voltage

Cell 11 Voltage

Cell 12 Voltage

Read all cell voltages

---------------------------------------------------------------------------------------------------

VCx =

ifHEXvalue  8191

10

8192

HEXvalue  2  2.5

10

----------------------------------------------------

ifHEXvalue  8191

10

8192

HEXvalue  15.9350784  2.5

10

--------------------------------------------------------------------------------------------------------------------------

VBAT =

8192

HEXvalue = Hex to Decimal conversion of the register contents.

10

Temperature Data, Secondary Voltage Reference Data, Scan Count

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b001

See

6’h10 - 6’h16 Measured temperature, Secondary reference, Scan Count. Address 011111 accesses all these data in a

individual

register

and 6’h1F

continuous read (see Figure 71D on page 61). Temperature and reference values are output as 14-bit

unsigned integers, (for example, full scale is 14’h3FFF (16383 decimal).

FN8830 Rev 3.00

May 10, 2018

Page 84 of 100

ISL78610

PAGE

ADDR

REGISTER

ADDRESS

ACCESS

DESCRIPTION

Read Only 3’b001

6’h10

Internal temperature reading.

HEXvalue – 9180

10

------------------------------------------------

+ 25

T

C =

INTERNAL

31.9

HEXvalue = Hex to Decimal conversion of the register contents.

10

6’h11

6’h12

6’h13

6’h14

External temperature Input 1 reading.

External temperature Input 2 reading.

External temperature Input 3 reading.

External temperature Input 4 reading.

HEXvalue  2.5

10

--------------------------------------------

=

V

T

TEMP

16384

C = V_TEMP R

EXTERNAL

DIVIDER

where R

depends on the external resistor divider circuit that

DIVIDER

includes an NTC thermistor (see Figure 50 on page 29 for an example

external circuit.)

6’h15

6’h16

Reference voltage (raw ADC) value. Use to calculate the corrected reference value with reference coefficient data.

See Page 2 data, address 6’h38 – 6’h3A.

Read/

Write

3’h001

Scan Count: Current scan instruction count. Count is incremented each time a scan command is received and

wraps to zero when overflowed. Register may be compared to previous value to confirm scan command receipt.

Bit Designations:

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

SCN3 SCN2 SCN1 SCN0

0

Read Only 3’h001

6’h1F

Read all: Temperature Data, Secondary Voltage Reference Data, Scan Count (locations 6’h10 - 6’h16)

Fault Registers

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

6’h00 - 6’h05 Fault registers. Fault setup and status information. Address 6’h0F accesses all fault data in a continuous

3’h010

Read/

Write

and 6’h0F

read (daisy chain configuration only). See Figure 71D on page 61.

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’h010

6’h00

Overvoltage Fault:

Overvoltage fault on Cells 12 to 1 correspond with Bits OF12 to OF1, respectively.

Default values are all zero.

Bits are set to 1 when faults are detected.

The contents of this register can be reset through a register write (14’h0000).

13

12

11

10

9

8

OF9

0

7

OF8

0

6

OF7

0

5

OF6

0

4

OF5

0

3

OF4

0

2

OF3

0

1

OF2

0

OF1

0

RESERVED

OF12 OF11 OF10

0

Read/

Write

3’h010

6’h01

Undervoltage Fault:

Undervoltage fault on Cells 12 to 1 correspond with Bits UF12 to UF1, respectively.

Default values are all zero.

Bits are set to 1 when faults are detected.

The contents of this register can be reset through a register write (14’h0000).

13

12

11

10

9

8

UF9

0

7

UF8

0

6

UF7

0

5

UF6

0

4

UF5

0

3

UF4

0

2

UF3

0

1

UF2

0

UF1

0

RESERVED

UF12 UF11 UF10

0

FN8830 Rev 3.00

May 10, 2018

Page 85 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’h010

6’h02

Open-Wire Fault:

Open-Wire fault on Pins VC12 to VC0 correspond with Bits OC12 to OC0, respectively.

Default values are all zero.

Bits are set to 1 when faults are detected.

The contents of this register can be reset through a register write (14’h0000).

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESER OC12 OC11 OC10 OC9

VED

OC8

OC7

OC6

OC5

OC4

OC3

OC2

OC1

OC0

0

Read/

Write

3’h010

6’h03

Fault Setup:

These bits control various Fault configurations.

Default values and descriptions of each bit are shown below.

13 12 11 10

9

8

7

6

5

4

3

2

1

0

RESER TST4 TST3 TST2 TST1 TST0 TOT2 TOT1 TOT0 WSCN SCN3 SCN2 SCN1 SCN0

VED

0

1

0

1

0

SCN0, 1, 2, 3

Scan interval code. Decoded to provide the scan interval setup for the auto scan function.

Initialized to 0000 (16ms scan interval). See Table 14 on page 42.

WSCN

Scan wires timing control. Set to 1 for tracking of the temperature scan interval. Set to 0 for

tracking of the cell voltage scan interval above 512ms. Interval is fixed at 512ms for faster

cell scan rates. See Table 14 on page 42.

TOT0, 1, 2

Fault Totalizer code bits. Decoded to provide the required fault totalization. An unbroken

sequence of positive fault results equal to the totalize amount is needed to verify a fault

condition. Initialized to 011 (8 sample totalizing.) See Table 45 on page 73.

This register must be rewritten following an error detection resulting from totalizer overflow.

TST0

Controls temperature testing of internal IC temperature. Set this bit to 1 to enable internal

temperature test. Set to 0 to disable (not recommended). Initialized to 1 (on).

TST1 to TST4

Controls temperature testing on the external temperature Inputs 1 to 4, respectively. Set

this bit to 1 to enable the corresponding temperature test. Set to 0 to disable. Allows

external inputs to be used for general voltage monitoring without imposing a limit value.

TST1 to TST4 are initialized to 0 (off).

FN8830 Rev 3.00

May 10, 2018

Page 86 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’h010

6’h04

Fault Status:

The FAULT logic output is an OR function of the bits in this register: the output will be asserted low if any bits in the

Fault Status register are set.

13

MUX

0

12

REG

0

11

REF

0

10

9

8

7

6

UV

0

5

OV

0

4

OT

0

3

2

1

0

PAR OVSS OVBAT OW

WDGF OSC

RESERVED

0

OSC

Oscillator fault bit. Bit is set in response to a fault on either the 4MHz or 32kHz oscillators.

Note that communications functions can be disrupted by a fault in the 4MHz oscillator.

WDGF

OT

Watchdog timeout fault. Bit is set in response to a watchdog timeout.

Over-temperature fault. ‘OR’ of over-temperature fault bits: TFLT0 to TFLT4. This bit is

latched. The bits in the Over-temperature Fault register must first be reset before this bit can

be reset. Reset by writing 14’h0000 to this register.

OV

UV

Overvoltage fault. ‘OR’ of Overvoltage fault bits: OF1 to OF12. This bit is latched. The bits in

the Overvoltage Fault register must first be reset before this bit can be reset. Reset by

writing 14’h0000 to this register.

Undervoltage fault. ‘OR’ of Undervoltage fault bits: UF1 to UF12. This bit is latched. The bits

in the Undervoltage Fault register must first be reset before this bit can be reset. Reset by

writing 14’h0000 to this register.

OW

Open-Wire fault. ‘OR’ of open-wire fault bits: OC0 to OC12. This bit is latched. The bits in the

Open-Wire Fault register must first be reset before this bit can be reset. Reset by writing

14’h0000 to this register.

OV

Open-wire fault on V

connection. Bit set to 1 when a fault is detected. Can be reset

BAT

through a register write (14’h0000).

OVSS

PAR

Open-wire fault on V connection. Bit set to 1 when a fault is detected. Can be reset

SS

through a register write (14’h0000).

Register checksum (Parity) error. This bit is set in response to a register checksum error. The

checksum is calculated and stored in response to a Calc Register Checksum command and

acts on the contents of all Page 2 registers. The Check Register Checksum command is

used to repeat the calculation and compare the results to the stored value. The PAR bit is

then set if the two results are not equal. This bit is not set in response to a nonvolatile

EEPROM memory checksum error. See Table 78 on page 94.

REF

REG

MUX

Voltage reference fault. This bit is set if the voltage reference value is outside its

“power-good” range.

Voltage regulator fault. This bit is set if a voltage regulator value (V3P3, VCC or V2P5) is

outside its “power-good” range.

Temperature multiplexer error. This bit is set if the VCC loopback check returns a fault. The

VCC loopback check is performed at the end of each temperature scan.

Read/

Write

3’h010

6’h05

Cell Setup:

Default values are shown below, as are descriptions of each bit.

13

12

11

C12

0

10

C11

0

9

C10

0

8

C9

0

7

C8

0

6

C7

0

5

C6

0

4

C5

0

3

C4

0

2

C3

0

1

C2

0

C1

0

FFSN FFSP

0

C1 to C12

Enable/disable cell overvoltage, undervoltage and open-wire detection on Cells 1 to 12,

respectively. Set to 1 to disable OV/UV and open-wire tests.

FFSP

FFSN

Force ADC input to Full Scale Positive. All cell scan readings forced to 14'h1FFF. All

temperature scan readings forced to 14'h3FFF.

Force ADC input to Full Scale Negative. All cell scan readings forced to 14'h2000. All

temperature scan readings forced to 14'h0000.

NOTE: The ADC input functions normally if both FFSN and FFSP are set to '1' but this setting is not supported.

FN8830 Rev 3.00

May 10, 2018

Page 87 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’h010

6’h06

Over-Temperature Fault:

Over-temperature fault on Cells 12 to 1 correspond with bits OF12 to OF1, respectively.

Default values are all zero.

Bits are set to 1 when fault are detected.

The contents of this register can be reset through a register write (14’h0000).

13

12

0

11

0

10

9

RESERVED

0

8

7

6

5

4

3

2

1

0

TFLT4 TFLT3 TFLT2 TFLT1 TFLT0

0

TFLT0

Internal over-temperature fault. Bit set to 1 when a fault is detected. Can be reset through

a register write (14’h0000).

TFLT1 - TFLT4

External over-temperature inputs 1 to 4 (respectively.) Bit set to 1 when a fault is detected.

Can be reset through a register write (14’h0000).

Read Only 3’h010

6’h0F

Read all Fault and Cell Setup data from locations: 6’h00 - 6’h06. See Figure 71D on page 61.

Set-Up Registers

BASE ADDR

ADDRESS

(PAGE)

Access

RANGE

DESCRIPTION

3’b010

6’h10 - 6’h1D Device Set-up registers. All device setup data.

and 6’h1F

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’b010

6’h10

6’h11

6’h12

Overvoltage Limit:

Overvoltage Limit Value

Overvoltage limit is compared to the measured values for Cells 1 to 12 to test for an overvoltage condition at any of

the cells.

Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESER OV12 OV11 OV10

VED

OV9

OV8

OV7

OV6

OV5

OV4

OV3

OV2

OV1

OV0

0

1

Read/

Write

Undervoltage Limit:

Undervoltage Limit Value

Undervoltage limit is compared to the measured values for Cells 1 to 12 to test for an undervoltage condition at any

of the cells.

Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESER UV12 UV11 UV10

VED

UV9

UV8

UV7

UV6

UV5

UV4

UV3

UV2

UV1

UV0

0

Read/

Write

External Temperature Limit:

Over-temperature limit value

Over-temperature limit is compared to the measured values for external temperatures 1 to 4 to test for an

over-temperature condition at any input. The temperature limit assumes NTC temperature measurement devices

(i.e., an over-temperature condition is indicated by a temperature reading below the limit value).

Bit 0 is the LSB, Bit 13 is the MSB.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ETL13 ETL12 ETL11 ETL10 ETL9 ETL8 ETL7 ETL6 ETL5 ETL4 ETL3 ETL2 ETL1 ETL0

0

FN8830 Rev 3.00

May 10, 2018

Page 88 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’b010

6’h13

Balance Setup:

Default values are shown below, as are descriptions of each bit.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

BEN BSP3 BSP2 BSP1 BSP0 BWT2 BWT1 BWT0 BMD1 BMD0

0

BMD0, 1

Balance mode. These bits set balance mode.

BMD1 BMD0

MODE

OFF

0

1

0

1

0

1

Manual

Timed

Auto

BWT0, 1, 2

Balance wait time. Register contents are decoded to provide the required wait time

between device balancing. This assists with thermal management and is used with Auto

Balance mode. See Table 19 on page 46.

BSP0, 1, 2, 3

Balance Status register pointer. Points to one of the 13 incidents of the Balance Status

register. Balance Status register 0 is used for Manual Balance mode and Timed Balance

mode. Balance status registers 1 to 12 are used for Auto Balance mode. Reads and writes

to the Balance Status register are accomplished by first configuring the Balance Status

register pointer (for example, to read (write) Balance Status register 5, load 0101 to the

Balance Status register pointer, then read (write) to the Balance Status register). See

Table 19 on page 46.

BEN

Balance enable. Set to ‘1’ to enable balancing. ‘0’ inhibits balancing. Setting or clearing this

bit does not affect any other register contents. Balance Enable and Balance Inhibit

commands are provided to allow control of this function without requiring a register write.

These commands have the same effect as setting this bit directly. This bit is cleared

automatically when balancing is complete and the EOB bit (see “6’h19” on page 90) is set.

Read/

Write

3’b010

6’h14

Balance Status

The Balance Status register is a multiple incidence register controlled by the BSP0-4 bits in the Balance setup

register. See Table 19 on page 46.

Bit 0 is the LSB, Bit 11 is the MSB.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

BAL

12

BAL

11

BAL

10

BAL

8

BAL

8

BAL

7

BAL

6

BAL

5

BAL

4

BAL

3

BAL

2

BAL

1

0

BAL1 to BAL12

Cell 1 to Cell 12 balance control, respectively. A bit set to 1 enables balance control (turns

FET on) of the corresponding cell. Writing this bit enables balance output for the current

incidence of the Balance Status register for the cells corresponding to the particular bits,

depending on the condition of BEN in the Balance Setup register. Read this bit to determine

the current status of each cell’s balance control.

Read/

Write

3’b010

6’h15

Watchdog/Balance Time

Defaults are shown below:

13 12 11

10

9

8

7

6

5

4

3

2

1

0

BTM6 BTM5 BTM4 BTM3 BTM2 BTM1 BTM0 WDG6 WDG5 WDG4 WDG3 WDG2 WDG1 WDG0

0

1

WDG0 to WDG6

Watchdog timeout setting. Decoded to provide the time out value for the watchdog function.

See “Watchdog Function” on page 76 for details. The watchdog may only be disabled (set

to 7’h00) if the watchdog password is set. The watchdog setting can be changed to a

nonzero value without writing to the watchdog password. Initialized to 7’h7F (128 minutes).

BTM0 to BTM6

Balance timeout setting. Decoded to provide the time out value for Timed Balance mode

and Auto Balance mode. Initialized to 7’00 (Disabled). See Table 21 on page 47.

FN8830 Rev 3.00

May 10, 2018

Page 89 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read/

Write

3’b010

6’h16

6’h17

User Register

28 bits of register space arranged as 2 x 14 bits available for user data. These registers have no effect on the

operation of the ISL78610. These registers are included in the register checksum function.

Read Only 3’b010

6’h18

Comms Setup

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

CRAT1 CRAT0 CSEL CSEL SIZE

SIZE

2

SIZE

1

SIZE ADDR ADDR ADDR ADDR

2

1

3

0

3

2

1

0

COMS COMS COMS COMS

RATE1 RATE0 SEL2 SEL1

0

ADDR0-3

Device stack address. The stack address (device position in the stack) is determined

automatically by the device in response to an “Identify” command. The resulting address is

stored in ADDR0-3 and is used internally for communications pairing and sequencing. The

stack address can be read by the user but not written to.

SIZE0-3

Device stack size (top stack device address). Corresponds to the number of devices in the

stack. The stack size is determined automatically by the stack devices in response to an

“Identify” command. The resulting number is stored in SIZE0-3 and is used internally for

communications pairing and sequencing. The stack size can be read by the user but not

written to.

CSEL1, 2

CRAT0, 1

Communications setup bits. These bits reflect the state of the COMMS SELECT 1,2 pins and

determine the operating mode of the communications ports. See Table 6 on page 27.

Communications rate bits. These bits reflect the state of the COMMS RATE 0,1 pins and

determine the bit rate of the daisy chain communications system. See Table 7 on page 28.

Read/

Write

3’b010

6’h19

Device Setup

13 12

WP5 WP4 WP3 WP2 WP1 WP0 BDDS RESER ISCN SCAN EOB RESER PIN37 PIN39

11

10

9

8

7

6

5

4

3

2

1

0

VED

0

PIN37, PIN39

EOB

These bits indicate the signal level on Pin 37 and Pin 39 of the device.

End Of Balance. This bit is set by the device when balancing is complete. This function is

used in the Timed Balance mode and Auto Balance mode. The BEN bit is cleared as a result

of this bit being set. Initialized to 1.

SCAN

Scan Continuous mode. This bit is set in response to a Scan Continuous command and

cleared by a Scan Inhibit command.

ISCN

Set wire scan current source/sink values. Set to 0 for 150µA. Set to 1 for 1mA.

BDDS

Balance condition during measurement. Controls the balance condition in Scan Continuous

mode and Auto Balance mode. Set to 1 to turn balancing functions off 10ms before and

during cell voltage measurement. Set to 0 for normal operation (balancing functions are not

affected by measurement).

WP5:0

Watchdog disable password. These bits must be set to 6’h3A (111010) before the

watchdog can be disabled. Disable the watchdog by writing 7’h00 to the watchdog bits.

Read Only 3’b010

Value set in

6’h1A

Internal Temperature Limit

Bit 0 is the LSB, Bit 13 is the MSB.

EEPROM

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ITL

13

ITL

12

ITL

11

ITL

10

ITL

8

ITL

8

ITL

7

ITL

6

ITL

5

ITL

4

ITL

3

ITL

2

ITL

1

ITL

0

NV

ITL1 to ITL12

IC over-temperature limit value. The over-temperature limit is compared to the measured

values for the internal IC temperature to test for an over-temperature condition. The internal

temperature limit value is stored in nonvolatile memory during test and loaded to these

register bits at power up. The register contents can be read by the user but not written to.

Read Only 3’b010

6’h1B

6’h1C

Serial Number

The 28b serial number programmed in nonvolatile memory during factory test is mirrored to these 2 x 14 bit

registers. The serial number may be read at any time but may not be written.

FN8830 Rev 3.00

May 10, 2018

Page 90 of 100

ISL78610

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Read Only 3’b010

Value set in

6’h1D

Trim Voltages

EEPROM

13

TV5

NV

12

TV4

NV

11

TV3

NV

10

TV2

NV

9

8

7

6

5

4

3

2

1

0

TV1

NV

TV0

NV

RESERVED

Ignore the Contents of these bits

TV5:0

Trim voltage (VNOM). The nominal cell voltage is programmed to nonvolatile memory during

test and loaded to the Trim Voltage register at power up. The VNOM value is a 7-bit

representation of the 0V to 5V cell voltage input range with 50 (7’h32) representing 5V (for

example, LSB = 0.1V). The parts are additionally marked with the trim voltage by the

addition of a two digit code to the part number. For example, 3.3V is denoted by the code

33 (1 bit per 0.1V of trim voltage, so 0 to 50 decimal covers the full range).

Read Only 3’h010

6’h1F

Read all Setup data from locations: 6’h10 - 6’h1D. See Figure 71D on page 61.

Cell Balance Registers

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b010

Read/

Write

6’h20 - 6’h37 Cell balance registers. These registers are loaded with data related to change in SOC desired for each cell.

This data is then used during Auto Balance mode. The data value is decremented with each successive ADC

sample until a zero value is reached. The register space is arranged as 2 x 14-bit per cell for 24 x 14-bit total.

The registers are cleared at device power up or by a Reset command. See “Auto Balance Mode” on page 47.

PAGE

REGISTER

ACCESS

ADDR

ADDRESS

6’h20

6’h21

~

DESCRIPTION

Read/

Write

3’b010

Cell 1 balance value Bits 0 to 13.

Cell 1 balance value Bits 14 to 27.

6’h36

6’h37

Cell 12 balance value Bits 0 to 13.

Cell 12 balance value Bits 14 to 27.

Reference Coefficient Registers

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b010

Read Only 6’h38 - 6’h3A Reference Coefficients

Bit 13 is the MSB, Bit 0 is the LSB

PAGE

ADDR

REGISTER

ADDRESS

ACCESS

DESCRIPTION

Read Only 3’b010

Value set in

EEPROM

6’h38

Reference Coefficient C

Reference calibration coefficient C LSB. Use with coefficients A and B and the measured reference value to obtain

the compensated reference measurement. Compare this result to the limits in the “Electrical Specifications” table

to check that the reference is within limits. The register contents may be read by the user but not written to.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RCC

13

RCC

12

RCC

11

RCC

10

RCC

9

RCC

8

RCC

7

RCC

6

RCC

5

RCC

4

RCC

3

RCC

2

RCC

1

RCC

0

NV

FN8830 Rev 3.00

May 10, 2018

Page 91 of 100

ISL78610

PAGE

ADDR

REGISTER

ADDRESS

ACCESS

DESCRIPTION

Read Only 3’b010

6’h39

Reference Coefficient B

Reference calibration coefficient B LSB. Use with coefficients A and C and the measured reference value to obtain

the compensated reference measurement. Compare this result to the limits in the “Electrical Specifications” table

to check that the reference is within limits. The register contents may be read by the user but not written to.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RCB

13

RCB

12

RCB

11

RCB

10

RCB

9

RCB

8

RCB

7

RCB

6

RCB

5

RCB

4

RCB

3

RCB

2

RCB

1

RCB

0

NV

Read Only 3’b010

6’h3A

Reference Coefficient A

Reference calibration coefficient A LSB. Use with coefficients B and C and the measured reference value to obtain

the compensated reference measurement. Compare this result to the limits in the “Electrical Specifications” table

to check that the reference is within limits. The register contents may be read by the user but not written to.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RCA

8

RCA

7

RCA

6

RCA

5

RCA

4

RCA

3

RCA

2

RCA

1

RCA

0

RESERVED

NV

Ignore the content of these bits

Cells In Balance Register

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b010

Read Only

6’h3B

Cells In Balance

PAGE REGISTER

ADDR ADDRESS

ACCESS

DESCRIPTION

Cells Balance Enabled (Valid for non-daisy chain configuration only).

Read Only 3’b010

6’h3B

This register reports the current condition of the cell balance outputs.

Bit 0 is the LSB, Bit 11 is the MSB.

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

CBEN CBEN CBEN CBEN CBEN CBEN CBEN CBEN CBEN CBEN CBEN CBEN

12

0

11

0

10

0

8

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

BALI1 to BALI12

Indicates the current balancing status of Cell 1 to Cell 12 (respectively). “1” indicates

balancing is enabled for this cell. “0” indicates that balancing is turned off.

FN8830 Rev 3.00

May 10, 2018

Page 92 of 100

ISL78610

Device Commands

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

3’b011

Read Only 6’h01 - 6’h14 Device commands. Actions and communications administration. Not physical registers but memory

mapped device commands. Commands from host and device responses are all configured as reads (BASE

ADDR MSB = 0).

Write operations break the communication rules and produce a NAK from the target device.

PAGE

REGISTER

ADDR

ADDRESS

DESCRIPTION

3’b011

6’h01

Scan Voltages. Device responds by scanning V

and all 12-cell voltages and storing the results in local memory.

BAT

6’h02

Scan Temperatures. Device responds by scanning external temperature inputs, internal temperature, and the secondary

voltage reference, and storing the results in local memory.

6’h03

Scan Mixed. Device responds by scanning V , cell, and ExT1 voltages and storing the results in local memory. The ExT1

BAT

measurement is performed in the middle of the cell voltage scans to minimize measurement latency between the cell

voltages and the voltage on ExT1.

6’h04

6’h05

Scan Wires. Device responds by scanning for pin connection faults and storing the results in local memory.

Scan All. Device responds by performing the functions of the Scan Voltages, Scan temperatures, and Scan Wires commands

in sequence. Results are stored in local memory.

6’h06

6’h07

6’h08

Scan Continuous. Places the device in Scan Continuous mode by setting the Device Setup register SCAN bit.

Scan Inhibit. Stops Scan Continuous mode by clearing the Device Setup register SCAN bit.

Measure. Device responds by measuring a targeted single parameter (cell voltage/V /external or internal temperatures

BAT

or secondary voltage reference).

6’h09

Identify. Special mode function used to determine device stack position and address. Devices record their own stack address

and the total number of devices in the stack. See “Identify Command” on page 49 for details.

6’h0A

6’h0B

Sleep. Places the part in Sleep mode (wake up through daisy comms). See “Communication Timing” on page 61.

NAK. Device response if communications is not recognized. The device responds NAK down the daisy chain to the host

microcontroller. The host microcontroller typically retransmits after receiving a NAK.

6’h0C

6’h0E

ACK. Used by host microcontroller to verify communications without changing anything. Devices respond with an ACK.

Comms Failure. Used in daisy chain implementations to communicate comms failure. If a communication is not

acknowledged by a stack device, the last stack device that did receive the communication responds with Comms Failure.

This is part of the communications integrity checking. Devices downstream of a communications fault are alerted to the fault

condition by the watchdog function.

6’h0F

Wake-up. Used in daisy chain implementations to wake up a sleeping stack of devices. The Wake-up command is sent to the

bottom stack device (master device) through SPI. The master device then wakes up the rest of the stack by transmitting a

low frequency clock. The top stack device responds ACK once it is awake. See “Wake-Up Command” on page 44.

6’h10

6’h11

6’h12

Balance Enable. Enables cell balancing by setting BEN. Can be used to enable cell balancing on all devices simultaneously

using the address All Stack Address 1111.

Balance Inhibit. Disables cell balancing by clearing BEN. Can be used to disable cell balancing on all devices simultaneously

using the address All Stack Address 1111.

Reset. Resets all digital registers to its power-up state (reloads the factory programmed configuration data from nonvolatile

memory). Stops all scan and balancing activity. Daisy chain devices must be reset in sequence starting with the top stack

device and proceeding down the stack to the bottom (master) device. The Reset command must be followed by an Identify

command (daisy chain configuration) before volatile registers can be rewritten.

6’h13

6’h14

Calculate register checksum. Calculates the checksum value for the current Page 2 register contents (registers with base

address 0010). See “System Hardware Connection” on page 22.

Check register checksum. Verifies the register contents are correct for the current checksum. An incorrect result sets the PAR

bit in the Fault status register which starts a standard fault response. See “System Hardware Connection” on page 22.

FN8830 Rev 3.00

May 10, 2018

Page 93 of 100

ISL78610

checksum value that is calculated each time the nonvolatile

memory is loaded to shadow registers, either after a power cycle

or after a device reset. See “Fault Diagnostics” on page 77. for

more information.

Nonvolatile Memory (EEPROM) Checksum

A checksum is provided to verify the contents of EEPROM

memory. Two registers are provided. The MISR register (Table 78)

contains the correct checksum value, which is calculated during

factory testing. The MISR Shadow register contains the

TABLE 78. MISR REGISTER

BASE ADDR

(PAGE)

ADDRESS

RANGE

ACCESS

DESCRIPTION

100

Read Only

6’h3F

Nonvolatile memory Multiple Input Shift Register (MISR) register. This is the checksum value for the

nonvolatile memory contents. It is programmed during factory testing.

101

Read Only

6’h00

MISR shadow register checksum value. This value is calculated when shadow registers are loaded from

nonvolatile memory either after a power cycle or a reset.

Register Map

R/W + PAGE

BIT 7

VB7

BIT 6

VB6

BIT 5

BIT 13

VB5

BIT 4

BIT 12

VB4

BIT 3

BIT 11

VB3

BIT 2

BIT 10

VB2

BIT 1

BIT 9

VB1

BIT 0

BIT 8

VB0

READ WRITE

0001

ADDRESS

000000

REGISTER NAME

Voltage

V

BAT

VB13

VB12

C1V4

VB11

VB10

VB9

VB8

0001

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

Cell 1 Voltage

Cell 2 Voltage

Cell 3 Voltage

Cell 4 Voltage

Cell 5 Voltage

Cell 6 Voltage

Cell 7 Voltage

Cell 8 Voltage

Cell 9 Voltage

Cell 10 Voltage

Cell 11 Voltage

Cell 12 Voltage

C1V7

C2V7

C3V7

C4V7

C5V7

C6V7

C7V7

C8V7

C9V7

C1V6

C2V6

C3V6

C4V6

C5V6

C6V6

C7V6

C8V6

C9V6

C1V5

C1V3

C1V2

C1V1

C1V9

C2V1

C2V9

C3V1

C3V9

C4V1

C4V9

C5V1

C5V9

C6V1

C6V9

C7V1

C7V9

C8V1

C8V9

C9V1

C9V9

C1V0

C1V8

C2V0

C2V8

C3V0

C3V8

C4V0

C4V8

C5V0

C5V8

C6V0

C6V8

C7V0

C7V8

C8V0

C8V8

C9V0

C9V8

C1V13

C2V5

C1V12

C2V4

C1V11

C2V3

C1V10

C2V2

C2V13

C3V5

C2V12

C3V4

C2V11

C3V3

C2V10

C3V2

C3V13

C4V5

C3V12

C4V4

C3V11

C4V3

C3V10

C4V2

C4V13

C5V5

C4V12

C5V4

C4V11

C5V3

C4V10

C5V2

C5V13

C6V5

C5V12

C6V4

C5V11

C6V3

C5V10

C6V2

C6V13

C7V5

C6V12

C7V4

C6V11

C7V3

C6V10

C7V2

C7V13

C8V5

C7V12

C8V4

C7V11

C8V3

C7V10

C8V2

C8V13

C9V5

C8V12

C9V4

C8V11

C9V3

C8V10

C9V2

C9V13

C10V5

C9V12

C10V4

C9V11

C10V3

C9V10

C10V2

C10V7 C10V6

C11V7 C11V6

C12V7 C12V6

C10V1 C10V0

C10V13 C10V12 C10V11 C10V10 C10V9 C10V8

C11V5 C11V4 C11V3 C11V2 C11V1 C11V0

C11V13 C11V12 C11V11 C11V10 C11V9 C11V8

C12V5 C12V4 C12V3 C12V2 C12V1 C12V0

C12V13 C12V12 C12V11 C12V10 C12V9 C12V8

FN8830 Rev 3.00

May 10, 2018

Page 94 of 100

ISL78610

Register Map(Continued)

R/W + PAGE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 9

BIT 0

BIT 8

READ WRITE

0001

ADDRESS

001111

REGISTER NAME

All Cell Voltage Data

BIT 13

BIT 12

BIT 11

BIT 10

Daisy chain configuration only. This command returns all Page 1 data from address

6’h00 through 6’h0C in a single data stream. See “Communication Sequences” on

page 57 and “System Out of Limit Detection” on page 73. See example in

Figure 71D on page 61.

0001

010000

010001

010010

010011

IC Temperature

ICT7

ICT6

ICT5

ICT13

ET1V5

ICT4

ICT12

ET1V4

ICT3

ICT11

ET1V3

ICT2

ICT10

ET1V2

ICT1

ICT0

ICT9

ICT8

External Temperature Input 1

Voltage (ExT1 pin)

ET1V7 ET1V6

ET2V7 ET2V6

ET3V7 ET3V6

ET1V1

ET1V9

ET2V1

ET2V9

ET3V1

ET3V9

ET1V0

ET1V8

ET2V0

ET2V8

ET3V0

ET3V8

ET1V13 ET1V12 ET1V11 ET1V10

ET2V5 ET2V4 ET2V3 ET2V2

ET2V13 ET2V12 ET2V11 ET2V10

ET3V5 ET3V4 ET3V3 ET3V2

ET3V13 ET3V12 ET3V11 ET3V10

External Temperature Input 2

Voltage (ExT2 pin)

External Temperature Input 3

Voltage (ExT3 pin)

0001

010100

External Temperature Input 4

Voltage (ExT4 pin)

ET4V7 ET4V6

ET4V5

ET4V4

ET4V3

ET4V2

ET4V1

ET4V9

ET4V0

ET4V8

ET4V13 ET4V12 ET4V11 ET4V10

0001

010101

010110

011111

Secondary Reference Voltage

Scan Count

RV7

RV6

RV5

RV4

RV3

RV11

SCN3

RV2

RV10

SCN2

RV1

RV9

RV0

RV8

RV13

RV12

SCN1

SCN0

All Temperature Data

Daisy chain configuration only. This command returns all Page 1 data from address

6’h10 through 6’h16 in a single data stream. See “Communication Sequences” on

page 57 and “System Out of Limit Detection” on page 73.

0010

1010

000000

000001

000010

000011

000100

000101

000110

001111

Overvoltage Fault

Undervoltage Fault

Open-Wire Fault

Fault Setup

OF8

UF8

OC7

TOT2

OW

OF7

UF7

OC6

TOT1

UV

OF6

OF5

OF4

OF12

UF4

OF3

OF11

UF3

OF2

OF10

UF2

OF1

OF9

UF1

UF9

OC0

OC8

SCN0

TTST0

0

UF6

UF5

UF12

OC3

UF11

OC2

UF10

OC1

OC9

SCN1

TTST1

0

OC5

TOT0

OC4

OC12

WSCN

TTST4

OT

OC11

SCN3

TTST3

WDGF

REF

OC10

SCN2

TTST2

OSC

Fault Status

OV

MUX

C6

REG

PAR

OVSS

C2

OV

BAT

Cell Setup

C8

C7

C5

C4

C3

C1

FFSN

FFSP

TFLT4

C12

C11

C10

C9

Over-Temperature Fault

All Fault Data

TFLT3

TFLT2

TFLT1

TFLT0

Daisy chain configuration only. This command returns all Page 2 data from address

6’h00 through 6’h06 in a single data stream. See “Communication Sequences” on

page 57 and “System Out of Limit Detection” on page 73.

0010

1010

010000

Overvoltage Limit

OV7

OV6

OV5

OV4

OV3

OV2

OV1

OV9

OV0

OV8

OV13

OV12

OV11

OV10

FN8830 Rev 3.00

May 10, 2018

Page 95 of 100

ISL78610

Register Map(Continued)

R/W + PAGE

BIT 7

UV7

BIT 6

UV6

BIT 5

BIT 13

UV5

BIT 4

BIT 12

UV4

BIT 3

BIT 11

UV3

BIT 2

BIT 10

UV2

BIT 1

BIT 9

UV1

BIT 0

BIT 8

UV0

READ WRITE

ADDRESS

010001

REGISTER NAME

Undervoltage Limit

0010

1010

UV13

ETL5

UV12

ETL4

UV11

ETL3

UV10

ETL2

UV9

UV8

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011111

External Temp Limit

Balance Setup

ETL7

BSP2

ETL6

BSP1

BAL7

ETL1

ETL9

BMD1

BEN

ETL0

ETL8

BMD0

BSP3

BAL1

BAL9

WDG0

BTM1

UR0

ETL13

BSP0

ETL12

BWT2

ETL11

BWT1

ETL10

BWT0

Balance Status (Cells to Balance) BAL8

BAL6

BAL5

BAL4

BAL12

WDG3

BTM4

UR3

BAL3

BAL11

WDG2

BTM3

UR2

BAL2

BAL10

WDG1

BTM2

UR1

Watchdog/Balance Time

User Register

BTM0 WDG6

WDG5

BTM6

UR5

WDG4

BTM5

UR4

UR7

UR21

SIZE3

BDDS

ITL7

UR6

UR20

SIZE2

0

UR13

UR19

UR27

SIZE1

UR12

UR18

UR26

SIZE0

UR11

UR17

UR25

ADDR3

CRAT1

EOB

UR10

UR16

UR24

UR9

UR8

User Register

UR15

UR23

UR14

UR22

Comms Setup

ADDR2 ADDR1 ADDR0

CRAT0

0

CSEL2

Pin 37

WP1

ITL1

CSEL1

Pin 39

WP0

ITL0

1010

Device Setup

ISCN

WP5

ITL5

SCAN

WP4

ITL4

WP3

WP2

ITL2

Internal Temp Limit

Serial Number 0

Serial Number 1

Trim Voltage

ITL6

SN6

SN20

ITL3

ITL13

SN5

ITL12

SN4

ITL11

SN3

ITL10

SN2

ITL9

ITL8

SN7

SN1

SN0

SN13

SN19

SN27

SN12

SN18

SN26

SN11

SN17

SN25

SN10

SN16

SN24

SN9

SN8

SN21

SN15

SN23

SN14

SN22

RESERVED

TV5

TV4

TV3

TV2

TV1

TV0

All Setup Data

Daisy chain configuration only. This command returns all Page 2 data from address

6’h10 through 6’h1D in a single data stream. See “Communication Sequences” on

page 57 and “System Out of Limit Detection” on page 73.

0010

1010

100000

100001

100010

100011

~

Cell 1 Balance Value 0

Cell 1 Balance Value 1

Cell 2 Balance Value 0

Cell 2 Balance Value 1

~

B0107 B0106

B0105

B0113

B0104

B0112

B0118

B0126

B0204

B0212

B0218

B0226

B0103

B1011

B0117

B0125

B0203

B1011

B0217

B0225

B0102

B0110

B0116

B0124

B0202

B0210

B0216

B0224

B0101 B0100

B0109 B0108

B0115 B0114

B0123 B0122

B0201 B0200

B0209 B0208

B0215 B0214

B0223 B0222

B0121 B0120 B0119

B0127

B0207 B0206 B0205

B0213

B0221 B0220 B0219

B0227

~

FN8830 Rev 3.00

May 10, 2018

Page 96 of 100

ISL78610

Register Map(Continued)

R/W + PAGE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 12

B1218

B1226

RCC4

BIT 3

BIT 11

B1217

B1225

RCC3

BIT 2

BIT 10

B1216

B1224

RCC2

BIT 1

BIT 9

BIT 0

BIT 8

READ WRITE

ADDRESS

110111

REGISTER NAME

BIT 13

0010

1010

Cell 12 Balance Value 1

B1221 B1220 B1219

B1227

B1215 B1214

B1223 B1222

111000

111001

111010

111011

Reference Coefficient C

Reference Coefficient B

Reference Coefficient A

RCC7

RCB7

RCA2

RCC6

RCB6

RCA1

RCC5

RCC13

RCB5

RCB13

RCA0

RCC1

RCC9

RCB1

RCB9

RCC0

RCC8

RCB0

RCB8

RCC12

RCB4

RCC11

RCB3

RCC10

RCB2

RCB12

RCB11

RCB10

RESERVED

RCA5

RCA8

RCA7

RCA6

RCA4

BAL2

RCA3

Cells Balance Enabled (Valid in

Stand-Alone only. Register read

responds NAK otherwise).

CBEN8 CBEN7 CBEN6

CBEN5

CBEN4

CBEN3

CBEN1

CBEN12 CBEN11 CBEN10 CBEN9

0011

0100

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001110

001111

010000

010001

010010

010011

010100

111111

Scan Voltages

Scan Temperatures

Scan Mixed

Scan Wires

Scan All

Scan Continuous

Scan Inhibit

Measure

Identify

Sleep

NAK

ACK

Comms Failure

Wake-up

Balance Enable

Balance Inhibit

Reset

Calc Register Checksum

Check Register Checksum

EEPROM MISR Data Register

14-bit MISR EEPROM checksum value. Programmed during test.

0101

000000

MISR Calculated Checksum

14-bit shadow register MISR checksum value. Calculated when shadow registers are

loaded from nonvolatile memory.

FN8830 Rev 3.00

May 10, 2018

Page 97 of 100

ISL78610

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure you have the latest revision.

DATE

REVISION

FN8830.3

CHANGE

May 10, 2018

Updated the Ordering Information table (removed Note 4, added tape and reel quantity column, added

ISL78610EVKIT1Z, and updated Note 1).

Removed Note 15 in Figure 63.

Added Section “Daisy Chain Receive Buffer” on page 57.

Added Figure 66 on page 57 and text to clarify Buffer over-flow.

In Figures 61 to 63 and Figure 69, removed a 30us time reference between CS and first SPI clock.

Changed the following abs Max values from 4.1V to 5.5V (BASE, DIN, SCLK, CS, DOUT, DATA READY, COMMS

SELECT n, TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n, EN, VDDEXT).

Updated Figure 41 and Figure 42 on page 24, Figure 43 and Figure 44 on page 25, Figure 51 on page 31,

Figure 55 on page 35, and Figure 56 on page 36 to reflect new recommended input filter circuits. Added

Table 2 on page 24 and Table 3 on page 25 and updated Table 11 on page 38.

Added a paragraph in Section, “Daisy Chain Circuits,” on page 28 that discusses board capacitance effect on

capacitor selection and changed Table 8 on page 28 and Table 9 on page 29 to match.

Updated Figure 45 and added Table 5 (No actual changes to content).

Updated Figure 48 and Table 8 (No actual changes to content).

Updated Figure 49 and Table 9 (No actual changes to content).

Updated Figure 50 and Table 10 (No actual changes to content).

Removed About Intersil section and added new disclaimer.

Dec 21, 2016

FN8830.2

Clarified that “Cells in Balance” register is available only during Stand-Alone operation (page 49, page 92,

page 97).

Clarified that Scan Continuous functions during Manual, Timed, and Auto Balance Modes (page 42 and

page 49).

Clarified that the “BDDS” bit function in Timed and Auto Balance modes (page 49).

Clarified the calculation of internal and external temperature values (page 84).

Updated POD Q64.10x10D from rev 2 to rev 3. Changes:

Added land pattern back in (as in rev 1), but removed the exposed pad.

Jun 16, 2016

FN8830.1

Updated ESD specification references to AEC on page 8.

On page 15 in the “Performance Characteristics” tables updated the following MIN/MAX values:

Initial Cell Reading Error

-Minimum from “-3” to “-3.2” Maximum from “3” to “3.2”

Initial VBAT Reading Error

-Minimum from “-105” to “-175” Maximum from “105” to “175”

-Minimum from “-175” to “-300” Maximum from “175” to “300”

Initial Cell Monitor Voltage Error

-Minimum from “-15” to “-12” Maximum from “-15” to “12”

Initial VBAT Reading Error

-Minimum from “-155” to “-250” Maximum from “155” to “250”

-Minimum from “-285” to “-425” Maximum from “285” to “425”

Replaced Figures 5 through 13 based on new bench board characterization.

Apr 12, 2016

FN8830.0

Initial Release

FN8830 Rev 3.00

May 10, 2018

Page 98 of 100

ISL78610

For the most recent package outline drawing, see Q64.10x10D.

Package Outline Drawing

Q64.10x10D

64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE

Rev 3, 11/16

12.00

4

5

10.00

D

3

A

3

12.00

10.00

4

5

B

3

0.50

4X

0.20 C A-B D

4X

0.20 H A-B D

TOP VIEW

BOTTOM VIEW

11/13°

1.20 MAX

C

0.05

/ / 0.10 C

0° MIN.

0.08

SIDE VIEW

SEE DETAIL "A"

H

2

1.00 ±0.05

0.05/0.15

M C A-B D

0.08

7

0.08

WITH LEAD FINISH

0.25 GAUGE

PLANE

R. MIN.

0.22 ±0.05

0-7°

0.20 MIN.

0.60 ±0.15

0.09/0.20

0.09/0.16

(1.00)

DETAIL "A"

SCALE: NONE

0.20 ±0.03

BASE METAL

NOTES:

(10.00)

1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.

(0.28) TYP

2. Datum plane H located at mold parting line and coincident

with lead, where lead exits plastic body at bottom of parting line.

3. Datums A-B and D to be determined at centerline between

leads where leads exit plastic body at datum plane H.

4. Dimensions do not include mold protrusion. Allowable mold

protrusion is 0.254mm.

10.00

5. These dimensions to be determined at datum plane H.

6. Package top dimensions are smaller than bottom dimensions

and top of package will not overhang bottom of package.

7. Does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm total at maximum material

condition. Dambar cannot be located on the lower radius

or the foot.

8. Controlling dimension: millimeter.

(1.50) TYP

9.

This outline conforms to JEDEC publication 95 registration

MS-026, variation ACD.

10. Dimensions in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

FN8830 Rev 3.00

May 10, 2018

Page 99 of 100

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

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型号：	ISL78610ANZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Multi-Cell Li-Ion Battery Manager 电池
文件：	总100页 (文件大小：3878K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL78610ANZ-T [RENESAS]

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