ISL80101AIRAJZ-T7 [RENESAS]
Adjustable Positive LDO Regulator;
| 型号： | ISL80101AIRAJZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Adjustable Positive LDO Regulator 输出元件 调节器 |
| 文件： | 总13页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
High Performance 1A Linear Regulator with
Programmable Current Limiting
ISL80101A
Features
The ISL80101A is a low dropout voltage, single output LDO
with programmable current limiting. This LDO operates from
input voltages of 2.2V to 6V, and is capable of providing output
voltages of 0.8V to 5V. Other custom voltage options are
available upon request.
• ±2% V
accuracy guaranteed over line, load and
T = -40°C to +125°C
ADJ
J
• Very low 212mV dropout voltage at V = 4.5V
IN
• High accuracy current limit programmable up to 1.75A
• Very fast transient response
A submicron BiCMOS process is utilized for this product family
to deliver the best-in-class analog performance and overall
value. The programmable current limiting improves system
reliability of end applications. An external capacitor on the
soft-start pin provides an adjustable soft-starting ramp. The
ENABLE feature allows the part to be placed into a low
quiescent current shutdown mode.
• 100µV
output noise
RMS
• Power-good output
• Programmable soft-start
• Over-temperature protection
• Small 10 Ld DFN package
This CMOS LDO will consume significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints. Quiescent current is modestly compromised to
achieve a very fast load transient response.
Applications
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• USB devices
Table 1 shows the differences between the ISL80101A and
others in its family:
• Gaming
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
• Routers and switchers
PROGRAMMABLE
I
ADJ or FIXED
LIMIT
PART NUMBER
ISL80101-ADJ
ISL80101
I
(DEFAULT)
V
LIMIT
No
OUT
1.75A
ADJ
No
1.75A
1.8V, 2.5V,
3.3V, 5.0V
ISL80101A
ISL80121-5
Yes
Yes
1.62A
0.75A
ADJ
5.0V
5.0V ± 5%
10µF
3.3V
1
10
9
V
V
V
V
IN
OUT
1.5
1.2
V
= 4.5V
IN
10µF
2
IN
OUT
C
C
OUT
IN
2.61k
100pF
R
SET
R
C
3
PB
3
8
10k
1
100k
I
ADJ
SET
R
0.9
0.6
0.464k
ISL80101A
V
= 5.5V
IN
R
2
4
7
6
V
= 5.0V
ENABLE
SS
PG
IN
0.3
0.0
0.01µF
GND
C
SS
5
10
100
(kΩ)
1000
R
SET
2.9x2xV – 1
IN
---------------------------------------
I
~ 1.62 –
LIMIT
R
k
SET
FIGURE 1. TYPICAL APPLICATION
August 11, 2015
FN7712.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80101A
Block Diagram
SS
THERMAL
SHUTDOWN
VIN
+
-
CURRENT
LIMITER
VOUT
ISET
PG
VOLTAGE
REFERENCE
POWER-
GOOD
ADJ
ENABLE
GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
PACKAGE
(RoHS Compliant)
PKG
DWG. #
V
VOLTAGE
ADJ
(°C)
OUT
ISL80101AIRAJZ
DZAC
Evaluation Board
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80101AEVAL2Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101A. For more information on MSL please see techbrief TB363.
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2
ISL80101A
Pin Configuration
ISL80101A
(10 LD 3x3 DFN)
TOP VIEW
V
V
V
1
10
OUT
OUT
IN
V
I
2
3
4
5
9
8
7
6
IN
ADJ
PG
EPAD
SET
ENABLE
GND
SS
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
V
Output voltage. A minimum 10µF X5R/X7R output capacitor (for V
from 1.5V to 5V) is required for stability.
OUT
OUT
See “External Capacitor Requirements” on page 8 for more details.
3
ADJ
LDO output feedback input. To adjust the output voltage, connect this pin to a resistive voltage divider from the
V
to GND.
OUT
4
5
6
7
8
PG
GND
V
in regulation signal. Logic low indicates V
is not in regulation, and must be grounded if not used.
OUT
OUT
Ground.
SS
External capacitor adjusts in-rush current.
ENABLE
V
-independent chip enable. TTL and CMOS compatible.
IN
I
Current limit setting. Current limit is 1.62A when this pin is left floating. This default value can be increased by
tying R to GND, or decreased by tying R to V . See “Programmable Current Limit” on page 8 for more
SET
SET
details.
SET
IN
9, 10
-
V
Input supply. A minimum of 10µF X5R/X7R input capacitor is required for stability. See “External Capacitor
Requirements” on page 8 for more details.
IN
EPAD
EPAD at ground potential. Soldering it directly to GND plane is required for thermal considerations. See “Power
Dissipation and Thermals” on page 9 for more details.
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ISL80101A
Absolute Maximum Ratings (Note 6)
Thermal Information
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
10 Ld 3x3 DFN Package (Notes 4, 5). . . . .
JA (°C/W)
48
JC (°C/W)
IN
OUT
7
PG, ENABLE, ADJ, SS, I
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
SET
Human Body Model (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . ±100mA at +125°C
Recommended Operating Conditions (Note 7)
Junction Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
J
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
IN
OUT
PG, ENABLE, ADJ, SS, I
Relative to GND . . . . . . . . . . . . . . . . . . 0V to 6V
SET
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
7. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < V < 6V, V
IN OUT
= 0.5V, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
LOAD
J
temperature. Please refer to “Functional Description” on page 8 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
DC ADJ Pin Voltage Accuracy
V
V
+ 0.4V < V < 6V, V
IN
= 2.5V;
= 2.5V
490
-1
500
0.2
510
1
mV
%
ADJ
OUT
0A < I
OUT
< 1A
LOAD
DC Input Line Regulation
DC Output Load Regulation
(V
OUT
low line -
high
V
+ 0.4V < V < 6V, V
OUT
IN
OUT
V
OUT
line)/V
low
OUT
line
(V
OUT
no load -
high
V
+ 0.4V < V < 6V, V
IN
= 2.5V;
-1
1
%
OUT
OUT
V
0A < I
< 1A
OUT
LOAD
load)/V
no
OUT
load
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
3
1
5
µA
mA
mA
µA
mV
A
ADJ
I
I
I
= 0A, V
+ 0.4V < V < 6V, V
IN
= 2.5V
= 2.5V
Q
LOAD
LOAD
OUT
OUT
OUT
= 1A, V
+ 0.4V < V < 6V, V
IN
5
7
OUT
Ground Pin Current in Shutdown
Dropout Voltage (Note 9)
Output Current Limit
I
ENABLE = 0.2V, V = 6V
IN
0.2
90
12
212
SHDN
V
I
= 1A, V = 4.5V, V = 0V
IN ADJ
DO
LOAD
I
4.5V < V < 6V, I
is floating
1.62
0.640
160
30
LIMIT
IN
SET
= 25.5kΩ
SET
V
= 5V, R
0.540
0.740
A
IN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TSD
°C
°C
TSDn
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ISL80101A
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < V < 6V, V
IN OUT
= 0.5V, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
LOAD
J
temperature. Please refer to “Functional Description” on page 8 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines established limits. (Continued)
J
A
MIN
MAX
PARAMETER
AC CHARACTERISTICS
SYMBOL
PSRR
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
Input Supply Ripple Rejection
f = 1kHz, I
= 1A, V = 5.0V, V
IN OUT
= 3.3V
= 3.3V
48
48
dB
dB
LOAD
f = 120Hz, I
= 1A, V = 5.0V, V
IN OUT
LOAD
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz, V = 3.7,
IN
100
µV
LOAD
RMS
V
= 3.3V
OUT
V
= 2.2V, V
OUT
= 1.8V, I
= 1A,
LOAD
53
µV
IN
RMS
BW = 100Hz < f < 100kHz
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
V
0.5
10
0.8
80
80
1.0
V
EN(HIGH)
Hysteresis
V
200
mV
EN(HYS)
ENABLE Pin Turn-on Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
Reset Pull-down Current
Soft-start Charge Current
PG PIN CHARACTERISTICS
t
C
= 10µF, I = 1A
LOAD
µs
EN
OUT
V
= 6V, ENABLE = 3V
1
µA
IN
I
V
= 3.5V, EN = 0V, SS = 1V
0.5
1
1.3
mA
µA
PD
IN
I
-3.3
-2
-0.8
CHG
V
V
PG Flag Threshold
PG Flag Hysteresis
75
84
4
92
% V
OUT
OUT
%
OUT
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
I
= 500µA
47
100
1
mV
µA
SINK
V
= 6V, PG = 6V
0.05
IN
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. Dropout is defined by the difference in supply V and V when the output is below its nominal regulation.
IN OUT
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ISL80101A
Typical Operating Performance Unless otherwise noted: V = 5V, V = 3.3V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I = 0A.
J
L
0.505
0.504
0.503
0.502
0.501
0.500
0.499
0.498
0.497
0.496
0.495
150
120
90
60
30
0
+125°C
+25°C
-40°C
0.6
0
0.2
0.4
0.8
1.0
-40
-20
0
20
40
60
80
100 120
LOAD CURRENT (A)
TEMPERATURE (°C)
FIGURE 2. DROPOUT vs LOAD
FIGURE 3. V
vs TEMPERATURE
ADJ
1.8
1.2
0.6
0
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
+25°C
+25°C
-40°C
+125°C
-40°C
-0.6
-1.2
-1.8
+125°C
2
3
4
5
6
0.25
0
0.50
OUTPUT CURRENT (A)
0.75
1.00
0
1
SUPPLY VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 5. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
+25°C
+125°C
-40°C
0
0.2
0.4
0.6
0.8
1.0
2
3
4
5
6
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FIGURE 6. GROUND CURRENT vs LOAD CURRENT
FIGURE 7. GROUND CURRENT vs SUPPLY VOLTAGE
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ISL80101A
Typical Operating Performance Unless otherwise noted: V = 5V, V = 3.3V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I = 0A. (Continued)
J
L
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
ENABLE (5V/DIV)
SS (1V/DIV)
R
= OPEN
SET
V
(2V/DIV)
OUT
R
= 25.5kΩ
SET
PG (2V/DIV)
-40
10
60
TEMPERATURE (°C)
110
TIME (5ms/DIV)
FIGURE 8. ENABLE START-UP
FIGURE 9. CURRENT LIMIT vs TEMPERATURE
90
80
70
60
50
40
30
20
10
0
100mA
0mA
V
AT 50mV/DIV
OUT
I
= 1A
OUT
1000mA
500mA
I
= 10mA
OUT
100
1k
10k
FREQUENCY (Hz)
100k
1M
TIME (20µs/DIV)
FIGURE 10. LOAD TRANSIENT RESPONSE
FIGURE 11. PSRR vs FREQUENCY
10
1
0.1
V
V
C
= 2.2V
IN
= 1.8V
= 10µF
OUT
OUT
I
= 1A
OUT
0.01
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 12. OUTPUT NOISE SPECTRAL DENSITY
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ISL80101A
not be left floating, and should be tied to V if not used. A 1kΩ to
10kΩ pull-up resistor is required for applications that use open
collector or open drain outputs to control the ENABLE pin. The
IN
Functional Description
Input Voltage Requirements
ENABLE pin may be connected directly to V for applications
IN
ISL80101A is capable of delivering output voltages from 0.8V to
with outputs that are always on.
5.0V. Due to the nature of an LDO, V must be some margin
IN
higher than V
OUT
the application if active filtering (PSRR) is expected from V to
plus dropout at the maximum rated current of
Power-good Operation
PG is a logic output that indicates the status of V , current limit
tripping, and V . The PG flag is an open-drain NMOS that can sink
IN
up to 10mA during a fault condition. The PG pin requires an
IN
OUT
V
. The generous dropout specification of this family of LDOs
OUT
allows applications to design for a level of efficiency that can
accommodate profiles smaller than the TO220/263.
external pull-up resistor typically connected to the V
pin. The PG
OUT
pin should not be pulled up to a voltage source greater than V .
IN
Programmable Current Limit
PG goes low when the output voltage drops below 84% of the
nominal output voltage, the current limit faults, or the input
voltage is too low. PG functions during shutdown, but not during
thermal shutdown. For applications not using this feature, connect
this pin to ground.
The ISL80101A protects against overcurrent due to short circuit
and overload conditions applied to the output. When this
happens, the LDO performs as a constant current source. If the
short circuit or overload condition is removed, the output returns
to normal voltage regulation operation.
Soft-start Operation
The current limit is set at 1.62A by default when the I
left floating.
pin is
SET
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up this
This limit can be increased by tying a resistor R
SET
from the I
SET
as shown
pin to ground. The current limit is determined by R
SET
in Equation 1. Do not short this pin to ground. Increasing the
current limit past 1.75A may cause damage to the part and is
highly discouraged.
C
and the feedback reference voltage is clamped to the
SS
voltage across it. The start-up time is set by Equation 3.
C x0.5
SS
----------------------------
=
T
(EQ. 3)
start
2.9
2A
(EQ. 1)
----------------------------
1.62 +
I
LIMIT
R
k
SET
Equation 4 determines the C required for a specific start-up inrush
SS
current, where V
is the output voltage, C is the total
The current limit can be decreased from the 1.62A default by
OUT
OUT
capacitance on the output and I
INRUSH
is the desired inrush current.
(EQ. 4)
tying R
from the I
pin to V . The current limit is then
SET
determined by both R
SET
IN
and V following Equation 2.
V
xC
x2A
OUT
x0.5V
SET
IN
OUT
I
--------------------------------------------------------
=
C
SS
2.9 2 V – 1
INRUSH
IN
k
------------------------------------------
1.62 –
(EQ. 2)
I
LIMIT
R
SET
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
Figure 13 shows the relationship between R
SET
and the current
limit when R
values..
is tied from the I
pin to V for various V
SET
SET
IN
IN
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
1.5
1.2
V
= 4.5V
IN
programmed to any level between 0.8V and 5V. An external
resistor divider, R and R , is used to set the output voltage as
2
3
shown in Equations 5 and 6. Please see Table 2 on page 9 for
recommended values of R and R .
0.9
0.6
2
3
V
= 5.5V
IN
R
3
(EQ. 5)
------
V
= 0.5V
+ 1
OUT
R
2
V
= 5.0V
IN
0.3
V
OUT
(EQ. 6)
---------------
R
= R
2
– 1
3
0.5V
0.0
10
100
(kΩ)
1000
External Capacitor Requirements
R
SET
FIGURE 13. CURRENT LIMIT vs R
SET
AT DIFFERENT V
IN
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
Enable Operation
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
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ISL80101A
OUTPUT CAPACITOR
INPUT CAPACITOR
The ISL80101A applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
customer. Stable operation over full temperature, V range,
connected to the V and GND pins of the LDO with PCB traces no
IN
IN
V
range and load extremes are guaranteed for all capacitor
longer than 0.5cm.
OUT
types and values assuming a minimum of 10µF X5R/X7R is used
for local bypass on V . This output capacitor must be
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 7)” on page 4.
The power dissipation can be calculated by using Equation 8:
OUT
and GND pins of the LDO with PCB traces
connected to the V
no longer than 0.5cm.
OUT
There is a growing trend to use very-low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age and temperature. X7R and X5R dielectric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
P
= V – V
I
+ V I
GND
(EQ. 8)
D
IN
OUT
OUT
IN
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
the maximum allowable power dissipation, as shown in
Equation 9:
and the
determine
J(MAX)
P
= T
– T
JMAX A JA
(EQ. 9)
DMAX
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
is the junction-to-ambient thermal resistance.
JA
For safe operation, ensure that the power dissipation P ,
D
calculated from Equation 8, is less than the maximum allowable
power dissipation P
Phase Boost Capacitor
.
D(MAX)
A small phase boost capacitor, C , can be placed across the top
resistor, R , in the feedback resistor divider network in order to
3
place a zero at:
PB
The DFN package uses the copper area on the PCB as a heat-sink.
The EPAD of this package must be soldered to the copper plane
(GND plane). Figure 14 shows a curve for the of the DFN
JA
1
(EQ. 7)
---------------------------------
F
=
package for different copper area sizes.
z
2xR xC
3
PB
46
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
44
42
40
38
36
34
It is also important to note that the LDO stability and load
transient are affected by the type of output capacitor used. For
optimal result, empirical tuning is suggested for each specific
application.
Table 2 shows the recommended C , R and R for different
PB
3
2
output voltage and ceramic C
.
OUT
2
4
6
8
10
12
14 16
18 20
22 24
2
TABLE 2. RECOMMENDED C FOR DIFFERENT V
PB OUT
AND C
OUT
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
V
R
R
C
C
PB
OUT
3
2
OUT
(V)
5.0
3.3
2.5
1.8
1.5
1.5
1.2
1.2
1.0
0.8
(kΩ)
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
(kΩ)
0.287
0.464
0.649
1.0
(µF)
10
10
10
10
10
22
22
47
47
47
(pF)
100
100
82
FIGURE 14. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL
VIAS vs EPAD-MOUNT COPPER LAND AREA ON PCB
JA
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the die
temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
82
1.3
68
1.3
150
120
270
220
220
1.87
1.87
2.61
4.32
FN7712.4
August 11, 2015
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9
ISL80101A
General PowerPAD Design Considerations
Figure 15 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low
thermal resistance for efficient heat transfer. Complete
connection of the plated-through hole to each plane is important.
It is not recommended to use “thermal relief” patterns to connect
the vias.
FIGURE 15. PCB VIA PATTERN
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
August 11, 2015
FN7712.4 Figure 1 on page 1 - updated equation.
Removed Sense Voltage Version from “Block Diagram” on page 2
Changed PAD to EPAD in Pin Configuration on page 3
“Pin Descriptions” on page 3 - V
OUT
pin - added after the word capacitor: “(for V from 1.5V to 5V)”.
OUT
Changed “SENSE” to “ADJ” under “Absolute Maximum Ratings (Note 6)” and “Recommended Operating Conditions
(Note 7)” on page 4
Changed in “Absolute Maximum Ratings (Note 6)” on page 4 - Latch-up temp from: +85°C to +125°C
Electrical Spec Table changes beginning on page 4:
Electrical Spec table conditions changed from: V = V
IN OUT
+ 0.4V, V
OUT
= 3.3V, C = C
IN
= 10µF, T = +25°C,
OUT J
I
= 0A, to: 2.2V < V < 6V, V
= 0.5V, T = +25°C, I
= 0A
LOAD
IN OUT
J
LOAD
DC ADJ Pin Voltage Accuracy - changed test conditions from: V
+ 0.4V < V < 6V; 0A < I < 1A
IN LOAD
OUT
to: V
OUT
+ 0.4V < V < 6V, V
IN OUT
= 2.5V; 0A < I
< 1A
LOAD
DC Input Line Regulation - changed test conditions from: V
+ 0.4V < V < 6.0V, V
IN OUT
= 5.0V to: V + 0.4V < V
OUT
OUT
IN
<
< 6V, V
= 2.5V. Added “-1” MIN
DC Output Load Regulation – Test Conditions added: V
OUT
+ 0.4V < V < 6V, V
IN OUT
= 2.5V Added “1” MAX
OUT
Ground Pin Current – changed Test Conditions from: I
= 0A, 2.2V < V <6V to: I
= 0A, V
+ 0.4V < V
= 2.5V
LOAD
IN
LOAD
OUT
OUT
IN
6V, V
= 2.5V. And from: I
= 1A, 2.2V < V <6V to: I
= 1A, V
OUT
+ 0.4V < V < 6V, V
OUT
LOAD
IN
LOAD
IN
Dropout voltage test condition: changed "VSENSE = 0V" to "Vadj = 0"
Output Current Limit changed Test Conditions
from: V
OUT
and from: V
= 2V, 4.5V < V < 5.5V, I
IN SET
is floating; to: 4.5V < V < 6V, ISET is floating
IN
= 2V, V = 5.0V, R
= 25.5k to: V = 5V, R
= 25.5kΩ
OUT
IN IN
SET
SET
Thermal Shutdown Temperature - removed Test Conditions
Thermal Shutdown Hysteresis - Removed “Rising Threshold”. Removed Test Conditions
PSRR - added Vout = 3.3V to both test conditions
Output Noise Voltage - added V = 3.7, V
= 3.3V to the first test conditions
IN OUT
Turn-on Threshold: Removed Test Conditions. Changed MIN “0.3” to “0.5”
Hysteresis - Removed “Rising Threshold”. Removed Test Conditions
Reset Pull-down Current - Changed Test Condition from: V = 5.4V, ENABLE = 0V, SS = 1V; to: V = 3.5V, EN = 0V,
IN IN
SS = 1V
Page 6-replaced/updated Figure 4 “OUTPUT VOLTAGE vs SUPPLY VOLTAGE” with new. Added Figure 12 on page 7.
Updated Equations 1 and 2 on page 8
Updated POD L10.3x3 on page 13 to most recent revision with changes as follows:
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm
from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line up with
the centers of the corner pins.
Removed former Note 4: Lead width applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip.
Updated tiebar note From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
FN7712.4
August 11, 2015
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10
ISL80101A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision. (Continued)
DATE
REVISION
CHANGE
September 19, 2011 FN7712.3 Table 1 on page 1 updated to include more information on Intersil's 1A LDO portfolio.
Added standard MSL Note to “Ordering Information” (Note 3)
February 2, 2011
FN7712.2 1. On page 1, “Features”
a."±1.8% Vout Accuracy Guaranteed…" changed to "±2% Vadj Accuracy Guaranteed…"
2. Figure 1 on page 1
a."Typical Applications" changed to "Typical Application"
b."82pF" for Cpb changed to "100pF"
3. On page 3, Pin Number 8
a. On "Description" of ISET, change 2nd sentence from "Current limit is 0.75mA when…" to "Current limit is 1.62A
when…"
4. On page 4, “Electrical Specifications”
a."DC Input Line Regulation" given own line, added symbol, and changed test conditions
b. “Feedback Input Current”, added typical "0.01" and max "1" with units "µA"
5. On page 5, “Electrical Specifications”
a. “PG PIN CHARACTERISTICS” “VOUT PG Flag Threshold”, Typical "85" changed to "84" %Vout
7. On page 8, “Programmable Current Limit”
a. Equation 1 changed to "Ilimit=1.62+…"
b. Equation 2 changed to "Ilimit=1.62-…"
8. Added "The current limit can be decreased from the 0.75A default…" changed to "The current limit can be
decreased from the 1.62A default…" on page 8, between Equation 1 and Equation 2
9. On page 8, beginning of last paragraph
a. "Figure 11 shows the relationship…" changed to "Figure 13 shows the relationship…"
10. “External Capacitor Requirements” on page 8:
a. "The ISL80121-5 applies…" changed to "The ISL80101A applies…
11. On page 4, “Electrical Specifications”, “DC CHARACTERISTICS”, “Output Current Limit”
a. "VOUT = 2V, VIN = 5.5V, RSET = 25.5k " changed to ""VOUT = 2V, VIN = 5.0V, RSET = 25.5k "
12. On page 4, “Electrical Specifications”, “AC CHARACTERISTICS”, “Input Supply Ripple Rejection”
a. "58db" typical changed to "48"
b. "62dB" typical changed to "48"
13. On page 8, revised Figure 13. Updated same graphic on page 1
14. Throughout: All "VIN" changed to "V
"
IN
15. Throughout: All "VOUT" changed to "V
"
"
OUT
16. Throughout: All "RSET" changed to "R
SET
17. Throughout: All "ISET" changed to "I
"
SET
18. Throughout: All "EN" and "enable" changed to "ENABLE"
19. Throughout: All "PGOOD" changed to "PG"
20. “Block Diagram” on page 2, subscripted pin names for V , V , I . Changed PGOOD to PG
IN OUT SET
21. On page 3, EPAD Description
a. "directly to GND plane is optional." Changed to "directly to GND plane is required for thermal considerations.
See “Power Dissipation and Thermals” on page 9 for more details."
22. On page 1, in paragraph 2, "The programmable current limiting improves system reliability of applications"
changed to "The programmable current limiting improves system reliability of end applications."
23. On page 1, “Features”, "Programmable Soft-starting" changed to "Programmable Soft-Start"
24. On page 4, “Electrical Specifications”, “DC CHARACTERISTICS”, "DC Output Voltage Accuracy" changed to “DC
ADJ Pin Voltage Accuracy”
25. On page 5, Notes 10 and 11 deleted (they were not referenced in the spec table).
26. “Output Voltage Selection” on page 8, "An external resistor divider, R2 and R3, is used to set the output voltage
as shown in Equation 5. The recommended value for R3 is 500Ω to 1kΩ. R2 is then chosen according to Equation
6." changed to "An external resistor divider, R2 and R3, is used to set the output voltage as shown in Equations 5
and 6. Please see Table 2 on page 9 for recommended values of R2 and R3."
29. Added “General PowerPAD Design Considerations” on page 10
30. Revised Figure 8
December 6, 2010 FN7712.1 Modified “Block Diagram” on page 2.
In “Ground Pin Current” on page 4 Test Conditions:
-Changed 1st line from "V + 0.4V < V < 5V, VSENSE = 0V" to "I
= 0A, 2.2V < V <6V"
IN
OUT IN
LOAD
LOAD
-Changed 2nd line from "V
+ 0.4V < V < 6V, VSENSE = 0V" to "I
= 1A, 2.2V < V <6V"
OUT IN
IN
Figure 2 “DROPOUT vs LOAD” on page 6:
-Switched colors on 25°C and 125°C.
November 29, 2010 FN7712.0 Initial Release
FN7712.4
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11
ISL80101A
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7712.4
August 11, 2015
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12
ISL80101A
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
0.415
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7712.4
August 11, 2015
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13
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